Method for manufacturing a multi-gate device and multi-gate device structure

Abstract

Methods of fabricating multi-gate transistors using dummy oxide interposers are disclosed herein. An exemplary method includes forming a multilayer stack including a first semiconductor layer, a sacrificial semiconductor layer, and a substrate extension. A source / drain recess is formed by removing the first semiconductor layer, the sacrificial semiconductor layer, and a portion of the substrate extension in the source / drain region, and a source / drain structure is formed in the source / drain recess. The source / drain structure includes a second semiconductor layer and an insulator layer, and the insulator layer is disposed between the second semiconductor layer and the substrate extension. The sacrificial semiconductor layer is replaced with a sacrificial dielectric layer prior to forming the source / drain structure. After forming the source / drain structure, the sacrificial dielectric layer is removed from the channel region to form a portion of the gate opening. A gate stack is formed in a portion of the gate opening. The embodiment of the invention also relates to a method for manufacturing the multi-gate device and a multi-gate device structure.

Description

Technical Field

[0001] Embodiments of this disclosure relate to methods for manufacturing multi-gate devices and multi-gate device structures. Background Technology

[0002] Recently, multi-gate devices have been introduced to improve gate control. These devices have gates that extend partially or completely around a channel to provide access to the channel on at least both sides. Exemplary multi-gate devices include FinFETs and gate-all-around (GAA) transistors, such as nanowire transistors. Multi-gate devices enable significant scaling down of integrated circuit (IC) technology while maintaining gate control and mitigating short-channel effects (SCE), while seamlessly integrating with existing IC manufacturing processes and / or technologies. As multi-gate devices continue to shrink, advanced techniques are needed to optimize their reliability and / or performance. Summary of the Invention

[0003] Embodiments of this disclosure provide a method for manufacturing a multi-gate device, comprising: forming a multilayer stack including a first semiconductor layer and a first sacrificial layer having a first component, wherein the multilayer stack is disposed above a protrusion; forming a source / drain trench by removing portions of the first semiconductor layer, the first sacrificial layer, and the protrusion in a source / drain region; forming a source / drain structure in the source / drain trench, wherein the source / drain structure includes a second semiconductor layer and an insulating layer, wherein the insulating layer is disposed between the second semiconductor layer and the protrusion; replacing the first sacrificial layer with a second sacrificial layer having a second component different from the first component before forming the source / drain structure; removing the second sacrificial layer from a channel region after forming the source / drain structure to form a portion of a gate opening; and forming a gate stack in the portion of the gate opening.

[0004] Another embodiment of this disclosure provides a method for manufacturing a multi-gate device, comprising:

[0005] A multilayer stack is formed, the multilayer stack comprising a semiconductor layer, a sacrificial semiconductor layer, and a substrate extension;

[0006] Source / drain trenches are formed by removing portions of the semiconductor layer, the sacrificial semiconductor layer, and the substrate extension in the source / drain regions;

[0007] The source / drain structure is formed in the source / drain trench by the following steps: forming an undoped semiconductor layer above the substrate extension, the undoped semiconductor layer partially filling the source / drain trench; forming an insulating layer above the undoped semiconductor layer, the insulating layer partially filling the source / drain trench; and forming a doped semiconductor layer above the insulating layer, the doped semiconductor layer filling the remaining portion of the source / drain trench.

[0008] Before forming the source / drain structure in the source / drain trench, the sacrificial semiconductor layer in the channel region is replaced with a sacrificial oxide layer; and

[0009] After the source / drain structure is formed in the source / drain trench, the sacrificial oxide layer in the channel region is replaced with a gate stack.

[0010] Another embodiment of this disclosure provides a multi-gate device structure, including:

[0011] A first p-type transistor includes a first semiconductor layer, a first gate stack, and first internal spacers. The first semiconductor layer has a first length extending from a first p-doped source / drain to a second p-doped source / drain. The first gate stack is disposed above the first semiconductor layer. A portion of the first gate stack is disposed between the first internal spacers, which extend beyond the ends of the first semiconductor layer. The first p-doped source / drain is disposed on a first source / drain insulating layer.

[0012] The second p-type transistor includes a second semiconductor layer, a second gate stack, and a second internal spacer. The second semiconductor layer has a second length extending from a third p-doped source / drain to a fourth p-doped source / drain. The second gate stack is disposed above the second semiconductor layer, wherein a portion of the second gate stack is disposed between the second internal spacers. The second length is greater than the first length, and the third p-doped source / drain is disposed on the second source / drain insulating layer. Attached Figure Description

[0013] This disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various parts are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various parts may be arbitrarily increased or decreased for clarity of discussion.

[0014] Figure 1This is a flowchart of part or all of a method for manufacturing a multi-gate device (e.g., a p-type transistor) according to various aspects of this disclosure.

[0015] Figure 2 This is a partial or complete top view of a device having bottom source / drain insulation according to various aspects of this disclosure, which can be fabricated by employing a sacrificial dielectric interlayer, such as by... Figure 1 The method.

[0016] Figures 3A to 19A It is based on various aspects of this disclosure at various manufacturing stages (such as with Figure 1 The methods associated with those) along line AA Figure 2 A schematic cross-sectional view of part or all of the device.

[0017] Figures 3B to 19B It is based on various aspects of this disclosure at various manufacturing stages (such as with Figure 1 The methods associated with those along line BB Figure 2 A schematic cross-sectional view of part or all of the device.

[0018] Figure 17C Based on all aspects of this disclosure Figure 17A and Figure 17B Along the CC line at the manufacturing stage Figure 2 A cross-sectional view of part or all of the device.

[0019] Figures 20 to 22 It is based on various aspects of this disclosure at various manufacturing stages (such as with Figure 1 The methods associated with those) along line AA Figure 2 A cross-sectional view of part or all of the device.

[0020] Figure 23 and Figure 24 It is based on various aspects of this disclosure at various manufacturing stages (such as with Figure 1 The methods associated with those) along line AA Figure 2 A cross-sectional view of part or all of the device.

[0021] Figure 25A and Figure 25B According to various aspects of this disclosure, methods can be employed by using a sacrificial dielectric interposer (such as through...). Figure 1 A partial or complete cross-sectional view of a device manufactured by a method.

[0022] Figure 26A and Figure 26BThis is a graph illustrating the performance differences between devices having source / drain structures configured to have and not have bottom source / drain insulation according to various aspects of this disclosure.

[0023] Figure 27 It is a partial or complete cross-sectional view of a device that may employ bottom source / drain insulation according to various aspects of this disclosure. Detailed Implementation

[0024] This disclosure generally relates to multi-gate devices (such as all-around gate transistors) and methods of fabricating them for improving overall performance.

[0025] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, for the convenience of describing the relationship between one component and another component, spatially relative terms are used, such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “under,” “below,” “upward,” “downward,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.). Spatially relative terms are intended to cover different orientations of devices including components. Furthermore, when numerical values ​​or ranges of values ​​are described using terms such as “about,” “approximately,” “basically,” etc., the term is intended to cover values ​​within a reasonable range, taking into account the variations inherent during manufacturing as understood by those skilled in the art. For example, based on known manufacturing tolerances for manufacturing parts having characteristics associated with that value, the value or range of values ​​encompasses a reasonable range including the described value, such as within + / - 20% of the described value. For instance, a material layer with a thickness of “about 5 nm” can cover a size range from 4.25 nm to 5.75 nm, where manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to be + / - 15%. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not, in itself, indicate a relationship between the discussed embodiments and / or configurations.

[0026] Multi-gate devices include gate structures that extend partially or completely around a channel region to provide access to the channel region on at least two sides. One such multi-gate device is a gate all-around (GAA) device, which includes a channel layer (region) stacked vertically or horizontally, and the channel layer is suspended above a substrate in a manner that allows the gate stack to wrap around and engage the channel layer. The channel layer extends between a source region and a drain region (e.g., an epitaxial source / drain), and a voltage can be applied to the gate stack, the source region, and / or the drain region to control the current flow between the source and drain regions. GAA devices can significantly increase the contact area between the gate stack and the channel region, which has been observed to reduce subthreshold sway (SS), reduce short-channel effect (SCE), increase drive current, and / or improve channel control compared to other multi-gate devices such as FinFETs.

[0027] However, as integrated circuit (IC) technology nodes shrink (i.e., by increasing device density (i.e., the number of interconnect devices in a given chip area) and / or reducing geometry (e.g., the size and / or dimensions of device components and / or the spacing between them)), leakage current in GAA devices has become a significant challenge. For example, parasitic transistors can be formed between the gate stack, the raised portion of the substrate (with the channel layer and gate stack positioned above the raised portion), and the epitaxial source / drain, and current can undesirably flow through / leak through the raised portion of the substrate between the epitaxial source and drain. Because the gate stack can wrap around the raised portion of the substrate instead of surrounding it as the channel layer does, the control of the off-state leakage current in the raised portion of the substrate by the gate stack may be limited to three sides (e.g., tri-gate control), which has proven insufficient as IC technology nodes shrink and has been observed to cause and / or exacerbate drain-induced barrier reduction (DIBL) and degrade performance.

[0028] This disclosure proposes inserting an insulating material (e.g., a dielectric layer) and / or a material with low conductivity (e.g., an undoped epitaxial layer at the bottom) between the epitaxial source / drain and the substrate to reduce leakage current through the underlying substrate and / or the raised portion of the substrate (hereinafter referred to as a mesa). However, this disclosure also recognizes that epitaxial sources / drains formed on an insulating material (e.g., above an amorphous surface) (rather than on a semiconductor material) can exhibit less strain / stress than epitaxial sources / drains formed on a semiconductor material, such that incorporating the insulating material into the source / drain structure can reduce parasitic capacitance and / or leakage current, while undesirably reducing the desired source / drain strain / stress. In particular, p-type epitaxial sources / drains formed above an insulating layer (e.g., p-doped silicon-germanium sources / drains) can exhibit significant stress losses, which degrade the performance of p-type transistors.

[0029] Therefore, this disclosure proposes to reduce other undesirable stresses that may be introduced into the epitaxial source / drain and / or channel of a transistor during manufacturing, in order to compensate for source / drain stress losses that may arise from the bonding of bottom source / drain isolation. For example, this disclosure recognizes that sacrificial pseudo-semiconductor layers (e.g., sacrificial silicon-germanium (SiGe) layers, which may be referred to as sacrificial SiGe interposers) interlaced between semiconductor layers in the channel region (which becomes the channel layer of the transistor) may cause undesirable stresses in the channel layer, such as undesirable tensile stresses in the channel layer of a p-type transistor. Therefore, this disclosure proposes to replace sacrificial pseudo-semiconductor layers with sacrificial pseudo-dielectric layers (such as pseudo-oxide layers, which may be referred to as pseudo-oxide interposers) to eliminate stresses introduced into the channel layer during its manufacturing. Thus, the pseudo-dielectric interposer can compensate for any source / drain stress / strain losses resulting from bonding bottom source / drain isolation to the source / drain structure. It has been observed that transistors fabricated using a pseudo-dielectric interposer and with source / drain bottom insulation exhibit less performance loss than transistors fabricated using a pseudo-semiconductor interposer and with source / drain bottom insulation.

[0030] The following describes in detail a proposed method for fabricating multi-gate devices (e.g., p-type GAA transistors) with bottom source / drain isolation using a pseudo-dielectric interposer. As can be seen from the description herein, multi-gate devices fabricated according to the method described in this disclosure have advantages over multi-gate devices fabricated according to other methods, such as those using a pseudo-semiconductor interposer. However, it should be understood that different embodiments may have different advantages, and no particular advantage is required in every embodiment.

[0031] Figure 1This is a flowchart of part or all of method 10 for fabricating a multi-gate device (e.g., a p-type transistor) using a sacrificial dielectric layer (also known as a pseudo-oxide interposer) according to various aspects of this disclosure. At block 15, method 10 includes forming a multilayer stack including a sacrificial semiconductor layer (e.g., a silicon-germanium layer), a semiconductor layer (e.g., a silicon layer), and a substrate extension. At block 20, a gate structure may be formed over the multilayer stack in a channel region. The gate structure may include a pseudo-gate stack and gate spacers. At block 25, a source / drain trench is formed by removing portions of the semiconductor layer, the sacrificial semiconductor layer, and the substrate extension of the multilayer stack in the source / drain regions. Method 10 further includes removing the sacrificial semiconductor layer of the multilayer stack from the channel region at block 30 to form a first gap between the semiconductor layers of the multilayer stack in the channel region. At block 35, a sacrificial dielectric layer (e.g., an oxide layer) is formed in the first gap. Method 10 may further include recessing the sacrificial dielectric layer at block 40 to form an internal spacer notch between the ends of the semiconductor layers of the multilayer stack in the channel region, and forming an internal spacer in the internal spacer notch at block 45. At block 50, method 10 includes forming a source / drain structure in a source / drain trench, which may include forming an undoped semiconductor layer at block 52, an insulating layer at block 54, and a doped semiconductor layer at block 56. Method 10 may include removing a dummy gate stack at block 60 to form a gate opening, removing the sacrificial dielectric layer at block 65 to form a second gap between the semiconductor layers of the multilayer stack in the channel region, and forming a gate stack in the gate opening and the second gap at block 70. Additional processing is contemplated in this disclosure. Additional steps may be provided before, during, and after method 10, and some of the described steps may be moved, replaced, or eliminated for additional embodiments of method 10. The following discussion illustrates a device that can be fabricated according to method 10.

[0032] Figure 2 This is a top view of part or all of the device 100 according to various aspects of this disclosure, which can be viewed by... Figure 1 Method 10 processes device 100 to include bottom source / drain insulation. Figures 3A to 19A It is based on various aspects of this disclosure at various manufacturing stages (such as with Figure 1 Method 10 (related to those) along Figure 2 A schematic cross-sectional view of part or all of the device 100 of line AA. Figures 3B to 19B It is based on various aspects of this disclosure at various manufacturing stages (such as with Figure 1 Method 10 (related to those) along Figure 2 A schematic cross-sectional view of part or all of the device 100 of line BB. Figure 17CBased on all aspects of this disclosure Figure 17A and Figure 17B Along the manufacturing stage Figure 2 A partial or complete cross-sectional view of the device 100 of line CC. For ease of description and understanding, this article also discusses... Figure 2 , Figures 3A to 19A , Figures 3B to 19B and Figure 17C For clarity, it has been simplified. Figure 2 , Figures 3A to 19A , Figures 3B to 19B and Figure 17C To better understand the inventive concept of this disclosure. Additional components may be added to device 100, and some components described below may be replaced, modified, or eliminated in other embodiments of device 100.

[0033] In experience and Figure 2 , Figures 3A to 19A , Figures 3B to 19B and Figure 17C Following associated processing, device 100 may include at least one GAA transistor (i.e., a transistor having a gate that at least partially surrounds a suspended channel (e.g., nanowire, nanosheet, nanorod, etc.) extending between the source and drain). In the depicted embodiments, device 100 is processed to fabricate a p-type transistor with bottom source / drain insulation using a pseudo-dielectric (e.g., oxide) interposer, which improves its performance. For example, p-type transistors fabricated as described herein may exhibit smaller leakage current, smaller parasitic capacitance, smaller channel resistance, smaller bottom source / drain insulation RO loss, or combinations thereof, compared to p-type transistors with bottom source / drain insulation fabricated using a pseudo-semiconductor (e.g., SiGe) interposer. In some embodiments, device 100 is processed to form an n-type transistor. In some embodiments, device 100 is processed to form both an n-type transistor and a p-type transistor. In such embodiments, device 100 may include a complementary metal-oxide-semiconductor (CMOS) transistor. Device 100 may be included in a microprocessor, memory, other IC devices, or combinations thereof. In some embodiments, device 100 is part of an IC chip, a system-on-a-chip (SoC), or a portion thereof, and device 100 may include a variety of passive and / or active electronic devices, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type FETs (NFETs), metal-oxide-semiconductor FETs (MOSFETs), CMOS transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof.

[0034] refer to Figure 2 , Figure 3A and Figure 3B Fabrication of device 100 may include forming and / or receiving a device precursor, which may include a substrate 105 and a multilayer stack 110. The multilayer stack 110 may include a sacrificial semiconductor layer 115 and a semiconductor layer 120, and the multilayer stack 110 may be disposed above a mesa (protrusion) 105' of the substrate 105. The multilayer stack 110 may correspond to and / or define an active region 122 of device 100. The active region 122 extends longitudinally along the x-direction (i.e., its length is along the x-direction, its width is along the y-direction, and its height is along the z-direction), and the active region 122 may be substantially parallel to other active region orientations. The active region 122 may include a channel region (C), a source region, and a drain region. The source region and drain region may be collectively referred to as the source / drain region (S / D).

[0035] Substrate 105 includes: elemental semiconductors, such as silicon and / or germanium; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or combinations thereof; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof; or combinations thereof. In some embodiments, substrate 105 is a silicon substrate. In some embodiments, substrate 105 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Substrate 105 (and mesa 105') may include various doped regions, such as p-type doped regions (e.g., p-wells), n-type doped regions (e.g., n-wells), or combinations thereof. n-type doped regions include n-type dopants, such as phosphorus, arsenic, other n-type dopants, or combinations thereof. p-type doped regions include p-type dopants, such as boron, indium, gallium, other p-type dopants, or combinations thereof. In some embodiments, the doped region includes p-type dopant and n-type dopant. The doped region may be formed in the substrate 105, mesa 105', multilayer stack 110, or a combination thereof.

[0036] In some embodiments, a multilayer stack 110 is formed by depositing sacrificial semiconductor layers 115 and 120 and patterning the sacrificial semiconductor layers 115 and 120 over a substrate 105. In some embodiments, the patterning extends to the substrate 105 to form its mesa 105'. The sacrificial semiconductor layers 115 and 120 are vertically stacked from the top of the substrate 105 in an alternating and / or staggered configuration (e.g., along the z-direction). In some embodiments, the deposition includes epitaxially growing the sacrificial semiconductor layers 115 and 120 in the shown alternating / staggered configuration. For example, a first sacrificial semiconductor layer 115 is epitaxially grown on the substrate 105, a first semiconductor layer 120 is epitaxially grown on the first sacrificial semiconductor layer 115, a second sacrificial semiconductor layer 115 is epitaxially grown on the first semiconductor layer 120, and so on, until the multilayer stack 110 has a desired number of sacrificial semiconductor layers 115 and 120. In such embodiments, the sacrificial semiconductor layers 115 and 120 may be referred to as epitaxial layers. In some embodiments, the epitaxial growth of the sacrificial semiconductor layer 115 and the semiconductor layer 120 is achieved by molecular beam epitaxy (MBE), chemical vapor deposition (CVD), metal-organic (MOCVD), other suitable epitaxial growth processes, or combinations thereof.

[0037] The composition of the sacrificial semiconductor layer 115 differs from that of the semiconductor layer 120 to achieve etch selectivity. For example, the sacrificial semiconductor layer 115 and the semiconductor layer 120 may comprise different materials, atomic percentages of components, weight percentages of components, other properties, or combinations thereof to achieve etch selectivity. In some embodiments, the sacrificial semiconductor layer 115 comprises silicon germanium, the semiconductor layer 120 comprises silicon, and the etch rate of the semiconductor layer 120 differs from the etch rate of the sacrificial semiconductor layer 115 against a given etchant. In some embodiments, the sacrificial semiconductor layer 115 and the semiconductor layer 120 may comprise the same material but have different atomic percentages of components. For example, the sacrificial semiconductor layer 115 and the semiconductor layer 120 may comprise silicon germanium, and the sacrificial semiconductor layer 115 and the semiconductor layer 120 may have different percentages of germanium atoms to provide etch selectivity. The sacrificial semiconductor layer 115 and the semiconductor layer 120 may comprise any combination of materials that provide desired etch selectivity, desired oxidation rate differences, desired performance characteristics (e.g., materials that maximize current), or combinations thereof.

[0038] Semiconductor layer 120, or a portion thereof, can form the channel of a transistor. In the depicted embodiment, the multilayer stack 110 includes three sacrificial semiconductor layers 115 and three semiconductor layers 120. Thus, the multilayer stack 110 includes three pairs of semiconductor layers disposed over substrate 105, each pair having a corresponding sacrificial semiconductor layer 115 and a corresponding semiconductor layer 120. After processing the multilayer stack 110, this configuration can produce a transistor with three channels. However, in some embodiments, the multilayer stack 110 includes a different number of semiconductor layers 120, depending on, for example, the desired number of channels for the transistor. For example, the multilayer stack 110 may include two to six pairs of semiconductor layers, each pair having a corresponding sacrificial semiconductor layer 115 and a corresponding semiconductor layer 120.

[0039] After patterning, the multilayer stack 110 includes a semiconductor layer stack (i.e., sacrificial semiconductor layer 115 and semiconductor layer 120) disposed above a mesa 105' (also referred to as a substrate extension, substrate fin portion, fin portion, protrusion, etched substrate portion, etc.). The multilayer stack 110 may be referred to as a fin, fin structure, fin element, active fin region, active region, etc. In some embodiments, as depicted, the mesa 105' may be considered as part of the multilayer stack 110. The multilayer stack 110 extends substantially along the x-direction and has a length along the x-direction, a width along the y-direction, and a height along the z-direction. In some embodiments, photolithography and / or etching processes are performed to pattern the sacrificial semiconductor layer 115, semiconductor layer 120, and substrate 105 to form the multilayer stack 110. In some embodiments, the multilayer stack 110 is formed by multiple patterning processes, such as dual patterning lithography (DPL) processes (e.g., lithography-etch-lithography-etch (LELE) processes, self-aligned dual patterning (SADP) processes, spacer-dielectric (SID) processes, other dual patterning processes, or combinations thereof), triple patterning processes (e.g., lithography-etch-lithography-etch-lithography-etch (LELELE) processes, self-aligned triple patterning (SATP) processes, other triple patterning processes, or combinations thereof), other multiple patterning processes (e.g., self-aligned quadruple patterning (SAQP) processes), or combinations thereof. In some embodiments, directional self-assembly (DSA) technology is employed. In some embodiments, the multilayer stack 110 is formed by a fin manufacturing process.

[0040] The substrate isolation structure 125 may be formed adjacent to and around the lower portion of the multilayer stack 110 (e.g., its mesa 105') and surrounding the lower portion of the multilayer stack 110, and the multilayer stack 110 may be separated from other multilayer stacks and / or other device regions by the substrate isolation structure 125. The substrate isolation structure 125 may electrically isolate active device regions (e.g., multilayer stack 110) from other device regions (such as other multilayer stacks). The substrate isolation structure 125 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (including silicon, oxygen, nitrogen, carbon, other suitable isolation components, or combinations thereof) or combinations thereof. The substrate isolation structure 125 may have a multilayer structure. For example, the substrate isolation structure 125 may include a bulk dielectric (e.g., an oxide layer) located above a dielectric liner (e.g., silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, or combinations thereof). In another example, the substrate isolation structure 125 may include a bulk dielectric located above a doped liner, such as a borosilicate glass (BSG) liner and / or a phosphosilicate glass (PSG) liner. The dimensions and / or characteristics of the substrate isolation structure 125 may be configured to provide a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, a localized oxidation of silicon (LOCOS) structure, other suitable isolation structures, or combinations thereof.

[0041] refer to Figure 4A and Figure 4B Gate structures 130 may be formed over the channel region (C) of the active region 122 and between the corresponding source / drain regions (S / D) of the active region 122. Each gate structure 130 may include a corresponding dummy gate stack 132 and a corresponding gate spacer 134. The dummy gate stack 132 extends longitudinally in a direction different from (e.g., orthogonal to) the longitudinal direction of the multilayer stack 110. For example, the dummy gate stack 132 extends along the y-direction, having a length along the y-direction, a width along the x-direction, and a height along the z-direction. The dummy gate stacks 132 may extend substantially parallel to each other. Figure 4A In a cross-sectional view (e.g., along the gate width direction), the dummy gate stack 132 is disposed on top of the respective channel region, and the dummy gate stack 132 is disposed between the respective source / drain regions. In a cross-sectional view along the gate longitudinal direction, the dummy gate stack 132 may enclose the respective channel region (e.g., disposed above its top and sidewalls), and the dummy gate stack 132 may be disposed above the top of the substrate isolation structure 125.

[0042] Each dummy gate stack 132 may include a dummy gate 136 and a hard mask 138. In some embodiments, the dummy gate 136 includes a dummy gate dielectric and a dummy gate electrode. The dummy gate dielectric includes a dielectric material, such as silicon oxide and / or other suitable dielectric materials. The dummy gate electrode includes a suitable dummy gate material, such as polysilicon. In some embodiments, forming the dummy gate stack 132 includes depositing a dummy gate dielectric layer over a multilayer stack 110, depositing a dummy gate electrode layer over the dummy gate dielectric layer, and depositing a hard mask layer over the dummy gate electrode layer. One or more photolithography and etching processes may then be performed to pattern the hard mask layer, the dummy gate electrode layer, and the dummy gate dielectric layer, and, as described, the remaining portions of the hard mask layer, the dummy gate electrode layer, and the dummy gate dielectric layer may respectively form the dummy gate dielectric, the dummy gate electrode, and the hard mask of the dummy gate stack 132.

[0043] Then, gate spacers 134 are formed adjacent to and along the sidewalls of the dummy gate stack 132. In some embodiments, such as Figure 4B As depicted, fin spacers 135 are formed adjacent to and along the sidewalls of the multilayer stack 110 in the source / drain regions. Gate spacers 134 and fin spacers 135 can be formed by any suitable process, and in some embodiments, gate spacers 134 and fin spacers 135 are formed simultaneously. Gate spacers 134 and fin spacers 135 comprise a dielectric material, which may include silicon, oxygen, carbon, nitrogen, other suitable dielectric components, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonoxynitride, silicon carbonoxynitride, silicon carbonitride, or combinations thereof). In some embodiments, gate spacers 134 and / or fin spacers 135 have a multilayer structure, such as two or more dielectric layers with different compositions. In some embodiments, gate spacers 134 include more than one set of spacers, such as sealing spacers, offset spacers, sacrificial spacers, dummy spacers, main spacers, or combinations thereof. In such embodiments, the sets of spacers may have different compositions.

[0044] refer to Figure 5A and Figure 5BSource / drain etching removes portions of the multilayer stack 110 not covered by the gate structure 130, thereby forming a source / drain recess (trench) 140. For example, source / drain etching removes the semiconductor layer 120 and the sacrificial semiconductor layer 115 in the source / drain region, thereby exposing the mesas 105' therein. Source / drain etching may also remove some (but not all) of the mesas 105' in the source / drain region, such that the source / drain recess 140 extends into the mesas 105' but does not penetrate the mesas 105'. After source / drain etching, the sacrificial semiconductor layer 115, the semiconductor layer 120, and the protrusion formed by the mesas 105' (hereinafter referred to as mesas 105P') remain in the channel region, and the source / drain recess 140 exposes the sidewalls of the sacrificial semiconductor layer 115, the semiconductor layer 120, and the mesas 105P' remaining in the channel region. Source / drain etching is dry etching, wet etching, other suitable etching, or a combination thereof. In some embodiments, source / drain etching is a multi-step etching process that may use etchants alternately to remove the sacrificial semiconductor layer 115 and the semiconductor layer 120 individually and alternately. In some embodiments, source / drain etching parameters (e.g., the etchant) are adjusted to selectively remove semiconductor material (e.g., semiconductor layer 120, sacrificial semiconductor layer 115, and mesa 105') while neglecting (or even not removing) dielectric material (e.g., dummy gate stack 132, gate spacer 134, fin spacer 135, substrate isolation structure 125, etc.).

[0045] refer to Figures 6A to 8A and Figures 6B to 8B The sacrificial semiconductor layer 115 is replaced with a sacrificial oxide layer 146. (See reference.) Figure 6A and Figure 6BThe etching process selectively removes the sacrificial semiconductor layer 115 exposed by the source / drain trench 140, thereby forming a gap 144 in the channel region. The etching process can selectively remove the sacrificial semiconductor layer 115 relative to the substrate 105, semiconductor layer 120, dummy gate stack 132 (e.g., its hard mask 138), gate spacers 134, fin spacers 135, or combinations thereof. In other words, the etching process removes the sacrificial semiconductor layer 115 while potentially neglecting (or even not removing) the substrate 105, semiconductor layer 120, dummy gate stack 132 (e.g., its hard mask), gate spacers 134, fin spacers 135, or combinations thereof. In some embodiments, an etchant is selected for the etching process that etches silicon germanium (e.g., the sacrificial semiconductor layer 115) at a higher rate than silicon (e.g., semiconductor layer 120 and mesa 105') and dielectric material (e.g., gate spacers 134, fin spacers 135, and the hard mask 138 of the dummy gate stack 132). The etching process is dry etching, wet etching, other suitable etching, or a combination thereof. In some embodiments, an oxidation process may be performed prior to the etching process to convert the sacrificial semiconductor layer 115 into a semiconductor oxide layer (e.g., a silicon germanium oxide layer). In such embodiments, the etching process removes the semiconductor oxide layer to form gaps 144.

[0046] After the sacrificial semiconductor layer 115 is removed, the semiconductor layer 120 remaining in the channel region is suspended above the mesa 105P'. In the depicted embodiment, each channel region has three suspended semiconductor layers 120, hereinafter referred to as channel layers 120'. The channel layers 120' are stacked vertically along the z-direction, and the channel layers 120' can provide three channels through which current can flow between the corresponding subsequently formed source / drain electrodes. In some embodiments, after the sacrificial semiconductor layer 115 is removed, an etching process can be performed to modify the profile of the channel layers 120' to provide its target size and / or target shape. For example, the etching process can provide the channel layers 120' with a cylindrical profile (e.g., nanowire), a rectangular profile (e.g., nanorod), a sheet profile (e.g., nanosheet), or any other suitable shape profile. In some embodiments, the channel layers 120' have nanoscale dimensions and may be referred to as "nanostructures". In some embodiments, the channel layers 120' have subnanoscale dimensions and / or other suitable dimensions.

[0047] refer to Figure 7A (and Figure 7B )and Figure 8A (and Figure 8BA sacrificial oxide layer 146 is formed in the gap 144. The sacrificial oxide layer 146 comprises oxygen and silicon, carbon, nitrogen, other suitable components, or combinations thereof. For example, the sacrificial oxide layer 146 comprises oxygen and silicon, and the sacrificial oxide layer 146 is a silicon oxide layer. In some embodiments, by depositing the oxide layer 146' (e.g., ...) over the device 100... Figure 7A and Figure 7B ) and etching oxide layer 146', such that oxide layer 146' is removed from the source / drain region of device 100 rather than the channel region (e.g., Figure 8A and Figure 8B To form the sacrificial oxide layer 146. (Reference) Figure 7A and Figure 7B The deposited oxide layer 146' fills gaps 144, partially fills source / drain trenches 140, and linings source / drain trenches 140. The deposited oxide layer 146' may also be disposed over gate structure 130, substrate isolation structure 125, fin spacers 135, other components of device 100, or combinations thereof. The oxide layer 146' is formed by flowable chemical vapor deposition (FCVD), atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), other deposition processes, or combinations thereof. In some embodiments, the sacrificial oxide layer 146 has a multilayer structure, such as a first oxide layer and a second oxide layer. The first oxide layer and the second oxide layer may be formed from the same material (e.g., silicon oxide) but by different deposition processes. For example, the first oxide layer may be formed by ALD, and the second oxide layer may be formed over the first oxide layer by FCVD. In some embodiments, the first oxide layer and the second oxide layer are formed from different oxide materials by the same type of deposition process or different types of deposition processes.

[0048] refer to Figure 8A and Figure 8BThe etching process removes exposed portions of the oxide layer 146' (e.g., those not filling gaps 144). For example, the etching process may remove portions of the oxide layer 146' disposed on the sidewalls of the channel layer 120', the sidewalls of the mesa 105P', the surface of the mesa 105' forming the bottom of the source / drain recess 140, the top and sidewalls of the fin spacer 135, the top and sidewalls of the gate spacer 134, the top of the dummy gate stack 132, and the top of the substrate isolation structure 125. The remaining portions of the oxide layer 146' provide a sacrificial oxide layer 146 in the channel region. The etching process selectively removes the oxide layer 146' relative to the substrate 105, the channel layer 120', the dummy gate stack 132 (e.g., its hard mask 138), the gate spacer 134, the fin spacer 135, the substrate isolation structure 125, or combinations thereof. In other words, the etching process removes the oxide layer 146' while potentially neglecting (or even not removing) the substrate 105, channel layer 120', dummy gate stack 132, gate spacer 134, fin spacer 135, substrate isolation structure 125, or combinations thereof. In some embodiments, an etchant is selected that etches the oxide material (e.g., oxide layer 146') at a higher rate than silicon (e.g., channel layer 120' and mesa 105') and a dielectric material different from the oxide material (e.g., gate spacer 134, fin spacer 135, hard mask 138, etc.). The etching process is dry etching, wet etching, other suitable etching, or combinations thereof.

[0049] refer to Figure 9A and Figure 9B An etching process (e.g., anisotropic etching) laterally recesses the sacrificial oxide layer 146 to form a notch 148 beneath the gate structure 130 (e.g., beneath its gate spacer 134). For example, the etching process may laterally etch (e.g., along the x and / or y directions) the sacrificial oxide layer 146 to reduce its length along the x direction, such that the length of the sacrificial oxide layer 146 is less than the length of the channel layer 120'. The sacrificial oxide layer 146 can be removed from the ends of the channel layer 120', thereby exposing the top and bottom of the ends of the channel layer 120'. In some embodiments, the notch 148 extends laterally beneath the dummy gate stack 132 (e.g., along the x direction). In some embodiments, the etching process may recess the substrate isolation structure 125. In such embodiments, the substrate isolation structure 125 may have a curved (e.g., concave) top surface.

[0050] refer to Figure 10A and Figure 10BAn internal spacer 149 is formed in the notch 148, and the remaining portion of the sacrificial oxide layer 146 is disposed between the respective internal spacers 149. The internal spacers 149 may replace the ends of the sacrificial oxide layer 146. The internal spacers 149 are disposed below the gate spacer 134 along the sidewalls of the sacrificial oxide layer 146. In addition, the internal spacers 149 are disposed between the ends of the respective semiconductor layers 120, and the bottom internal spacers 149 are disposed between the ends of the respective bottom semiconductor layer 120 and the respective mesa 105P'. The internal spacers 149 can be formed by internal spacer deposition and internal spacer etching. An internal spacer deposition layer is formed over the device 100, and the internal spacer layer at least partially fills the notch 148. In some embodiments, a single deposition process is performed to form the internal spacer layer that fills the notch 148. In some embodiments, the internal spacer 149 has a multilayer structure, and the internal spacer deposition includes more than one deposition process to form multiple internal spacer layers, such as a first deposition process forming a first internal spacer sublayer and a second deposition process forming a second internal spacer sublayer. The first internal spacer sublayer partially fills the notch 148, and the second internal spacer sublayer may partially or completely fill the notch 148. The composition of the first internal spacer sublayer may be the same as or different from the composition of the second internal spacer sublayer.

[0051] The internal spacer etching can selectively etch the internal spacer layer while ignoring (or even not etching) the channel layer 120', mesa 105P', dummy gate stack 132 (e.g., its hard mask 138), gate spacer 134, fin spacer 135, substrate isolation structure 125, or combinations thereof. The remainder of the internal spacer layer provides internal spacers 149, as described. To achieve the desired etch selectivity, the composition of the internal spacer layer (and therefore internal spacer 149) differs from the composition of the channel layer 120', mesa 105P', dummy gate stack 132, gate spacer 134, fin spacer 135, substrate isolation structure 125, or combinations thereof. In some embodiments, the internal spacer layer includes a dielectric material comprising silicon, oxygen, carbon, nitrogen, other suitable dielectric components, or combinations thereof. For example, the internal spacer layer may be a silicon carbide layer, a silicon carbonitride layer, a silicon carbonitride oxycarbonate layer, a silicon carbon oxide layer, or combinations thereof. Internal spacer etching is dry etching, wet etching, other suitable etching, or a combination thereof. In some embodiments, parameters of internal spacer deposition and / or internal spacer etching are configured and / or adjusted to provide an internal spacer 149 with an air gap. In some embodiments, device 100 does not include an internal spacer 149. In such embodiments, the internal spacer 149 may be omitted. Figure 9A , Figure 9B , Figure 10A and Figure 10BProcessing of associated device 100.

[0052] refer to Figures 11A to 13A and Figures 11B to 13B A source / drain structure 150 is formed in the source / drain recess 140. Each source / drain structure 150 may include an undoped semiconductor layer 152, an insulating layer 154, and a doped semiconductor layer 156. In some embodiments, the doped semiconductor layer 156 has a multilayer structure. For example, each doped semiconductor layer 156 may include a doped semiconductor layer 158 and a doped semiconductor layer 160. In some embodiments, the source / drain structure 150 forms the source / drain of a p-type transistor, and the source / drain structure 150 may include a semiconductor material doped with a p-type dopant (e.g., boron, gallium, other p-type dopants, or combinations thereof). In some embodiments, the source / drain structure 150 forms the source / drain of an n-type transistor, and the source / drain structure 150 may include a semiconductor material doped with an n-type dopant (e.g., carbon, phosphorus, arsenic, antimony, other n-type dopants, or combinations thereof). As used herein, source / drain region, source / drain structure, source / drain component, epitaxial source / drain, epitaxial source / drain component, etc., can refer to the source of device 100, the drain of device 100, or the source and / or drain of multiple devices (including device 100).

[0053] refer to Figure 11A and Figure 11B A semiconductor layer, such as an undoped semiconductor layer 152, can be formed in the source / drain trench 140. The undoped semiconductor layer 152 can be formed in the bottom of the source / drain trench 140. The undoped semiconductor layer 152 is disposed below (e.g., below the bottom of) the bottommost channel layer 120'. In the depicted embodiment, the undoped semiconductor layer 152 extends slightly above the top surface of the mesa 105P'. In some embodiments, the top surface of the undoped semiconductor layer 152 is substantially flush with or below the top surface of the mesa 105P' (i.e., the undoped semiconductor layer 152 does not extend beyond the top surface of the mesa 105P'). The undoped semiconductor layer 152 is free of dopants (i.e., substantially free of n-type and p-type dopants). For example, no intentional doping is performed when the undoped semiconductor layer 152 is formed. The undoped semiconductor layer 152 can provide a high-resistance path at the bottom of the source / drain, thereby suppressing leakage current into the substrate 105 / mesa 105P'. The undoped semiconductor layer 152 includes silicon, germanium, silicon-germanium, other suitable semiconductor materials, or combinations thereof. In the depicted embodiment, the undoped semiconductor layer 152 is a dopant-free silicon-germanium layer. In some embodiments, the undoped semiconductor layer 152 is a dopant-free silicon layer. In some embodiments, the dopant concentration is less than about 5 x 10⁻⁶. 18cm -3 (For example, approximately 1 x 10) 18 cm -3 To approximately 5 x 10 18 cm -3 Semiconductor materials (e.g., SiGe) can be considered as undoped and / or unintentionally doped (UID).

[0054] An undoped semiconductor layer 152 may be deposited on and / or grown from a substrate 105, mesas 105', mesas 105P', or combinations thereof. In some embodiments, the undoped semiconductor layer 152 is formed by a selective epitaxial growth (SEG) process, which selectively deposits / grows a semiconductor material (e.g., silicon-germanium) on / from an exposed semiconductor surface. Therefore, the undoped semiconductor layer 152 may be referred to as an undoped epitaxial layer. The SEG process may utilize chemical vapor deposition (CVD) techniques (e.g., vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), low-pressure CVD (LPCVD), PECVD, etc.), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. In some embodiments, an undoped semiconductor layer 152 is formed by a bottom-up deposition process, such that semiconductor material is deposited on the mesa 105P', mesa 105', and / or substrate 105 (i.e., at the bottom of the source / drain trench 140), while semiconductor material deposition on the channel layer 120' is minimal (or even nonexistent). In some embodiments, an etching process may be performed after the bottom-up deposition process to remove any semiconductor material that may have formed on the channel layer 120'. Post-deposition etching may be dry etching, wet etching, other suitable etching, or a combination thereof.

[0055] refer to Figure 12A and Figure 12B An insulating layer 154 may be formed in a source / drain trench 140 above an undoped semiconductor layer 152. The insulating layer 154 partially fills the source / drain trench 140 and is disposed below (e.g., below) the bottommost channel layer 120'. The insulating layer 154 may be disposed on the bottommost internal spacer 149 and / or mesas 105P', as depicted. The insulating layer 154 includes an electrically insulating material, such as a dielectric material, which can reduce undesirable leakage currents, such as currents that might undesirably flow between the doped semiconductor layers 156 through the mesas 105P'. For example, see reference... Figure 26ADevices with source / drain structures (with bottom source / drain insulation, e.g., insulating layer 154) (corresponding to lines K1 and K2) have been observed to exhibit smaller body leakage currents (IL1) than devices with source / drain structures (without bottom source / drain insulation, e.g., without insulating layer 154) (corresponding to lines L1 and L2). boff Additionally, see reference. Figure 26B Furthermore, it has been observed that devices with source / drain structures (with bottom source / drain insulation) (corresponding to lines M1 and M2) exhibit smaller capacitance (C) than devices with source / drain structures (without bottom source / drain insulation, corresponding to lines N1 and N2). eff In some embodiments, insulating layer 154 comprises a silicon-containing dielectric material, such as silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, silicon carbon oxynitride, other silicon-containing dielectric materials (which may include silicon and nitrogen, carbon, oxygen, other suitable dielectric components, or combinations thereof) or combinations thereof. For example, in the depicted embodiment, insulating layer 154 is a silicon nitride layer. In some embodiments, insulating layer 154 comprises a metal-containing dielectric material, such as a metal oxide material and / or a metal nitride material.

[0056] An insulating layer 154 can be formed by depositing an insulating material over device 100 (e.g., by CVD, physical vapor deposition (PVD), other suitable processes, or combinations thereof) and etching the insulating material such that the remainder of the insulating material is disposed over the undoped semiconductor layer 152. The deposited insulating material can be disposed on the top of the gate structure 130 (e.g., the top of the gate spacer 134 and the dummy gate stack 132), the sidewalls of the gate structure 130 (e.g., the gate spacer 134), the sidewalls of the channel layer 120', the sidewalls of the internal spacer 149, and the sidewalls of the mesa 105P'. In some embodiments, due to the characteristics of the deposition process, the thickness of the insulating material over the horizontally oriented surfaces (e.g., the top of the undoped semiconductor layer 152 and the top of the gate structure 130) can be greater than the thickness of the insulating material over the vertically oriented surfaces (e.g., the sidewalls of the gate structure 130, the sidewalls of the channel layer 120', and the sidewalls of the internal spacer 149). Therefore, etching parameters can be adjusted to remove vertically oriented portions of the insulating material, such as portions on the sidewalls of the gate structure 130, the channel layer 120', and the internal spacer 149. In such embodiments, due to the etch load effect, etching can also remove horizontally oriented portions of the insulating material on the top of the gate structure 130, but not (or at least minimally) remove horizontally oriented and / or vertically oriented portions of the insulating material in the bottom of the source / drain trench 140 (such as those disposed on the undoped semiconductor layer 152) (i.e., the etching process can thin these portions). In some embodiments, the deposited insulating material fills the source / drain trench 140, and etching trenches the insulating material down to at least the bottom sacrificial oxide layer 146. Etching can be dry etching, wet etching, other suitable etching, or combinations thereof.

[0057] refer to Figure 13A and Figure 13BA doped semiconductor layer 156 may be formed in the source / drain recess 140 above the insulating layer 154 and / or the undoped semiconductor layer 152. The doped semiconductor layer 156 fills the remaining portion of the source / drain recess 140 and is coupled to the edge / end of the channel layer 120'. In the depicted embodiment, the doped semiconductor layer 156 includes a doped semiconductor layer 158 and a doped semiconductor layer 160. The doped semiconductor layer 158 may be formed above the channel layer 120' and partially fill the source / drain recess 140, and the doped semiconductor layer 160 may be formed above the doped semiconductor layer 158 and / or the insulating layer 154 and fill the remaining portion of the source / drain recess 140. The doped semiconductor layer 158 is located between the channel layer 120' and the doped semiconductor layer 160, and the insulating layer 154 is located between the doped semiconductor layer 160 and the undoped epitaxial layer 152. In the depicted embodiments, the doped semiconductor layer 158 is discontinuous and formed of discrete and separate portions, each portion disposed at an end of a corresponding channel layer 120' (i.e., portions of the doped semiconductor layer 158 disposed on adjacent channel layers 120' are not connected to each other). In such embodiments, a doped semiconductor layer 160 may wrap around the doped semiconductor layer 158, and / or the doped semiconductor layer 160 may extend to and be disposed on the inner spacer 149. In some embodiments, one or more discrete, separate portions of the doped semiconductor layer 158 may wrap around a corresponding channel layer 120' such that the discrete, separate portions are formed above the top and / or bottom of the corresponding channel layer 120'. In some embodiments, the discrete, separate portions extend over and / or into the inner spacer 149. In some embodiments, one or more discrete, separate portions of the doped semiconductor layer 158 are connected. In such embodiments, portions of the doped semiconductor layer 160 may be separated from the inner spacer 149 by the doped semiconductor layer 158. In some embodiments, the doped semiconductor layer 158 encloses the doped semiconductor layer 160, and the doped semiconductor layer 158 is also located between the internal spacer 149 and the doped semiconductor layer 160.

[0058] Doped semiconductor layers 158 and 160 comprise silicon, germanium, silicon-germanium, other suitable semiconductor materials, or combinations thereof. In some embodiments, doped semiconductor layers 158 and 160 comprise the same semiconductor material with different concentrations. For example, doped semiconductor layers 158 and 160 may comprise silicon-germanium and p-type dopants (e.g., boron and / or gallium), but with different germanium concentrations and / or different p-type dopant concentrations, such as in a source / drain structure 150 belonging to a p-type transistor. In this example, doped semiconductor layer 158 may have a smaller germanium concentration (e.g., Ge%) and / or a smaller p-type dopant concentration (e.g., B%) than doped semiconductor layer 160. In other words, doped semiconductor layer 160 may be a heavily doped semiconductor layer, while doped semiconductor layer 158 may be a lightly doped semiconductor layer. In another example, doped semiconductor layer 158 and doped semiconductor layer 160 may comprise silicon and an n-type dopant (e.g., phosphorus and / or arsenic), but with different n-type dopant concentrations, such as in which the source / drain structure 150 is an n-type transistor. In this example, doped semiconductor layer 158 may have a smaller n-type dopant concentration (e.g., P%) than doped semiconductor layer 160. In some embodiments, doped semiconductor layer 158 and doped semiconductor layer 160 are different semiconductor materials with the same or different compositional concentrations. In some embodiments, doped semiconductor layer 156 includes a material and / or dopant that provides compressive stress in channel layer 120', such as in which the source / drain structure 150 is a p-type transistor. In some embodiments, doped semiconductor layer 156 includes a material and / or dopant that provides tensile stress in channel layer 120', such as in which the source / drain structure 150 is an n-type transistor.

[0059] A doped semiconductor layer 158 may be deposited on and / or grown from the channel layer 120', and a doped semiconductor layer 160 may be deposited on and / or grown from the doped semiconductor layer 158. In some embodiments, the doped semiconductor layer 158 and the doped semiconductor layer 160 are formed by a corresponding SEG process, which may employ CVD deposition techniques (e.g., VPE, UHV-CVD, LPCVD, PECVD, etc.), molecular beam epitaxy, other suitable SEG processes, or combinations thereof. The SEG process may use gaseous and / or liquid precursors that interact with components of the channel layer 120', the doped semiconductor layer 158, or combinations thereof. Epitaxial growth / deposition conditions (such as those described herein) are adjusted to selectively deposit (grow) semiconductor materials (e.g., silicon-germanium) on semiconductor surfaces (e.g., channel layer 120' and / or doped semiconductor layer 158) while restricting (or preventing) the growth of semiconductor materials from dielectric surfaces and / or non-semiconductor surfaces (e.g., internal spacers 149, dummy gate stacks 132, gate spacers 134, fin spacers 135, substrate isolation structures 125, or combinations thereof). In some embodiments, doped semiconductor layers 158 and / or doped semiconductor layers 160 are doped during deposition (i.e., in-situ doping), such as by adding dopants to the source material of a SEG process. In some embodiments, doped semiconductor layers 158 and / or doped semiconductor layers 160 are doped after deposition, such as by an ion implantation process. In some embodiments, annealing is performed to activate the dopants in doped semiconductor layers 158, 160, other source / drain regions / parts (such as source / drain junction implantation), or combinations thereof. The source / drain structure 150 can be fabricated to provide source / drain structures 150 with various dimensions. For example, in some embodiments, the width of the source / drain structure 150 (e.g., along the y-direction) differs from the thickness of the source / drain structure 150 (e.g., along the z-direction). In some embodiments, this dimensional difference is provided to the doped semiconductor layer 160 (e.g., its width may be greater than its thickness).

[0060] refer to Figure 14A and Figure 14BFabrication of device 100 may include forming a dielectric layer 170 over source / drain structures 150. The dielectric layer 170 may fill spaces between adjacent gate structures 130, such as spaces between their gate spacers and spaces between adjacent source / drain structures 150. Forming the dielectric layer 170 may include depositing a contact etch stop layer (CESL) 172, depositing an interlayer dielectric (ILD) layer 174 over the CESL 172, and performing CMP and / or other planarization processes until reaching the dummy gate stack 132 (e.g., its hard mask 138). In some embodiments, the planarization process may partially remove the dummy gate stack 132, such as its hard mask 138, to expose the underlying dummy (e.g., polysilicon) gate 136. In some embodiments, the planarization process may reduce the height of the dummy gate stack 132 and / or the gate spacers 134.

[0061] ILD layer 174 includes a dielectric material, including, for example, silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, oxides formed from tetraethyl orthosilicate (TEOS), BSG, PSG, borosilicate glass, fluorosilicate glass, degel, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutenyl (BCB) dielectric material, polyimide, other suitable dielectric materials, or combinations thereof. In some embodiments, ILD layer 174 includes a low-k dielectric material whose dielectric constant is less than that of silicon dioxide (e.g., k < 3.9). In some embodiments, ILD layer 174 includes a dielectric material with a dielectric constant less than about 2.5 (i.e., an extremely low-k (ELK) dielectric material), such as porous silicon dioxide, silicon carbide, carbon-doped oxides (e.g., SiCOH-based materials having, for example, Si-CH3 bonds), or combinations thereof, each dielectric material being tuned / configured to exhibit a dielectric constant less than about 2.5. CESL 172 includes materials different from those of ILD layer 174, such as dielectric materials different from those of ILD layer 174. For example, if ILD layer 174 includes a low-k dielectric material containing silicon and oxygen, CESL 172 may include silicon and nitrogen, such as silicon nitride or silicon oxynitride. ILD layer 174 and / or CESL 172 may have a multilayer structure and / or include multiple dielectric materials.

[0062] refer to Figures 15A to 17A and Figures 15B to 17BThe fabrication of device 100 may include a gate replacement process that replaces the dummy gate stack 132 and the sacrificial oxide layer 146 with a gate stack 180. The gate stack 180 (also referred to as a high-k / metal gate) is disposed between corresponding gate spacers 134, between corresponding internal spacers 149, between corresponding channel layers 120', and between corresponding channel layers 120' and corresponding mesa 105P'. Each gate stack 180 may include a corresponding gate dielectric 182 and a corresponding gate electrode 184. In the depicted embodiment, where device 100 includes a GAA transistor, the gate stack 180 may, for example, surround and bond the corresponding channel layer 120' in the YZ plane (see example...). Figure 17C In some embodiments, the gate stack 180 may wrap around and / or partially surround the respective channel layer 120' (i.e., disposed on at least both sides thereof).

[0063] refer to Figure 15A and Figure 15B The dummy gate stack 132 is removed from the gate structure 130 to form a gate opening 175. The gate opening 175 exposes a channel region including a channel layer 120' and a sacrificial oxide layer 146. In some embodiments, the etching process selectively removes the dummy gate stack 132 (e.g., a polysilicon gate) while ignoring (or even not removing) the dielectric layer 170, gate spacer 134, internal spacer 149, sacrificial oxide layer 146, semiconductor layer 120, channel layer 120', or combinations thereof. The etching process is dry etching, wet etching, other suitable etching processes, or combinations thereof. In some embodiments, the etching process uses a patterned mask layer as an etching mask, wherein the patterned mask layer covers the dielectric layer 170 and / or the gate spacer 134. In some embodiments, the dummy gate dielectric layer (e.g., the dummy oxide layer) of the dummy gate stack 132 is retained.

[0064] refer to Figure 16A and Figure 16BThe etch process removes the sacrificial oxide layer 146 from the channel region, thereby forming a gap (opening) 178 that exposes the channel layer 120'. Therefore, the gate opening 175 extends between the channel layers 120' and between the channel layers 120' and the mesa 105P'. In some embodiments, the etch process selectively removes the sacrificial oxide layer 146 relative to the mesa 105P', the channel layer 120', the gate spacer 134, the internal spacer 149, the dielectric layer 170, or combinations thereof. In other words, the etch process removes the sacrificial oxide layer 146 while potentially neglecting (or even not removing) the mesa 105P', the channel layer 120', the gate spacer 134, the internal spacer 149, the dielectric layer 170, or combinations thereof. For example, an etchant is selected for the etching process that etches the oxide material (e.g., sacrificial oxide layer 146) at a higher rate than silicon (e.g., channel layer 120' and mesa 105P') and dielectric materials with a different composition than the oxide material (e.g., gate spacer 134, internal spacer 149, CESL 172, ILD layer 174, etc.) (i.e., the etchant has high etch selectivity for the oxide material). The etching process is dry etching, wet etching, other suitable etching, or a combination thereof. In some embodiments, the etching process removes any remaining portions of the dummy gate stack 132, such as its dummy oxide layer.

[0065] refer to Figures 17A to 17C Gate stack 180 is formed in gate opening 175 and / or gap 178. For example, gate dielectric 182 is formed in gate opening 175 and gap 178, and partially fills gate opening 175 and / or gap 178. Gate dielectric 182 is disposed on a corresponding channel layer 120', a corresponding internal spacer 149, a corresponding gate spacer 134, a substrate isolation structure 125, or a combination thereof. Gate dielectric 182 includes at least one dielectric layer, such as an interface layer and / or a high-k dielectric layer. The interface layer includes a dielectric material, such as SiO2, SiGeO x High-k dielectric layers consist of HfSiO, SiON, other dielectric materials, or combinations thereof. The interface layer is formed through thermal oxidation, chemical oxidation, ALD, CVD, other processes, or combinations thereof. High-k dielectric layers include high-k dielectric materials, which are typically dielectric materials with a dielectric constant greater than that of silicon dioxide, such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, and HfAlO. xThe high-k dielectric layer comprises ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, LaO3, La2O3, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3, (Ba,Sr)TiO3 (BST), HfO2-Al2O3, other high-k dielectric materials, or combinations thereof. The high-k dielectric layer is formed by ALD, CVD, PVD, oxide-based deposition processes, other processes, or combinations thereof. In some embodiments, the high-k dielectric layer comprises a hafnium-based oxide (e.g., HfO2) layer. In some embodiments, the high-k dielectric layer comprises a zirconium-based oxide (e.g., ZrO2) layer.

[0066] A gate electrode 184 is formed in the gate opening 175 and the gap 178, and fills the remaining portions of the gate opening 175 and the gap 178. The gate electrode 184 is disposed on the gate dielectric 182. The gate electrode 184 includes a conductive layer formed of a conductive material, such as Al, Cu, Ti, Ta, W, Mo, Co, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other conductive materials, or combinations thereof. In some embodiments, the conductive layer includes a work function layer conditioned to have a desired work function (e.g., an n-type work function or a p-type work function). The function layer comprises function metals and / or alloys thereof, such as Ti, Ta, Al, Ag, Mn, Zr, W, Ru, Mo, TiC, TiAl, TiAlC, TiAlSiC, TaC, TaCN, TaSiN, TiSiN, TiN, TaN, TaSN, WN, WCN, ZrSi2, MoSi2, TaSi2, NiSi2, TaAl, TaAlC, TaSiAlC, TiAlN, or combinations thereof. In some embodiments, the conductive layer comprises a body layer located above the gate dielectric and / or the function layer. The body layer may comprise Al, W, Cu, Ti, Ta, TiN, TaN, polysilicon, other suitable metals and / or alloys thereof, or combinations thereof. In some embodiments, the conductive layer comprises a barrier layer located above the function layer and / or the gate dielectric. The barrier layer comprises materials that can prevent diffusion and / or reaction of components between adjacent layers and / or promote adhesion between adjacent layers (such as between the function layer and the body layer). In some embodiments, the barrier layer comprises a metal and nitrogen, such as titanium nitride, tantalum nitride, tungsten nitride, titanium silicon nitride, tantalum silicon nitride, other suitable metal nitrides, or combinations thereof.

[0067] Forming the gate stack 180 may include depositing a gate dielectric material (e.g., an interface layer, a high-k dielectric layer, etc.) that partially fills the gate opening 175 and / or gap 178, depositing a gate electrode material (e.g., a power function layer, a barrier layer, a body layer, etc.) over the gate dielectric material (to fill the remaining portion of the gate opening 175 and / or gap 178), and performing a planarization process (e.g., CMP) to remove portions of the gate dielectric material and / or gate electrode material over the dielectric layer 170. In some embodiments, fabrication of the device 100 may further include etching back the gate stack 180 and forming a hard mask (e.g., a self-aligned cap (SAC) structure) over the etched-back gate stack 180. The SAC structure includes a material different from the dielectric layer 170 and / or the subsequently formed dielectric layer to achieve etch selectivity. In some embodiments, the SAC structure includes silicon and nitrogen and / or carbon, such as silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, silicon carbonitride, silicon carbonitride, other silicon nitrides, other silicon carbides, or combinations thereof. In some embodiments, the SAC structure includes metals and oxygen and / or nitrogen, such as aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, hafnium oxide, aluminum zirconium oxide, other metal oxides, other metal nitrides, or combinations thereof.

[0068] Therefore, device 100 may include at least one transistor T. Transistor T may include a corresponding channel (e.g., channel layer 120'), a source / drain (e.g., source / drain structure 150), and a corresponding gate (e.g., gate stack 180). Gate stack 180 is disposed along the x-direction between the corresponding source / drain (e.g., source / drain structure 150), and an internal spacer 149 is disposed between gate stack 180 and the corresponding source / drain. Additionally, gate stack 180 engages the corresponding channel (e.g., channel layer 120'), and the corresponding channel extends along the x-direction between the corresponding source / drain (e.g., source / drain structure 150). In the depicted embodiment, transistor T is a GAA transistor. Therefore, gate stack 180 may surround its corresponding channel layer, and along the gate longitudinal direction, gate stack 180 may include a gate dielectric (e.g., gate dielectric 182) and a gate electrode (e.g., gate electrode 184) surrounding its corresponding channel. In some embodiments, the gate stack 180 may wrap around and / or partially surround its respective channel layer (i.e., disposed on at least both sides thereof), such as when the transistor T is a forked transistor or other type of multi-gate transistor.

[0069] In the depicted embodiment, transistor T is a p-type transistor. For example, transistor T may include a silicon channel (e.g., channel layer 120' may be a silicon layer) and a silicon-germanium epitaxial source / drain (e.g., doped semiconductor layer 156 may be a silicon-germanium structure). Because transistor T is fabricated using a disposable / pseudo-oxide interposer (e.g., sacrificial oxide layer 146), source / drain structure 150 exhibits improved stress characteristics and / or transistor T exhibits improved performance. For example, since sacrificial semiconductor layer 115 is replaced with sacrificial oxide layer 146 prior to source / drain fabrication, components from the pseudo-interposer (e.g., sacrificial semiconductor layer 115) do not migrate into channel layer 120' during fabrication of source / drain structure 150, such as germanium migration that may occur during thermal processes associated with this fabrication. Reducing and / or preventing the migration of components (e.g., germanium) from the pseudo-interposer can hinder undesirable changes in the stress characteristics of the channel layer 120', such as undesirably introducing tensile stress into the compressive stress channel layer 120', which can adversely affect the performance of the p-type transistor. Therefore, p-type transistors (such as transistor T) fabricated according to the disclosed methods (e.g., employing a sacrificial oxide layer 146) exhibit improved performance, such as lower channel resistance and / or improved stress characteristics (e.g., minimal or no tensile stress). In some cases, p-type transistors fabricated as described herein (i.e., using a pseudo-oxide interposer) with bottom source / drain insulation exhibit lower leakage current, lower parasitic capacitance, lower channel resistance, lower bottom source / drain insulation loss (RO), or combinations thereof, compared to p-type transistors fabricated using a pseudo-semiconductor (e.g., SiGe) interposer with bottom source / drain insulation.

[0070] refer to Figure 18A and Figure 18BFabrication of device 100 may include forming one or more front-side upper source / drain contacts, such as source / drain contacts 190. In some embodiments, forming source / drain contacts 190 includes forming source / source contact openings in dielectric layer 170 to expose corresponding source / drain structures 150, depositing at least one conductive material (e.g., a metallic body material) over dielectric layer 70 (to fill the source / drain contact openings), and performing a planarization process to remove any conductive material disposed on top of dielectric layer 170 and / or on top of gate structure 130. The planarization process may be performed until the gate stack 180 is reached and exposed (or, in some embodiments, a SAC structure located on top of the etched-back gate stack 180). The remaining portion of the conductive material forms a metallic plug and, in some embodiments, one or more liners for the source / drain contacts 190. Conductive materials include tungsten, ruthenium, cobalt, molybdenum, copper, aluminum, titanium, tantalum, iridium, palladium, platinum, nickel, tin, gold, silver, other suitable metals, alloys thereof, or combinations thereof. In some embodiments, a silicide layer is formed over the doped semiconductor layer 160 prior to the deposition of the conductive material. In some embodiments, the conductivity of the silicide layer (which may be referred to as the front (or top) silicide layer) is greater than the conductivity of the doped semiconductor layer 160 and less than the conductivity of the source / drain contact 190.

[0071] The fabrication of device 100 may further include a front-side back-end (BEOL) process to form a metallization layer for a front-side multilayer interconnect (F-MLI) structure. The F-MLI structure can electrically connect devices (e.g., transistors (e.g., transistor T), resistors, capacitors, inductors, etc.), components of devices (e.g., gate and / or source / drain), devices within the F-MLI structure, components of the F-MLI structure, or combinations thereof, such that the devices and / or their components can operate as specified in the design requirements. The metallization layer can route signals between devices and / or their components and / or distribute signals (e.g., clock signals, voltage signals, ground signals, other signals, or combinations thereof) to devices and / or their components. In some embodiments, the metallization layer / layer includes at least one interconnect structure disposed in the insulating layer, such as vias (e.g., source / drain vias 192) and conductive lines (e.g., metal lines 194) disposed in the dielectric layers (e.g., CESL 195, ILD layer 196, CESL 197, and ILD layer 198), wherein the vias (e.g., source / drain vias 192) connect the conductive lines (e.g., metal lines 194) to the underlying device layer interconnects (e.g., source / drain contacts 190) or the metal lines of interconnects in different metallization layers.

[0072] In some embodiments, forming the source / drain via 192 includes forming a dielectric layer (e.g., CESL 195 and ILD layer 196, which may be configured and formed similarly to CESL 172 and ILD layer 174, respectively) over a dielectric layer 170, forming source / drain via openings in the dielectric layer (exposing source / drain contacts 190), depositing at least one conductive material (e.g., a metallic body material) over the dielectric layer (filling the source / drain via openings), and performing a planarization process to remove any conductive material disposed on top of the dielectric layer. The planarization process may be performed until the ILD layer 196 is reached and exposed. The remaining portion of the conductive material forms a metallic plug and, in some embodiments, one or more liners forming the source / drain via 192. In some embodiments, forming the metal liner 194 includes forming a dielectric layer (e.g., CESL 197 and ILD layers 198, which may be configured and formed similarly to CESL 195 and ILD layers 196, respectively) over the ILD layer 196, patterning the dielectric layer to form openings therein (such as openings in which source / drain vias 192 are exposed), depositing at least one conductive material (e.g., a metallic body material) over the dielectric layer (to fill the openings), and performing a planarization process to remove any conductive material disposed on top of the dielectric layer. The planarization process may be performed until the ILD layer 198 is reached and exposed. The remaining portion of the conductive material forms a metal plug and, in some embodiments, one or more liners for the metal line 194. The conductive materials for the source / drain vias 192 and / or the metal line 194 include tungsten, ruthenium, cobalt, molybdenum, copper, aluminum, titanium, tantalum, iridium, palladium, platinum, nickel, tin, gold, silver, other suitable metals, alloys thereof, or combinations thereof. In some embodiments, the source / drain via 192 and the metal line 194 are formed using a dual damascene process. In such an embodiment, CESL 197 and ILD layer 198 can be formed over ILD layer 196 before forming the source / drain via openings, the metal line openings can expose the source / drain via openings, and conductive materials for the source / drain via 192 and metal line 194 can be deposited simultaneously.

[0073] The metal lines of the first metallization layer (e.g., metal line 194) can be collectively referred to as the metal-1 (M1) layer, and are individually referred to as M1 metal lines. Vias of the first metallization layer (e.g., source / drain via 192) can physically and / or electrically connect local device layer contacts (e.g., drain / source contacts 190) to the metal lines (e.g., metal line 194). In such embodiments, the vias of the first metallization layer can be collectively referred to as the via-zero (V0) layer (and are individually referred to as V0 vias). In such embodiments, the V0 layer can be the bottommost via layer of the F-MLI structure. Additional metallization layers (layers) of the F-MLI structure can be formed above the first metallization layer. For example, the BEOL process may include forming a second metallization layer (i.e., metal layer 2 (M2) and via layer 1 (V1)), a third metallization layer (i.e., metal layer 3 (M3) and via layer 2 (V2)), a fourth metallization layer (i.e., metal layer 4 (M4) and via layer 3 (V3)), a fifth metallization layer (i.e., metal layer 5 (M5) and via layer 4 (V4)), a sixth metallization layer (i.e., metal layer 6 (M6) and via layer 5 (V5)), and a seventh metallization layer (i.e., metal layer 7 (M7) and via layer 6 (V6)) to an X metallization layer (i.e., metal layer X (MX) and via layer Y (VY)) above the first metallization layer, where X is the total number of patterned metal lines of the MLI component and Y is the total number of patterned via layers of the MLI component. Each metallization layer may include patterned metal lines and patterned via layers, configured to provide at least one BEOL interconnect structure disposed in an insulating layer. Depending on design requirements, the F-MLI structure can have any number of metal layers, via layers, dielectric layers, or combinations thereof. In some embodiments, depending on design requirements, the metal layers, via layers, dielectric layers, or combinations thereof can be configured to have various dimensions. For example, in some embodiments, the thickness of ILD layer 196 (which may be the bottommost ILD layer of the F-MLI structure and / or its first metallization layer) is greater than the thickness of ILD layer 198 (and / or other ILD layers in the metallization layers above ILD layer 196).

[0074] refer to Figure 19A and Figure 19BFabrication of device 100 may include forming one or more backside lower source / drain contacts, such as source / drain contacts 200. In some embodiments, forming source / drain contacts 200 includes forming source / drain contact openings that expose a corresponding doped semiconductor layer 156 of a corresponding source / drain structure 150 (i.e., removing undoped semiconductor layer 152 and insulating layer 154 when forming source / drain contact openings), depositing at least one conductive material (e.g., a metal body material) over the backside of device 100 (to fill the source / drain contact openings), and performing a planarization process to remove any conductive material disposed over the backside of device 100 (which may be formed by a substrate 105 or a dielectric structure that replaces a portion of the substrate 105 before forming the source / drain contact openings). The remaining portion of the conductive material forms a metal plug and, in some embodiments, one or more liner materials for the source / drain contacts 200. Conductive materials include tungsten, ruthenium, cobalt, molybdenum, copper, aluminum, titanium, tantalum, iridium, palladium, platinum, nickel, tin, gold, silver, other suitable metals, alloys thereof, or combinations thereof. In some embodiments, a silicide layer is formed over the doped semiconductor layer 160 prior to the deposition of the conductive material. In some embodiments, the conductivity of the silicide layer (which may be referred to as the back-side (or bottom) silicide layer) is greater than the conductivity of the doped semiconductor layer 160 and less than the conductivity of the source / drain contact 200. In some embodiments, when the source / drain contact opening is formed, the insulating layer 154 of the corresponding source / drain structure 150 serves as an etch stop layer. In some embodiments, the source / drain contact 200 extends through the undoped semiconductor layer 152 and the insulating layer 154 of the corresponding source / drain structure 150. In some embodiments, the source / drain contact 200 is self-aligned with the source / drain structure 150 (e.g., its doped semiconductor layer 160) because the source / drain contact opening can be formed by removing the undoped semiconductor layer 152 and / or insulating layer 154. In other words, a separate patterning process to define the source / drain contact opening may not be required. In some embodiments, forming the source / drain contact 200 includes flipping the device 100 to facilitate back-side processing. In some embodiments, at least a portion of the substrate 105 is replaced by a dielectric structure such that the source / drain contact 200 is disposed in and / or extends through the dielectric structure. In some embodiments, forming the source / drain contact 200 includes thinning the substrate 105 (e.g., reducing the thickness of the substrate 105 and exposing the back side of the source / drain structure 150).

[0075] This disclosure contemplates various variations of the device 100 that may result when manufactured as described herein. In some embodiments, reference is made to... Figures 20 to 22The source / drain recess 140 may have sloping sidewalls, which can provide channel layers 120', internal spacers 149, gate stacks 180, or combinations thereof with different sizes. Figure 20 In the middle, the source / drain groove 140 is as described above. Figure 5A and Figure 5B The formation, in addition to the source / drain trench 140, includes... Figure 20 Instead of substantially straight sidewalls, the source / drain trench 140 has sloping sidewalls. As a result, the source / drain trench 140 has a tapered width (e.g., decreasing from top to bottom), and the semiconductor layer 120 and sacrificial semiconductor layer 115 retained in the channel region have increasing lengths (e.g., along the x-direction) from the gate structure 130 to the mesa 105P'. For example, the length of the topmost semiconductor layer 120 is less than the length of the middle semiconductor layer 120, and the length of the middle semiconductor layer 120 is less than the length of the bottommost semiconductor layer 120 (i.e., the length of the semiconductor layer 120 increases from the top to the bottom of the multilayer stack). Additionally, the length of the topmost sacrificial semiconductor layer 115 is less than the length of the middle sacrificial semiconductor layer 115, and the length of the middle sacrificial semiconductor layer 115 is less than the length of the bottommost sacrificial semiconductor layer 115. This difference in the length of the sacrificial semiconductor layers 115 can result in different widths (e.g., along the x-direction) for the internal spacers 149 and / or different lengths for the sacrificial oxide layer 146, such as... Figure 21 What is described Figure 21 Reference Figure 10A and Figure 10B The described manufacturing stage corresponds to this. Figure 21 In this configuration, the width of the topmost internal spacer 149 is smaller than the width of the middle internal spacer 149, and the width of the middle internal spacer 149 is smaller than the width of the bottommost internal spacer 149 (i.e., the width of the internal spacers 49 increases from top to bottom). In some embodiments, the width of the topmost internal spacer 149 is about 3.5 nm to about 4 nm, and the width of the bottommost internal spacer 149 is about 4 nm to about 4.5 nm. Additionally, the length of the topmost sacrificial oxide layer 146 is smaller than the length of the middle sacrificial oxide layer 146, and the length of the middle sacrificial oxide layer 146 is smaller than the length of the bottommost sacrificial oxide layer 146 (i.e., the length of the sacrificial oxide layer increases from top to bottom). This difference in the length of the sacrificial oxide layers 146 can result in portions of the gate stack 180 between the internal spacers 149 having different widths (e.g., along the x-direction), such as... Figure 22 What is described Figure 22 Reference Figures 17A to 17CThe manufacturing stages described correspond to this. For example, the width of the gate stack portion between the topmost inner spacers 149 is smaller than the width of the gate stack portion between the middle inner spacers 49, and the width of the gate stack portion between the middle inner spacers 49 is smaller than the width of the gate stack portion between the bottommost inner spacers 149. For ease of description and understanding, this document also discusses... Figures 20 to 22 For clarity, the following has been simplified. Figures 20 to 22 To better understand the inventive concept of this disclosure. Additional components may be added to device 100, and some components described below may be replaced, modified, or eliminated in other embodiments of device 100.

[0076] In some embodiments, reference Figure 23 , Figure 24 , Figure 25A and Figure 25B After the formation of the undoped semiconductor layer 152 and before the formation of the doped semiconductor layer 156 (and the insulating layer 154, in some embodiments), the fabrication of device 100 may include performing an etching process (e.g., anisotropic etching) to laterally recess the channel layers 120'. For example, the etching process may laterally etch (e.g., along the x-direction) the channel layers 120' to reduce their length along the x-direction. Figure 23 This reduces the distance between the subsequently formed gate stack 180 and the doped semiconductor layer 156. Figure 24 This can improve the performance of transistor T. In such an example, the length of the channel layer 120' is greater than the length of the sacrificial oxide layer 146 and / or greater than the width of the dummy gate stack 132, but less than the sum of the length of the given sacrificial oxide layer 146 and the total width of the inner spacers 149, which are disposed between the inner spacers 149 such that the inner spacers 49 extend beyond the channel layer 120', such as... Figure 23 As depicted. In some embodiments, the etching process may recess and / or thin the undoped semiconductor layer 152. In such embodiments, the top of the undoped semiconductor layer 152 may be lower than the top of the mesa 105P', and / or the thickness of the undoped semiconductor layer 152 may be less than the thickness of the undoped semiconductor layer 152 in other device / circuit regions. In such embodiments, the bottom of the insulating layer 154 may be lower than the bottom of the insulating layer 154 in other device / circuit regions. In some embodiments, the device 100 may include transistors (e.g., p-type transistors forming portions of logic regions / circuits) having laterally recessed channel layers 120', such as Figure 24 , Figure 25A (Top component) Figure 25BThe (top device) or combinations thereof depicted, and transistors having an unrecessed channel layer 120' (e.g., p-type transistors forming portions of memory regions / circuits or n-type transistors forming portions of logic regions or memory regions), such as Figure 17A , Figure 25A (Bottom component) Figure 25B (Bottom device) or combinations thereof are depicted. In some embodiments, the laterally recessed channel layer 120' (e.g., Figure 24 and / or Figure 25A The length l1 of the top device can be from about 20 nm to about 22 nm, and the channel layer 120' is not laterally recessed (e.g., Figure 24 and / or Figure 25A The length l2 of the top device can be from about 25 nm to about 27 nm. In some embodiments, in a transistor having a laterally recessed channel layer 120' (e.g., Figure 24 and / or Figure 25B The top of the undoped semiconductor layer 152 is approximately 4 nm to approximately 5 nm below the top of the mesa 105P' (e.g., a distance d1), while in the transistor having an unrecessed channel layer 120' (e.g., ... Figure 17A and / or Figure 25B The bottom device), the top of the undoped semiconductor layer 152 is about 0 nm to about 2 nm above the top of the mesa 105P' (e.g., a distance d2). In some embodiments, the transistor has a laterally recessed channel layer 120' (e.g., Figure 24 and / or Figure 25A The thickness of the undoped semiconductor layer 152 of the top device can be smaller than that of a transistor having an unrecessed channel layer 120' (e.g., Figure 17A and / or Figure 25B The thickness of the undoped semiconductor layer 152 of the bottom device. In some embodiments, transistor T is a p-type transistor, and device 100 also includes an n-type transistor (which can form part of a logic region / circuit or a memory region / circuit), and the length of the channel layer of the n-type transistor can be from about 25 nm to about 27 nm (e.g., Figure 25A and / or Figure 25B The bottom device), and the top of the undoped semiconductor layer of the source / drain structure of the n-type transistor can be about 0 nm to about 2 nm above the top of its mesa (e.g., Figure 25A and / or Figure 25B (The bottom components). For ease of description and understanding, this section also discusses... Figure 23 , Figure 24 , Figure 25A and Figure 25B For clarity, it has been simplified. Figure 23 , Figure 24 , Figure 25A and Figure 25B To better understand the inventive concept of this disclosure. Additional components may be added, and some components described below may be replaced, modified, or eliminated.

[0077] Due to variations during processing, the bottom source / drain insulation (e.g., insulation layer 154) can have various profiles and / or dimensions. In some embodiments, reference... Figure 12A and Figure 12B The insulating layer 154 has a convex top surface. In some embodiments, reference... Figure 27 The insulating layer 154 has a concave top surface. In some embodiments, the insulating layer 154 has a substantially uniform thickness (e.g., along the z-direction). For example, the thickness of the central portion of the insulating layer 154 may be substantially the same as the thickness of the edge portions (also referred to as corner portions) of the insulating layer 154. In some embodiments, the thickness is about 3 nm to about 5 nm. In some embodiments, the insulating layer 154 has a thickness variation. For example, refer to... Figure 27The insulating layer 154 may have a left edge / corner of thickness E1, a right edge / corner of thickness E2, and a center of thickness C, and the thicknesses E1, E2, and C may be different. In some embodiments, thickness E1 is about 3 nm to about 5 nm, thickness E2 is about 3 nm to about 5 nm, and thickness C is about 3 nm to about 5 nm. In some embodiments, thickness C is greater than thickness E1 and thickness E2. In some embodiments, thickness C is less than thickness E1 and thickness E2. In some embodiments, thickness C is greater than thickness E2 and less than thickness E1. In some embodiments, thickness C is less than thickness E2 and greater than thickness E1. In some embodiments, thickness E1 is greater than thickness E2. In some embodiments, thickness E2 is greater than thickness E1. In some embodiments, the thickness of the insulating layer 154 decreases from left to right (i.e., thickness E1 is greater than thickness C, and thickness C is greater than thickness E2). In some embodiments, the thickness variation of the insulating layer 154 depends on the dimensions of the channel layer 120' (e.g., its width and / or length). For example, the thickness of the insulating layer 154 may decrease as the channel width increases. In some embodiments, the thickness of the insulating layer 154 of the first device having a first channel width (e.g., a center thickness of about 4 nm to about 5 nm and a corner thickness of about 3 nm to about 6 nm) can be greater than the thickness of the insulating layer 154 of the second device having a second width greater than the first width (e.g., a center thickness of about 4 nm to about 4.5 nm and a corner thickness of about 2.5 nm to about 4.5 nm), and the thickness of the insulating layer 154 of the second device can be greater than the thickness of the insulating layer 154 of the third device having a third width greater than the second width (e.g., a center thickness of about 3 nm to about 4 nm and a corner thickness of about 2 nm to about 3.5 nm). In another example, the thickness variation of the insulating layer 154 (e.g., the difference between its center thickness and edge / corner thickness) can decrease as the channel width increases. In some embodiments, the thickness variation of the insulating layer 154 depends on the contact polysilicon pitch (CPP) (i.e., the distance between adjacent gates (e.g., gate structure 130)). For example, the thickness variation of the insulating layer 154 (e.g., the difference between its center thickness and corner thickness) can increase with increasing CPP. In some embodiments, the thickness of the channel layer 120' (e.g., along the z-direction) is about 5 nm to about 6 nm. In some embodiments, the thickness of the sacrificial oxide layer 146 (e.g., along the z-direction) is greater than the thickness of the channel layer 120'. For example, in the depicted embodiment, the thickness of the sacrificial oxide layer 146 is greater than the thickness of the channel layer 120'. In some embodiments, the thickness of the sacrificial oxide layer 146 is about 6 nm to about 7 nm.

[0078] This disclosure provides numerous different embodiments. This document discloses a method for fabricating a multi-gate transistor using a pseudo-oxide interposer. An exemplary method includes forming a multilayer stack including a first semiconductor layer, a first sacrificial layer having a first composition, and a protrusion. The first semiconductor layer and the first sacrificial layer are disposed over the protrusion. A source / drain trench is formed by removing portions of the first semiconductor layer, the first sacrificial layer, and the protrusion in a source / drain region, and a source / drain structure is formed in the source / drain trench. The source / drain structure includes a second semiconductor layer and an insulating layer, with the insulating layer disposed between the second semiconductor layer and the protrusion. Before forming the source / drain structure, the first sacrificial layer is replaced with a second sacrificial layer having a second composition different from the first composition. After forming the source / drain structure, the second sacrificial layer is removed from the channel region to form a portion of a gate opening. A gate stack is formed in the portion of the gate opening.

[0079] An exemplary method includes: forming a multilayer stack including a first semiconductor layer and a first sacrificial layer having a first component, wherein the multilayer stack is disposed above a protrusion; forming a source / drain trench by removing portions of the first semiconductor layer, the first sacrificial layer, and the protrusion in a source / drain region; forming a source / drain structure in the source / drain trench, wherein the source / drain structure includes a second semiconductor layer and an insulating layer, wherein the insulating layer is disposed between the second semiconductor layer and the protrusion; replacing the first sacrificial layer with a second sacrificial layer having a second component different from the first component before forming the source / drain structure; removing the second sacrificial layer from a channel region after forming the source / drain structure to form a portion of a gate opening; and forming a gate stack in the portion of the gate opening.

[0080] In some embodiments, the method further includes replacing the ends of the second sacrificial layer with internal spacers before forming the source / drain structure. In some embodiments, the method further includes front-side source / drain contacts formed to the source / drain structure. In some embodiments, the method further includes back-side source / drain contacts formed to the source / drain structure.

[0081] In some embodiments, the first semiconductor layer is formed of a first semiconductor material, the first sacrificial layer is formed of a second semiconductor material, and the second sacrificial layer is formed of a dielectric material. In some embodiments, the first semiconductor material is silicon, the second semiconductor material is germanium-silicon, and the dielectric material is silicon oxide. In some embodiments, the insulating layer is a silicon nitride layer.

[0082] In some embodiments, the source / drain structure further includes a third semiconductor layer disposed between the insulating layer and the protrusion. The second semiconductor layer is doped, and the third semiconductor layer is undoped. In some embodiments, the method further includes laterally recessing the first semiconductor layer after forming the third semiconductor layer and before forming the insulating layer and the second semiconductor layer. In some embodiments, laterally recessing the first semiconductor layer reduces the thickness of the third semiconductor layer.

[0083] Another exemplary method includes forming a multilayer stack, the multilayer stack including a semiconductor layer, a sacrificial semiconductor layer, and a substrate extension. The method further includes forming a source / drain trench by removing portions of the semiconductor layer, the sacrificial semiconductor layer, and the substrate extension in the source / drain region, and forming a source / drain structure in the source / drain trench. The source / drain structure can be formed by forming an undoped semiconductor layer over the substrate extension, the undoped semiconductor layer partially filling the source / drain trench, forming an insulating layer over the undoped semiconductor layer, the insulating layer partially filling the source / drain trench, and forming a doped semiconductor layer over the insulating layer, the doped semiconductor layer filling the remaining portion of the source / drain trench. The method further includes replacing the sacrificial semiconductor layer in the channel region with a sacrificial oxide layer before forming the source / drain structure in the source / drain trench. The method further includes replacing the sacrificial oxide layer in the channel region with a gate stack after forming the source / drain structure in the source / drain trench.

[0084] In some embodiments, the method further includes laterally recessing the sacrificial oxide layer to form an internal spacer notch before forming the source / drain structure in the source / drain recess, and forming an internal spacer in the internal spacer notch. In some embodiments, the method further includes forming a gate structure over a multilayer stack in the channel region before forming the source / drain recess. The gate structure may include a dummy gate and gate spacers. In such embodiments, the method further includes removing the dummy gate to form a gate opening after forming the source / drain structure and before replacing the sacrificial oxide layer with a gate stack. The gate stack fills the gate opening.

[0085] In some embodiments, forming an insulating layer includes forming a nitrogen-containing dielectric layer over an undoped semiconductor layer. In some embodiments, the method further includes laterally recessing the semiconductor layer in the channel region after forming the undoped semiconductor layer and before forming the insulating layer. In some embodiments, the method further includes forming front-side source / drain contacts to the source / drain structure. In some embodiments, the method further includes forming back-side source / drain contacts to the source / drain structure. In some embodiments, forming back-side source / drain contacts includes removing the undoped semiconductor layer and the insulating layer. In some embodiments, the source / drain recess has sloped sidewalls.

[0086] Another exemplary method includes forming a multilayer stack comprising a first semiconductor layer, a sacrificial semiconductor layer, and a substrate extension. A source / drain trench is formed by removing portions of the first semiconductor layer, the sacrificial semiconductor layer, and the substrate extension in the source / drain regions, and a source / drain structure is formed in the source / drain trench. The source / drain structure includes a second semiconductor layer and an insulating layer, with the insulating layer disposed between the second semiconductor layer and the substrate extension. Before forming the source / drain structure, the sacrificial semiconductor layer is replaced with a sacrificial dielectric layer. After forming the source / drain structure, the sacrificial dielectric layer is removed from the channel region to form a portion of a gate opening. A gate stack is formed in the portion of the gate opening.

[0087] An exemplary device structure includes a first p-type transistor, which includes a first semiconductor layer, a first gate stack, and a first internal spacer. The first semiconductor layer has a first length extending from a first p-doped source / drain to a second p-doped source / drain. The first gate stack is disposed above the first semiconductor layer. The device structure also includes a second p-type transistor, which includes a second semiconductor layer, a second gate stack, and a second internal spacer. The second semiconductor layer has a second length extending from a third p-doped source / drain to a fourth p-doped source / drain. The second gate stack is disposed above the second semiconductor layer. A portion of the first gate stack is disposed between the first internal spacers, which extend beyond the ends of the first semiconductor layer, and the first p-doped source / drain is disposed on a first source / drain insulating layer. A portion of the second gate stack is disposed between the second internal spacers, the second length being greater than the first length, and the third p-doped source / drain is disposed on the second source / drain insulating layer.

[0088] In some embodiments, a first p-type transistor forms a portion of a logic circuit, and a second p-type transistor forms a portion of a memory circuit. In some embodiments, a first gate stack is disposed above a first semiconductor mesa, a second gate stack is disposed above a second semiconductor mesa, and the top of a first source / drain insulating layer is disposed below the top of the first semiconductor mesa, and the top of a second source / drain insulating layer is disposed above the top of the second semiconductor mesa. In some embodiments, a first gate stack is disposed above a first semiconductor substrate portion; a second gate stack is disposed above a second semiconductor substrate portion; and wherein the top of the first source / drain insulating layer is disposed below the top of the first semiconductor substrate portion, and the top of the second source / drain insulating layer is disposed above the top of the second semiconductor substrate portion.

[0089] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for manufacturing a multi-gate device, comprising: A multilayer stack is formed, the multilayer stack including a first semiconductor layer and a first sacrificial layer having a first component, wherein the multilayer stack is disposed above a protrusion; Source / drain recesses are formed by removing portions of the first semiconductor layer, the first sacrificial layer, and the protrusion in the source / drain regions. A source / drain structure is formed in the source / gate groove, wherein the source / drain structure includes a second semiconductor layer and an insulating layer, wherein the insulating layer is disposed between the second semiconductor layer and the protrusion; Before forming the source / drain structure, the first sacrificial layer is replaced with a second sacrificial layer having a second component that is different from the first component; After forming the source / drain structure, the second sacrificial layer is removed from the channel region to form a portion of the gate opening; and A gate stack is formed in the portion of the gate opening.

2. The method according to claim 1, wherein, The first semiconductor layer is formed of a first semiconductor material, the first sacrificial layer is formed of a second semiconductor material, and the second sacrificial layer is formed of a dielectric material.

3. The method according to claim 2, wherein, The first semiconductor material is silicon, the second semiconductor material is germanium silicon, and the dielectric material is silicon oxide.

4. The method according to claim 3, wherein, The insulating layer is a silicon nitride layer.

5. The method according to claim 1, further comprising: Before forming the source / drain structure, the ends of the second sacrificial layer are replaced with internal spacers.

6. The method according to claim 1, wherein, The source / drain structure further includes a third semiconductor layer disposed between the insulating layer and the protrusion, wherein the second semiconductor layer is doped and the third semiconductor layer is undoped.

7. The method according to claim 6, further comprising: After the formation of the third semiconductor layer and before the formation of the insulating layer and the second semiconductor layer, the first semiconductor layer is laterally recessed.

8. The method according to claim 7, wherein, The first semiconductor layer is laterally recessed to reduce the thickness of the third semiconductor layer.

9. A method for manufacturing a multi-gate device, comprising: A multilayer stack is formed, the multilayer stack comprising a semiconductor layer, a sacrificial semiconductor layer, and a substrate extension; Source / drain trenches are formed by removing portions of the semiconductor layer, the sacrificial semiconductor layer, and the substrate extension in the source / drain regions; The source / drain structure is formed in the source / drain groove by the following steps: An undoped semiconductor layer is formed over the substrate extension, the undoped semiconductor layer partially filling the source / drain trench. An insulating layer is formed over the undoped semiconductor layer, the insulating layer partially filling the source / drain trenches, and A doped semiconductor layer is formed over the insulating layer, the doped semiconductor layer filling the remaining portion of the source / drain trench; Before forming the source / drain structure in the source / drain trench, the sacrificial semiconductor layer in the channel region is replaced with a sacrificial oxide layer; as well as After the source / drain structure is formed in the source / drain trench, the sacrificial oxide layer in the channel region is replaced with a gate stack.

10. A multi-gate device structure, comprising: A first p-type transistor includes a first semiconductor layer, a first gate stack, and first internal spacers. The first semiconductor layer has a first length extending from a first p-doped source / drain to a second p-doped source / drain. The first gate stack is disposed above the first semiconductor layer. A portion of the first gate stack is disposed between the first internal spacers, which extend beyond the ends of the first semiconductor layer. The first p-doped source / drain is disposed on a first source / drain insulating layer. The second p-type transistor includes a second semiconductor layer, a second gate stack, and a second internal spacer. The second semiconductor layer has a second length extending from a third p-doped source / drain to a fourth p-doped source / drain. The second gate stack is disposed above the second semiconductor layer, wherein a portion of the second gate stack is disposed between the second internal spacers. The second length is greater than the first length, and the third p-doped source / drain is disposed on the second source / drain insulating layer.

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