GaN HEMT preparation method based on HVPE source drain regrowth
The method of fabricating ohmic contact electrodes by HVPE source-drain regrowth and patterned etching solves the problem of GaN surface defects caused by high-temperature annealing, realizes efficient ohmic contacts for Si-based GaN HEMT devices, and is suitable for Si-CMOS process lines.
Patent Information
- Application Number
- CN202511004608.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-21
- Publication Date
- 2025-11-11
AI Technical Summary
High-temperature annealing processes can cause defects on the surface of GaN materials, affecting the ohmic contact characteristics of Si-based GaN HEMT devices and making them incompatible with Si-CMOS process lines.
The method for fabricating ohmic contact electrodes using HVPE source/drain regrowth and patterned etching includes defining source/drain regrowth regions on a SiN mask layer, forming source and drain trenches using RIE and ICP etching processes, and depositing Ti/Au ohmic contact metal to avoid high-temperature annealing.
Ohmic contact electrodes were fabricated without the need for high-temperature annealing, which improved contact characteristics and device stability, increased the ohmic contact area, and reduced the surface defect density, making them suitable for Si-CMOS process lines.
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Figure CN120936058A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor technology, specifically relating to a method for fabricating GaN HEMTs based on HVPE source-drain regeneration length. Background Technology
[0002] GaN, as a third-generation semiconductor material, has attracted widespread attention for its application in power devices. Among them, HEMTs (High Electron Mobility Transistors) based on AlGaN / GaN heterojunction structures have advantages such as high frequency, high power density, and high operating temperature, making them a promising direction for the development of solid-state microwave power devices and power electronic devices. Excellent ohmic contact, including low ohmic contact resistivity and good ohmic contact morphology, is fundamental to realizing high-performance GaN devices.
[0003] To improve production efficiency, the industry has chosen Si substrates for the epitaxial growth of GaN, a third-generation semiconductor material, and has developed a fabrication process for Si-based GaN HEMTs. Furthermore, compatibility with mature Si-CMOS process lines can further increase yield.
[0004] High-temperature annealing can introduce O and N defects on the surface of GaN materials, creating deep-level interface states. To achieve compatibility between Si-based GaN HEMT device fabrication processes and Si-CMOS process lines, and to better facilitate market applications, it is essential to avoid the adverse effects of high-temperature annealing on the morphology of ohmic contact surfaces. Summary of the Invention
[0005] To address the aforementioned problems in the existing technology, this invention provides a GaN HEMT fabrication method based on HVPE source-drain regeneration length. The technical problem to be solved by this invention is achieved through the following technical solution: A method for preparing GaN HEMTs based on HVPE source-drain regeneration length includes: A GaN buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, and a GaN cap layer are sequentially formed on the substrate surface; wherein, the stacked structure of the AlN insertion layer, the AlGaN barrier layer, and the GaN cap layer is located in the central region of the surface of the GaN channel layer, and a two-dimensional electron gas channel is formed between the GaN channel layer and the AlN insertion layer. A SiN mask layer is deposited on the surface of the current device using LPCVD process, and source / drain regrowth regions are defined on both sides using photolithography. The SiN mask layer corresponding to the source / drain regrowth region was removed using a RIE dry etching process. An n+-AlGaInN layer was epitaxially grown on the surface of the exposed source / drain regrowth region using the HVPE process; Gate trenches are etched in the central region of the SiN mask layer; source and drain etching pattern regions are defined on the surface of the n+-AlGaInN layer using photolithography, and ICP etching is used to etch until the material does not exceed the lower surface of the n+-AlGaInN layer to obtain source and drain trenches. Ohmic contact metal is deposited in the source and drain trenches, and Schottky contact metal is deposited in the gate trench.
[0006] In one embodiment of the present invention, the substrate material includes Si, SiC, SiGe, GeAs, InAs, InP, and other III-V or II-VI group compound semiconductors.
[0007] In one embodiment of the present invention, the location of the source / drain regrowth region corresponds to the regions on both sides of the stacked structure.
[0008] In one embodiment of the present invention, the RIE dry etching process employs slow etching, with a corresponding etching rate of 5 nm / min.
[0009] In one embodiment of the present invention, the upper surface of the n+-AlGaInN layer is flush with the upper surface of the SiN mask layer.
[0010] In one embodiment of the present invention, the source / drain etched pattern region is cylindrical.
[0011] In one embodiment of the present invention, the ICP etching process employs slow etching, with a corresponding etching rate of 8 nm / min.
[0012] In one embodiment of the invention, before depositing ohmic contact metal in the source and drain trenches, the method further includes: The source and drain trenches are cleaned.
[0013] In one embodiment of the present invention, the ohmic contact metal is Ti / Au.
[0014] The beneficial effects of this invention are: (1) This invention focuses on Si-based GaN heterostructures and has carried out a series of technical research and optimization work on ohmic contact electrodes for GaN HEMTs. A method for fabricating ohmic contact electrodes based on HVPE source / drain regrowth and patterned etching has been successfully developed. The method employs ICP slow etching technology to incompletely etch the n+-AlGaInN regrowth layer. This method for fabricating ohmic contact electrodes based on source / drain regrowth and patterned etching produces ohmic contact electrodes with good contact characteristics without the need for high-temperature annealing, and these electrodes are then applied to the fabrication of GaN HEMTs.
[0015] (2) The method of the present invention can effectively improve the contact characteristics of the source and drain ohmic contact electrodes and the device characteristics of GaN HEMTs. The ohmic electrode surface of the Si-based GaN HEMT electronic device fabricated by this method has a better surface morphology and a smaller ohmic contact resistance, and the stability is significantly improved. It can be better compatible with Si-based CMOS process lines and avoids the adverse effects caused by high-temperature annealing process. Attached Figure Description
[0016] Figure 1 This is a schematic flowchart of a GaN HEMT fabrication method based on HVPE source-drain regeneration length provided in an embodiment of the present invention. Figures 2a-2f This is a schematic diagram of the process for preparing GaN HEMT based on HVPE source-drain regeneration length provided in an embodiment of the present invention. Detailed Implementation
[0017] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.
[0018] The contact between a metal and a semiconductor forms a non-rectified contact, namely an ohmic contact. It does not generate significant additional impedance, nor does it significantly alter the equilibrium carrier concentration within the semiconductor. Ohmic contacts have important practical applications. Semiconductor devices generally utilize metal electrodes to input or output current, which requires good ohmic contact between the metal and the semiconductor. In ultra-high frequency and high-power devices, ohmic contact is one of the key design and manufacturing issues. Based on this, this invention studies the fabrication process of ohmic contact electrodes based on HVPE source-drain regeneration and patterned etching, improving the ohmic metal filling effect, and providing a GaN HEMT fabrication method based on HVPE source-drain regeneration, such as... Figure 1 As shown, the method may include the following steps: S1, GaN buffer layer, GaN channel layer, AlN insertion layer, AlGaN barrier layer and GaN cap layer are sequentially formed on the substrate surface; In this embodiment of the invention, the substrate material includes Si, SiC, SiGe, GeAs, InAs, InP, and other III-V or II-VI group compound semiconductors.
[0019] In this embodiment of the invention, Si is used as the substrate material for illustrative purposes.
[0020] Please see Figure 2a As shown, the stacked structure of the AlN insertion layer, AlGaN barrier layer, and GaN cap layer is located in the central region of the GaN channel layer surface. That is, the stacked structure, together with the Si substrate, GaN buffer layer, and GaN channel layer, forms a convex shape. The GaN channel layer and AlGaN barrier layer form an AlGaN / GaN heterojunction structure, and a two-dimensional electron gas channel is formed between the GaN channel layer and the AlN insertion layer.
[0021] Figure 2a The thickness of each layer can be set as needed, and there are no restrictions here.
[0022] S2, deposit a SiN mask layer on the surface of the current device using LPCVD (Low Pressure Chemical Vapor Deposition) process, and define source and drain regrowth regions on both sides using photolithography. exist Figure 2a On the surface of the device shown, a SiN mask layer is deposited using LPCVD as a regrowth mask. This SiN mask layer covers the surface of the GaN cap layer and the exposed GaN channel layer. The thickness of the SiN mask layer can be set as needed, for example, 200 nm. Then, photolithography (such as an MA6 lithography machine) is used to define source / drain regrowth regions on both sides. The locations of these regions correspond to the areas on both sides of the stacked structure of the AlN insertion layer, AlGaN barrier layer, and GaN cap layer. Please refer to [link to relevant documentation]. Figure 2b understand.
[0023] S3, the SiN mask layer corresponding to the source / drain regrowth region is removed by RIE (Reactive Ion Etching) dry etching process; The RIE dry etching process employs a slow etching rate of 5 nm / min. This slow etching rate effectively reduces etching damage to the material surface. Through RIE dry etching, the SiN mask layers corresponding to the source / drain regrowth regions on both sides, as well as any remaining nitrides generated during the preceding processes, can be completely removed.
[0024] S4. An n+-AlGaInN layer is epitaxially grown on the surface of the exposed source / drain regrowth region using the HVPE (Hydride Vapor Phase Epitaxy) process. Please see Figure 2c It is understood that the upper surface of the n+-AlGaInN layer is flush with the upper surface of the SiN mask layer. In the experiments of this invention, the thickness of the n+-AlGaInN layer can be 100 nm, but it can be set as needed and is not limited here.
[0025] In this embodiment of the invention, an n+-AlGaInN layer is grown on the surface of the source / drain regrowth region to form donor doping, which can increase the carrier concentration. The selected dopant ion is N ion, and the doping concentration is 5 × 10⁻⁶. 16 cm -3 This invention innovatively uses n+-AlGaInN as the source / drain regrowth region material.
[0026] S5, etch gate trenches in the central region of SiN mask layer; define source and drain etching pattern regions on the surface of n+-AlGaInN layer using photolithography, and use ICP etching process to etch until it does not exceed the lower surface of n+-AlGaInN layer to obtain source and drain trenches. For etching gate trenches in the central region of the SiN mask layer, please refer to [link / reference]. Figure 2d It is understood that conventional etching processes can be used, and no restrictions are imposed here.
[0027] In one optional embodiment, the source / drain etched pattern region is cylindrical. Using cylindrical pattern etching can effectively increase the contact area between the ohmic contact metal and the n+-AlGaInN material, thereby improving electron tunneling and enhancing electrode IV characteristics.
[0028] ICP etching is used to etch until the surface of the n+-AlGaInN layer is no more than 1 / 2 surface to obtain the source and drain trenches. Please refer to [link to relevant documentation]. Figure 2e Understand, where S represents the source trench and D represents the drain trench, both of which are cylindrical. The bottom of both the source and drain trenches does not reach the lower surface of the n+-AlGaInN layer; the height of the remaining portion can be set as needed, for example, it can be 20nm.
[0029] The ICP etching process employs a slow etching rate of 8 nm / min. This slow etching facilitates increasing the contact area between the ohmic metal and the n+-AlGaInN layer, thereby improving the ohmic contact characteristics.
[0030] S6, deposit ohmic contact metal in the source and drain trenches, and deposit Schottky contact metal in the gate trench.
[0031] In one alternative embodiment, before depositing ohmic contact metal in the source and drain trenches, the method further includes: The source and drain trenches are cleaned.
[0032] Specifically, acid and alkaline solutions are used to clean the source and drain areas after slow etching, removing etching residues and oxides, improving the 2DEG leakage problem caused by etching, increasing the current when forming ohmic contacts, and reducing the difficulty of forming ohmic contacts.
[0033] In embodiment S6 of this invention, the ohmic contact metal is Ti / Au. That is, the first metal layer is Ti and the second metal layer is Au. The Ti / Au ohmic contact metal is prepared using an electron beam evaporation stage.
[0034] Ti is the first metal layer of the ohmic electrode. It undergoes a solid-state reaction with the diffused N atoms in n-GaN to form a half-metal TiN, which has good chemical stability, thermal stability, and high electrical conductivity. It can serve as the contact layer for the ohmic metal. At the same time, it leaves a high density of N vacancies in GaN, which act as shallow donors. Au is the second metal layer of the ohmic electrode. It is stable and has good electrical conductivity. Ti / Au is deposited in a stacked manner.
[0035] Preferably, the Ti / Au metal layers are deposited sequentially using electron beam evaporation. Of course, other suitable methods can also be used. The source and drain electrodes are formed by a lift-off process, which refers to the removal of the deposited multilayer ohmic metal except for the ohmic contact pattern area. This invention's process does not require high-temperature rapid thermal annealing, thus avoiding damage to the GaN lattice caused by high-temperature annealing, reducing interface damage, lowering surface defect density, improving device reliability, resulting in a smoother ohmic contact surface morphology and edges, while the low temperature improves process compatibility.
[0036] In S6, Schottky contact metal is deposited within the gate trench. See also... Figure 2f Understand, G represents the gate metal, i.e., the Schottky contact metal.
[0037] In summary, this invention utilizes HVPE source / drain regrowth and patterned etching to fabricate ohmic contact electrodes, thereby preparing GaN HEMT devices. This effectively improves the ohmic metal filling effect, resulting in a good ohmic contact morphology. By using ICP dry etching for incomplete etching of the n+-AlGaInN layer, the contact area between the ohmic contact metal and the n+-AlGaInN layer is increased, while interface damage is reduced, surface defect density is decreased, and ohmic contact performance is improved.
[0038] It should be noted that, in the description of this invention, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.
[0039] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.
[0040] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.
[0041] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.
Claims
1. A method for preparing GaN HEMTs based on HVPE source-drain regeneration length, characterized in that, include: A GaN buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, and a GaN cap layer are sequentially formed on the substrate surface; wherein, the stacked structure of the AlN insertion layer, the AlGaN barrier layer, and the GaN cap layer is located in the central region of the surface of the GaN channel layer, and a two-dimensional electron gas channel is formed between the GaN channel layer and the AlN insertion layer. A SiN mask layer is deposited on the surface of the current device using LPCVD process, and source / drain regrowth regions are defined on both sides using photolithography. The SiN mask layer corresponding to the source / drain regrowth region was removed using a RIE dry etching process. An n+-AlGaInN layer was epitaxially grown on the surface of the exposed source / drain regrowth region using the HVPE process; Gate trenches are etched in the central region of the SiN mask layer; source and drain etching pattern regions are defined on the surface of the n+-AlGaInN layer using photolithography, and ICP etching is used to etch until the material does not exceed the lower surface of the n+-AlGaInN layer to obtain source and drain trenches. Ohmic contact metal is deposited in the source and drain trenches, and Schottky contact metal is deposited in the gate trench.
2. The method according to claim 1, characterized in that, The substrate material includes Si, SiC, SiGe, GeAs, InAs, InP, and other III-V or II-VI group compound semiconductors.
3. The method according to claim 1, characterized in that, The location of the source / drain regrowth region corresponds to the regions on both sides of the stacked structure.
4. The method according to claim 1, characterized in that, The RIE dry etching process uses slow etching, with a corresponding etching rate of 5 nm / min.
5. The method according to claim 1, characterized in that, The upper surface of the n+-AlGaInN layer is flush with the upper surface of the SiN mask layer.
6. The method according to claim 1, characterized in that, The source / drain etched pattern area is cylindrical.
7. The method according to claim 1, characterized in that, The ICP etching process uses slow etching, with a corresponding etching rate of 8 nm / min.
8. The method according to claim 1, characterized in that, The method further includes, prior to depositing ohmic contact metal within the source and drain trenches: The source and drain trenches are cleaned.
9. The method according to claim 1, characterized in that, The ohmic contact metal is Ti / Au.