Conductive plug and preparation method thereof
By introducing a diffusion barrier layer into the conductive plug, the defect problem caused by Si atom enrichment on the conductive plug surface is solved, the electrical performance of the device is improved and the forward conduction voltage drop is reduced.
Patent Information
- Application Number
- CN202511055335.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-29
- Publication Date
- 2025-11-11
AI Technical Summary
In the fabrication process of traditional fast recovery diodes, a large number of Si atoms accumulate near the grain boundaries on the surface of the conductive plug, leading to surface defects and affecting the electrical performance of the device.
In the fabrication process of the conductive plug, a diffusion barrier layer is introduced between the bottom metal layer and the top metal layer to prevent silicon atoms from expanding outward, forming a sandwich structure conductive plug.
It effectively avoids surface defects of conductive plugs, improves the electrical performance of the device, and reduces forward conduction voltage drop.
Smart Images
Figure CN120936081A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, specifically to a conductive plug and its preparation method. Background Technology
[0002] In the development of traditional 12-inch automotive-grade fast recovery diodes (FRDs), to reduce the forward voltage drop (VF) of the FRD, conductive plugs (also known as contact holes) are typically fabricated in the peripheral lead-out area using a process where an aluminum-copper alloy layer is deposited on a silicon substrate. These conductive plugs are used to lead out the base region of the FRD. The aluminum-copper alloy layer can reduce the contact resistance of the conductive plug, thereby reducing the forward voltage drop of the FRD. However, during the manufacturing process, after the aluminum-copper alloy layer is deposited, a large number of Si atoms that have expanded outward from the silicon substrate accumulate near the grain boundaries on its surface, causing defects on the conductive plug surface and also affecting the electrical performance of the device. Summary of the Invention
[0003] This application provides a conductive plug and its preparation method, which can solve the problem that a large number of Si atoms expanding outward from the silicon substrate accumulate near the grain boundary on the surface of the conductive plug in the peripheral lead-out area, resulting in defects on the surface of the conductive plug and also affecting the electrical performance of the device.
[0004] On one hand, embodiments of this application provide a method for preparing a conductive plug, comprising:
[0005] An N-type doped silicon substrate is provided, the silicon substrate including an internal device region and a peripheral lead-out region, a first P-type well region is formed in the silicon substrate of the internal device region, a second P-type well region is formed in the silicon substrate of the peripheral lead-out region, and a plurality of shallow trench isolation structures for isolating the first P-type well region and the second P-type well region are also formed in the silicon substrate.
[0006] An insulating dielectric layer is formed, which covers the first P-type well region, the second P-type well region, and the shallow trench isolation structure;
[0007] The insulating dielectric layer of the peripheral lead-out area is etched and a portion of the thickness of the second P-type well region is etched to form a contact hole, wherein the contact hole opens a portion of the second P-type well region;
[0008] A bottom metal layer is formed, which covers the sidewalls and bottom wall of the contact hole and the insulating dielectric layer;
[0009] A diffusion barrier layer is formed, which covers the underlying metal layer;
[0010] A top metal layer is formed, which covers the diffusion barrier layer and fills the remaining space of the contact hole;
[0011] The top metal layer, the diffusion barrier layer, and the bottom metal layer of the internal device region are etched away to the surface of the insulating dielectric layer, wherein the remaining top metal layer, the remaining diffusion barrier layer, and the remaining bottom metal layer constitute a conductive plug with a sandwich structure.
[0012] Optionally, in the method for preparing the conductive plug, the bottom metal layer is an aluminum layer.
[0013] Optionally, in the method for preparing the conductive plug, the thickness of the bottom metal layer is 2000 angstroms to 3000 angstroms.
[0014] Optionally, in the method for preparing the conductive plug, the diffusion barrier layer comprises: a stacked titanium layer and a titanium nitride layer, wherein the titanium layer covers the underlying metal layer and the titanium nitride layer covers the titanium layer.
[0015] Optionally, in the method for preparing the conductive plug, the thickness of the diffusion barrier layer is 1000 angstroms to 2000 angstroms.
[0016] Optionally, in the method for preparing the conductive plug, the top metal layer is an aluminum-copper alloy layer.
[0017] Optionally, in the method for preparing the conductive plug, the insulating dielectric layer is formed using a furnace tube CVD process.
[0018] Optionally, in the method for preparing the conductive plug, a dry etching process is used to etch the insulating dielectric layer of the peripheral lead-out area and to etch a portion of the thickness of the second P-type well region to form a contact hole.
[0019] Optionally, in the method for preparing the conductive plug, a dry etching process is used to etch away the top metal layer, the diffusion barrier layer, and the bottom metal layer of the internal device region down to the surface of the insulating dielectric layer.
[0020] On the other hand, embodiments of this application also provide a conductive plug, including:
[0021] An N-type doped silicon substrate, the silicon substrate comprising an internal device region and a peripheral lead-out region, wherein a first P-type well region is formed in the silicon substrate of the internal device region, and a second P-type well region is formed in the silicon substrate of the peripheral lead-out region, and a plurality of shallow trench isolation structures for isolating the first P-type well region and the second P-type well region are also formed in the silicon substrate.
[0022] An insulating dielectric layer covering the first P-type well region, the second P-type well region, and the shallow trench isolation structure;
[0023] A contact hole is located in the insulating dielectric layer and part of the thickness of the second P-type well region in the peripheral lead-out area, wherein the contact hole opens a portion of the second P-type well region;
[0024] A bottom metal layer that covers the sidewalls and bottom wall of the contact hole and a portion of the insulating dielectric layer near the peripheral lead-out area of the contact hole;
[0025] A diffusion barrier layer, wherein the diffusion barrier layer covers the underlying metal layer;
[0026] A top metal layer covers the diffusion barrier layer and fills the remaining space of the contact hole, wherein the top metal layer, the diffusion barrier layer and the bottom metal layer constitute a conductive plug with a sandwich structure.
[0027] The technical solution of this application has at least the following advantages:
[0028] In the method for fabricating the conductive plug provided in this application, a bottom metal layer, a diffusion barrier layer, and a top metal layer are deposited in the contact hole of the peripheral lead-out area to prepare a conductive plug in the form of a sandwich structure of the peripheral lead-out area. By introducing a thin diffusion barrier layer between the bottom metal layer and the top metal layer, this application can effectively prevent silicon atoms in the substrate from expanding outward to the surface of the conductive plug (top metal layer), avoid the problem of defects on the surface of the conductive plug, and improve the electrical performance of the device. Attached Figure Description
[0029] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0030] Figure 1 This is a flowchart of the method for preparing the conductive plug according to an embodiment of the present invention;
[0031] Figures 2-7 This is a schematic diagram of the semiconductor structure in each process step of preparing the conductive plug according to an embodiment of the present invention;
[0032] The reference numerals in the attached figures are explained as follows:
[0033] 10-Silicon substrate, 11-Shallow trench isolation structure, 21-First P-type well region, 22-Second P-type well region, 30-Insulating dielectric layer, 31-Contact hole, 41-Bottom metal layer, 42-Diffusion barrier layer, 43-Top metal layer. Detailed Implementation
[0034] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0035] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0036] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0037] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0038] This application provides a method for preparing a conductive plug, referring to... Figure 1 , Figure 1 This is a flowchart of a method for preparing a conductive plug according to an embodiment of the present invention. The method for preparing the conductive plug includes:
[0039] First, perform step S1: Refer to Figure 2 , Figure 2This is a schematic diagram of the semiconductor structure after the formation of the insulating dielectric layer according to an embodiment of this application. An N-type doped silicon substrate 10 is provided. The silicon substrate 10 includes an internal device region and a peripheral lead-out region. A first P-type well region 21 is formed in the silicon substrate 10 of the internal device region, and a second P-type well region 22 is formed in the silicon substrate 10 of the peripheral lead-out region. A plurality of shallow trench isolation structures 11 for isolating the first P-type well region 21 and the second P-type well region 22 are also formed in the silicon substrate 10.
[0040] The second P-type well region 22 is an annular P-type well region.
[0041] Furthermore, the first P-type well region 21 is a strip-shaped P-type well region.
[0042] Then, proceed to step S2: Continue to refer to Figure 2 An insulating dielectric layer 30 is formed, which covers the first P-type well region 21, the second P-type well region 22 and the shallow trench isolation structure 11.
[0043] Preferably, the insulating dielectric layer 30 is formed using a furnace tube CVD process. The furnace tube CVD process still occupies an important position in the front-end semiconductor (FEOL) process due to its stability, high step coverage and high uniformity, and is irreplaceable, especially in scenarios that require a high-quality insulating dielectric layer.
[0044] In this embodiment, the insulating dielectric layer 30 is made of silicon dioxide.
[0045] Next, proceed to step S3: (Refer to...) Figure 3 , Figure 3 This is a schematic diagram of the semiconductor structure after the formation of the contact hole in an embodiment of this application. The insulating dielectric layer 30 of the peripheral lead-out area is etched and the second P-type well region 22 of a certain thickness is etched to form the contact hole 31. The contact hole 31 opens a portion of the second P-type well region 22, that is, the lateral opening size of the contact hole 31 is smaller than the critical size of the second P-type well region 22 in width.
[0046] In this embodiment, the insulating dielectric layer 30 of the peripheral lead-out area is etched using a dry etching process, and a portion of the thickness of the second P-type well region 22 is etched to form a contact hole 31.
[0047] Further, proceed to step S4: (Refer to...) Figure 4 , Figure 4This is a schematic diagram of the semiconductor structure after the formation of the bottom metal layer in an embodiment of this application. The bottom metal layer 41 is formed, which covers the sidewalls and bottom wall of the contact hole 31 and the insulating dielectric layer 30. The bottom metal layer 41 contacts the second P-type well region 22 at the bottom of the contact hole 31.
[0048] In this embodiment, the bottom metal layer 41 is an aluminum layer.
[0049] Preferably, the thickness of the bottom metal layer 41 is 2000 angstroms to 3000 angstroms.
[0050] In this application, an aluminum layer is first formed as the bottom metal layer of the contact hole structure, which can reduce the contact resistance of the conductive plug of the device, thereby reducing the forward voltage drop of the fast recovery diode.
[0051] Next, proceed to step S5: (Refer to...) Figure 5 , Figure 5 This is a schematic diagram of the semiconductor structure after the formation of the diffusion barrier layer in an embodiment of this application. The diffusion barrier layer 42 is formed and covers the underlying metal layer 42.
[0052] In this embodiment, the diffusion barrier layer 42 includes: a stacked titanium layer and a titanium nitride layer, wherein the titanium layer covers the underlying metal layer 41 and the titanium nitride layer covers the titanium layer.
[0053] Preferably, the thickness of the diffusion barrier layer 42 is 1000 angstroms to 2000 angstroms.
[0054] In this application, the diffusion barrier layer 42 located on the bottom metal layer 41 can effectively prevent silicon atoms in the substrate from expanding outward to the surface of the subsequent top metal layer, thereby avoiding the problem of defects on the surface of the top metal layer and improving the electrical performance of the device.
[0055] Further, proceed to step S6: Refer to Figure 6 , Figure 6 This is a schematic diagram of the semiconductor structure after the formation of the top metal layer in an embodiment of this application. The top metal layer 43 is formed, which covers the diffusion barrier layer 42 and fills the remaining space of the contact hole 31.
[0056] In this embodiment, the top metal layer 43 is an aluminum-copper alloy layer.
[0057] In this application, an aluminum-copper alloy layer is used as the top metal layer. The top metal layer is the main metal layer of the conductive plug, which can further reduce the contact resistance of the conductive plug of the device, thereby further reducing the forward voltage drop of the fast recovery diode.
[0058] Finally, proceed to step S7: (Refer to...) Figure 7 , Figure 7 This is a schematic diagram of the semiconductor structure after the formation of the sandwich structure conductive plug according to an embodiment of this application. The top metal layer 43, the diffusion barrier layer 42 and the bottom metal layer 43 of the internal device region are etched away to the surface of the insulating dielectric layer 30. The remaining top metal layer 43, the remaining diffusion barrier layer 42 and the remaining bottom metal layer 41 constitute the sandwich structure conductive plug.
[0059] In this embodiment, a dry etching process is used to etch away the top metal layer 43, the diffusion barrier layer 42, and the bottom metal layer 41 of the internal device region to the surface of the insulating dielectric layer 30.
[0060] Based on the same inventive concept, this application also provides a conductive plug, see reference. Figure 7 The conductive plugs in the peripheral device area of the fast recovery diode include:
[0061] An N-type doped silicon substrate 10 includes an internal device region and a peripheral lead-out region. A first P-type well region 21 is formed in the internal device region of the silicon substrate 10, and a second P-type well region 22 is formed in the peripheral lead-out region of the silicon substrate 10. A plurality of shallow trench isolation structures 11 for isolating the first P-type well region 21 and the second P-type well region 22 are also formed in the silicon substrate 10.
[0062] An insulating dielectric layer 30 covers the first P-type well region 21, the second P-type well region 22, and the shallow trench isolation structure 11.
[0063] Contact hole 31, the contact hole 31 is located in the insulating dielectric layer 30 of the peripheral lead-out area and the second P-type well region 22 of a certain thickness, wherein the contact hole 11 opens a portion of the second P-type well region 22;
[0064] A bottom metal layer 41 covers the sidewalls and bottom wall of the contact hole 31 and a portion of the insulating dielectric layer 30 near the peripheral lead-out area of the contact hole 31.
[0065] A diffusion barrier layer 42, which covers the underlying metal layer 41;
[0066] A top metal layer 43 covers the diffusion barrier layer 42 and fills the remaining space of the contact hole 31, wherein the top metal layer 43, the diffusion barrier layer 42 and the bottom metal layer 41 constitute a conductive plug with a sandwich structure.
[0067] In this application, a bottom metal layer, a diffusion barrier layer, and a top metal layer are deposited in the contact holes of the peripheral lead-out area to prepare a conductive plug in the form of a sandwich structure of the peripheral lead-out area. By introducing a thin diffusion barrier layer between the bottom metal layer and the top metal layer, this application can effectively prevent silicon atoms in the substrate from expanding outward to the surface of the conductive plug (top metal layer), avoid the problem of defects on the surface of the conductive plug, and improve the electrical performance of the device.
[0068] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A method for preparing a conductive plug, characterized in that, include: An N-type doped silicon substrate is provided, the silicon substrate including an internal device region and a peripheral lead-out region, a first P-type well region is formed in the silicon substrate of the internal device region, a second P-type well region is formed in the silicon substrate of the peripheral lead-out region, and a plurality of shallow trench isolation structures for isolating the first P-type well region and the second P-type well region are also formed in the silicon substrate. An insulating dielectric layer is formed, which covers the first P-type well region, the second P-type well region, and the shallow trench isolation structure; The insulating dielectric layer of the peripheral lead-out area is etched and a portion of the thickness of the second P-type well region is etched to form a contact hole, wherein the contact hole opens a portion of the second P-type well region; A bottom metal layer is formed, which covers the sidewalls and bottom wall of the contact hole and the insulating dielectric layer; A diffusion barrier layer is formed, which covers the underlying metal layer; A top metal layer is formed, which covers the diffusion barrier layer and fills the remaining space of the contact hole; The top metal layer, the diffusion barrier layer, and the bottom metal layer of the internal device region are etched away to the surface of the insulating dielectric layer, wherein the remaining top metal layer, the remaining diffusion barrier layer, and the remaining bottom metal layer constitute a conductive plug with a sandwich structure.
2. The method for preparing the conductive plug according to claim 1, characterized in that, The bottom metal layer is an aluminum layer.
3. The method for preparing the conductive plug according to claim 1, characterized in that, The thickness of the bottom metal layer is 2000 angstroms to 3000 angstroms.
4. The method for preparing the conductive plug according to claim 1, characterized in that, The diffusion barrier layer comprises: a stacked titanium layer and a titanium nitride layer, wherein the titanium layer covers the underlying metal layer and the titanium nitride layer covers the titanium layer.
5. The method for preparing the conductive plug according to claim 1, characterized in that, The thickness of the diffusion barrier layer is 1000 angstroms to 2000 angstroms.
6. The method for preparing the conductive plug according to claim 1, characterized in that, The top metal layer is an aluminum-copper alloy layer.
7. The method for preparing the conductive plug according to claim 1, characterized in that, The insulating dielectric layer is formed using a furnace tube CVD process.
8. The method for preparing the conductive plug according to claim 1, characterized in that, The insulating dielectric layer of the peripheral lead-out area is etched using a dry etching process, and a portion of the thickness of the second P-type well region is etched to form a contact hole.
9. The method for preparing the conductive plug according to claim 1, characterized in that, The top metal layer, the diffusion barrier layer, and the bottom metal layer of the internal device region are removed by dry etching down to the surface of the insulating dielectric layer.
10. A conductive plug, characterized in that, include: An N-type doped silicon substrate, the silicon substrate comprising an internal device region and a peripheral lead-out region, wherein a first P-type well region is formed in the silicon substrate of the internal device region, and a second P-type well region is formed in the silicon substrate of the peripheral lead-out region, and a plurality of shallow trench isolation structures for isolating the first P-type well region and the second P-type well region are also formed in the silicon substrate. An insulating dielectric layer covering the first P-type well region, the second P-type well region, and the shallow trench isolation structure; A contact hole is located in the insulating dielectric layer and part of the thickness of the second P-type well region in the peripheral lead-out area, wherein the contact hole opens a portion of the second P-type well region; A bottom metal layer that covers the sidewalls and bottom wall of the contact hole and a portion of the insulating dielectric layer near the peripheral lead-out area of the contact hole; A diffusion barrier layer, wherein the diffusion barrier layer covers the underlying metal layer; A top metal layer covers the diffusion barrier layer and fills the remaining space of the contact hole, wherein the top metal layer, the diffusion barrier layer and the bottom metal layer constitute a conductive plug with a sandwich structure.