Ultrathin solar cells with selective poly-silicon passivated contacts and methods of fabrication

Abstract

The application discloses an ultrathin solar cell with selective polysilicon passivation contact and a preparation method thereof, which comprises the following steps: forming a boron-doped emitter on the surface of an N-type monocrystalline silicon wafer; performing ablation treatment on part of the area of the back surface of the silicon wafer to form a recess structure; performing polishing etching on the back surface of the silicon wafer to form a plurality of patterned structures; preparing a tunneling oxide layer and a phosphorus-doped polysilicon layer on the back surface of the silicon wafer; and removing the tunneling oxide layer and the doped polysilicon layer on the non-metal contact area of the back surface of the silicon wafer. The method can save the cost of the silicon wafer, the prepared ultrathin solar cell has good flexibility, the current value of the cell is improved, and the transmission of carriers in the cell is more efficient.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of ultra-thin solar cells, and particularly relates to an ultra-thin solar cell with selective poly-silicon passivated contact and a preparation method thereof. BACKGROUND

[0002] The emergence of tunnel oxide passivated contact solar cells (TOPCon) has attracted great attention to high-efficiency crystalline silicon solar cell technology. TOPCon cells use N-type silicon as a substrate material, composed of an ultra-thin silicon oxide layer and a highly doped polysilicon layer. Since the tunneling potential of the tunnel oxide layer (4.5eV) is higher than that of the electron (3.1eV), it can reduce the carrier recombination between the metal electrode and the silicon, so that the electron is more easily tunneling and collected; the other function of the tunnel oxide layer is full-area passivation, and the excellent passivation capability further improves the efficiency of the TOPCon solar cell. The record of the photoelectric conversion efficiency of TOPCon cells has exceeded 26.5%.

[0003] Starting from 2023, the photovoltaic industry has a problem of overcapacity, and cost reduction and efficiency improvement have become the main theme of solar cell development. Studies have shown that ultra-thin solar cells with a thickness of one-third of conventional solar cells have unique potential. They can convert solar energy into electricity efficiently while achieving cost advantages due to material savings. In addition, ultra-thin solar cells have good flexibility and can be bent or rolled, which makes them suitable for installation on various complex-shaped surfaces. Moreover, ultra-thin solar cells have shorter carrier transport paths during their lifetime, which helps to reduce the problem of shortened carrier lifetime caused by substrate defects.

[0004] Currently, the thickness of advanced crystalline silicon solar cells is generally in the range of 110µm~150µm. According to different technical routes, they can be roughly divided into TOPCon, HJT and BC, etc. Among them, TOPCon cells form a passivation contact structure by preparing an ultra-thin tunnel oxide layer and a highly doped polysilicon film in the metal electrode contact area, thereby improving the power generation efficiency. HJT cells passivate by depositing intrinsic amorphous silicon film and P / N-type amorphous silicon film on the front and back surfaces, and then depositing transparent conductive film (TCO) for conduction. BC cells improve current value by placing all metal grid lines on the back surface of the cell. As a platform technology, it can provide technical upgrading for TOPCon or HJT cells. At present, TOPCon occupies the mainstream position due to its low cost, high reliability and high market acceptance.

[0005] Meanwhile, another study found that on the basis of HJT cells, by preventing passivation layer damage through low-damage continuous plasma vapor deposition, superimposing laser transfer technology, high-efficiency solar cells of different thicknesses were prepared. Compared with the efficiency of the base thickness of 125 mu m, the efficiency of 106 mu m thickness decreased by 0.25%, the efficiency of 84 mu m thickness decreased by 0.31%, the efficiency of 74 mu m thickness decreased by 0.62%, and the efficiency of 57 mu m thickness decreased by 0.75%. The 57 mu m flexible ultrathin solar cell has the highest power-to-weight ratio. It can be found that the efficiency decrease caused by the thinning of the cell is not linear, and the thinning of the cell reduces the weight and cost of the solar cell.

[0006] However, the solar cells prepared by the existing method also have some problems:

[0007] 1. Currently, only HJT cells have the preparation process of laboratory ultrathin cells. TOPCon is the most mainstream solar cell category at present, and there is no corresponding ultrathin cell technology process for mass production;

[0008] 2. When the thickness of the ultrathin cell is reduced, the light absorption rate of the silicon wafer will decrease with the thinning of the light absorption layer, resulting in a decrease in the current density of the cell, thereby affecting the photoelectric conversion efficiency of the solar cell;

[0009] 3. The conventional TOPCon solar cell structure has a full-area phosphorus-doped polysilicon deposition on the back surface. The heavily doped polysilicon helps to reduce the contact resistance between silicon and metal and improve the fill factor of the cell. However, the heavily doped polysilicon itself has a free carrier absorption effect, which will cause serious parasitic absorption of long-wavelength photons, also leading to a decrease in the current density of the cell. In the ultrathin cell, the thickness of the silicon wafer is thinned, and the light absorption of the silicon wafer will decrease. The long-wavelength photons will be reflected back and forth in the silicon wafer multiple times, and the number of times of passing through the heavily doped polysilicon layer will increase. Compared with the TOPCon cell with normal thickness of the silicon wafer, in the TOPCon cell with ultrathin silicon wafer, the parasitic absorption loss caused by the heavily doped polysilicon layer will be further increased. SUMMARY

[0010] The purpose of the present application is to provide an ultrathin solar cell preparation method based on the prior art, which can prepare an ultrathin solar cell with selective polysilicon passivation contact. The cell has the characteristics of tunneling oxide layer + doped polysilicon passivation, which fills the gap in the preparation process of TOPCon ultrathin solar cells.

[0011] The ultra-thin solar cell prepared by the application is different from the polished back surface of a conventional cell, and the application forms a patterned structure on the back surface of a silicon substrate by using a laser process on the basis of an ultra-thin crystalline silicon (20 µm-100 µm), which can form a resonant cavity structure, effectively increase the effective optical path length of absorbed light in the cell, improve the current value of the solar cell through optical effects, and compensate for the negative impact of the reduced light absorption thickness of the cell on the current value.

[0012] The method of the application forms a selective polysilicon passivation contact structure on the back surface of a TOPCon cell, which is different from the structure of a conventional TOPCon cell in which phosphorus-doped polysilicon is deposited on the entire back surface, and the method only sets a tunneling oxide layer and a doped polysilicon layer on the resonant cavity structure corresponding to the metallization area, which can effectively reduce the parasitic absorption of the doped polysilicon and improve the current value, and the conductivity type of the doped polysilicon is equivalent to that of a metal material, which is more conducive to the transmission of charge carriers.

[0013] The object of the application can be achieved by the following measures:

[0014] A preparation method of an ultra-thin solar cell with a selective polysilicon passivation contact, the method comprising:

[0015] forming a boron-doped emitter on the surface of an N-type monocrystalline silicon wafer;

[0016] performing ablation treatment on part of the back surface of the silicon wafer to form a recessed structure;

[0017] polishing and etching the back surface of the silicon wafer to form a plurality of patterned structures;

[0018] preparing a tunneling oxide layer and a phosphorus-doped polysilicon layer on the back surface of the silicon wafer;

[0019] removing the tunneling oxide layer and the doped polysilicon layer from the non-metal contact area of the back surface of the silicon wafer;

[0020] The N-type monocrystalline silicon wafer is an ultra-thin crystalline silicon, the patterned structure includes a resonant cavity structure and a recessed structure, the resonant cavity structure is a protruding structure on the back surface of the silicon wafer, and the recessed structure is located between two adjacent resonant cavity structures; the resonant cavity structure includes a first resonant cavity and a second resonant cavity, the first resonant cavity is located in the metal contact area of the back surface of the silicon wafer, and the second resonant cavity and the recessed structure are located in the non-metal contact area of the back surface of the silicon wafer.

[0021] The depths D of the first resonant cavity and the second resonant cavity are independently 0.5 µm-10 µm, the widths W of the protruding top of the first resonant cavity and the second resonant cavity are independently 20 µm-200 µm, and the width S of the recessed structure is 50 µm-1000 µm.

[0022] The thickness of the ultra-thin crystal silicon used in the present application is 20 µm to 100 µm. The "ultra-thin" in the ultra-thin solar cell prepared by the present application refers to the use of ultra-thin crystal silicon.

[0023] In a preferred embodiment, the depth D of the first resonant cavity and the second resonant cavity is independently 1 µm to 5 µm, the width W of the convex top of the first resonant cavity and the second resonant cavity is independently 40 µm to 100 µm, and the width S of the recessed structure is 100 µm to 1000 µm. The depth D of each first resonant cavity and each second resonant cavity can be the same or different, the width W of the convex top of each first resonant cavity and each second resonant cavity can be the same or different, and the width S of each recessed structure can be the same or different.

[0024] The method of the present application can form resonant cavity structures and recessed structures of uniform size or non-uniform size on the back surface of the silicon wafer, i.e., the depth D of the convex structures of different resonant cavity structures is the same or different, the width W of the convex top of the convex structures of different resonant cavity structures is the same or different, and the width S of different recessed structures is the same or different. Further, as shown in Figure 4 The depth (i.e., the height of the convex structure) D of each convex structure forming the resonant cavity structure on the back surface of the battery based on the light trapping capability of the resonant structure design of the present application can be the same or different, i.e., D1=D2 or D1≠D2, the W of the convex top of the convex structure forming each resonant cavity structure can also be the same or different, i.e., W1=W2 or W1≠W2, the width S of the recessed structure can be the same or different, i.e., S1=S2 or S1≠S2, and each resonant cavity structure is periodically distributed or not periodically distributed.

[0025] The number of the second resonant cavities in a single non-metallic contact area on the back surface of the silicon wafer in the present application is n, and n≥2.

[0026] The method of the present application further comprises forming a passivation and anti-reflection film on the front and back surfaces of the silicon wafer.

[0027] The method can further perform a pre-treatment such as texturing before forming the boron-doped emitter.

[0028] When preparing the boron-doped emitter, it can be directly formed on one surface of the N-type monocrystalline silicon wafer; or the boron-doped emitter can be formed on both surfaces of the N-type monocrystalline silicon wafer, and then the boron-doped emitter on one surface is removed.

[0029] The present application forms recessed structures in part of the area on the back surface of the silicon wafer by ablation, wherein the ablation can be performed by laser ablation or by a process of mask + dry etching.

[0030] The wavelength of the laser used in the ablation process is 200-1200 nm, and the laser is at least one of a picosecond laser or a nanosecond laser. 2 .

[0031] The front surface passivation anti-reflection film or the rear surface passivation anti-reflection film in the application can adopt a laminated film design, that is, the passivation anti-reflection film adopts at least one of aluminum oxide, silicon nitride, silicon dioxide and silicon oxynitride, preferably two of them, and more preferably an aluminum oxide + silicon nitride passivation anti-reflection film laminated design.

[0032] In a preferred scheme, the front surface passivation anti-reflection film or the rear surface passivation anti-reflection film comprises an aluminum oxide layer and a silicon nitride layer.

[0033] In a preferred scheme, the thickness of the tunneling oxide layer is 0.5-2.5 nm.

[0034] In a preferred scheme, the thickness of the phosphorus-doped polysilicon layer is 60-200 nm.

[0035] The application is based on the premise of ultra-thin battery sheet application. After the boron expansion process of the silicon wafer is completed, a patterned structure, i.e., a first resonant cavity, a second resonant cavity and a recess structure, is formed on the entire area of the back surface of the silicon wafer by using laser technology and wet process. Through this resonant structure, the reflection path length of the absorbed light in the silicon substrate can be effectively increased, and the current value of the solar cell can be improved. Compared with the back surface polished by the conventional cell, in addition to the conventional mirror reflection of long-wave light after reaching the back surface, part of the long-wave light will be trapped in the resonant structure to form an additional reflection path (see the attached Figure 10 );At the same time, by using laser technology combined with wet process, the doped polysilicon in the non-metallic grid line area is completely removed, reducing the negative impact of the parasitic absorption of the doped polysilicon itself on the current value of the cell. In addition, the heavy-doped polysilicon layer has a metal-like conductive property, and the remaining doped polysilicon is in direct contact with the substrate silicon, which is more conducive to the transmission of carriers.

[0036] The application further provides a specific preparation method of an ultra-thin solar cell with selective polysilicon passivation contact, which comprises the following steps:

[0037] S1, wet cleaning and texturing of N-type monocrystalline silicon wafer; the N-type monocrystalline silicon wafer is an ultrathin crystalline silicon;

[0038] S2, double-sided boron diffusion process is performed on the textured silicon wafer to form a boron-doped emitter;

[0039] S3, ablation treatment is performed on part of the area of the back surface of the silicon wafer by laser or dry etching with a mask to form a recessed structure; the laser is processed in a direction parallel to the fine grid, and the laser power is kept consistent or inconsistent, so that the depth of the formed recessed structure is consistent or inconsistent; the spot size of the laser is kept consistent or inconsistent, so that the width of the formed recessed structure is consistent or inconsistent;

[0040] S4, polishing and etching treatment is performed on the back surface of the silicon wafer to form a plurality of patterned structures; the patterned structures include a resonant cavity structure and a recessed structure, the resonant cavity structure is a protruding structure protruding from the back surface of the silicon wafer, and the recessed structure is located between two adjacent resonant cavity structures; the resonant cavity structure includes a first resonant cavity and a second resonant cavity, the first resonant cavity is located in a metal contact area of the back surface of the silicon wafer, and the second resonant cavity and the recessed structure are located in a non-metal contact area of the back surface of the silicon wafer; wherein the number of the second resonant cavities in a single non-metal contact area is multiple;

[0041] S5, a tunneling oxide layer and a phosphorus-doped polysilicon layer are prepared on the back surface of the silicon wafer, and the tunneling oxide layer and the phosphorus-doped polysilicon layer in the non-metal contact area are removed;

[0042] S6, forming a passivation anti-reflective film on the front and back surfaces of the silicon wafer;

[0043] S7, printing and sintering a metal electrode.

[0044] In step S1, preferably, the ultrathin crystalline silicon is placed in a texturing device, and the surface damage layer caused by wire cutting is etched at a reaction temperature of 70±10℃ with a sodium hydroxide solution, followed by a wet chemical process of alkali solution and texturing additives to generate a random pyramid surface structure, and RCA wet cleaning is performed, and the random pyramid height prepared is 0.5-2µm.

[0045] In step S2, preferably, the boron source used for boron diffusion is boron tribromide or boron trichloride, and the peak temperature of diffusion is 1000-1100℃.

[0046] In step S3, a preferred method is to use laser ablation to form a recess structure on part of the back surface of the silicon wafer, thereby pre-preparing a patterned structure. The laser parameters used are: the length of the light spot is 100 µm to 500 µm, and the width is 100 µm to 500 µm; the wavelength of the laser is 200 to 1200 nm; the laser is a picosecond laser or a nanosecond laser; the length of the rectangular or square light spot formed is 100 to 500 µm, and the width is 100 to 500 µm; the frequency of the laser is 50 to 300 KHz; the scanning speed is 5 to 25 m / s; and the energy density of the laser is 0.1 to 5 J / cm 2 .

[0047] In step S3, another preferred method is to use a mask + dry etching process to form a recess structure on part of the back surface of the silicon wafer, thereby pre-preparing a patterned structure. One specific method includes: after boron diffusion on the silicon wafer, a graphite mask is added on the back surface of the silicon wafer to cover part of the area, the mask shielding part is the later resonant cavity area on the back surface, and the mask hollow part is the later recessed area on the back surface. Then, the mask hollow area is etched by using a dry etching technology, i.e. a reactive ion etching (RIE) technology, and the part where the mask exists is protected and is not affected by this process, thereby finally forming the structure shown in Figure 3 The specific steps of dry etching are: placing the boron-diffused silicon wafer into a plasma device process chamber for plasma dry etching, introducing a gas such as CHF3, CF4, or SF6, etc. fluorine-based gas, and etching to a depth of 0.5 µm to 10 µm, preferably 1 µm to 5 µm.

[0048] In one preferred embodiment, step S4 includes:

[0049] S41, wet polishing the back surface of the silicon wafer, using 3% to 10% HF to remove the BSG layer on the back surface and the edge of the boron-diffused silicon wafer;

[0050] S42, polishing and etching the back surface of the silicon wafer using a wet additive + KOH / NaOH + water combined solution, at a reaction temperature of 60 ± 10°C, to form a patterned structure with multiple resonant cavities;

[0051] wherein the depths D of each first resonant cavity and each second resonant cavity are the same or different, the widths W of the protruding top of each first resonant cavity and each second resonant cavity are the same or different, and the widths S of each recess structure are the same or different; the number of second resonant cavities in a single non-metal contact area is n, and n ≥ 2.

[0052] In one preferred embodiment, step S5 includes:

[0053] S51, preparing a tunnel oxide layer and a phosphorus-doped polysilicon layer on the back surface of the silicon wafer;

[0054] S52, depositing an ultra-thin tunnel oxide layer on the back surface of the silicon wafer by low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition, the deposition reaction temperature being 400-600 DEG C, the thickness being 0.5-2.5 nm, and the silane being reacted and deposited to grow an intrinsic polysilicon layer on the back surface of the silicon wafer under low-pressure conditions, the deposition reaction temperature of the intrinsic polysilicon being 500-650 DEG C, and the thickness being 60-200 nm;

[0055] S53, phosphorus diffusion; in the process of phosphorus diffusion, phosphorus pentachloride and diphosphorus pentoxide are generated by decomposition of phosphorus oxychloride at high temperature in the presence of oxygen, the generated diphosphorus pentoxide reacts with silicon at the diffusion temperature to generate silicon dioxide and phosphorus atoms, the phosphorus atoms enter the intrinsic polysilicon layer to form a phosphorus-doped polysilicon layer;

[0056] S54, removing the excess tunnel oxide layer and doped polysilicon in the non-metal contact area by laser technology and wet process, and only leaving the tunnel oxide layer and doped polysilicon layer structure in the metallization area.

[0057] In step S6, preferably, a passivation anti-reflection film is formed on the front and back surfaces of the silicon wafer by using a laminated film design; the passivation anti-reflection film uses at least one of aluminum oxide, silicon nitride, silicon dioxide, and silicon oxynitride. Preferably, an aluminum oxide + silicon nitride passivation anti-reflection film laminated design is used.

[0058] In step S7, preferably, a metal electrode is printed and sintered on the front and back surfaces of the silicon wafer; the metal electrode grid line uses at least one of silver paste, silver-aluminum paste, aluminum, copper, titanium, or nickel metal material, the front and back surface metal fine grid line width is 10-60 µm, the height is 5-10 µm, the fine grid interval is 0.9-1.5 mm, and the number is 150-250; the main grid line width is 30-100 µm, the height is 2-8 µm, the main grid interval is 10-20 mm, and the number is 10-20, and the sintering temperature is 700-850 DEG C.

[0059] The application also includes an ultra-thin solar cell with selective polysilicon passivation contact prepared by the above method. Further, in the ultra-thin solar cell, the N-type monocrystalline silicon wafer is an ultra-thin crystalline silicon, the back surface metal contact area of the silicon wafer is sequentially provided with a tunnel oxide layer, a phosphorus-doped polysilicon layer, and a back surface passivation anti-reflection film from inside to outside, and the back surface non-metal contact area of the silicon wafer is provided with a back surface passivation anti-reflection film.

[0060] In the ultra-thin solar cell, the thickness of the ultra-thin crystalline silicon is 20 µm-100 µm; the depth D of the first resonant cavity and the second resonant cavity is independently 1 µm-5 µm respectively, the width W of the convex top of the first resonant cavity and the second resonant cavity is independently 40 µm-100 µm respectively, and the width S of the recessed structure is 100 µm-1000 µm.

[0061] The application also includes a photovoltaic module comprising a front encapsulation layer, a photovoltaic cell and a back encapsulation layer, wherein the photovoltaic cell is an ultra-thin solar cell with selective poly-silicon passivated contact prepared according to the method of the application.

[0062] In a preferred solution, the single patterned structure in the application comprises a first resonant cavity, a plurality of second resonant cavities and a plurality of recessed structures between the resonant cavities, and the range of the single patterned structure comprises an adjacent metal contact area and a non-metal contact area.

[0063] The application adopts a method of laser processing to form a resonant cavity structure, and forms a new selective poly-silicon passivated contact ultra-thin solar cell structure. The application designs the TOPCon cell structure based on the ultra-thin cell thickness (20 µm-100 µm), so that the cell has the advantages of material saving and good flexibility; the design of the resonant structure on the back surface of the cell is beneficial to increase the conduction path of long-wave light in the cell structure, and to offset the negative impact of the reduced thickness and the reduced light absorption layer on the current value of the cell. The design of the selective poly-silicon passivated contact on the back surface of the cell is beneficial to reduce the parasitic absorption of the doped poly-silicon; the design retains the passivation structure composed of the tunneling oxide layer + doped poly-silicon on both sides of the first resonant cavity structure, which is beneficial to increase the area of carrier transport and to more efficiently transport the carriers.

[0064] Through comparison of three different structures of TOPCon solar cell, the method of the application has the following advantages:

[0065] ① The application is designed based on the ultra-thin cell, and compared with the conventional thickness TOPCon cell, the ultra-thin solar cell can save the cost of silicon wafer, for example, if the current conventional TOPCon cell adopts a 40 µm thin silicon wafer material, the cost of the silicon wafer can be reduced to 1 / 3 of the original; at the same time, the ultra-thin solar cell has good flexibility and can be bent or curled, and is more suitable for distributed scenarios such as industrial and commercial roofs;

[0066] ②The resonance structure prepared on the back surface of the battery in the method can effectively increase the length of the reflection path of the absorbed light in the silicon substrate, improve the current value of the battery, and compared with the polished back surface of the conventional battery, in addition to the conventional mirror reflection of the long-wave band light after reaching the back surface of the battery, part of the medium and long-wave band light will be trapped in the resonance structure and then reflected multiple times, which can make up for the negative impact of the battery thickness thinning and the reduction of the light absorption layer on the battery current value (see the attached Figure 10 );

[0067] ③The method ablates the doped polysilicon in the non-metalized area on the back of the battery structure, reducing the negative impact of the parasitic absorption of the doped polysilicon itself on the battery current value;

[0068] ④The method retains the structure of the tunneling oxide layer + doped polysilicon of the resonance cavity corresponding to the metal gate line area. For ultra-thin batteries, the passivation layer on both sides of the first resonance cavity structure is retained, increasing the area of carrier transport and facilitating more efficient carrier transport. BRIEF DESCRIPTION OF DRAWINGS

[0069] Figure 1 is a schematic diagram of the structure of the silicon wafer after texturing in step S1 of the present application;

[0070] Figure 2 is a schematic diagram of the structure of the silicon wafer after double-sided boron diffusion in step S2 of the present application;

[0071] Figure 3 is a schematic diagram of the structure of the silicon wafer after laser preparation of the resonance cavity structure in step S3 of the present application;

[0072] Figure 4 is a schematic diagram of the patterned structure of the silicon wafer formed in step S4 of the present application;

[0073] Figure 5 is a schematic diagram of the structure of the silicon wafer after forming the phosphorus-doped polysilicon layer in step S5 of the present application;

[0074] Figure 6 is a schematic diagram of the structure of the silicon wafer after removing the tunneling oxide layer and the doped polysilicon layer in the non-metal contact area in step S5 of the present application;

[0075] Figure 7 is a schematic diagram of the structure of the silicon wafer after forming the passivation anti-reflection film in step S6 of the present application;

[0076] Figure 8 is a conventional TOPCon solar cell structure diagram;

[0077] Figure 9 is a TOPCon solar cell structure diagram with selective polysilicon contact in the prior art;

[0078] Figure 10 is a kind of back surface of the ultra-thin solar cell structure with the light capturing ability of patterned structure and the selective passivation ability of polycrystalline silicon prepared by the embodiment 1 of the present application;

[0079] Figure 11 is a kind of back surface of the ultra-thin solar cell structure with the light capturing ability of patterned structure and the selective passivation ability of polycrystalline silicon prepared by the embodiment 2 of the present application;

[0080] In the figure, 1 is an N-type silicon wafer substrate, 2 is a boron-doped emitter, 3 is a patterned structure, 31 is a first resonant cavity, 32 is a second resonant cavity, 33 is a recessed structure, 4 is a tunneling oxide layer, 5 is a phosphorus-doped polycrystalline silicon layer, 61 is a front surface passivation / anti-reflection film, 62 is a back surface passivation / anti-reflection film, 71 is a front surface metal electrode, and 72 is a back surface metal electrode. DETAILED DESCRIPTION

[0081] The present application can be better understood according to the following examples. However, it is readily apparent to a person skilled in the art that the examples described are only for the purpose of illustrating the present application and should not and will not limit the present application as described in detail in the claims.

[0082] The TOPCon cell referred to in the present application is a full name: Tunnel Oxide Passivated Contact solar cell.

[0083] As shown in Figures 10-11 , the ultra-thin solar cell of the present application comprises an N-type monocrystalline silicon wafer, wherein the N-type monocrystalline silicon wafer is an ultra-thin crystalline silicon with a thickness of 20 µm to 100 µm; the back surface of the silicon wafer comprises a metal contact area and a non-metal contact area.

[0084] A patterned structure 3 with multiple resonant cavities is formed on the back surface of the silicon wafer through a boron diffusion laser and a wet process, the patterned structure 3 comprises multiple resonant cavity structures and multiple recessed structures 33; the resonant cavity structure is a protruding structure protruding from the back surface of the silicon wafer, comprising a first resonant cavity 31 and a second resonant cavity 32; the recessed structure 33 is a structure between adjacent two resonant cavity structures and recessed towards the inside of the silicon wafer, the first resonant cavity 31 is located in the metal contact area, and the second resonant cavity 32 and the recessed structure 33 are located in the non-metal contact area.

[0085] The depth D of the first resonant cavity and the second resonant cavity is independently 1 µm-5 µm, the width W of the convex top of the first resonant cavity and the second resonant cavity is independently 40 µm-100 µm, and the width S of the recessed structure is 100 µm-1000 µm. The depth D of each first resonant cavity and each second resonant cavity is the same or different, the width W of the convex top of each first resonant cavity and each second resonant cavity is the same or different, and the width S of each recessed structure is the same or different. Figure 4 For example, the depth (i.e. the convex height) D of each convex structure of the resonant cavity structure can be the same or different, i.e. D1=D2 or D1≠D2, the width W of the convex top of each convex structure of the resonant cavity structure can be the same or different, i.e. W1=W2 or W1≠W2, and the width S of the recessed structure can be the same or different, i.e. S1=S2 or S1≠S2.

[0086] The number of the second resonant cavities in the single non-metallic contact area is n, and n≥2.

[0087] The metallic contact area of the back surface of the silicon wafer is sequentially provided with a tunneling oxide layer 4 and a phosphorus-doped polysilicon layer 5 from inside to outside. The thickness of the tunneling oxide layer 4 is 0.5 nm-2.5 nm. The thickness of the phosphorus-doped polysilicon layer 5 is 60-200 nm.

[0088] The back surface passivation anti-reflection film 62 is provided on the phosphorus-doped polysilicon layer 5 of the metallic contact area of the back surface of the silicon wafer and on the non-metallic contact area of the back surface of the N-type silicon wafer substrate.

[0089] The front surface passivation anti-reflection film 61 is sequentially provided on the front surface of the silicon wafer from inside to outside.

[0090] The front surface passivation anti-reflection film or the back surface passivation anti-reflection film herein adopts a passivation anti-reflection film stack design of aluminum oxide+silicon nitride, i.e. the passivation anti-reflection film comprises an aluminum oxide layer and a silicon nitride layer, the thickness of the aluminum oxide layer is 1-10 nm, and the thickness of the silicon nitride layer is 20-50 nm.

[0091] The front surface metal electrode 71 is further provided on the front surface of the N-type silicon wafer substrate, and the back surface metal electrode 72 is provided on the metallic contact area of the back surface of the N-type silicon wafer substrate.

[0092] The present application also comprises a photovoltaic module comprising a front encapsulation layer, a photovoltaic cell and a back encapsulation layer, wherein the photovoltaic cell is an ultrathin solar cell with selective polysilicon passivation contact prepared by the method of the present application.

[0093] Embodiments 1 and 2

[0094] A specific preparation method of an ultrathin solar cell with selective polysilicon passivation contact comprises the following steps:

[0095] S1, wet cleaning of N-type monocrystalline silicon wafer to remove the surface damage layer, clean the surface metal impurities and oil stains and make the surface texturing. The thickness of the N-type monocrystalline silicon wafer is 40 pm, and the resistivity is 1 Ω*cm. The original silicon wafer is placed in a texturing device, and a 10% sodium hydroxide solution is used to etch the surface damage layer caused by wire cutting at a reaction temperature of 70±10℃. The etching thickness on both sides is about 5 pm. Then, a wet chemical process of alkaline solution + texturing additive is used to produce random pyramid surface texture, and a standard RCA wet cleaning is performed. The height of the random pyramid produced is about 0.5-2 pm (see the attached Figure 1 ).

[0096] S2, double-sided boron diffusion process is performed on the textured silicon wafer to form a surface emitter. The boron source used in the boron diffusion process is boron tribromide (BBr3) or boron trichloride (BCl3), and the peak temperature of the diffusion is 1000-1100℃. After the boron diffusion process, the boron emitter sheet resistance is obtained by four-probe test method, which is 100-250 Ω / sq (see the attached Figure 2 ).

[0097] S3, laser ablation is used to process part of the area on the back surface of the silicon wafer to form a recess structure and prepare a patterned structure. After double-sided boron diffusion of the silicon wafer, laser is used to process the back surface of the silicon wafer. The laser is processed in the direction parallel to the fine grid, and the laser power can be consistent or inconsistent. The depth of the recess structure 33 formed is adjusted by adjusting the size of the laser power, and the width of the recess structure 33 is adjusted by controlling the spot size of the laser. The laser parameters used are: the length of the spot is 100-500 pm, and the width is 100-500 pm; the wavelength of the laser is 200-1200 nm, and is at least one of picosecond laser or nanosecond laser, for example, selected from 355 nm ultraviolet laser, 532 nm green laser, 650 nm red laser, 820 nm near-infrared laser or 1030 nm infrared laser, the length of the rectangular spot or square spot is 100-500 pm, the width is 100-500 pm, the laser frequency is 50-300 KHz, the scanning speed is 5-25 m / s, and the energy density of the laser is 0.1-5 J / cm 2 (see the attached Figure 3 ).

[0098] S4, wet polishing and etching treatment of the back surface of the battery to form a patterned structure with multiple resonant cavities. A 3% to 10% HF solution is used to remove the BSG layer on the back surface and edges of the boron-doped silicon wafer, followed by a wet additive + KOH & NaOH + water combined solution (ratio 1:5:90) for polishing and etching treatment of the back surface of the silicon wafer. The reaction temperature is 60±10℃. The front process laser irradiation part has poor corrosion resistance due to surface modification, and etches downward to a certain depth. The part without laser irradiation forms a polished surface of the silicon substrate, and finally forms multiple resonant cavity structures. The resonant cavities can be periodically distributed or non-periodically distributed, and the depth or width of the protruding silicon substrate can be consistent or inconsistent. The number of resonant cavities in a single non-metallized area is greater than or equal to 2 (see the accompanying Figure 4 The resonant cavity structure includes a first resonant cavity and a second resonant cavity, and a recess structure is located between the two adjacent resonant cavity structures. The depth D of the first resonant cavity and the second resonant cavity is independently in the range of 1µm to 5µm, and the width W of the protruding top of the first resonant cavity and the second resonant cavity is independently in the range of 40µm to 100µm. The width S of the recess structure is in the range of 100µm to 1000µm.

[0099] S5, preparation of a selective tunneling oxide layer and a doped polysilicon layer on the back surface. A low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD) method is used to deposit an ultra-thin tunneling oxide layer on the back surface under high-temperature oxygen conditions. The deposition reaction temperature is 400-600℃, and the thickness is selected to be 0.5nm to 2.5nm. Silane (SiH4) is reacted and deposited to grow a polysilicon layer on the back surface of the silicon wafer under low-pressure conditions. The deposition reaction temperature of the intrinsic polysilicon is 500-650℃, and the thickness is selected to be 60-200nm. The phosphorus diffusion process is carried out in the presence of oxygen. Phosphorus oxychloride (POCl3) decomposes to generate phosphorus pentachloride (PCl5) and phosphorus pentoxide (P2O5) at high temperature. The generated P2O5 reacts with silicon at the diffusion temperature to generate silicon dioxide (SiO2) and phosphorus atoms (P), which enter the intrinsic polysilicon layer to form a phosphorus-doped polysilicon layer (see the accompanying Figure 5 The excess doped polysilicon in the non-metallized area is then treated by laser technology and wet process, and only the metallized area remains with the tunneling oxide layer and doped polysilicon layer structure. The laser parameters are the same as step S3. (see the accompanying Figure 6

[0100] S6, deposition of passivation film and anti-reflection film on the front and back surfaces. The passivation and anti-reflection film on the front and back surfaces adopts an aluminum oxide + silicon nitride passivation and anti-reflection film stack design. The thickness of the aluminum oxide is 1-10nm, and the thickness of the silicon nitride is 20-50nm. The refractive index of the silicon nitride is 2.1-2.2 (see the accompanying Figure 7 ​​

[0101] S7. Metal electrode printing and sintering on the front and back surfaces. Metallized patterns are printed on the front and back surfaces (printing is done by screen printing or laser transfer, etc.). The metal grid lines can be made of silver paste, silver-aluminum paste, or other metal materials (aluminum, copper, titanium, nickel, etc.). The width of the fine metal grid lines on the front and back is 10-60µm, the height is 5-10µm, the spacing between the grid lines is 0.9-1.5mm, and the number is 150-250. The width of the main grid lines is 30-100µm, the height is 2-8µm, the spacing between the main grid lines is 10-20mm, and the number is 10-20. The sintering temperature is 700-850℃. Alternatively, a laser-assisted enhanced sintering process can be used to enhance contact and reduce contact resistivity.

[0102] During the fabrication process, the laser parameters in step S3 and the etching parameters in step S4 can be adjusted to form first resonant cavities, second resonant cavities, and recessed structures of different sizes.

[0103] In Example 1, with Figure 10 For example, in this scheme, the depth and width of each resonant cavity are the same and they are periodically distributed. The number of second resonant cavities in a single non-metallized region is n=2; the widths of the protruding tops of the two second resonant cavities 32 in a single non-metallized region are W1 and W2, W1=W2=60µm; the depths of the two second resonant cavities in a single non-metallized region are D1 and D2, D1=D2=5µm; the widths of the two recessed structures in a single non-metallized region are S1 and S2, S1=S2=200µm (this product is marked as Example 1).

[0104] In Example 2, with Figure 11 For example, in this scheme, the depth and width of each resonant cavity are different and not periodically distributed. The number of second resonant cavities in a single non-metallized region is n=2; the widths of the protruding tops of the two second resonant cavities 32 in a single non-metallized region are W1 and W2, W1=30µm and W2=100µm; the depths of the two second resonant cavities in a single non-metallized region are D1 and D2, D1=2µm and D2=5µm; the widths of the two recessed structures in a single non-metallized region are S1 and S2, S1=100µm and S2=500µm (this product is marked as Example 2).

[0105] Example 3

[0106] A specific method for fabricating an ultrathin solar cell with selective polycrystalline silicon passivated contacts includes the following steps:

[0107] S1, wet cleaning of N-type monocrystalline silicon wafer to remove the damaged layer on the surface of the wafer, clean the surface metal impurities and oil stains and make the positive surface rough. The thickness of the N-type monocrystalline silicon wafer is 40 pm, and the resistivity is 1 Ω*cm. The original silicon wafer is placed in a texturing device, and the positive surface of the wafer is etched with a 10% sodium hydroxide solution at a reaction temperature of 70±10℃. The etching thickness is about 5 pm, and then a wet chemical process of alkaline solution + texturing additive is used to produce a random pyramid surface texture, and a standard RCA wet cleaning is performed. The height of the random pyramid is about 0.5-2 pm.

[0108] S2, boron diffusion process is performed on the positive surface of the textured silicon wafer to form a surface emitter. The boron source used in the boron diffusion process is boron tribromide (BBr3) or boron trichloride (BCl3), and the peak temperature of the diffusion is 1000-1100℃. After the boron diffusion process, the boron emitter sheet resistance is 100-250 Ω / sq obtained by four-probe test method.

[0109] S3, etching treatment is performed on the back surface of the silicon wafer using a mask + dry etching process to form a recessed structure. After boron diffusion on the silicon wafer, a graphite mask is added to cover part of the back surface. The mask shielding part is the later resonant cavity area on the back surface, and the mask hollow part is the later recessed area on the back surface. Then, the mask hollow area is etched using dry etching technology, i.e. reactive ion etching (RIE) technology. The mask is partially protected and is not affected by the process. The specific steps of dry etching are as follows: the boron-diffused silicon wafer is placed in a plasma equipment process chamber for plasma dry etching. The gas introduced is CHF3 gas, and the etching depth is 0.5-5 pm.

[0110] S4, back surface etching treatment of the cell to form a patterned structure with multiple resonant cavities. A combined solution of wet additives + KOH & NaOH + water (ratio 1:5:90) is used to polish and etch the back surface of the silicon wafer. The reaction temperature is 60±10℃. The mask hollow part of the previous process is etched downward to a certain depth, and the mask shielding part forms a polished surface of the silicon substrate, finally forming multiple resonant cavity structures. The resonant cavities can be periodically distributed or non-periodically distributed, and the depth or width of the substrate silicon protruding downward can be consistent or inconsistent. The number of resonant cavities in a single non-metalized area is greater than or equal to 2. The resonant cavity structure includes a first resonant cavity and a second resonant cavity, and a recessed structure is located between the two adjacent resonant cavity structures. The depth D of the first resonant cavity and the second resonant cavity is independently in the range of 1-5 pm, and the width W of the protruding top of the first resonant cavity and the second resonant cavity is independently in the range of 40-100 pm. The width S of the recessed structure is in the range of 100-1000 pm.

[0111] The steps of subsequent steps S5-S7 are the same as those of Example 1. The mask width in step S3, the dry etching depth, and the etching parameters in S4 are adjusted to form first resonant cavities, second resonant cavities, and recessed structures of different sizes.

[0112] In this scheme, the depths and widths of the resonant cavities are different and are not periodically distributed. The number of second resonant cavities in a single non-metallized region is n = 2; the widths W1 and W2 of the convex top of the convex structure of the two second resonant cavities 32 in a single non-metallized region are W1 = 40 µm and W2 = 90 µm; the depths D1 and D2 of the two second resonant cavities in a single non-metallized region are D1 = 3 µm and D2 = 6 µm; and the widths S1 and S2 of the two recessed structures in a single non-metallized region are S1 = 200 µm and S2 = 600 µm.

[0113] Comparative Example 1

[0114] Comparative Example 1 used a 130 µm silicon wafer as the substrate to prepare a solar cell, and the specific preparation process was as follows:

[0115] (1) Wet cleaning was performed on an N-type monocrystalline silicon wafer to remove the surface damage layer of the silicon wafer, clean the surface metal impurities and oil stains, and produce a textured surface. The thickness of the N-type monocrystalline silicon wafer was (40-150) µm, and the resistivity was 1 Ω*cm. The original silicon wafer was placed in a texturing device, and a 10% sodium hydroxide solution was used to etch the surface damage layer caused by line cutting at a reaction temperature of 70±10°C. The etching thickness on both sides was about 5 µm. Then, a wet chemical process of alkaline solution + texturing additive was used to produce random pyramid surface texture, and standard RCA wet cleaning was performed. The height of the random pyramid produced was about 0.5-2 µm.

[0116] (2) A boron diffusion process was performed on both sides of the textured silicon wafer to form a surface emitter. The boron source used in the boron diffusion process was boron tribromide (BBr3) or boron trichloride (BCl3), and the peak temperature of the diffusion was 1000-1100°C. After the boron diffusion process, the boron emitter sheet resistance was obtained by a four-probe test method, which was 100-250 Ω / sq.

[0117] (3) Back surface wet polishing. A 3%-10% HF solution was used to remove the BSG layer on the back surface and edge of the silicon wafer after boron diffusion, and then a combined solution of wet additive + KOH / NaOH + water (mass ratio 1:5:90) was used to polish the back surface of the silicon wafer at a reaction temperature of 60±10°C.

[0118] (4) Growth of a tunneling oxide layer and an intrinsic amorphous silicon layer on the back surface of the battery; phosphorus diffusion to form a phosphorus-doped polysilicon structure. A low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD) method is used to make silane (SiH4) react and deposit a layer of ultra-thin tunneling oxide and polysilicon on the back surface of the silicon wafer under low pressure. The structure of the ultra-thin tunneling oxide layer is SiO2, the deposition reaction temperature is 400-600°C, and the thickness is selected to be 0.5-2.5 nm. The deposition reaction temperature of the intrinsic amorphous silicon is 500-650°C, and the thickness is selected to be 60-200 nm. The process of phosphorus diffusion is as follows: under the condition of oxygen, phosphorus oxychloride (POCl3) decomposes into phosphorus pentachloride (PCl5) and diphosphorus pentoxide (P2O5) at high temperature. The generated P2O5 reacts with silicon at the diffusion temperature to generate silicon dioxide (SiO2) and phosphorus atoms (P). The phosphorus atoms enter the intrinsic polysilicon layer to form a phosphorus-doped polysilicon layer, and the thickness of the polysilicon is 130 nm.

[0119] (5) Wet treatment of the surface of the battery. 3%-10% HF is used to remove the PSG layer on the front surface and edges of the silicon wafer after phosphorus diffusion, and then a combined solution of wet additives + KOH & NaOH + water (ratio 1:5:90) is used for polishing and etching treatment of the silicon wafer, with a reaction temperature of 60±10°C.

[0120] (6) Deposition of passivation films and anti-reflection films on the front and back surfaces. The passivation and anti-reflection films on the front and back surfaces are designed as a laminated film, which is a combination of two materials such as aluminum oxide, silicon nitride, silicon dioxide, and silicon oxynitride. As an optimization, the passivation and anti-reflection film laminated design uses aluminum oxide + silicon nitride, wherein the preferred thickness of aluminum oxide is 1-10 nm, and the preferred thickness of silicon nitride is 20-50 nm. The refractive index of silicon nitride is 2.1-2.2.

[0121] (7) Printing and sintering of metal electrodes on the front and back surfaces. Metalized patterns are printed on the front and back surfaces (printing is done by screen printing or laser transfer printing, etc.), and the metal grid lines can be made of silver paste, silver-aluminum paste, or other metal materials (aluminum, copper, titanium, nickel, etc.). The width of the front and back metal fine grid lines is 10-60 µm, the height is 5-10 µm, the fine grid spacing is 0.9-1.5 mm, and the number is 150-250. The width of the main grid lines is 30-100 µm, the height is 2-8 µm, the main grid spacing is 10-20 mm, and the number is 10-20. The sintering temperature is 700-850°C. Or use laser-assisted enhanced sintering process to enhance the contact and reduce the contact resistance.

[0122] Comparative Example 2

[0123] Comparative Example 2 uses a 40 µm silicon wafer as the substrate to prepare a solar cell, and the other preparation methods are the same as those in Comparative Example 1.

[0124] Comparative Example 3

[0125] Comparative Example 3 uses 40 µm silicon wafer as substrate to prepare solar cells, other preparation methods are the same as Comparative Example 1, only in the middle of step 4 and step 5, the following laser process is added:

[0126] Laser ablation, forming a selective poly-silicon layer. In the non-metallized area, the non-metallized area is treated by laser ablation through the laser process scheme, the laser spot is a rectangular or square spot, the length of the spot is 100 µm~500 µm, the width is 100 µm~500 µm, the line spacing is 200 µm~600 µm, there is no overlapping part between the spot lines, and the main grid part is also reserved 100 µm~500 µm width without laser treatment. In terms of laser, ultraviolet picosecond or nanosecond laser with wavelength of 200~600 nm is used, preferably 355 nm violet laser or 532 nm green laser, laser frequency is 50~300 KHz, laser scanning speed is 5~25 m / s, and laser treatment energy density is 0.1~5 J / cm 2 .

[0127] Test Example

[0128] The electrical performance of each batch of solar cells obtained in Examples 1 and 2 and Comparative Examples 1-3 is tested, and the results are shown in Table 1.

[0129] Comparative Example 1 is a conventional TOPCon cell structure with a thickness of 130 µm;

[0130] Comparative Example 2 is a conventional TOPCon structure cell with a thickness of 40 µm (structure see attached Figure 8 );

[0131] Comparative Example 3 is a selective poly-silicon passivation solar cell under the prior art with a thickness of 40 µm (structure see attached Figure 9 );

[0132] Example 1 is a selective poly-silicon passivation structure solar cell based on the design of the present application with a thickness of 40 µm, and the resonance cavity depth and width are the same and periodically distributed (structure see attached Figure 10 );

[0133] Example 2 is a selective poly-silicon passivation structure solar cell based on the design of the present application with a thickness of 40 µm, and the resonance cavity depth and width are different and not periodically distributed (structure see attached Figure 11 ).

[0134] Table 1

[0135]

[0136] In this table, the electrical performance data of each type of scheme is the average data of 100 Pcs of cells.

[0137] From the analysis of Table 1, it can be seen that:

[0138] 1) Compared with Comparative Example 1, Comparative Examples 2 / 3 and Examples 1 / 2 have less light-absorbing layer due to the thinning of the battery, which negatively affects the current density value of the battery; while Comparative Examples 2 / 3 and Examples 1 / 2 have advantages in cost as ultra-thin solar cells, and the open-circuit voltage is improved due to fewer bulk defects.

[0139] 2) Compared with Comparative Examples 2 / 3, the selective polysilicon passivated contact solar cell structure is prepared in Examples 1 / 2 of the present application, and the resonance structure on the back of the cell increases the propagation path length of light inside the cell through optical effects, thereby improving the current density value.

[0140] 3) Compared with Example 1, the resonance structure prepared in Example 2 has aperiodic distribution, which makes the propagation path of long-wave band light inside the cell longer, thereby further improving the current density value.

[0141] In summary, the method of the present application can prepare a low-cost, high-efficiency selective polysilicon passivated contact ultra-thin solar cell.

[0142] The above examples are only used to illustrate the technical solutions of the present application, but not to limit it; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing examples, or make equivalent replacements for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method of fabricating an ultrathin solar cell with selective poly-silicon passivated contact, characterized in that, The method comprises the following steps: forming a boron-doped emitter on the surface of an N-type monocrystalline silicon wafer; ablation treatment is performed on part of the back surface of the silicon wafer to form a recess structure (33); polishing and etching the back surface of the silicon wafer to form a plurality of patterned structures (3); a tunneling oxide layer and a phosphorus-doped polysilicon layer are prepared on the back surface of the silicon wafer; the tunneling oxide layer and the doped polysilicon layer on the non-metallic contact area of the back surface of the silicon wafer are removed; wherein the N-type monocrystalline silicon wafer is an ultrathin crystalline silicon; the patterned structure (3) comprises a resonant cavity structure and a recess structure (33), the resonant cavity structure is a protruding structure protruding from the back surface of the silicon wafer, and the recess structure (33) is located between two adjacent resonant cavity structures; the resonant cavity structure comprises a first resonant cavity (31) and a second resonant cavity (32), the first resonant cavity (31) is located in the metallic contact area of the back surface of the silicon wafer, and the second resonant cavity (32) and the recess structure (33) are located in the non-metallic contact area of the back surface of the silicon wafer; the depth D of the first resonant cavity (31) and the second resonant cavity (32) is independently 0.5 µm-10 µm, and the width W of the protruding top of the first resonant cavity (31) and the second resonant cavity (32) is independently 20 µm-200 µm, and the width S of the recess structure (33) is 50 µm-1000 µm.

2. The method of producing an ultrathin solar cell with selective poly-silicon passivated contact according to claim 1, wherein, The thickness of the ultrathin crystalline silicon is 20 µm-100 µm; the depth D of the first resonant cavity (31) and the second resonant cavity (32) is independently 1 µm-5 µm, the width W of the protruding top of the first resonant cavity (31) and the second resonant cavity (32) is independently 40 µm-100 µm, and the width S of the recess structure (33) is 100 µm-1000 µm.

3. The method of producing an ultrathin solar cell with selective poly-silicon passivated contact according to claim 1, wherein, The number of the second resonant cavities (32) in a single non-metallic contact area of the back surface of the silicon wafer is n, and n≥2.

4. The method of producing an ultrathin solar cell with selective poly-silicon passivated contact according to claim 1, wherein, The depth D of each first resonant cavity (31) and each second resonant cavity (32) is the same or different, the width W of the protruding top of each first resonant cavity (31) and each second resonant cavity (32) is the same or different, and the width S of each recess structure (33) is the same or different.

5. The method of producing an ultrathin solar cell with selective poly-silicon passivated contact according to claim 1, wherein, The method further comprises forming a passivation anti-reflection film on the front and back surfaces of the silicon wafer.

6. The method of producing an ultrathin solar cell with selective poly-silicon passivated contact according to claim 1, wherein, Ablation treatment is performed on part of the back surface of the silicon wafer using a laser or a mask; during the ablation treatment, the wavelength of the laser used is 200-1200 nm, and the laser is at least one of a picosecond laser or a nanosecond laser.

7. The method of producing an ultrathin solar cell with selective poly-silicon passivated contact according to claim 6, wherein, The laser is at least one of 355nm ultraviolet laser, 532nm green laser, 650nm red laser, 820nm near-infrared laser or 1030nm infrared laser; and the length of the rectangular or square spot formed by the laser is 100-500µm, the width is 100-500µm, the laser frequency is 50-300KHz, the scanning speed is 5-25m / s; the energy density of the laser is 0.1-5J / cm 2 .

8. The method of producing an ultrathin solar cell with selective poly-silicon passivated contact according to claim 1, wherein, The method comprises the following steps: S1, wet cleaning and texturing of an N-type monocrystalline silicon wafer; the N-type monocrystalline silicon wafer is an ultrathin crystalline silicon; S2, boron diffusion process on both sides of the textured silicon wafer to form a boron-doped emitter; S3, ablation treatment is performed on part of the area of the back surface of the silicon wafer by laser or by mask dry etching to form a recess structure (33); wherein the laser is processed in a direction parallel to the fine grid, the laser power is consistent or inconsistent, the depth of the formed recess structure (33) is consistent or inconsistent; the spot size of the laser is consistent or inconsistent, the width of the formed recess structure (33) is consistent or inconsistent; S4, polishing and etching treatment is performed on the back surface of the silicon wafer to form a plurality of patterned structures (3); The number of the second resonant cavities (32) in a single non-metallic contact area is multiple. S5, a tunneling oxide layer and a phosphorus-doped polysilicon layer are prepared on the back surface of the silicon wafer, and the tunneling oxide layer and the phosphorus-doped polysilicon layer in the non-metallic contact area are removed; S6, a passivation and anti-reflection film is formed on the front and back surfaces of the silicon wafer; S7, a metal electrode is printed and sintered.

9. The method of producing an ultrathin solar cell with selective poly-silicon passivated contact according to claim 8, wherein, In step S1, the ultra-thin crystalline silicon is placed in a texturing device, a sodium hydroxide solution is used to etch the damage layer on the surface of the silicon wafer caused by wire cutting at a reaction temperature of 70±10℃, then a wet chemical process of an alkaline solution and a texturing additive is used to generate a random pyramid surface structure, and RCA wet cleaning is performed, so that a random pyramid with a height of 0.5-2µm is obtained.

10. The method of producing an ultrathin solar cell with selective poly-silicon passivated contact according to claim 8, wherein, In step S2, the boron source used for boron diffusion is boron tribromide or boron trichloride, and the peak temperature of diffusion is 1000-1100℃.

11. The method of producing an ultrathin solar cell with selective poly-silicon passivated contact according to claim 8, wherein In step S3, ablation treatment is performed on part of the area of the back surface of the silicon wafer by laser or by mask dry etching to form a recess structure and pre-prepare a patterned structure; the laser parameters used are: the length of the light spot is 100-500 pm, the width is 100-500 pm; the wavelength of the laser is 200-1200 nm, the laser is a picosecond laser or a nanosecond laser, the length of the rectangular light spot or square light spot formed is 100-500 pm, the width is 100-500 pm, the laser frequency is 50-300 KHz, the scanning speed is 5-25 m / s, and the energy density of the laser is 0.1-5 J / cm 2 .

12. The method of producing an ultrathin solar cell with selective poly-silicon passivated contact according to claim 8, wherein, Step S4 includes: S41, wet polishing is performed on the back surface of the silicon wafer, and 3%-10% HF is used to remove the BSG layer on the back surface and the edge of the silicon wafer after boron diffusion; S42, a combined solution of a wet additive, KOH / NaOH and water is used to perform polishing and etching treatment on the back surface of the silicon wafer, the reaction temperature is 60±10℃, and a patterned structure with multiple resonant cavities is formed; The depth D of each first resonant cavity (31) and each second resonant cavity (32) is the same or different, the width W of the protruding top of each first resonant cavity (31) and each second resonant cavity (32) is the same or different, the width S of each recess structure (33) is the same or different, and the number of the second resonant cavities (32) in a single non-metallic contact area is n, and n≥2.

13. The method of producing an ultrathin solar cell with selective poly-silicon passivated contact according to claim 8, wherein, Step S5 includes: S51, a tunneling oxide layer and a phosphorus-doped polysilicon layer are prepared on the back surface of the silicon wafer; S52, a layer of ultra-thin tunneling oxide layer is deposited on the back surface of the silicon wafer by low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition, the deposition reaction temperature is 400-600℃, the thickness is selected to be 0.5nm-2.5nm, and in a low-pressure condition, silane is reacted and deposited to grow a layer of intrinsic polysilicon on the back surface of the silicon wafer, the deposition reaction temperature of the intrinsic polysilicon is 500-650℃, and the thickness is selected to be 60-200nm; S53, phosphorus diffusion; in the process of phosphorus diffusion, phosphorus pentachloride and diphosphorus pentoxide are generated by decomposition of phosphorus oxychloride at high temperature in the condition of oxygen, diphosphorus pentoxide generated at diffusion temperature reacts with silicon to generate silicon dioxide and phosphorus atom, phosphorus atom enters intrinsic polysilicon layer to form phosphorus doped polysilicon layer; S54, by laser technology and wet process, remove the excess tunneling oxide layer and doped polysilicon in the non-metal contact area, only the metalized area remains tunneling oxide layer and doped polysilicon layer structure.

14. The method of producing an ultrathin solar cell with selective poly-silicon passivated contact according to claim 8, wherein, In step S6, a passivation anti-reflection film is formed on the front and back surfaces of the silicon wafer using a laminated film design; the passivation anti-reflection film uses at least one of aluminum oxide, silicon nitride, silicon dioxide, and silicon oxynitride.

15. The method of producing an ultrathin solar cell with selective poly-silicon passivated contact according to claim 8, wherein, In step S7, a metal electrode is printed and sintered on the front and back surfaces of the silicon wafer; the metal electrode grid line uses at least one of silver paste, silver-aluminum paste, aluminum, copper, titanium, or nickel metal material, the front and back surface metal fine grid line width is 10-60µm, the height is 5-10µm, the fine grid spacing is 0.9-1.5mm, the number is 150-250; the main grid line width is 30-100µm, the height is 2-8µm, the main grid spacing is 10-20mm, the number is 10-20, and the sintering temperature is 700-850℃.

16. An ultrathin solar cell with selective polysilicon passivated contact prepared by the method of any one of claims 1-14.

17. The ultrathin solar cell with selective poly-silicon passivated contact of claim 16, wherein, The N-type monocrystalline silicon wafer is an ultrathin crystalline silicon; the back surface metal contact area of the silicon wafer is sequentially provided with a tunneling oxide layer, a phosphorus doped polysilicon layer, and a back surface passivation anti-reflection film from inside to outside, and the back surface non-metal contact area of the silicon wafer is provided with a back surface passivation anti-reflection film.

18. The ultrathin solar cell with selective poly-silicon passivated contact of claim 16, wherein, The thickness of the ultrathin crystalline silicon is 20µm-100µm; the depth D of the first resonant cavity (31) and the second resonant cavity (32) is independently 1µm-5µm, the width W of the protruding top of the first resonant cavity (31) and the second resonant cavity (32) is independently 40µm-100µm, and the width S of the recessed structure (33) is 100µm-1000µm.

19. A photovoltaic module, characterized by It comprises a front encapsulation layer, a photovoltaic cell, and a back encapsulation layer, wherein the photovoltaic cell is an ultrathin solar cell with selective polysilicon passivated contact prepared by the method of any one of claims 1-14.

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