Back contact battery, manufacturing method thereof and photovoltaic module

Abstract

The invention discloses a back contact battery, a manufacturing method thereof and a photovoltaic module, relates to the technical field of photovoltaic, and aims to reduce the electric leakage risk of the edge part, close to a groove, of a first doped semiconductor part and facilitate the improvement of the conversion efficiency of the back contact battery. The back contact battery comprises a semiconductor substrate, a first doped semiconductor part, an isolation layer and a second doped semiconductor part. The bottom surface of the third region is recessed into the semiconductor substrate relative to the surfaces of the first region and the second region, respectively, to form a groove. The surface height of the second area is smaller than the surface height of the first area in the direction from the second face to the first face. The first doped semiconductor portion is disposed in the first region. The isolation layer is at least arranged on the portion, close to the notch of the groove, of the first side face. The second doped semiconductor portion is disposed on the second region and a side of the isolation layer facing away from the semiconductor substrate. And the doping types of the second doped semiconductor part and the first doped semiconductor part are opposite.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic technology, and in particular to a back contact battery and its manufacturing method, and a photovoltaic module. Background Technology

[0002] A back-contact solar cell is a solar cell where the second side of the cell has no electrodes, and both the positive and negative electrodes are located on the back side of the cell. This reduces the shading of the cells by the electrodes, increases the short-circuit current, and improves the energy conversion efficiency of the cells.

[0003] However, the existing back-contact batteries have a higher risk of leakage on the back side, which is not conducive to improving the conversion efficiency of back-contact batteries. Summary of the Invention

[0004] The purpose of this invention is to provide a back contact battery and its manufacturing method, as well as a photovoltaic module, to reduce the leakage risk of the first doped semiconductor part near the edge of the groove, reduce the carrier recombination rate, and improve the conversion efficiency of the back contact battery.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a back contact battery, comprising: a semiconductor substrate, a first doped semiconductor portion, an isolation layer, and a second doped semiconductor portion. The semiconductor substrate includes a first surface and a second surface opposite to each other. The first surface includes alternating first and second regions, and a third region located between the first and second regions. The bottom surface of the third region is recessed into the semiconductor substrate relative to the surfaces of the first and second regions, forming a groove. The groove has a first side surface near the first region and a second side surface near the second region. Along the direction from the second surface to the first surface, the surface height of the second region is less than the surface height of the first region. The first doped semiconductor portion is disposed in the first region. The isolation layer is disposed at least on the portion of the first side surface near the groove opening. The second doped semiconductor portion is disposed on the second region and on the side of the isolation layer facing away from the semiconductor substrate. The doping types of the second doped semiconductor portion and the first doped semiconductor portion are opposite.

[0006] In the case of the above technical solution, in the back contact battery provided by the present invention, the surface height of the second region where the second doped semiconductor portion is provided is less than the surface height of the first region where the first doped semiconductor portion is provided, so that the surface of the first region and the surface of the second region can be staggered along the thickness direction of the semiconductor substrate. At this time, in the actual manufacturing process of the back contact battery, after the patterning process of the entire layer of the first doped semiconductor portion, it is easy to remove all the first doped semiconductor portion located in the second region, thereby reducing the leakage risk of the second region and making the second doped semiconductor portion have a higher carrier collection efficiency.

[0007] Furthermore, the bottom surface of the third region is recessed into the semiconductor substrate relative to the surfaces of the first and second regions, forming a groove that further cuts off the leakage path between the first and second doped semiconductor portions, reducing the leakage risk on the first side. The groove also has a first side surface near the first region, and an isolation layer is provided on at least the portion of this first side surface near the groove opening. In other words, the isolation layer is at least provided on the portion of the first side surface near the first doped semiconductor portion. Therefore, even during actual manufacturing, due to the difference in etching rates between the first doped semiconductor portion and the semiconductor substrate, after selective etching of the entire layer of the first doped semiconductor portion, the edge portion of the first doped semiconductor portion near the third region may be suspended above a portion of the groove. This makes it difficult to completely remove the portion of the second doped semiconductor portion deposited between this suspended edge portion and the semiconductor substrate. In this case, the isolation layer can separate the first doped semiconductor portion from the remaining second doped semiconductor portion, reducing the leakage risk at the edge portion of the first doped semiconductor portion. Meanwhile, the presence of the isolation layer can also prevent the dopant from entering the part of the semiconductor substrate near the first doped semiconductor part through the second doped semiconductor part during the doping process, thereby reducing the carrier recombination rate at the edge of the first doped semiconductor part. At the same time, it enables the edge of the first doped semiconductor part to have a higher carrier collection efficiency, which is beneficial to improving the conversion efficiency of the back contact battery.

[0008] Furthermore, it is understandable that the presence of the insulating layer can reduce the leakage risk of the back contact battery. Given a small reverse leakage current in the back contact battery, the requirements for manufacturing the electrode structure using laser sintering technology can be met. Based on this, manufacturing the electrode structure of the back contact battery provided by this invention using laser sintering not only allows for the formation of a metal-semiconductor alloy with low contact resistivity through the high temperatures generated during laser sintering, improving contact performance, but also enables the use of semi-burn-through electrode paste (with low glass content), which is difficult to use in conventional high-temperature sintering processes. This reduces damage to the surface passivation layer, resulting in a larger passivation contact area between the surface passivation layer and one side of the first surface, thus reducing the carrier recombination rate.

[0009] As one possible implementation, in the width direction of the third region, the first doped semiconductor portion extends further above the partial groove along a direction close to the second region.

[0010] When the back contact battery provided by the present invention is in operation, light rays are refracted from one side of the second surface into the semiconductor substrate along the direction from the second surface to the first surface. After absorbing photon energy, the semiconductor substrate generates electrons and holes. These electrons and holes move towards the first doped semiconductor portion and the second doped semiconductor portion, respectively, and are eventually discharged by the corresponding electrodes, forming a photocurrent. However, not all light rays entering the semiconductor substrate are absorbed and utilized; some light rays are refracted from one side of the first surface of the semiconductor substrate. In this case, the first doped semiconductor portion located on one side of the first surface of the semiconductor substrate extends above a portion of the groove along the direction close to the second region. At this time, the end of the first doped semiconductor portion adjacent to the third region is suspended, allowing some light rays refracted from one side of the first surface of the semiconductor substrate to return to the semiconductor substrate and be absorbed and utilized by the semiconductor substrate through reflection from the suspended end of the first doped semiconductor portion adjacent to the third region. This increases the utilization rate of light by the back contact battery and improves the photoelectric conversion efficiency of the back contact battery.

[0011] As one possible implementation, in the width direction of the third region, the first side includes a first connection region, a platform region, and a second connection region that are sequentially and continuously distributed along the direction close to the second region. The surface of the platform region is substantially perpendicular to the thickness direction of the semiconductor substrate. The surfaces of the first connection region and / or the second connection region are disposed perpendicularly to or inclined relative to the surface of the platform region.

[0012] When adopting the above technical solution, the first side not only includes a first connection region and a second connection region arranged parallel or inclined to the thickness direction of the semiconductor substrate, but also includes a platform region approximately perpendicular to the thickness direction of the semiconductor substrate. The presence of this platform region not only increases the light absorption area of ​​the first side, but also, in conjunction with the portion of the first doped semiconductor extending above a certain groove, alters the light transmission path, allowing more light to be refracted into the semiconductor substrate, thereby improving the bifaciality of the back contact battery. Furthermore, the presence of the platform region also provides a high buffering effect during the formation of the surface passivation layer on one side of the first side, improving the coverage of the surface passivation layer on the first side, enhancing the passivation effect of the surface passivation layer on the first side, and reducing the carrier recombination rate. In addition, when the electrode structure of the back contact battery provided by this invention is manufactured using laser sintering technology, reducing the carrier recombination rate, i.e., reducing leakage current, also helps to improve the quality of the formed electrode structure, improve contact performance, and ultimately improve the conversion efficiency of the back contact battery.

[0013] As one possible implementation, the height of the first connection region is H along the thickness direction of the semiconductor substrate. The width of the platform region is W along the width direction of the third region. Wherein, H is greater than or equal to 0.1 μm and less than or equal to 5 μm; and / or, W is greater than or equal to 0.1 μm and less than or equal to 8 μm; and / or, the difference between H and W is greater than or equal to 0 and less than or equal to 3 μm.

[0014] When the above technical solution is adopted, the height H of the first connection region is within the above range, which helps to prevent the formation range of the isolation layer on the first side from being too small due to H being too small, and further reduces the leakage risk of the edge portion of the first doped semiconductor part; in addition, it can also prevent the portion of the semiconductor substrate corresponding to the third region and the second region from being over-etched due to the excessive height of the first connection region, so that each part of the semiconductor substrate has a large light absorption depth, improves the light utilization rate of the semiconductor substrate, and helps to improve the conversion efficiency of the back contact battery.

[0015] Furthermore, by ensuring the width W of the platform region is within the aforementioned range, it prevents the platform region from having a smaller width, which would result in a weaker height buffering effect and a smaller light absorption area. This further improves the coverage of the surface passivation layer on the first side and increases the bifaciality of the back contact cell. Secondly, when an isolation layer is also disposed on the platform region, it prevents the isolation layer from having a smaller formation area due to a smaller platform region width W, reducing the risk of leakage at the edge of the first doped semiconductor portion. Additionally, it prevents the first and second regions located on the same side of the first surface from having a smaller width due to a larger platform region width W. This allows for a larger passivation contact area between the first and / or second doped semiconductor portions and the semiconductor substrate, facilitating carrier collection and reducing the carrier recombination rate.

[0016] As one possible implementation, the surface height of the platform area is approximately the same as the surface height of the second area along the direction from the second surface to the first surface.

[0017] In the above-described technical solution, during the actual manufacturing process, after the first doped semiconductor portion is formed in the first region, a deposition process is required to form a full-coverage isolation layer. Next, the isolation layer is selectively etched to expose at least the second region used to fabricate the second doped semiconductor portion. Then, the second doped semiconductor portion is formed on the second region, and the first and second doped semiconductor portions are isolated to form a groove. Based on this, when the surface height of the plateau region is approximately the same as the surface height of the second region, it indicates that after selective etching of the isolation layer, the etchant did not further erode the semiconductor substrate, resulting in a larger light absorption depth in the portion of the semiconductor substrate corresponding to the second region, which is beneficial for improving the light utilization rate of the semiconductor substrate.

[0018] As one possible implementation, an isolation layer is disposed on the first connection region and extends to cover at least a portion of the platform region. In this case, the isolation layer has a larger formation area on the first side, which helps to reduce the leakage risk at the edge of the first doped semiconductor portion.

[0019] As one possible implementation, no isolation layer is provided on the second connection region. In this case, it indicates that the portion corresponding to the second connection region was etched during the patterning process of the second doped semiconductor portion, specifically the portion of the semiconductor substrate in the third region. This facilitates the complete removal of the portion of the second doped semiconductor portion located at the bottom of the trench, reducing the risk of leakage current in the third region.

[0020] As one possible implementation, the second doped semiconductor portion does not extend into the edge region of the isolation layer near the first doped semiconductor portion. In this case, after patterning, the coverage area of ​​the second doped semiconductor portion remaining on the first side on the isolation layer is small, reducing the risk of leakage at the edge of the isolation layer.

[0021] As one possible implementation, when the first side includes a first connection region, a plateau region, and a second connection region, the second doped semiconductor portion and / or isolation layer are locally distributed on the plateau region. In this case, the formation range of the second doped semiconductor portion and / or isolation layer on the plateau region is small, which reduces the risk of leakage current and also reduces the photoparasitic absorption of the second doped semiconductor portion and / or isolation layer, thereby improving the bifaciality of the back contact cell.

[0022] As one possible implementation, the first region includes a first sub-region and a second sub-region located outside the first sub-region. The surface reflectivity of the second sub-region is greater than that of the first sub-region. In this case, the first sub-region has a lower surface reflectivity, which is beneficial for improving its light-trapping effect and increasing the bifaciality of the back contact cell. In addition, the second sub-region located outside the first sub-region has a higher surface reflectivity, resulting in a relatively smaller specific surface area. This is beneficial for improving the formation quality of the isolation layer on the edge portion of the first doped semiconductor portion, enhancing the protective effect of the isolation layer on the edge portion of the first doped semiconductor portion, and further reducing the leakage risk at the edge portion of the first doped semiconductor portion.

[0023] As one possible implementation, the surfaces of the second sub-region and the second sub-region are staggered along the thickness direction of the semiconductor substrate. In this case, not only can the light absorption area of ​​the first region be increased, but the one with the smaller height between the first and second sub-regions can also cooperate with the side surface used to connect the two to change the light transmission path, thereby facilitating light absorption.

[0024] As one possible implementation, the surface of the first sub-region is textured. In this case, the first sub-region has a higher light-trapping effect, improving the bifaciality of the back-contact battery.

[0025] As one possible implementation, the surface of the second sub-region is planar. In this case, the surface of the second sub-region is relatively flat, which is beneficial to the formation quality of the isolation layer on the edge portion of the first doped semiconductor portion, improves the protective effect of the isolation layer on the edge portion of the first doped semiconductor portion, and further reduces the leakage risk of the edge portion of the first doped semiconductor portion.

[0026] As one possible implementation, the surface of the first region is textured. In this case, the first region has a higher light-trapping effect, improving the bifaciality of the back contact battery.

[0027] As one possible implementation, the first doped semiconductor portion is a doped region disposed within the first region. In this case, compared to the first doped semiconductor portion being a semiconductor layer disposed on the first region, when the first doped semiconductor portion is disposed within the first region, the photoparasitic absorption of the first doped semiconductor portion can be reduced, and the bifaciality of the back contact cell can be improved.

[0028] As one possible implementation, the surface of the second region is planar. In this case, it is beneficial to improve the formation quality of the second doped semiconductor portion on the second region and the field passivation effect, and reduce the carrier recombination rate.

[0029] As one possible implementation, the back contact battery also includes a first interface passivation layer disposed between the second doped semiconductor portion and the semiconductor substrate.

[0030] As one possible implementation, when the back contact battery also includes a first interface passivation layer, the thickness of the isolation layer is greater than the thickness of the first interface passivation layer. This configuration gives the isolation layer a higher diffusion barrier effect. Therefore, even during actual manufacturing, when the second doped semiconductor portion is doped, the dopant can diffuse downwards through the second doped semiconductor portion into the first interface passivation layer and the isolation layer. However, the isolation layer's barrier reduces or even prevents the dopant from diffusing into the portion of the semiconductor substrate near the edge of the first doped semiconductor portion, lowering the carrier recombination rate at that edge. Simultaneously, it ensures that the edge portion of the first doped semiconductor portion has a higher carrier collection efficiency, which is beneficial for improving the conversion efficiency of the back contact battery in the forward voltage region.

[0031] In a second aspect, the present invention provides a photovoltaic module comprising: a battery string and an encapsulation layer. The battery string is formed by the electrical connection of multiple back-contact batteries as provided in the first aspect and its various implementations; the encapsulation layer covers the surface of the battery string.

[0032] The beneficial effects of the second aspect and its various implementations in this invention can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0033] Thirdly, the present invention provides a method for manufacturing a back contact battery, the method comprising: first, providing a semiconductor substrate. The semiconductor substrate includes a first surface and a second surface opposite to each other. The first surface includes alternating first and second regions, and a third region located between the first and second regions. Next, forming a first doped semiconductor portion in the first region of the semiconductor substrate. The second and third regions of the semiconductor substrate are etched such that, along the direction from the second surface to the first surface, the surface height of the second and third regions is less than the surface height of the first region. Next, forming an isolation layer on the portion of the third region near the first region. Next, forming a second doped semiconductor portion on the second region of the semiconductor substrate and on the side of the isolation layer away from the semiconductor substrate. The doping type of the second doped semiconductor portion is opposite to that of the first doped semiconductor portion. Next, etching a portion of the third region of the semiconductor substrate so that the bottom surface of the third region is recessed into the semiconductor substrate relative to the surfaces of the first and second regions, respectively, forming a groove. The groove has a first side surface near the first region and a second side surface near the second region.

[0034] As one possible implementation, a first doped semiconductor portion is formed in a first region of the semiconductor substrate, including: forming the first doped semiconductor portion on a first surface. Next, the first doped semiconductor portions located in the second and third regions are selectively removed.

[0035] As one possible implementation, the first region includes a first sub-region and a second sub-region located outside the first sub-region. In this case, after providing a semiconductor substrate, before forming a first doped semiconductor portion in the first region of the semiconductor substrate, the method for manufacturing the back contact cell further includes: texturing the entire first surface. Next, the second sub-region, the second region, and the third region are planarized to make the surface reflectivity of the second sub-region greater than that of the first sub-region.

[0036] As one possible implementation, the first region includes a first sub-region and a second sub-region located outside the first sub-region. In this case, after providing a semiconductor substrate, before forming a first doped semiconductor portion in the first region of the semiconductor substrate, the method for manufacturing the back contact cell further includes: forming a mask layer on a first surface. The mask layer is used to expose the first sub-region. Next, under the protection of the mask layer, the first sub-region is textured so that the surface reflectivity of the first sub-region is less than the surface reflectivity of the second sub-region.

[0037] The beneficial effects of the third aspect and its various implementations in this invention can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here. Attached Figure Description

[0038] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0039] Figure 1 A longitudinal cross-sectional view of a first structure of a back-contact battery provided in an embodiment of the present invention;

[0040] Figure 2 This is an enlarged schematic diagram of a first structure of a back contact battery at the first side surface provided in an embodiment of the present invention.

[0041] Figure 3 A longitudinal cross-sectional view of a second structure of a back-contact battery provided in an embodiment of the present invention;

[0042] Figure 4 A longitudinal cross-sectional view of a third structure of a back-contact battery provided in an embodiment of the present invention;

[0043] Figure 5 A longitudinal cross-sectional view of a fourth structure of a back-contact battery provided in an embodiment of the present invention;

[0044] Figure 6 A longitudinal cross-sectional view of the fifth structure of the back contact battery provided in an embodiment of the present invention;

[0045] Figure 7 This is an enlarged schematic diagram of a second structure of a back contact battery at the first side provided in an embodiment of the present invention.

[0046] Figure 8 This is an enlarged schematic diagram of a third structure of a back-contact battery at the first side surface provided in an embodiment of the present invention.

[0047] Figure 9 This is a schematic diagram of the structure of the back contact battery during the manufacturing process provided in an embodiment of the present invention. Figure 1 ;

[0048] Figure 10 This is a schematic diagram of the structure of the back contact battery during the manufacturing process provided in an embodiment of the present invention. Figure 2 ;

[0049] Figure 11 A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 3 ;

[0050] Figure 12 A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 4 ;

[0051] Figure 13 A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 5 ;

[0052] Figure 14 A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 6 ;

[0053] Figure 15 A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 7 ;

[0054] Figure 16 A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 8 ;

[0055] Figure 17 A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 9 ;

[0056] Figure 18 A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 10 ;

[0057] Figure 19 A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 10 one;

[0058] Figure 20 A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 10 two;

[0059] Figure 21 A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 10 three;

[0060] Figure 22 A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 10 Four;

[0061] Figure 23 A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 10 five;

[0062] Figure 24 A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 10six;

[0063] Figure 25 A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 10 seven;

[0064] Figure 26 A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 10 eight;

[0065] Figure 27 A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 10 Nine;

[0066] Figure 28 A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 2 ten;

[0067] Figure 29 A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 2 eleven;

[0068] Figure 30 A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 2 twelve;

[0069] Figure 31 A schematic diagram of the back contact battery during the manufacturing process provided in this embodiment of the invention. Figure 2 Thirteen.

[0070] Reference numerals: 11 is semiconductor substrate, 12 is first region, 13 is second region, 14 is third region, 15 is groove, 16 is first side surface, 17 is second side surface, 18 is first doped semiconductor section, 19 is isolation layer, 20 is second doped semiconductor section, 21 is first connection region, 22 is plateau region, 23 is second connection region, 24 is first sub-region, 25 is second sub-region, 26 is mask layer, 27 is second interface passivation layer, 28 is first interface passivation layer. Detailed Implementation

[0071] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the invention. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0072] The accompanying drawings illustrate various structural schematic diagrams according to embodiments of the present invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0073] In the context of this invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0074] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0075] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0076] Solar cells are increasingly widely used as a new energy alternative. Photovoltaic solar cells, in particular, are devices that convert sunlight into electrical energy. Specifically, solar cells utilize the photovoltaic principle to generate charge carriers, which are then extracted using electrodes, thus facilitating the efficient use of electrical energy. When both the positive and negative electrodes of a solar cell are located on the back side of the cell, it is called a back-contact cell. Because the front side of a back-contact cell is not obstructed by metal electrodes, it has a higher short-circuit current I. sc This is one of the current technological directions for achieving high-efficiency crystalline silicon solar cells.

[0077] Specifically, existing back-contact batteries include at least a semiconductor substrate and a first doped semiconductor portion and a second doped semiconductor portion formed on a portion of the back side of the semiconductor substrate. The first doped semiconductor portion and the second doped semiconductor portion have opposite doping types and are spaced apart in a direction parallel to the back side to prevent short circuits.

[0078] In the actual manufacturing process of the aforementioned back-contact battery, a first doped semiconductor layer is first formed on one side of the back of the semiconductor substrate, and then the first doped semiconductor layer in a portion of the back side is selectively removed. However, because the first doped semiconductor layer contains impurities, there is an etching rate difference between itself and the semiconductor substrate, resulting in the edge portion of the first doped semiconductor layer being suspended on the semiconductor substrate after selective etching. In this case, after forming the first doped semiconductor layer, in the process of forming the second doped semiconductor layer, a second doped semiconductor material layer is formed on one side of the back of the semiconductor substrate, and then the second doped semiconductor material layer located on the first doped semiconductor layer and the back side portion is selectively removed to obtain the second doped semiconductor layer. However, the second doped semiconductor material layer filling the gap between the suspended edge portion of the first doped semiconductor layer and the semiconductor substrate is difficult to remove. This residual second doped semiconductor material will at least be electrically connected to the sidewall of the first doped semiconductor layer, resulting in a high risk of leakage on the back side of the existing back-contact battery, which is not conducive to improving the conversion efficiency of the back-contact battery.

[0079] To address the aforementioned technical problems, in a first aspect, embodiments of the present invention provide a back-contact battery. For example... Figure 1 and Figure 2As shown, the back contact battery includes: a semiconductor substrate 11, a first doped semiconductor portion 18, an isolation layer 19, and a second doped semiconductor portion 20. The semiconductor substrate 11 includes a first surface and a second surface opposite to each other. The first surface includes alternating first regions 12 and second regions 13, and a third region 14 located between the first regions 12 and 13. The bottom surface of the third region 14 is recessed into the semiconductor substrate 11 relative to the surfaces of the first regions 12 and 13, forming a groove 15. The groove 15 has a first side surface 16 near the first region 12 and a second side surface 17 near the second region 13. Along the direction from the second surface to the first surface, the surface height of the second region 13 is less than the surface height of the first region 12. The first doped semiconductor portion 18 is disposed in the first region 12. The isolation layer 19 is disposed at least on the portion of the first side surface 16 near the opening of the groove 15. The second doped semiconductor portion 20 is disposed on the second region 13 and on the side of the isolation layer 19 facing away from the semiconductor substrate 11. The doping types of the second doped semiconductor portion 20 and the first doped semiconductor portion 18 are opposite.

[0080] When the above technical solution is adopted, such as Figure 1 and Figure 2 As shown, in the back contact battery provided in this embodiment of the invention, the surface height of the second region 13 where the second doped semiconductor portion 20 is disposed is less than the surface height of the first region 12 where the first doped semiconductor portion 18 is disposed, so that the surfaces of the first region 12 and the second region 13 can be offset along the thickness direction of the semiconductor substrate 11. In this case, during the actual manufacturing process of the back contact battery, after patterning the entire layer of the first doped semiconductor portion 18, it is advantageous to completely remove the first doped semiconductor portion 18 located in the second region 13, reducing the leakage risk of the second region 13 while enabling the second doped semiconductor portion 20 to have a higher carrier collection efficiency. Furthermore, as... Figure 1As shown, the bottom surface of the third region 14 is recessed into the semiconductor substrate 11 relative to the surfaces of the first region 12 and the second region 13, respectively. The resulting groove 15 is used to further cut off the leakage path between the first doped semiconductor portion 18 and the second doped semiconductor portion 20, reducing the leakage risk on the first side. Furthermore, the groove 15 has a first side surface 16 near the first region 12, and an isolation layer 19 is provided on at least the portion of the first side surface 16 near the groove opening of the groove 15. In other words, the isolation layer 19 is provided at least on the portion of the first side surface 16 near the first doped semiconductor portion 18. Therefore, even during actual manufacturing, due to the difference in etching rates between the first doped semiconductor portion 18 and the semiconductor substrate 11, after selective etching of the entire layer of the first doped semiconductor portion 18, the edge portion of the first doped semiconductor portion 18 near the third region 14 is suspended above the partial groove 15. This makes it difficult to completely remove the portion of the second doped semiconductor portion 20 deposited between the suspended edge portion and the semiconductor substrate 11. In this case, the isolation layer 19 can be used to isolate the first doped semiconductor portion 18 and the remaining second doped semiconductor portion 20, reducing the risk of leakage at the edge portion of the first doped semiconductor portion 18. At the same time, the presence of the isolation layer 19 can also prevent the dopant from entering the portion of the semiconductor substrate 11 near the first doped semiconductor portion 18 through the second doped semiconductor portion 20 during doping treatment, reducing the carrier recombination rate at the edge portion of the first doped semiconductor portion 18. This also results in a higher carrier collection efficiency at the edge portion of the first doped semiconductor portion 18, which is beneficial for improving the conversion efficiency of the back contact battery. Furthermore, it is understandable that the presence of the isolation layer 19 can reduce the leakage risk of the back contact battery. Given that the back contact battery has a small reverse leakage current, the requirements for manufacturing the electrode structure using laser sintering technology can be met. Based on this, manufacturing the electrode structure of the back contact battery provided in this embodiment of the invention using laser sintering not only allows for the formation of a metal-semiconductor alloy with low contact resistivity through the high temperature generated during laser sintering, improving contact performance, but also enables the use of semi-burn-through electrode paste (with low glass content), which is difficult to use in conventional high-temperature sintering processes. This reduces damage to the surface passivation layer, resulting in a larger passivation contact area between the surface passivation layer and one side of the first surface, thus reducing the carrier recombination rate.

[0081] In practical applications, the embodiments of the present invention do not specifically limit the material and doping type of the semiconductor substrate. For example, the semiconductor substrate described above can be a silicon substrate. Alternatively, the semiconductor substrate can also be a substrate made of any semiconductor material, such as a germanium-silicon substrate, a germanium substrate, or a gallium arsenide substrate.

[0082] In terms of doping type, semiconductor substrates can be P-type substrates, N-type substrates, or intrinsic substrates.

[0083] Furthermore, the first surface of the aforementioned semiconductor substrate corresponds to the backlight surface of the back contact battery, and the second surface of the semiconductor substrate corresponds to the light-facing surface (directly illuminated surface) of the back contact battery. The distribution of the first, second, and third regions on the first surface can be determined based on the distribution of the first and second doped semiconductor portions formed on one side of the first surface. Specifically, since the first doped semiconductor portion of the back contact battery is disposed in the first region, the distribution range of the first region on the first surface can be determined based on the distribution requirements of the first doped semiconductor portion in the actual application scenario. Since the second doped semiconductor portion of the back contact battery is disposed on the second region of the first surface, the distribution range of the second region on the first surface can be determined based on the distribution requirements of the second doped semiconductor portion on the semiconductor substrate in the actual application scenario. Additionally, since the bottom surface of the third region is recessed into the semiconductor substrate relative to the surfaces of the first and second regions, the range of the third region on the first surface can be determined based on the first and second side surfaces of the recess in the third region as boundaries.

[0084] It is understandable that the first region roughly corresponds to the first emitter region, and the second region roughly corresponds to the second emitter region; one of the first and second regions is roughly the P region, and the other is roughly the N region, while the third region is the PN region isolation area.

[0085] In terms of surface morphology, the first surface can also be planar. Alternatively, the second surface of the semiconductor substrate can be textured to improve its light-trapping effect and increase the photoelectric conversion efficiency of the back-contact battery. In this case, the embodiments of the present invention do not specifically limit the morphology of the textured structure on the second surface, and it can be a pyramid-shaped textured structure, a V-groove textured structure, or a perforated textured structure, etc.

[0086] As for the first side, such as Figure 1 As shown, the surface of the first region 12 can be textured. In this case, each area of ​​the surface of the first region 12 has a textured structure, which helps the first region 12 to have a higher light-trapping effect and improve the bifaciality of the back contact battery. In this case, each area of ​​the surface of the first region 12 can have approximately the same surface reflectivity.

[0087] Alternatively, the surface of the first region can also be planar. In this case, when the first doped semiconductor portion is disposed on the first region, it is beneficial to improve the formation quality of the first doped semiconductor portion and the field passivation effect.

[0088] Or, as Figure 3 and Figure 4As shown, the first region 12 may include a first sub-region 24 and a second sub-region 25 located outside the first sub-region 24. Furthermore, the surface reflectivity of the second sub-region 25 may be greater than that of the first sub-region 24. In this case, the first sub-region 24 has a lower surface reflectivity, which is beneficial for improving its light-trapping effect and increasing the bifaciality of the back contact cell. It also helps to increase the contact area of ​​the electrode structure disposed in the middle region of the first doped semiconductor portion 18, improving contact performance. Additionally, the second sub-region 25 located outside the first sub-region 24 has a higher surface reflectivity, resulting in a relatively smaller specific surface area. This is beneficial for improving the formation quality of the isolation layer 19 on the edge portion of the first doped semiconductor portion 18, enhancing the protective effect of the isolation layer 19 on the edge portion of the first doped semiconductor portion 18, and further reducing the leakage risk at the edge portion of the first doped semiconductor portion 18.

[0089] In this embodiment of the invention, there are no specific limitations on the area ratio of the first sub-region and the second sub-region within the first region, or on the surface morphology of the first sub-region and the second sub-region, as long as the surface reflectivity of the first sub-region is less than that of the second sub-region.

[0090] Specifically, the first and second sub-regions can have the same type of texture structure on their surfaces, but the one-dimensional dimensions (and / or distribution density) of the texture structure in the first sub-region are different from those in the second sub-region, so that the surface reflectivities of the first and second sub-regions are different. For example, both the first and second sub-regions can have a pyramidal velvet structure, and the one-dimensional dimensions (such as the base side length or diagonal length, side edge length or height) and / or distribution density of the pyramidal velvet structure in the first sub-region are smaller than those in the second sub-region.

[0091] Alternatively, the types of texture structures on the surfaces of the first and second sub-regions can also be different.

[0092] Optional, such as Figure 3 and Figure 4 As shown, the surface of the first sub-region 24 can be textured. In this case, it is beneficial for the first sub-region 24 to have a higher light-trapping effect, thereby improving the bifaciality of the back contact battery. In this case, the morphology of the textured structure on the first sub-region 24 is not specifically limited in this embodiment of the invention, and it can be a pyramid-shaped textured structure, a V-groove textured structure, or a perforated textured structure, etc.

[0093] Optional, such as Figure 3 and Figure 4As shown, the surface of the second sub-region 25 is planar. In this case, the surface of the second sub-region 25 is relatively flat, which is beneficial to the formation quality of the isolation layer 19 on the edge portion of the first doped semiconductor portion 18, improves the protective effect of the isolation layer 19 on the edge portion of the first doped semiconductor portion 18, and further reduces the leakage risk of the edge portion of the first doped semiconductor portion 18.

[0094] Furthermore, along the thickness direction of the semiconductor substrate, the surface of the second sub-region can be flush with the surface of the second sub-region. Or, as... Figure 3 and Figure 4 As shown, along the thickness direction of the semiconductor substrate 11, the surfaces of the second sub-region 25 and the second sub-region 25 can also be staggered. In this case, not only can the light absorption area of ​​the first region 12 be increased, but the one with the smaller height between the first sub-region 24 and the second sub-region 25 can also cooperate with the side surface used to connect the two to change the light transmission path, which is beneficial to light absorption.

[0095] The height at which the first and second sub-regions are offset in the semiconductor substrate thickness direction can be set according to the surface morphology of the first and second sub-regions and actual needs, and no specific limitation is made here.

[0096] Furthermore, in the case where the second side is velvet and at least a portion of the first area is velvet, such as Figure 1 , Figure 3 and Figure 4 As shown, the surface reflectivity of the second surface can be less than or equal to the surface reflectivity of the velvet area in the first region 12. For example, when at least a portion of the first region 12 and the second surface have a pyramidal velvet structure, the one-dimensional dimension (such as the base side length or diagonal length, side edge length or height) and / or distribution density of the pyramidal velvet structure in at least a portion of the first region 12 are respectively less than the one-dimensional dimension and / or distribution density of the pyramidal velvet structure in the second surface.

[0097] As for the second zone, such as Figure 1 , Figure 3 and Figure 4 As shown, the surface of the second region 13 can be planar. In this case, it is beneficial to improve the formation quality of the second doped semiconductor section 20 on the second region 13 and the field passivation effect, and reduce the carrier recombination rate.

[0098] Alternatively, the surface of the second region can be textured to increase the contact area between the second doped semiconductor portion disposed on the second region and the electrode structure, thereby improving contact performance.

[0099] As for the third zone, the bottom surface of the groove in the third zone can be a plane; or, as... Figure 1 , Figure 3 and Figure 4 As shown, the bottom surface of the groove 15 can also be a velvety surface to further improve the bifaciality of the back contact battery.

[0100] Where at least a portion of the first region and the bottom surface of the groove are velvety, the one-dimensional dimension of the velvety structure in the first region and the one-dimensional dimension of the velvety structure on the bottom surface of the groove can be the same or different.

[0101] Optionally, the dimensional uniformity and / or distribution uniformity of the textured structure in the first region can be greater than that of the textured structure on the bottom surface of the groove. And / or, the surface reflectivity of the textured region in the first region can be less than the surface reflectivity of the bottom surface of the groove. And / or, the lateral dimension of the textured structure in the first region (the lateral dimension is approximately perpendicular to the thickness direction of the semiconductor substrate; for example, when the textured structure is a pyramidal textured structure, the lateral dimension can be the side length of the base or the diagonal length) can be smaller than the lateral dimension of the textured structure on the bottom surface of the groove. In this case, the etching solution used for texturing achieves a higher degree of etching on the semiconductor substrate corresponding to the third region, which helps to further reduce the risk of leakage current and the carrier recombination rate, while improving the yield of electrode structures manufactured using laser sintering technology.

[0102] Furthermore, when both the second surface and the bottom surface of the groove are velvety, the one-dimensional dimension of the velvety structure on the second surface and the one-dimensional dimension of the velvety structure on the bottom surface of the groove can be the same or different.

[0103] Optionally, the dimensional uniformity and / or distribution uniformity of the textured structure in the second surface can be greater than that of the textured structure in the bottom surface of the groove. And / or, the surface reflectivity of the textured region in the second surface can be less than the surface reflectivity of the bottom surface of the groove. And / or, the lateral dimension of the textured structure in the second surface (which is approximately perpendicular to the thickness direction of the semiconductor substrate) can be smaller than the lateral dimension of the textured structure in the bottom surface of the groove. The beneficial effects in this case can be found above and will not be repeated here.

[0104] The first and second sides of the groove can be planar, or they can be provided with a textured surface. Furthermore, at least a portion of the first and / or second side can be parallel to the thickness direction of the semiconductor substrate, or it can be inclined to the thickness direction of the semiconductor substrate (the inclination angle can be set according to actual needs). The angles between the surfaces of different regions of the first and / or second side and the thickness direction of the semiconductor substrate can be approximately the same.

[0105] Or, such as Figure 2 , Figure 7 and Figure 8As shown, in the width direction of the third region 14, the first side surface 16 may include a first connection region 21, a platform region 22, and a second connection region 23 sequentially distributed along the direction close to the second region 13. The surface of the platform region 22 is substantially perpendicular to the thickness direction of the semiconductor substrate 11. The surfaces of the first connection region 21 and / or the second connection region 23 are arranged perpendicularly or obliquely relative to the surface of the platform region 22. In this case, the first side surface 16 not only includes the first connection region 21 and the second connection region 23 arranged parallel or obliquely to the thickness direction of the semiconductor substrate 11, but also includes the platform region 22 substantially perpendicular to the thickness direction of the semiconductor substrate 11. The presence of the platform region 22 not only helps to increase the light absorption area of ​​the first side surface 16, but also cooperates with the portion of the first doped semiconductor portion 18 extending above the partial groove 15 to change the light transmission path, which helps to refract more light into the semiconductor substrate 11, thereby improving the bifaciality of the back contact battery. Furthermore, the presence of the platform region 22 also serves as a buffer during the formation of the surface passivation layer on one side of the first surface, improving the coverage of the surface passivation layer on the first side 16, enhancing the passivation effect of the surface passivation layer on the first side 16, and reducing the carrier recombination rate. Additionally, when the electrode structure of the back contact battery provided in this embodiment of the invention is manufactured using laser sintering, reducing the carrier recombination rate, i.e., reducing leakage current, also helps to improve the quality of the formed electrode structure, improve contact performance, and ultimately improve the conversion efficiency of the back contact battery.

[0106] It is understandable that the heights of the first and second connection regions on the first side, and the angles between the first and second connection regions and the thickness direction of the semiconductor substrate, will affect the recess depth of the groove, thereby affecting the leakage prevention effect between the first and second doped semiconductor portions. Secondly, the isolation layer covers at least the portion of the first side near the groove opening. Since the first connection region and the platform region on the first side are closer to the groove opening, the height of the first connection region, the angle between the first connection region and the thickness direction of the semiconductor substrate, and the width of the platform region will affect the surface area of ​​the portion of the first side near the groove opening and the range of the isolation layer, thus affecting carrier recombination at the edge of the first doped semiconductor portion. Therefore, the heights of the first and second connection regions on the first side, the angles between the first and second connection regions and the thickness direction of the semiconductor substrate, and the width of the platform region can be determined based on the leakage requirements of one side of the first side in the actual application scenario; no specific limitations are made here.

[0107] Define the height of the first interconnect region as H along the thickness direction of the semiconductor substrate. Define the width of the plateau region as W along the width direction of the third region.

[0108] For example, H can be greater than or equal to 0.1 μm and less than or equal to 5 μm. In this case, the height H of the first connection region is within the above range, which helps to prevent the formation range of the isolation layer on the first side from being too small due to H being too small, and further reduces the leakage risk of the edge portion of the first doped semiconductor portion; in addition, it can also prevent the portion of the semiconductor substrate corresponding to the third region and the second region from being over-etched due to the height of the first connection region being too large, so that each part of the semiconductor substrate has a large light absorption depth, improves the light utilization rate of the semiconductor substrate, and helps to improve the conversion efficiency of the back contact battery.

[0109] For example, W can be greater than or equal to 0.1 μm and less than or equal to 8 μm. In this case, the width W of the platform region is within the above range, which can prevent the weak height buffering effect and small light absorption area caused by the small width of the platform region, further improving the coverage of the surface passivation layer on the first side and increasing the bifaciality of the back contact cell. Secondly, when the isolation layer is also disposed on the platform region, it can also prevent the formation range of the isolation layer from being small due to the small width W of the platform region, reducing the leakage risk at the edge of the first doped semiconductor portion. In addition, it can also prevent the width of the first region and the second region located on the first side from being small due to the large width W of the platform region, which is beneficial to have a large passivation contact area between the first doped semiconductor portion and / or the second doped semiconductor portion and the semiconductor substrate, which is beneficial to the collection of charge carriers and reduces the recombination rate of charge carriers.

[0110] For example, the difference between H and W can be greater than or equal to 0 and less than or equal to 3 μm. The application principle of the beneficial effect in this case can refer to the application principle of the beneficial effect described above, where H can be greater than or equal to 0.1 μm and less than or equal to 5 μm, and W can be greater than or equal to 0.1 μm and less than or equal to 8 μm, which will not be repeated here.

[0111] In terms of surface height, such as Figure 1 As shown, along the direction from the second surface to the first surface, the surface height of the second region 13 is less than the surface height of the first region 12. The height difference between the two can be determined based on the requirements of the carrier recombination rate of the second region 13, the carrier collection efficiency of the second doped semiconductor section 20, and the light absorption depth of the semiconductor substrate 11 in the second region 13 in the actual application scenario, and is not specifically limited here.

[0112] As for the depth of the groove, it can be determined based on the leakage prevention requirements between the first doped semiconductor section and the second doped semiconductor section in the actual application scenario, as well as the light absorption depth requirements of the semiconductor substrate in the third region. No specific limit is made here.

[0113] Furthermore, when the first side includes the aforementioned first connecting area, platform area, and second connecting area, the surface height of the platform area can be greater than the surface height of the second area in the direction from the second side to the first side.

[0114] Or, such as Figure 1 As shown, along the direction from the second surface to the first surface, the surface height of the platform region 22 is approximately the same as the surface height of the second region 13. In this case, during the actual manufacturing process, the formation of the platform region 22 may be due to the isolation layer 19 covering it and the precision of the patterning process. Specifically, after the first doped semiconductor portion 18 is formed in the first region 12, a full-layer isolation layer 19 needs to be formed using a deposition process; then, the isolation layer 19 is selectively etched to expose at least the second region 13 used to manufacture the second doped semiconductor portion 20; after the patterning process, in order to retain the isolation layer 19 covering the sidewalls and surrounding areas of the first doped semiconductor portion 18, an excessive portion of the isolation layer 19 covering the platform region 22 is reserved. Next, the second doped semiconductor portion 20 is formed on the second region 13, and the first doped semiconductor portion 18 and the second doped semiconductor portion 20 are isolated to form a groove 15. Based on this, when the surface height of the platform region 22 is approximately the same as the surface height of the second region 13, it indicates that after selective etching of the isolation layer 19, the etchant did not further etch the semiconductor substrate 11 downwards, so that the part of the semiconductor substrate 11 corresponding to the second region 13 has a larger light absorption depth, which is beneficial to improving the light utilization rate of the semiconductor substrate 11.

[0115] Regarding the first doped semiconductor section and the second doped semiconductor section, in terms of their placement, such as Figure 1 As shown, the first doped semiconductor portion 18 can be a doped region disposed within the first region 12. In this case, compared to the first doped semiconductor portion 18 being a semiconductor layer disposed on the first region 12, when the first doped semiconductor portion 18 is disposed within the first region 12, the photoparasitic absorption of the first doped semiconductor portion 18 can be reduced, thereby increasing the bifaciality of the back contact cell.

[0116] Or, such as Figure 5 As shown, the first doped semiconductor portion 18 can also be a doped semiconductor layer disposed on the first region 12 to reduce the carrier recombination rate. In this case, the material of the first doped semiconductor portion 18 can include any semiconductor material such as silicon, silicon germanium, germanium, or gallium arsenide. In terms of the arrangement of matter, the crystal phase of the first doped semiconductor portion 18 can be amorphous, microcrystalline, nanocrystalline, single crystal, or polycrystalline.

[0117] In practical applications, the first doped semiconductor portion can be directly formed on the first region of the semiconductor substrate. Or, as... Figure 5As shown, the back contact battery also includes a second interface passivation layer 27 located between the first region 12 and the first doped semiconductor portion 18 of the semiconductor substrate 11. In this case, the second interface passivation layer 27 and the first doped semiconductor portion 18 can form a selective contact structure to achieve chemical passivation of the corresponding region on the first surface of the semiconductor substrate 11 and selective collection of carriers of the corresponding conductivity type, thereby reducing the carrier recombination rate on the first surface and improving the photoelectric conversion efficiency of the back contact battery.

[0118] Specifically, the material of the second interface passivation layer can be determined based on the material of the first doped semiconductor part and the type of selective contact structure composed of the second interface passivation layer and the first doped semiconductor part in the actual application scenario, and no specific limitation is made here.

[0119] For example, when the selective contact structure formed by the second interface passivation layer and the first doped semiconductor portion is a tunneling passivation contact structure, the first doped semiconductor portion is a doped polysilicon layer, and the second interface passivation layer is a tunneling passivation layer. The material of the tunneling passivation layer may include materials such as silicon oxide, aluminum oxide, or titanium oxide.

[0120] For example, when the selective contact structure formed by the second interface passivation layer and the first doped semiconductor portion is a heterogeneous contact structure, the material of the first doped semiconductor portion may include at least one of doped amorphous silicon, doped nanocrystalline silicon, and doped microcrystalline silicon, and the second interface passivation layer may be at least one of intrinsic amorphous silicon, intrinsic nanocrystalline silicon, and intrinsic microcrystalline silicon.

[0121] In addition, such as Figure 1 As shown, the first doped semiconductor section 18 can be provided only in the first region 12. In this case, the distance between the first doped semiconductor section 18 and the second doped semiconductor section 20 is larger along the width direction of the third region 14, which helps to reduce the risk of leakage.

[0122] Or, such as Figure 6As shown, in the width direction of the third region 14, the first doped semiconductor portion 18 may also extend above the portion of the groove 15 along the direction close to the second region 13. In this case, when the back contact battery provided in this embodiment of the invention is in operation, light is refracted from one side of the second surface into the semiconductor substrate 11 along the direction from the second surface to the first surface. After absorbing photon energy, the semiconductor substrate 11 can generate electrons and holes. Furthermore, the electrons and holes move towards the first doped semiconductor portion 18 and the second doped semiconductor portion 20, respectively, and are eventually discharged by the corresponding electrodes to form a photocurrent. However, the light entering the semiconductor substrate 11 is not completely absorbed and utilized by the semiconductor substrate 11; some light is refracted out from one side of the first surface of the semiconductor substrate 11. In this case, the first doped semiconductor portion 18 located on one side of the first surface of the semiconductor substrate 11 extends above the portion of the groove 15 along the direction close to the second region 13. At this time, the end of the first doped semiconductor section 18 adjacent to the third region 14 is suspended. Some of the light refracted from one side of the first surface of the semiconductor substrate 11 can return to the semiconductor substrate 11 under the reflection of the end of the first doped semiconductor section 18 adjacent to the third region 14 and suspended, and be absorbed and utilized by the semiconductor substrate 11. This can increase the utilization rate of light by the back contact battery and help improve the photoelectric conversion efficiency of the back contact battery.

[0123] As for the length of the portion of the first doped semiconductor extending above the partial groove, it can be set according to actual needs, and no specific limit is made here.

[0124] As for the second doped semiconductor section, the material of the second doped semiconductor section can be a semiconductor material such as silicon, germanium silicon, germanium, or gallium arsenide. The crystal phase of the second doped semiconductor section can be amorphous, nanocrystalline, microcrystalline, single crystal, or polycrystalline. Furthermore, the embodiments of the present invention do not specifically limit the thickness of the second doped semiconductor section, as long as it can be applied to the back contact battery provided in the embodiments of the present invention.

[0125] Optional, such as Figure 5 As shown, the back contact battery provided in this embodiment of the invention may further include a first interface passivation layer 28 located between the semiconductor substrate 11 and the second doped semiconductor portion 20. In this case, the first interface passivation layer 28 and the second doped semiconductor portion 20 can form a selective contact structure to achieve chemical passivation of the second region 13 and selective collection of carriers of the corresponding conductivity type, thereby reducing the carrier recombination rate on the first side and improving the photoelectric conversion efficiency of the back contact battery.

[0126] As for the material of the first interface passivation layer, the principle for determining it can be referred to the principle for determining the material of the second interface passivation layer described above, and will not be repeated here.

[0127] In terms of doping type, the first doped semiconductor portion can be N-type and the second doped semiconductor portion can be P-type. Alternatively, the first doped semiconductor portion can be P-type and the second doped semiconductor portion can be N-type.

[0128] Optionally, the first doped semiconductor region is a P-type doped region disposed within the first region. The second doped semiconductor region is an N-type doped polysilicon layer disposed on the second region, and the back contact cell further includes a tunneling oxide layer disposed between the N-type doped semiconductor layer and the semiconductor substrate.

[0129] Furthermore, in practical applications, the boundary of the portion of the second doped semiconductor disposed on the isolation layer can be aligned with the boundary of the isolation layer.

[0130] Alternatively, the second doped semiconductor portion may not extend to the edge region of the isolation layer near the first doped semiconductor portion. In this case, after patterning, the coverage area of ​​the second doped semiconductor portion remaining on the first side on the isolation layer is smaller, reducing the risk of leakage at the edge of the isolation layer. In this case, the distance between the boundary of the portion of the second doped semiconductor portion on the isolation layer and the boundary of the isolation layer can be set according to actual needs, and is not specifically limited here.

[0131] like Figure 2 , Figure 7 and Figure 8 As shown, when the first side 16 includes a first connection region 21, a platform region 22, and a second connection region 23, the second doped semiconductor portion 20 may be located only in the first connection region 21, or only in the platform region 22, or simultaneously in both the first connection region 21 and the platform region.

[0132] Wherein, when at least a portion of the second doped semiconductor portion is disposed on the first connection region, the second doped semiconductor portion may cover the area above each region of the first connection region; or, it may be partially distributed above the first connection region. Where at least a portion of the second doped semiconductor portion is disposed on the plateau region, the second doped semiconductor portion may cover the plateau region; or, it may be partially distributed on the plateau region.

[0133] It is worth noting that when the second doped semiconductor is locally distributed on the plateau region, the formation range of the second doped semiconductor on the plateau region is small, which reduces the risk of leakage current and also reduces the photoparasitic absorption of the second doped semiconductor, thereby improving the bifaciality of the back contact cell.

[0134] Secondly, the second doped semiconductor portion may not be disposed on the second connection region.

[0135] Regarding the isolation layer, this embodiment of the invention does not specifically limit the material and thickness of the isolation layer, as long as it can effectively separate the first doped semiconductor portion and the second doped semiconductor portion. The isolation layer can be a single-layer structure or a stacked structure formed by multiple materials. The isolation layer can be an insulating layer or a semi-insulating layer with a certain electrical isolation effect.

[0136] For example, the isolation layer may include a silicon oxide layer and / or a silicon nitride layer, etc.

[0137] Secondly, when the back contact battery also includes a first interface passivation layer, the first interface passivation layer is located between the second doped semiconductor portion and the isolation layer. The thickness of the isolation layer can be greater than the thickness of the first interface passivation layer to achieve higher electrical insulation and dopant diffusion resistance. The material of the isolation layer can be the same as that of the first interface passivation layer. In this case, the total thickness of the stack formed by the isolation layer and the first interface passivation layer located between the third region of the semiconductor substrate and the second doped semiconductor portion is greater than the thickness of the first interface passivation layer located between the second region of the semiconductor substrate and the second doped semiconductor portion. The presence of the isolation layer can be determined based on this thickness relationship.

[0138] Alternatively, at least a portion of the material of the isolation layer may be different from the material of the first interface passivation layer. In this case, the isolation layer and the first interface passivation layer located in the third region can be distinguished by the different types of materials.

[0139] In addition, the formation range of the isolation layer on the first side can be determined according to the morphology of the first side and the leakage prevention requirements of the edge portion of the first doped semiconductor in the actual application scenario, and is not specifically limited here.

[0140] Optionally, the isolation layer may be provided only on the portion of the first side near the groove opening. Alternatively, when the groove depth is small, the isolation layer may be provided on the area of ​​the first side other than near the bottom of the groove.

[0141] For example, in the case where the first side includes a first connection area, a platform area, and a second connection area, such as Figure 2 As shown, isolation layer 19 can be disposed only on the first connection area 21. Or, as... Figure 8 As shown, isolation layer 19 can also be set only on platform area 22. Alternatively, as... Figure 7 As shown, the isolation layer 19 can also be disposed on the first connection region 21 and extend to cover at least a portion of the platform region 22. In this case, the isolation layer 19 has a larger formation area on the first side surface 16, which helps to reduce the leakage risk at the edge of the first doped semiconductor portion 18.

[0142] When the isolation layer is also disposed on the first connection region, the isolation layer may be disposed only on a portion of the first connection region, or it may cover all regions of the first connection region. Additionally, when the isolation layer is also disposed on the platform region, the isolation layer may cover all regions of the platform region, or it may be partially distributed on the platform region. In this case, the formation area of ​​the isolation layer on the platform region is smaller, reducing the risk of leakage current and also reducing the impact of the isolation layer on light absorption, thereby improving the bifaciality of the back contact battery.

[0143] Additionally, optional, such as Figure 2 , Figure 7 and Figure 8 As shown, no isolation layer 19 is provided on the second connection region 23. In this case, it indicates that the portion corresponding to the second connection region 23 was etched in the third region 14 of the semiconductor substrate 11 during the patterning process of the second doped semiconductor portion 20. This facilitates the complete removal of the portion of the second doped semiconductor portion 20 located at the bottom of the groove 15, reducing the risk of leakage at the third region 14.

[0144] In addition to being disposed on the first side of the groove, when the first doped semiconductor portion extends above a portion of the groove, an isolation layer may also be disposed on the side of the first doped semiconductor portion extending above the groove, closer to the semiconductor substrate, to further reduce the risk of leakage.

[0145] Secondly, embodiments of the present invention provide a photovoltaic module, which includes: a battery string and an encapsulation layer. The battery string is formed by electrically connecting multiple back-contact batteries as provided in the first aspect and its various implementations; the encapsulation layer covers the surface of the battery string.

[0146] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0147] Thirdly, embodiments of the present invention provide a method for manufacturing a back-contact battery. The following will describe, based on... Figures 9 to 31 The cross-sectional view shown illustrates the manufacturing process. Specifically, the manufacturing method of this back contact battery includes:

[0148] First, a semiconductor substrate is provided. The semiconductor substrate includes a first surface and a second surface opposite to each other. The first surface includes a first region and a second region that are alternately distributed, and a third region located between the first region and the second region. The material of the semiconductor substrate, and the distribution range of the first region, the second region and the third region in the first surface, can be referred to the previous text, and will not be repeated here.

[0149] It is understandable that the different surface morphologies of the first region lead to different operational processes for forming the first doped semiconductor portion in the first region of the semiconductor substrate.

[0150] For example, if the first region is planar, then after providing a semiconductor substrate with a first planar surface, the subsequent formation operation of the first doped semiconductor portion can be performed directly.

[0151] For example, such as Figure 9 As shown, if the first region 12 is textured, then at least one side of the first surface of the semiconductor substrate 11 can be textured before the first doped semiconductor portion is formed.

[0152] For example, if the first region includes the first sub-region described above and the second sub-region located outside the first sub-region, then after providing a semiconductor substrate, and before forming the first doped semiconductor portion in the first region of the semiconductor substrate, as follows: Figure 9 As shown, wet etching and other processes are used to first texture the entire first surface. Next, as... Figure 16 As shown, wet etching and other processes can be used to planarize the second sub-region 25, the second sub-region 13 and the third sub-region 14 (e.g., polishing) so that the surface reflectivity of the second sub-region 25 is greater than that of the first sub-region 24.

[0153] Alternatively, if the first region includes a first sub-region and a second sub-region, this can also be done after providing a semiconductor substrate and before forming the first doped semiconductor portion in the first region of the semiconductor substrate, such as... Figure 23 As shown, a mask layer 26 can be formed on the first surface by sequentially employing processes such as deposition and etching (the material of the mask layer 26 can be set according to actual needs. For example, the material of the mask layer 26 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide). The mask layer 26 is used to expose the first sub-region 24. Next, as... Figure 24 As shown, under the protection of the mask layer 26, the first sub-region 24 is textured so that the surface reflectivity of the first sub-region 24 is less than that of the second sub-region 25. Then, the mask layer is selectively removed.

[0154] Next, as Figure 10 , Figure 11 , Figure 17 , Figure 18 , Figure 26 and Figure 27 As shown, a first doped semiconductor portion 18 is formed in the first region 12 of the semiconductor substrate 11; and the second region 13 and the third region 14 of the semiconductor substrate 11 are etched so that the surface height of the second region 13 and the third region 14 is less than the surface height of the first region 12 in the direction from the second surface to the first surface.

[0155] In the actual manufacturing process, such as Figure 10 , Figure 17 and Figure 26 As shown, if the first doped semiconductor portion 18 is a doped region disposed within the first region 12, a doping process such as diffusion or ion implantation can be used to dope the first surface, thus forming the first doped semiconductor portion 18 on the first surface. Alternatively, if the first doped semiconductor portion is a doped semiconductor layer disposed on the first region, a process such as physical vapor deposition can be used to first form an intrinsic semiconductor portion on the first surface; then, a process such as diffusion or ion implantation can be used to dope the intrinsic semiconductor portion to form the first doped semiconductor portion. Next, as... Figure 11 , Figure 18 and Figure 27 As shown, wet etching or laser etching processes can be used to selectively remove the first doped semiconductor portion 18 located in the second region 13 and the third region 14. Specifically, the mask layer used in the selective etching process can be a doped silicon glass layer formed during the doping treatment of the first doped semiconductor portion 18. By heat-treating the portions of the doped silicon glass layer located in the second region 13 and the third region 14, the density and corrosion resistance of the doped silicon glass layer in the second region 13 and the third region 14 are reduced, and the portion of the doped silicon glass layer located in the first region 12 forms a mask layer. Alternatively, after removing the doped silicon glass layer, or directly forming an additional mask layer on the doped silicon glass layer, and at least patterning the mask layer, the first doped semiconductor portion 18 located in the second region 13 and the third region 14 can be exposed.

[0156] After selectively etching the first doped semiconductor portion, the second and third regions of the semiconductor substrate can be etched under the protection of the same mask layer, so that the surface height of the second and third regions is less than the surface height of the first region along the direction from the second surface to the first surface. It should be noted that because the first doped semiconductor portion contains dopant, the etching rate of the first doped semiconductor portion and the semiconductor substrate may differ. Therefore, after etching the portions of the first doped semiconductor portion and the semiconductor substrate located in the second and third regions, the edge portion of the first doped semiconductor portion may be suspended above a portion of the third region.

[0157] In addition, if the first doped semiconductor portion is a doped semiconductor layer disposed on the first region, and the back contact battery also includes a second interface passivation layer, then before forming the intrinsic semiconductor portion, a process such as thermal oxidation or chemical vapor deposition is required to form the second interface passivation layer.

[0158] Next, as Figure 12 , Figure 13 , Figure 19 and Figure 20 , Figure 28 and Figure 29 As shown, an isolation layer 19 is formed at least on the portion of the third zone 14 that is close to the first zone 12.

[0159] In the actual manufacturing process, physical vapor deposition can be used to form a continuous isolation layer. Then, processes such as laser etching can be used to remove at least the isolation layer located in the second region.

[0160] Next, as Figure 14 , Figure 15 , Figure 21 , Figure 22 , Figure 30 and Figure 31 As shown, a second doped semiconductor portion 20 is formed on the second region 13 of the semiconductor substrate 11 and on the side of the isolation layer 19 opposite to the semiconductor substrate 11. The doping type of the second doped semiconductor portion 20 is opposite to that of the first doped semiconductor portion 18.

[0161] In the actual manufacturing process, such as Figure 14 , Figure 21 and Figure 30 As shown, a second doped semiconductor portion 20, which is formed as a single layer, can be created using processes such as physical vapor deposition. Then, as... Figure 15 , Figure 22 and Figure 31 As shown, an etching process is used to selectively remove the second-doped semiconductor portion 20 located in the first region 12 and the third region 14. Because the first-doped semiconductor portion 18 is suspended above the edge portion of the third region 14, the second-doped semiconductor portion 20 near the edge of the first region 12 is difficult to completely remove, leaving residue. The pre-formed isolation layer 19 not only prevents the etchant from entering the portion of the semiconductor substrate 11 around the edge of the first region 12 during the fabrication of the second-doped semiconductor portion 20, but also isolates the remaining second-doped semiconductor portion 20 from the edge portion of the first-doped semiconductor portion 18 and the portion of the semiconductor substrate 11 around the edge of the first region 12 after the second-doped semiconductor portion 20 is formed, reducing leakage current.

[0162] Next, as Figure 15 , Figure 22 and Figure 31 As shown, wet etching or similar processes can be used to etch a portion of the third region 14 of the semiconductor substrate 11, causing the bottom surface of the third region 14 to be recessed into the semiconductor substrate 11 relative to the surfaces of the first region 12 and the second region 13, forming a groove 15. The groove 15 has a first side 16 near the first region 12 and a second side 17 near the second region 13. Information regarding the depth and surface morphology of the groove 15 can be found in the preceding text and is not specifically limited here.

[0163] Next, processes such as laser sintering can be used to form electrode structures on the first doped semiconductor part and the second doped semiconductor part, respectively.

[0164] The beneficial effects of the third aspect and its various implementations in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0165] The above description does not provide detailed explanations of the technical aspects of each layer's patterning and etching. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0166] The embodiments of the present invention have been described above. However, these embodiments are merely for clarity and are not intended to limit the scope of the invention. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A back-contact battery, characterized in that, include: A semiconductor substrate includes a first surface and a second surface opposite to each other; the first surface includes an alternately spaced first region and a second region, and a third region located between the first region and the second region; the bottom surface of the third region is recessed into the semiconductor substrate relative to the surfaces of the first region and the second region, respectively, to form a groove; the groove has a first side surface near the first region and a second side surface near the second region; along the direction from the second surface to the first surface, the surface height of the second region is less than the surface height of the first region; A first doped semiconductor portion is disposed in the first region; An isolation layer is provided at least on the portion of the first side near the groove opening; A second doped semiconductor portion is disposed on the second region and on the side of the isolation layer opposite to the semiconductor substrate; the doping type of the second doped semiconductor portion is opposite to that of the first doped semiconductor portion.

2. The back contact battery according to claim 1, characterized in that, In the width direction of the third region, the first doped semiconductor portion extends further over a portion of the groove in a direction close to the second region.

3. The back contact battery according to claim 1, characterized in that, In the width direction of the third region, the first side includes a first connection region, a platform region, and a second connection region that are sequentially and continuously distributed along the direction close to the second region; the surface of the platform region is substantially perpendicular to the thickness direction of the semiconductor substrate; the surfaces of the first connection region and / or the second connection region are arranged perpendicularly or obliquely relative to the surface of the platform region.

4. The back contact battery according to claim 3, characterized in that, Along the thickness direction of the semiconductor substrate, the height of the first connection region is H; along the width direction of the third region, the width of the platform region is W; wherein H is greater than or equal to 0.1 μm and less than or equal to 5 μm; and / or W is greater than or equal to 0.1 μm and less than or equal to 8 μm; and / or the difference between H and W is greater than or equal to 0 and less than or equal to 3 μm; And / or, along the direction from the second surface to the first surface, the surface height of the platform area is approximately the same as the surface height of the second area.

5. The back contact battery according to claim 3, characterized in that, The isolation layer is disposed on the first connection area and extends to cover at least a portion of the platform area; And / or, the isolation layer is not provided on the second connection area.

6. The back contact battery according to any one of claims 1 to 5, characterized in that, The second doped semiconductor portion does not extend into the edge region of the isolation layer near the first doped semiconductor portion; And / or, in the case where the first side includes the first connection region, the platform region and the second connection region, the second doped semiconductor portion and / or the isolation layer are partially distributed on the platform region.

7. The back contact battery according to claim 1, characterized in that, The first region includes a first sub-region and a second sub-region located outside the first sub-region; the surface reflectivity of the second sub-region is greater than that of the first sub-region.

8. The back contact battery according to claim 7, characterized in that, Along the thickness direction of the semiconductor substrate, the surfaces of the second sub-region and the second sub-region are staggered. And / or, the surface of the first sub-region is velvety; And / or, the surface of the second sub-region is a plane.

9. The back contact battery according to any one of claims 1 to 5, characterized in that, The surface of the first area is velvety; And / or, the first doped semiconductor portion is a doped region disposed within the first region; And / or, the surface of the second region is planar; And / or, the back contact battery further includes a first interface passivation layer disposed between the second doped semiconductor portion and the semiconductor substrate.

10. The back contact battery according to claim 9, characterized in that, When the back contact battery further includes the first interface passivation layer, the thickness of the isolation layer is greater than the thickness of the first interface passivation layer.

11. A photovoltaic module, characterized in that, include: A battery string, wherein the battery string is formed by electrically connecting a plurality of back-contact batteries as described in any one of claims 1 to 10; And an encapsulation layer that covers the surface of the battery string.

12. A method for manufacturing a back-contact battery, characterized in that, include: A semiconductor substrate is provided; the semiconductor substrate includes a first surface and a second surface opposite to each other; the first surface includes a first region and a second region that are alternately distributed, and a third region located between the first region and the second region; A first doped semiconductor portion is formed in a first region of the semiconductor substrate; and the second and third regions of the semiconductor substrate are etched such that, along the direction from the second surface to the first surface, the surface height of the second and third regions is less than the surface height of the first region. An isolation layer is formed on the portion of the third region adjacent to the first region; A second doped semiconductor portion is formed on the second region of the semiconductor substrate and on the side of the isolation layer opposite to the semiconductor substrate; the doping type of the second doped semiconductor portion is opposite to that of the first doped semiconductor portion; A portion of the third region of the semiconductor substrate is etched so that the surface of the third region is recessed into the semiconductor substrate relative to the surfaces of the first region and the second region, respectively, to form a groove; the groove has a first side surface near the first region and a second side surface near the second region.

13. The method for manufacturing a back contact battery according to claim 12, characterized in that, The process of forming a first doped semiconductor portion in a first region of the semiconductor substrate includes: The first doped semiconductor portion is formed on the first surface; The first doped semiconductor portion located in the second region and the third region is selectively removed.

14. The method for manufacturing a back contact battery according to claim 13, characterized in that, The first region includes a first sub-region and a second sub-region located outside the first sub-region; After providing a semiconductor substrate, and before forming a first doped semiconductor portion in a first region of the semiconductor substrate, the method for manufacturing the back contact cell further includes: The entire first surface is textured; The second sub-region, the second region, and the third region are flattened to make the surface reflectivity of the second sub-region greater than that of the first sub-region.

15. The method for manufacturing a back contact battery according to claim 13, characterized in that, The first region includes a first sub-region and a second sub-region located outside the first sub-region; After providing a semiconductor substrate, and before forming a first doped semiconductor portion in a first region of the semiconductor substrate, the method for manufacturing the back contact cell further includes: A mask layer is formed on the first surface; the mask layer is used to expose the first sub-region; Under the protection of the mask layer, the first sub-region is textured so that the surface reflectivity of the first sub-region is less than that of the second sub-region.

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