Solar cell, photovoltaic module and photovoltaic system

Abstract

The invention is applicable to the technical field of photovoltaic cells, and provides a solar cell which comprises a silicon substrate and a dielectric film layer, and the silicon substrate comprises a first side surface and a second side surface which are opposite to each other along a first direction and a first surface and a second surface which are opposite to each other along a second direction. The dielectric film layer comprises a first dielectric film layer and a second dielectric film layer, the first dielectric film layer covers the first doping layer and at least partial region of at least one of the first side surface and the second side surface, and the second dielectric film layer covers the second doping layer and at least partial region of at least one of the first side surface and the second side surface; the first side face is provided with a first film covering area, the first side face comprises a first area arranged on the first film covering area and a second area not located in the first film covering area, and the first area is covered with a first dielectric film layer and avoids the second area. Through the arrangement of the avoidance second area, internal ions are promoted to be discharged, and the technical problem that a traditional full-coverage film layer hinders charge release is solved.

Description

Technical Field

[0001] This invention belongs to the field of photovoltaic cell technology, and particularly relates to a solar cell, a photovoltaic module, and a photovoltaic system. Background Technology

[0002] As the core component of a photovoltaic power generation system, the performance of solar cells directly affects the power generation efficiency of the entire system. In existing technologies, to improve the photoelectric conversion efficiency and long-term stability of cells, the common method is to deposit dielectric films on the cell surface. These dielectric films mainly include materials such as SiOx, AlOx, SiNx, and SiOxNy, used to achieve functions such as surface passivation, reducing light reflection, and blocking the intrusion of external impurity ions.

[0003] However, this traditional dielectric film design has significant technical drawbacks: on the one hand, while it effectively blocks the intrusion of external sodium ions, thus suppressing the PID effect, on the other hand, this full-coverage film structure also severely hinders the removal of hydrogen and sodium ions accumulated inside the battery. When solar cell modules operate in a high-voltage environment for extended periods, leakage current occurs between the glass and the encapsulation material, leading to a large accumulation of charge on the battery surface. This phenomenon significantly deteriorates surface passivation performance, specifically manifested in a substantial decrease in key performance parameters such as the fill factor, open-circuit voltage, and short-circuit current of the battery module. More seriously, in extreme cases, the PID effect can cause module power loss exceeding 50%, which not only severely impacts the power generation efficiency of the photovoltaic system but also reduces the overall system's operational stability. Furthermore, existing dielectric film structures often employ a uniform coverage approach, lacking targeted protection for specific areas on the sides of the battery, further limiting the potential for performance improvement. Summary of the Invention

[0004] The solar cell provided in this invention aims to solve the technical problem that existing solar cells are prone to performance degradation in long-term high-voltage environments.

[0005] The present invention is implemented as follows: a solar cell includes: A silicon substrate, the silicon substrate including a first side surface and a second side surface opposite each other along a first direction; The silicon substrate includes a first surface and a second surface opposite to each other along a second direction, wherein a first doped layer is disposed on the first surface and a second doped layer is disposed on the second surface; A dielectric film layer, the dielectric film layer including a first dielectric film layer and a second dielectric film layer, the first dielectric film layer covering at least a portion of the first doped layer and at least one of the first side and the second side, the second dielectric film layer covering at least a portion of the second doped layer and at least one of the first side and the second side; The first side is provided with a first coating area, the first side includes a first area disposed on the first coating area and a second area not located in the first coating area, the first area is covered with the first dielectric film layer and avoids the second area.

[0006] Furthermore, the first side is also provided with a second coating area, and the first side includes a third area disposed on the second coating area, the third area being covered by the second dielectric film layer and avoiding the second area.

[0007] Furthermore, the dielectric film layer also includes a third dielectric film layer, which covers at least a portion of the first dielectric film layer and at least one of the first side surface and the second side surface.

[0008] Furthermore, when the first region on the first side is covered with the third dielectric film layer, the first dielectric film layer on the first region is covered with the third dielectric film layer.

[0009] Furthermore, the dielectric film layer further includes a fourth dielectric film layer, which covers at least a portion of the second dielectric film layer and at least one of the first side surface and the second side surface.

[0010] Furthermore, when the third region on the first side is covered with the fourth dielectric film layer, the second dielectric film layer on the third region is covered with the fourth dielectric film layer.

[0011] Furthermore, the second side is provided with a third coating area, the second side including a fourth region disposed on the third coating area and a fifth region not located in the third coating area, the fourth region being covered by the first dielectric film layer and avoiding the fifth region.

[0012] Furthermore, the second side also has a fourth coating area, and the second side includes a sixth region disposed on the fourth coating area, the sixth region being covered by the second dielectric film layer and avoiding the fifth region.

[0013] Furthermore, the dielectric film layer also includes a third dielectric film layer, which covers at least a portion of the first dielectric film layer and at least one of the first side surface and the second side surface.

[0014] Furthermore, when the third dielectric film layer covers the fourth region on the second side, the third dielectric film layer covers the first dielectric film layer on the fourth region.

[0015] Furthermore, the dielectric film layer further includes a fourth dielectric film layer, which covers at least a portion of the second dielectric film layer and at least one of the first side surface and the second side surface.

[0016] Furthermore, when the sixth region on the second side is covered with the fourth dielectric film layer, the second dielectric film layer on the sixth region is covered with the fourth dielectric film layer.

[0017] Furthermore, the first side has a first extended region that protrudes outward from the second region. The first extended region includes a third surface and a third side adjacent to the first surface. The first dielectric film layer covers the third surface and avoids the third side.

[0018] Furthermore, the second side has a second extended region that protrudes outward from the fifth region. The second extended region includes a fourth surface and a fourth side adjacent to the fourth surface. The first dielectric film layer covers the fourth surface and avoids the fourth side.

[0019] Furthermore, the width of the first extended region along the first direction is greater than or equal to 100 μm.

[0020] Furthermore, the width of the second extended region along the first direction is greater than or equal to 100 μm.

[0021] Furthermore, the vertical height of the innermost layer of the first surface of the silicon substrate and the innermost layer of the third surface along the second direction is greater than or equal to 200 nm.

[0022] Furthermore, the vertical height of the innermost layer of the first surface of the silicon substrate and the innermost layer of the third surface along the second direction is greater than or equal to 500 nm.

[0023] Furthermore, the vertical height of the innermost layer of the first surface of the silicon substrate and the innermost layer of the third surface along the second direction is greater than or equal to 5 μm.

[0024] Furthermore, the vertical height of the innermost layer of the first surface of the silicon substrate and the innermost layer of the fourth surface along the second direction is greater than or equal to 200 nm.

[0025] Furthermore, the vertical height of the outermost layer of the first surface of the silicon substrate and the outermost layer of the third surface along the second direction is greater than or equal to 50 nm.

[0026] Furthermore, the vertical height of the outermost layer of the first surface of the silicon substrate and the outermost layer of the third surface along the second direction is greater than or equal to 500 nm.

[0027] Furthermore, the vertical height of the outermost layer of the first surface of the silicon substrate and the outermost layer of the third surface along the second direction is greater than or equal to 1 μm.

[0028] Furthermore, the vertical height of the outermost layer of the first surface of the silicon substrate and the outermost layer of the fourth surface along the second direction is greater than or equal to 50 nm.

[0029] Furthermore, a first electrode is also disposed on the first surface, and the first electrode is connected to the first doped layer through the dielectric film layer located on the first surface; A second electrode is also disposed on the second surface, and the second electrode is connected to the second doped layer through the dielectric film layer located on the second surface.

[0030] Furthermore, a tunneling oxide layer is disposed between the second surface of the silicon substrate and the second doped layer.

[0031] Furthermore, the first dielectric film layer and the second dielectric film layer are composed of one or more of the following: oxide layer, nitride layer, oxynitride layer, carbide layer, and amorphous silicon layer.

[0032] Furthermore, the tunneling oxide layer is one or more of the following: oxide layer, nitride layer, oxynitride layer, carbide layer, and amorphous silicon layer.

[0033] A photovoltaic module includes a plurality of solar cell strings, each solar cell string including a plurality of electrically connected solar cells, wherein the solar cells are any of the solar cells described above.

[0034] A photovoltaic system comprising the photovoltaic modules described above.

[0035] The beneficial effects achieved by the present invention are that by setting a selectively covered dielectric film structure on at least one of the first and second sides of the silicon substrate, it can effectively block external ions and promote the discharge of internal ions by setting a second area that avoids them. This solves the technical problem of traditional full-coverage film layers that hinder charge release. It has the advantages of blocking the intrusion of external impurity ions while promoting the discharge of internal ions, effectively balancing the surface passivation and charge release requirements, and improving battery performance and stability. Attached Figure Description

[0036] Figure 1 This is a cross-sectional schematic diagram of the solar cell provided in an embodiment of the present invention; Figure 2 This is another cross-sectional schematic diagram of the solar cell provided in an embodiment of the present invention; Figure 3 This is another cross-sectional schematic diagram of the solar cell provided in an embodiment of the present invention; Figure 4 This is another cross-sectional schematic diagram of the solar cell provided in an embodiment of the present invention; Figure 5 This is another cross-sectional schematic diagram of the solar cell provided in the embodiment of the present invention; Figure 6 This is another cross-sectional schematic diagram of the solar cell provided in the embodiment of the present invention; Figure 7 This is another cross-sectional schematic diagram of the solar cell provided in the embodiment of the present invention; Figure 8 This is another cross-sectional schematic diagram of the solar cell provided in the embodiment of the present invention; Figure 9 This is another cross-sectional schematic diagram of the solar cell provided in an embodiment of the present invention; Figure 10 This is another cross-sectional schematic diagram of the solar cell provided in an embodiment of the present invention; Figure 11 This is another cross-sectional schematic diagram of the solar cell provided in an embodiment of the present invention; Figure 12 This is another cross-sectional schematic diagram of the solar cell provided in an embodiment of the present invention. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0038] In existing technologies, to improve the photoelectric conversion efficiency and long-term stability of solar cells, a common method is to deposit dielectric films on the cell surface. These dielectric films mainly include materials such as SiOx, AlOx, SiNx, and SiOxNy, used to achieve surface passivation, reduce light reflection, and block the intrusion of external impurity ions. This traditional dielectric film design has significant technical drawbacks: on the one hand, although it can effectively block the intrusion of external sodium ions, thereby suppressing the PID effect; on the other hand, this full-coverage film structure also severely hinders the discharge of hydrogen and sodium ions accumulated inside the cell. When solar cell modules are in a high-voltage operating environment for a long time, leakage current will occur between the glass and the encapsulation material, causing a large amount of charge to accumulate on the cell surface. This phenomenon will significantly deteriorate the surface passivation performance, specifically manifested as a significant decrease in key performance parameters of the cell module such as fill factor, open-circuit voltage, and short-circuit current. More seriously, in extreme cases, the PID effect can lead to a power loss of over 50% in the module. This not only severely affects the power generation efficiency of the photovoltaic system but also reduces the operational stability of the entire system. Furthermore, existing dielectric film structures often employ a uniform coverage method, lacking targeted protection for specific areas on the sides of the cell, further limiting the potential for performance improvement. This application solves the technical problem of traditional full-coverage films hindering charge release by setting a selectively covering dielectric film structure on at least one of the first and second sides of the silicon substrate. This effectively blocks external ions while promoting internal ion discharge through the avoidance of the second area, thus addressing the issue of traditional full-coverage films hindering charge release. It offers advantages such as blocking external impurity ions while promoting internal ion discharge, effectively balancing surface passivation and charge release requirements, and improving cell performance and stability.

[0039] Example 1 Please see Figure 1 The present invention is implemented as follows: a solar cell 1000 includes: Silicon substrate 10, the silicon substrate 10 includes a first side surface 80 and a second side surface 90 opposite to each other along a first direction A; The silicon substrate 10 includes a first surface 101 and a second surface 102 opposite to each other along the second direction B. A first doped layer 20 is disposed on the first surface 101 and a second doped layer 30 is disposed on the second surface 102. The dielectric film layer includes a first dielectric film layer 40 and a second dielectric film layer 50. The first dielectric film layer 40 covers at least a portion of a first doped layer 20 and at least one of a first side surface 80 and a second side surface 90. The second dielectric film layer 50 covers at least a portion of a second doped layer 30 and at least one of a first side surface 80 and a second side surface 90. The first side 80 is provided with a first coating area 801. The first side 80 includes a first region 802 disposed on the first coating area 801 and a second region 803 not located on the first coating area 801. The first region 802 is covered with a first dielectric film layer 40 and avoids the second region 803.

[0040] In this embodiment, the silicon substrate 10 refers to a semiconductor substrate with a crystal structure, which can be formed by processing single-crystal silicon or polycrystalline silicon wafers, and its first surface 101 and second surface 102 form the emitter and base region, respectively. The first doped layer 20 refers to the N-type doped layer formed by diffusion of group V elements such as phosphorus, nitrogen, and arsenic. Specifically, it can be doped at high temperature using a tube diffusion furnace to establish a PN junction structure. The second doped layer 30 refers to a P-type doped layer formed by diffusion of group III elements such as boron, aluminum, and gallium. Specifically, it can be prepared by ion implantation combined with annealing process to form the back field structure of the battery. In some embodiments, the first doped layer 20 may also refer to a P-type doped layer formed by diffusion of group III elements such as boron, aluminum, and gallium, and the second doped layer 30 refers to a P-type doped layer formed by diffusion of group V elements such as phosphorus, nitrogen, and arsenic, without limitation.

[0041] The first dielectric film layer 40 avoids the second region 803. The first dielectric film layer 40 refers to an insulating layer with passivation function, which is composed of one or more of oxide layer, nitride layer, oxynitride layer, carbide layer, and amorphous silicon layer. Its thickness is controlled at the nanometer level, which effectively balances the surface passivation and charge release requirements, and improves the battery performance and stability. Of course, in other embodiments, the first dielectric film layer 40 can also be made of other materials. The specific materials can be considered according to the actual situation and are not limited here. For example, in other embodiments, the first dielectric film layer 40 can also be made of fluoride or transparent conductive oxide, which is not limited here. The first coating area 801 refers to the predetermined coverage area on the side, which can be specifically defined by the mask patterning process. The first area 802 is covered by the dielectric film layer while the second area 803 remains exposed, forming an ion dissipation channel.

[0042] Specifically, the first doped layer 20 and the second doped layer 30 of the silicon substrate 10 form the positive and negative electrode contact areas of the battery, respectively, and the dielectric film layer forms a continuous coverage on the surface to ensure passivation. In the side region, the first dielectric film layer 40 only covers the first region 802 within the first coating area 801, while the second region 803 remains uncoated. This exposed area provides a path for the hydrogen and sodium ions accumulated inside to escape. During battery operation, internal ions diffuse outward through the second side region 803, avoiding excessive accumulation at the interface. At the same time, the dielectric film layer covering the first region 802 can still prevent external sodium ions from penetrating from the side, maintaining the integrity of the surface passivation layer. This selective coating design achieves a dynamic balance of ion migration, both inhibiting the intrusion of external impurities and promoting the expulsion of internal ions.

[0043] Furthermore, the solar cell 1000 can be a TOPCon cell, an HJT cell, or an SHJ cell. Of course, in other embodiments, it can also be a cell other than the above-mentioned cell types. The specific type can be selected according to the actual situation. It is only necessary to deposit intrinsic and amorphous silicon thin films (ia-Si / H) and doped amorphous silicon thin films (p-type / n-type a-Si) on the front and back sides of the N-type silicon wafer to form a PN junction.

[0044] This embodiment effectively solves the technical problem of the dielectric film layer hindering the expulsion of internal ions. The second region 803 of the first side 80 is a non-coated region. The formation of the non-coated region provides an escape channel for internally accumulated ions, reduces the degree of interfacial charge accumulation, and thus maintains the stability of the surface passivation layer. This configuration allows the solar cell 1000 to prevent the intrusion of external sodium ions while promoting the expulsion of internal hydrogen and sodium ions, achieving a dynamic balance in ion migration and significantly improving the reliability of the solar cell 1000 under long-term high-voltage operating conditions.

[0045] It should be noted that in this embodiment, a textured structure (not shown in the figure) is also provided. Specifically, the textured structure can be provided on the first surface 101 and / or the second surface 102 of the silicon substrate 10. That is to say, it is mainly provided between the first doped layer 20 and the silicon substrate 10 and / or between the second doped layer 30 and the silicon substrate 10. By providing the textured structure, the reflectivity of sunlight is effectively reduced, and the propagation path of light in the silicon substrate 10 is increased, thereby greatly enhancing the ability of the solar cell 1000 to capture and absorb light energy, laying the foundation for improving the short-circuit current and the final conversion efficiency.

[0046] In this embodiment, the surface of the textured structure is uniformly covered with a tunneling oxide layer (not shown in the figure), and is mainly disposed between the second surface 102 and the second doped layer 30 of the silicon substrate 10 (common in TOPCon cells). The tunneling oxide layer is composed of one or more of oxide layers, nitride layers, oxynitride layers, carbide layers, and amorphous silicon layers. Of course, in other embodiments, the tunneling oxide layer can also be made of other materials. The setting of the tunneling oxide layer can realize the efficient and selective tunneling transport of charge carriers, and at the same time greatly reduce the surface recombination loss caused by the direct contact between the metal electrode and the silicon substrate 10, thereby significantly improving the open circuit voltage and fill factor.

[0047] In other embodiments, the tunneling oxide layer can be simultaneously disposed between the first surface 101 and the first doped layer 20 of the silicon substrate 10 and between the second surface 102 and the second doped layer 30 of the silicon substrate 10 (common in HJT cells and SHJ cells). The specific design can be made according to the actual situation and is not limited here.

[0048] Example 2 Please see Figure 2 Furthermore, the first side 80 is also provided with a second coating area 804, and the first side 80 includes a third area 805 disposed on the second coating area 804, the third area 805 being covered with a second dielectric film layer 50 and avoiding the second area 803.

[0049] The second coating region 804 refers to a functional area on the first side 80 of the silicon substrate 10 specifically used for arranging the second dielectric film layer 50. Its boundary range can be defined by photolithography masking process to achieve selective deposition of the dielectric film layer. The third region 805 refers to the portion of the second coating region 804 covered by the second dielectric film layer 50. Its area ratio can be controlled by adjusting the mask pattern size. The second dielectric film layer 50 refers to the passivation layer disposed on the surface of the second doped layer 30. Its material can be composed of one or more of oxide layers, nitride layers, oxynitride layers, carbide layers, and amorphous silicon layers. It is mainly used to block external ion penetration. Of course, in other embodiments, the second dielectric film layer 50 can also be made of other materials. The specific materials can be considered according to the actual situation and are not limited here. For example, in other embodiments, the second dielectric film layer 50 can also be made of fluoride or transparent conductive oxide, which is not limited here.

[0050] As can be seen from this embodiment and the embodiments described above, the second coating region 804 divides the first side surface 80 into a functionally defined third region 805 and a second region 803. The second dielectric film layer 50 covers the third region 805, using its dense structure to prevent external sodium ions from penetrating into the silicon substrate 10; while the second region 803 remains uncovered by the dielectric film, providing a diffusion path for hydrogen and sodium ions accumulated inside the battery. This partitioned structure allows the ion-blocking function of the dielectric film and the ion-emission function of the uncovered area to complement each other, avoiding the bidirectional ion blocking problem caused by a single dielectric film completely covering the side surface. During operation, external ions are confined outside the third region 805, while internal ions diffuse outward through the second region 803, achieving a dynamic balance in ion migration.

[0051] Specifically, the first coating area 801 may be located near the first surface 101 and the second coating area 804 may be located near the second surface 102.

[0052] Example 3 Please see Figure 3 Furthermore, the dielectric film layer also includes a third dielectric film layer 60, which covers at least a portion of the first dielectric film layer 40 and at least one of the first side surface 80 and the second side surface 90.

[0053] In this embodiment, the third dielectric film layer 60 can be implemented using silicon oxynitride or carbon-doped alumina. The third dielectric film layer 60 not only forms ion diffusion channels through interfacial gaps but also maintains surface passivation, resulting in a simple structure that is easy to implement.

[0054] Furthermore, after the first dielectric film layer 40 is deposited as a basic passivation layer, the third dielectric film layer 60 covers it in a discontinuous form. In the regions of the first side surface 80 and the second side surface 90, the third dielectric film layer 60 and the first dielectric film layer 40 form a stacked structure, and nanoscale gaps are generated at the interface between the two materials. When hydrogen ions and sodium ions migrate outward from inside the battery, they can gradually diffuse to the outside of the film layer through the interface gaps, while external sodium ions are blocked due to the density difference of the multilayer film.

[0055] Example 4 Please see Figure 3 Furthermore, when the first region 802 of the first side 80 is covered with the third dielectric film layer 60, the first dielectric film layer 40 on the first region 802 is covered with the third dielectric film layer 60.

[0056] In this embodiment, the first dielectric film layer 40 comprises silicon oxide, and the third dielectric film layer 60 comprises silicon nitride. In the first region 802, the silicon oxide layer first covers the surface of the silicon substrate 10 to achieve basic passivation, and then the silicon nitride layer is deposited on the surface of the silicon oxide layer in a precisely aligned manner. The silicon oxide layer reduces the surface defect density through chemical bonding, while the silicon nitride layer enhances its ability to block sodium ions with its dense structure. Due to the high hydrogen content of silicon oxide, the hydrogen ions accumulated inside it can diffuse outward through the microporous structure at the interface between silicon oxide and silicon nitride, while external sodium ions are difficult to penetrate in the reverse direction due to the high dielectric strength of silicon nitride.

[0057] It should be noted that the superposition thickness of the first dielectric film layer 40 and the third dielectric film layer 60 needs to be controlled below the critical value to avoid complete blockage of the internal ion migration path due to excessive thickness.

[0058] This configuration establishes a controllable ion migration path in at least a portion of at least one of the first side surface 80 and the second side surface 90 of the silicon substrate 10. This allows accumulated hydrogen ions to diffuse outward through the micropores of the silicon oxide layer, while the high dielectric strength of the silicon nitride layer blocks the intrusion of external sodium ions. The gradient dielectric structure effectively balances the requirements for ion blocking and removal, reducing the risk of surface passivation failure due to charge accumulation, thereby suppressing the occurrence of potential induced decay effects.

[0059] Example 5 Please see Figure 4 Furthermore, the dielectric film layer also includes a fourth dielectric film layer 70, which covers at least a portion of the second dielectric film layer 50 and at least one of the first side surface 80 and the second side surface 90.

[0060] In this embodiment, the fourth dielectric film layer 70 refers to an additional functional layer superimposed on the surface of the second dielectric film layer 50, and can also be implemented using silicon oxynitride or aluminum oxide materials. The fourth dielectric film layer 70 can be formed by chemical vapor deposition, forming a dense structure on the surface of the second dielectric film layer 50 to enhance the ability to block sodium ions.

[0061] Specifically, the fourth dielectric film layer 70 forms a partial covering structure on the surface of the second dielectric film layer 50. Its dense chemical properties effectively block the intrusion of external sodium ions, while the uncovered areas maintain the porous structure of the second dielectric film layer 50, allowing accumulated hydrogen ions to diffuse outward through the pores. During the operation of the solar cell 1000, the fourth dielectric film layer 70 and the second dielectric film layer 50 form a composite protection system. The former is responsible for ion blocking in high-voltage areas, while the latter provides basic passivation. The optimized design of the covered area enables the solar cell 1000 to suppress charge accumulation caused by leakage current and promote the directional migration of internal ions through the exposed areas, even under high potential difference environments.

[0062] Example 6 Please continue reading. Figure 4 Furthermore, when the third region 805 of the first side 80 is covered with the fourth dielectric film layer 70, the second dielectric film layer 50 on the third region 805 is covered with the fourth dielectric film layer 70.

[0063] Specifically, the fourth dielectric film 70 and the second dielectric film 50 form an energy level barrier through interfacial chemical bonding. With this configuration, the band structure selectively accelerates the tunneling effect of hydrogen ions.

[0064] In this embodiment, by forming the aforementioned composite dielectric layer in the third region 805, a controllable ion diffusion channel is established while maintaining the surface passivation layer's ability to suppress carrier recombination. This allows hydrogen ions generated inside the battery to be directionally discharged through the nanopores, while simultaneously blocking the intrusion of sodium ions from the external environment through the band barrier. This reduces the surface potential distortion in the third region 805 caused by ion accumulation, thereby significantly reducing the degradation rate of the solar cell 1000.

[0065] Example 7 Please see Figure 5 Furthermore, the second side 90 is provided with a third coating area 901. The second side 90 includes a fourth region 902 disposed on the third coating area 901 and a fifth region 903 not located in the third coating area 901. The fourth region 902 is covered with a first dielectric film layer 40 and avoids the fifth region 903.

[0066] It should be noted that in the above embodiments one to six, the solar cell 1000 pieces are divided into two pieces, that is, the solar cell 1000 pieces are divided by cutting in the middle. In this embodiment, the solar cell 1000 pieces are divided into three pieces, four pieces, etc. Since the solar cell 1000 pieces located in the middle need to be cut on both sides, uncovered areas can be provided on both the first side 80 and the second side 90 of the silicon substrate 10.

[0067] The third coating area 901 refers to the dielectric film layer coverage area pre-set on the second side 90, which can be implemented by photolithography or masking process, and is used to limit the coverage area of ​​the first dielectric film layer 40. The fourth region 902 refers to the part within the third coating region 901 that actually covers the first dielectric film layer 40. Specifically, it can be formed by chemical vapor deposition or physical vapor deposition to maintain the surface passivation effect. The fifth region 903 refers to the part of the second side 90 that is not covered by the third coating region 901. Specifically, it can be retained by selective etching or masking to form an ion discharge channel.

[0068] Specifically, after dividing the second side 90 into a fourth region 902 and a fifth region 903, the fourth region 902 achieves surface protection by covering the first dielectric film layer 40, while the fifth region 903 forms an open area by avoiding the first dielectric film layer 40. When hydrogen and sodium ions accumulate inside the battery due to the PID effect, the uncovered fifth region 903 allows ions to be discharged outward through diffusion or electric field action, thereby reducing charge accumulation on the battery surface. At the same time, since the fourth region 902 is covered by the first dielectric film layer 40, it can still effectively inhibit the intrusion of external impurities and avoid the degradation of the surface passivation layer performance. This combination of selective coverage and avoidance solves the problem of traditional full-film structures hindering the discharge of internal ions, reduces battery performance degradation caused by the PID effect, and improves the reliability and lifespan of the solar cell 1000.

[0069] Example 8 Please see Figure 6 Furthermore, the second side 90 is also provided with a fourth coating area 904, and the second side 90 includes a sixth region 905 disposed on the fourth coating area 904, the sixth region 905 being covered with a second dielectric film layer 50 and avoiding the fifth region 903.

[0070] The fourth coating area 904 refers to the area pre-set on the second side 90 for covering the second dielectric film layer 50. Specifically, it can be achieved by photolithography mask or laser etching process. By limiting the position and area of ​​the fourth coating area 904, the coverage range of the second dielectric film layer 50 can be controlled. The sixth region 905 refers to the part within the fourth coating area 904 that actually covers the second dielectric film layer 50. Specifically, it can be formed by chemical vapor deposition or physical vapor deposition processes. The setting of the sixth region 905 allows the second side 90 to retain the passivation protection function of the dielectric film layer at a specific location.

[0071] Furthermore, a sixth region 905 is defined on the second side 90 by a fourth coating region 904, and a second dielectric film layer 50 is deposited on the sixth region 905. This maintains passivation protection for a portion of the second side 90, preventing external impurity ions from intruding into the battery. Simultaneously, by avoiding the fifth region 903, the fifth region 903 of the second side 90 becomes an exposed surface. This provides a pathway for the discharge of hydrogen and sodium ions accumulated inside the battery, thereby reducing charge accumulation on the surface of the solar cell 1000 and mitigating the risk of PID effects caused by ion accumulation.

[0072] Example 9 Please see Figure 7Furthermore, the dielectric film layer also includes a third dielectric film layer 60, which covers at least a portion of the first dielectric film layer 40 and at least one of the first side surface 80 and the second side surface 90.

[0073] Furthermore, on the fourth region 902 of the second side 90, after the first dielectric film layer 40 serves as a basic passivation layer, the third dielectric film layer 60 forms a composite structure through stacking. The first dielectric film layer 40 and the third dielectric film layer 60 form a directional ion transport path through interface energy level matching. The first dielectric film layer 40 preferentially blocks the intrusion of external sodium ions, while the third dielectric film layer 60 provides diffusion channels for internal hydrogen and sodium ions through lattice gaps. During the operation of the solar cell 1000, ions accumulated inside the silicon substrate 10 can migrate outward along the grain boundary structure of the third dielectric film layer 60, while sodium ions in the external environment are effectively blocked by the dense structure of the first dielectric film layer 40. This layered coverage method maintains surface passivation performance while establishing a bidirectional selective ion penetration mechanism. This configuration, through the composite structure formed by the third dielectric film layer 60 and the first dielectric film layer 40, provides directional guidance for ions accumulated inside the silicon substrate 10, effectively mitigating excessive charge accumulation on the surface of the solar cell 1000. In high-temperature and high-humidity environment testing, the power decay caused by the PID effect can be reduced to within the industry standard requirements, while maintaining the initial passivation effect without significant degradation. The controllable adjustment of the ion migration rate allows the solar cell 1000 to maintain a stable surface potential distribution during long-term operation, thereby suppressing recombination losses caused by charge accumulation.

[0074] Example 10 Please see Figure 7 Furthermore, when the fourth region 902 of the second side 90 is covered with the third dielectric film layer 60, the first dielectric film layer 40 on the fourth region 902 is covered with the third dielectric film layer 60.

[0075] In the fourth region 902 of the second side 90, a first dielectric film layer 40 is deposited on the surface of the silicon substrate 10 to form a basic passivation layer, and then a third dielectric film layer 60 is superimposed on the first dielectric film layer 40. The dense structure of the first dielectric film layer 40 blocks the intrusion of external sodium ions, while the third dielectric film layer 60, by adjusting its material composition or interface state (e.g., introducing gradient doping or reducing internal stress), allows hydrogen and sodium ions accumulated inside the solar cell 1000 to diffuse to the outside along the film interface or grain boundaries. This layered structure, while maintaining surface passivation performance, provides a controllable diffusion channel for internal ions, avoiding ion retention due to excessively high barrier capacity in a single film layer. This helps reduce the risk of surface passivation performance degradation caused by the PID effect and improves the long-term stability of the solar cell 1000 under high-voltage environments.

[0076] Example 11 Please see Figure 8 Furthermore, the dielectric film layer also includes a fourth dielectric film layer 70, which covers at least a portion of the second dielectric film layer 50 and at least one of the first side surface 80 and the second side surface 90.

[0077] This embodiment eleven is largely the same as the scheme in embodiment five above. The fourth dielectric film layer 70 refers to an additional functional layer superimposed on the surface of the second dielectric film layer 50, and can also be implemented using silicon oxynitride or oxide materials. The fourth dielectric film layer 70 can be formed by chemical vapor deposition, forming a dense structure on the surface of the second dielectric film layer 50 to enhance the ability to block sodium ions.

[0078] Specifically, the fourth dielectric film layer 70 forms a partial covering structure on the surface of the second dielectric film layer 50. Its dense chemical properties effectively block the intrusion of external sodium ions, while the uncovered areas maintain the porous structure of the second dielectric film layer 50, allowing accumulated hydrogen ions to diffuse outward through the pores. During the operation of the solar cell 1000, the fourth dielectric film layer 70 and the second dielectric film layer 50 form a composite protection system. The former is responsible for ion blocking in high-voltage areas, while the latter provides basic passivation. The optimized design of the covered area enables the solar cell 1000 to suppress charge accumulation caused by leakage current and promote the directional migration of internal ions through the exposed areas, even under high potential difference environments.

[0079] Example 12 Please see Figure 8 Furthermore, when the sixth region 905 of the second side 90 is covered with the fourth dielectric film layer 70, the second dielectric film layer 50 on the sixth region 905 is covered with the fourth dielectric film layer 70.

[0080] This embodiment 12 is largely the same as the scheme of embodiment 6 above. Specifically, the fourth dielectric film layer 70 and the second dielectric film layer 50 form an energy level barrier through interfacial chemical bonding. With this configuration, the band structure selectively accelerates the tunneling effect of hydrogen ions.

[0081] In this embodiment, by forming the aforementioned composite dielectric layer in the third region 805, a controllable ion diffusion channel is established while maintaining the surface passivation layer's ability to suppress carrier recombination. This allows hydrogen ions generated inside the battery to be directionally discharged through the nanopores, while simultaneously blocking the intrusion of sodium ions from the external environment through the band barrier. This reduces the surface potential distortion in the third region 805 caused by ion accumulation, thereby significantly reducing the degradation rate of the solar cell 1000.

[0082] It should be noted that in Embodiments 5 and 6, the fourth dielectric film layer 70 mainly covers the second side 90, while in Embodiments 11 and 12, the fourth dielectric film layer 70 covers both the first side 80 and the second side 90.

[0083] Example 13 Please see Figure 9 Furthermore, the first side surface 80 has a first extension region 100, which protrudes outward from the second region 803. The first extension region 100 includes a third surface 103 and a third side surface 110 adjacent to the first surface 101. The first dielectric film layer 40 covers the third surface 103 and avoids the third side surface 110.

[0084] The first extended region 100 refers to a protruding structure extending outward from the second region 803 of the first side 80. Specifically, it can be formed by cutting or etching the silicon substrate 10 to form a local extended region on the first side 80 to optimize the carrier transport path. The third surface 103 refers to the planar portion of the first extension region 100 that is parallel to the first surface 101. Specifically, it can be achieved through mechanical polishing or chemical mechanical planarization to provide surface properties similar to the first surface 101. The third side 110 refers to the vertical or inclined surface adjacent to the third surface 103 in the first extension region 100. Specifically, it can be formed at a specific angle by dry etching. During the process of cutting the silicon substrate 10, such as the process of cutting two pieces from the middle, the first side 80 will not be cut during the cutting process due to the setting of the first extension region 100, thereby protecting the first side 80.

[0085] Furthermore, the first extended region 100 includes a fifth surface 105, and the first dielectric film layer 40 covers the fifth surface 105 and avoids the third side surface 110.

[0086] Specifically, in this embodiment, the fifth surface 105 is covered with a first dielectric film layer 40. In other embodiments, a third dielectric film layer 60 may also be provided, which covers the first dielectric film layer 40.

[0087] Example 14 Please see Figure 10 Furthermore, the second side 90 has a second extension region 200, which protrudes outward from the fifth region 903. The second extension region 200 includes the fourth surface 104 and the fourth side 210 adjacent to the fourth surface 104. The first dielectric film layer 40 covers the fourth surface 104 and avoids the fourth side 210.

[0088] The second extended region 200 refers to a protruding structure extending outward from the fifth region 903 of the second side 90. Specifically, it can be formed by cutting or etching the silicon substrate 10 and is used to form a local extended region on the first side 80 to optimize the carrier transport path. The fourth surface 104 refers to the planar portion of the second extended region 200 that is parallel to the first surface 101. Specifically, it can be achieved through mechanical polishing or chemical mechanical planarization to provide surface properties similar to the first surface 101. The fourth side 210 refers to the vertical or inclined surface adjacent to the fourth surface 104 in the first extension region 100. Specifically, it can be formed at a specific angle by dry etching. During the cutting process of the silicon substrate 10, such as three-part cutting or four-part cutting, the first extension region 100 and the second extension region 200 are used to increase the fault tolerance during the cutting process. The first side 80 or the second side 90 will not be cut during the cutting process, thereby protecting the first side 80 and the second side 90.

[0089] Furthermore, the second extended region 200 includes a sixth surface 106, and the second dielectric film layer 50 covers the sixth surface 106 and avoids the fourth side surface 210.

[0090] Specifically, in this embodiment, the sixth surface 106 is covered with a second dielectric film layer 50. In other embodiments, a fourth dielectric film layer 70 can also be provided, which covers the second dielectric film layer 50.

[0091] Example 15 Please see Figure 10 Furthermore, the width X of the first extension region 100 along the first direction A is greater than or equal to 100 μm.

[0092] The width X of the first extension region 100 is set to a minimum of 100μm or more. This not only ensures that the first extension region 100 has enough space to accommodate the structural layout of the dielectric film covering and avoiding it, but also increases the fault tolerance so that the first side 80 will not be cut during the silicon substrate 10 cutting process.

[0093] It is understood that in other embodiments, the width X of the first extension region 100 along the first direction A can also be other values, and can be designed according to the actual situation, without limitation here.

[0094] For example, in one embodiment, the width X of the first extension region 100 along the first direction A may be greater than or equal to 50 μm; For example, in another embodiment, the width X of the first extension region 100 along the first direction A may be greater than or equal to 80 μm; For example, in yet another embodiment, the width X of the first extension region 100 along the first direction A may be greater than or equal to 120 μm.

[0095] Example 16 Please refer to further information. Figure 10 Furthermore, the width Y of the second extension region 200 along the first direction A is greater than or equal to 100 μm.

[0096] The width Y of the second extension region 200 is set to a minimum of 100μm or more. This not only ensures that the second extension region 200 has enough space to accommodate the structural layout of the dielectric film covering and avoiding it, but also increases the fault tolerance so that the second side 90 will not be cut during the silicon substrate 10 cutting process.

[0097] It is understood that in other embodiments, the width Y of the second extension region 200 along the first direction A can also be other values, and can be designed according to the actual situation, without limitation here.

[0098] For example, in one embodiment, the width Y of the second extension region 200 along the first direction A may be greater than or equal to 50 μm; For example, in another embodiment, the width Y of the second extension region 200 along the first direction A can be greater than or equal to 80 μm; For example, in yet another embodiment, the width Y of the second extension region 200 along the first direction A may be greater than or equal to 120 μm.

[0099] Example 17 Please see Figure 11 Furthermore, the vertical height Z along the second direction B of the innermost layer of the first surface 101 and the innermost layer of the third surface 103 of the silicon substrate 10 is greater than or equal to 200 nm.

[0100] In this embodiment, the vertical height Z of the innermost layer of the first surface 101 and the innermost layer of the third surface 103 of the silicon substrate 10 along the second direction B is set to at least 200 nm. In other embodiments, the vertical height Z of the innermost layer of the first surface 101 and the innermost layer of the third surface 103 of the silicon substrate 10 along the second direction B can be designed according to different situations, and is not limited here.

[0101] For example, in one embodiment, the vertical height Z of the innermost layer of the first surface 101 and the innermost layer of the third surface 103 of the silicon substrate 10 along the second direction B is greater than or equal to 100 nm.

[0102] For example, in one embodiment, the vertical height Z along the second direction B of the innermost layer of the first surface 101 and the innermost layer of the third surface 103 of the silicon substrate 10 is greater than or equal to 500 nm.

[0103] For example, in another embodiment, the vertical height Z along the second direction B of the innermost layer of the first surface 101 and the innermost layer of the third surface 103 of the silicon substrate 10 is greater than or equal to 5 μm; For example, in another embodiment, the vertical height Z of the innermost layer of the first surface 101 and the innermost layer of the third surface 103 of the silicon substrate 10 along the second direction B is greater than or equal to 50 μm.

[0104] Example 17 Please continue reading. Figure 11 Furthermore, the vertical height L along the second direction B of the innermost layer of the first surface 101 and the innermost layer of the fourth surface 104 of the silicon substrate 10 is greater than or equal to 200 nm.

[0105] In this embodiment, the vertical height L along the second direction B of the innermost layer of the first surface 101 and the innermost layer of the fourth surface 104 of the silicon substrate 10 is set to at least 200 nm. In other embodiments, the vertical height L along the second direction B of the innermost layer of the first surface 101 and the innermost layer of the fourth surface 104 of the silicon substrate 10 can be designed according to different situations, and is not limited here.

[0106] For example, in one embodiment, the vertical height L along the second direction B between the innermost layer of the first surface 101 and the innermost layer of the fourth surface 104 of the silicon substrate 10 is greater than or equal to 100 nm.

[0107] For example, in one embodiment, the vertical height L along the second direction B of the innermost layer of the first surface 101 and the innermost layer of the fourth surface 104 of the silicon substrate 10 is greater than or equal to 500 nm.

[0108] For example, in another embodiment, the vertical height L along the second direction B between the innermost layer of the first surface 101 and the innermost layer of the fourth surface 104 of the silicon substrate 10 is greater than or equal to 5 μm. For example, in another embodiment, the vertical height L along the second direction B of the innermost layer of the first surface 101 and the innermost layer of the fourth surface 104 of the silicon substrate 10 is greater than or equal to 50 μm.

[0109] Example 18 Please see Figure 12 Furthermore, the vertical height M of the outermost layer of the first surface 101 and the outermost layer of the third surface 103 of the silicon substrate 10 along the second direction B is greater than or equal to 50 nm.

[0110] In this embodiment, the vertical height M of the outermost layer of the first surface 101 and the outermost layer of the third surface 103 of the silicon substrate 10 along the second direction B is at least 50 nm. In other embodiments, the vertical height M of the outermost layer of the first surface 101 and the outermost layer of the third surface 103 of the silicon substrate 10 along the second direction B can be designed according to different situations, and is not limited here.

[0111] For example, in one embodiment, the vertical height M of the outermost layer of the first surface 101 and the outermost layer of the third surface 103 of the silicon substrate 10 along the second direction B is greater than or equal to 100 nm.

[0112] For example, in one embodiment, the vertical height M of the outermost layer of the first surface 101 and the outermost layer of the third surface 103 of the silicon substrate 10 along the second direction B is greater than or equal to 500 nm.

[0113] For example, in another embodiment, the vertical height M of the outermost layer of the first surface 101 and the outermost layer of the third surface 103 of the silicon substrate 10 along the second direction B is greater than or equal to 1 μm; For example, in another embodiment, the vertical height M of the outermost layer of the first surface 101 and the outermost layer of the third surface 103 of the silicon substrate 10 along the second direction B is greater than or equal to 5 μm.

[0114] Example 19 Please see Figure 12 Furthermore, the vertical height N along the second direction B of the outermost layer of the first surface 101 and the outermost layer of the fourth surface 104 of the silicon substrate 10 is greater than or equal to 50 nm.

[0115] In this embodiment, the vertical height N of the outermost layer of the first surface 101 and the outermost layer of the fourth surface 104 of the silicon substrate 10 along the second direction B is at least 50 nm. In other embodiments, the vertical height N of the outermost layer of the first surface 101 and the outermost layer of the fourth surface 104 of the silicon substrate 10 along the second direction B can be designed according to different situations, and is not limited here.

[0116] For example, in one embodiment, the vertical height N of the outermost layer of the first surface 101 and the outermost layer of the fourth surface 104 of the silicon substrate 10 along the second direction B is greater than or equal to 100 nm.

[0117] For example, in one embodiment, the vertical height N along the second direction B of the outermost layer of the first surface 101 and the outermost layer of the fourth surface 104 of the silicon substrate 10 is greater than or equal to 500 nm.

[0118] For example, in another embodiment, the vertical height N along the second direction B between the outermost layer of the first surface 101 and the outermost layer of the fourth surface 104 of the silicon substrate 10 is greater than or equal to 1 μm; For example, in another embodiment, the vertical height N of the outermost layer of the first surface 101 and the outermost layer of the fourth surface 104 of the silicon substrate 10 along the second direction B is greater than or equal to 5 μm.

[0119] Example 20 Furthermore, a first electrode is also disposed on the first surface 101, and the first electrode passes through the dielectric film layer located on the first surface 101 and is connected to the first doped layer 20. A second electrode is also disposed on the second surface 102, and the second electrode passes through the dielectric film layer located on the second surface 102 and is connected to the second doped layer 30.

[0120] The first and second electrodes, serving as negative and positive poles respectively, form the current output ports. They pass through the dielectric film layer and form reliable physical contact and electrical connection with the first doped layer 20 and the second doped layer 30, enabling the carriers (electrons and holes) generated by the photovoltaic effect in the silicon substrate 10 to be collected separately and conducted to the external load through the electrodes to form the working current.

[0121] The first electrode and the second electrode are designed with fine grid lines and are mainly made of silver. Of course, in other embodiments, the first electrode and the second electrode can also be made of other materials, such as copper or aluminum. The specific design can be made according to the actual situation and is not limited here.

[0122] Example 21 A photovoltaic module includes a plurality of solar cell strings 1000, each of which includes a plurality of electrically connected solar cells 1000, wherein the solar cells 1000 are any of the aforementioned solar cells 1000.

[0123] A photovoltaic system comprising the aforementioned photovoltaic modules.

[0124] The beneficial effects achieved by the present invention are that by setting a selectively covered dielectric film structure on at least one of the first side surface 80 and the second side surface 90 of the silicon substrate 10, it can effectively block external ions and promote the discharge of internal ions by setting the avoidance area. This solves the technical problem of traditional full-coverage film layers hindering charge release. It has the advantages of blocking the intrusion of external impurity ions while promoting the discharge of internal ions, effectively balancing the surface passivation and charge release requirements, and improving battery performance and stability.

[0125] It is understood that those skilled in the art can combine various implementation methods in the above embodiments under the guidance of the above examples to obtain technical solutions with multiple implementation methods.

[0126] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A solar cell, characterized in that, include: A silicon substrate, the silicon substrate including a first side surface and a second side surface opposite each other along a first direction; The silicon substrate includes a first surface and a second surface opposite to each other along a second direction, wherein a first doped layer is disposed on the first surface and a second doped layer is disposed on the second surface; A dielectric film layer, the dielectric film layer including a first dielectric film layer and a second dielectric film layer, the first dielectric film layer covering at least a portion of the first doped layer and at least one of the first side and the second side, the second dielectric film layer covering at least a portion of the second doped layer and at least one of the first side and the second side; The first side is provided with a first coating area, the first side includes a first area disposed on the first coating area and a second area not located in the first coating area, the first area is covered with the first dielectric film layer and avoids the second area.

2. The solar cell as described in claim 1, characterized in that, The first side is further provided with a second coating area, and the first side includes a third area disposed on the second coating area, the third area being covered by the second dielectric film layer and avoiding the second area.

3. The solar cell as described in claim 1, characterized in that, The dielectric film layer further includes a third dielectric film layer, which covers at least a portion of the first dielectric film layer and at least one of the first side surface and the second side surface.

4. The solar cell as described in claim 3, characterized in that, When the third dielectric film layer is covered on the first region of the first side, the third dielectric film layer is covered on the first dielectric film layer in the first region.

5. The solar cell as described in claim 2, characterized in that, The dielectric film layer further includes a fourth dielectric film layer, which covers at least a portion of the second dielectric film layer and at least one of the first side and the second side.

6. The solar cell as described in claim 5, characterized in that, When the third region on the first side is covered by the fourth dielectric film layer, the second dielectric film layer on the third region is covered by the fourth dielectric film layer.

7. The solar cell according to claim 1, characterized in that, The second side is provided with a third coating area, and the second side includes a fourth region disposed on the third coating area and a fifth region not located in the third coating area. The fourth region is covered with the first dielectric film layer and avoids the fifth region.

8. The solar cell as claimed in claim 7, characterized in that, The second side also has a fourth coating area, and the second side includes a sixth area disposed on the fourth coating area, the sixth area being covered by the second dielectric film layer and avoiding the fifth area.

9. The solar cell as claimed in claim 7, characterized in that, The dielectric film layer further includes a third dielectric film layer, which covers at least a portion of the first dielectric film layer and at least one of the first side surface and the second side surface.

10. The solar cell as claimed in claim 9, characterized in that, When the third dielectric film layer is covered on the fourth region of the second side, the third dielectric film layer is covered on the first dielectric film layer in the fourth region.

11. The solar cell as claimed in claim 8, characterized in that, The dielectric film layer further includes a fourth dielectric film layer, which covers at least a portion of the second dielectric film layer and at least one of the first side and the second side.

12. The solar cell as claimed in claim 11, characterized in that, When the sixth region on the second side is covered by the fourth dielectric film layer, the second dielectric film layer on the sixth region is covered by the fourth dielectric film layer.

13. The solar cell according to claim 1, characterized in that, The first side has a first extended region that protrudes outward from the second region. The first extended region includes a third surface and a third side adjacent to the first surface. The first dielectric film layer covers the third surface and avoids the third side.

14. The solar cell as claimed in claim 7, characterized in that, The second side has a second extended region that protrudes outward from the fifth region. The second extended region includes a fourth surface and a fourth side adjacent to the fourth surface. The first dielectric film layer covers the fourth surface and avoids the fourth side.

15. The solar cell as claimed in claim 13, characterized in that, The width of the first extended region along the first direction is greater than or equal to 100 μm.

16. The solar cell according to claim 14, characterized in that, The width of the second extended region along the first direction is greater than or equal to 100 μm.

17. The solar cell as claimed in claim 13, characterized in that, The vertical height of the innermost layer of the first surface and the innermost layer of the third surface of the silicon substrate along the second direction is greater than or equal to 200 nm.

18. The solar cell as claimed in claim 17, characterized in that, The vertical height of the innermost layer of the first surface and the innermost layer of the third surface of the silicon substrate along the second direction is greater than or equal to 500 nm.

19. The solar cell as claimed in claim 18, characterized in that, The vertical height of the innermost layer of the first surface and the innermost layer of the third surface of the silicon substrate along the second direction is greater than or equal to 5 μm.

20. The solar cell as claimed in claim 14, characterized in that, The vertical height of the innermost layer of the first surface of the silicon substrate and the innermost layer of the fourth surface along the second direction is greater than or equal to 200 nm.

21. The solar cell as claimed in claim 13, characterized in that, The vertical height of the outermost layer of the first surface and the outermost layer of the third surface of the silicon substrate along the second direction is greater than or equal to 50 nm.

22. The solar cell as claimed in claim 21, characterized in that, The vertical height of the outermost layer of the first surface and the outermost layer of the third surface of the silicon substrate along the second direction is greater than or equal to 500 nm.

23. The solar cell as claimed in claim 22, characterized in that, The vertical height between the outermost layer of the first surface and the outermost layer of the third surface of the silicon substrate along the second direction is greater than or equal to 1 μm.

24. The solar cell as claimed in claim 14, characterized in that, The vertical height of the outermost layer of the first surface of the silicon substrate and the outermost layer of the fourth surface along the second direction is greater than or equal to 50 nm.

25. The solar cell as claimed in claim 1, characterized in that, A first electrode is also disposed on the first surface, and the first electrode is connected to the first doped layer through the dielectric film layer located on the first surface; A second electrode is also disposed on the second surface, and the second electrode is connected to the second doped layer through the dielectric film layer located on the second surface.

26. The solar cell as claimed in claim 25, characterized in that, A tunneling oxide layer is further disposed between the second surface of the silicon substrate and the second doped layer.

27. The solar cell according to claim 1, characterized in that, The first dielectric film and the second dielectric film are composed of one or more of the following: oxide layer, nitride layer, oxynitride layer, carbide layer, and amorphous silicon layer.

28. The solar cell as claimed in claim 26, characterized in that, The tunneling oxide layer is composed of one or more of the following: oxide layer, nitride layer, oxynitride layer, carbide layer, and amorphous silicon layer.

29. A photovoltaic module, characterized in that, It includes a plurality of solar cell strings, wherein the solar cell strings include a plurality of electrically connected solar cells, and the solar cells are the solar cells according to any one of claims 1-28.

30. A photovoltaic system, characterized in that, Includes the photovoltaic module as described in claim 29.

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