An axial micro-column array heterojunction photodetector chip and a preparation method thereof

Abstract

The application belongs to the technical field of semiconductor optoelectronic devices and micro-nano processing, and particularly relates to an axial micro-column array heterojunction photodetector chip and a preparation method thereof. The specific method is as follows: on a substrate with a bottom electrode, a perovskite layer and an organic semiconductor layer are formed by spin coating and heat treatment in sequence; a sacrificial layer and a UV glue layer are spin coated on the organic semiconductor layer in sequence; the UV glue layer is imprinted by using a PDMS elastic template with a micro-hole array, the template is removed after ultraviolet exposure and curing, and a UV glue micro-column array is obtained; a UV glue micro-hole array mask is formed by oxygen plasma etching, and the pattern is transferred to the sacrificial layer; a metal layer is evaporated, and a metal dot array mask is formed on the surface of the organic semiconductor layer by a stripping process; the metal dot array mask is used as an etching mask, two-step ICP reactive ion etching is carried out by using different etching gases, the organic semiconductor layer and the perovskite layer are etched in sequence, and the bottom electrode is exposed, so that an axial micro-column array heterojunction is finally formed.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor optoelectronic devices and micro / nano fabrication technology, specifically relating to an axial micropillar array heterojunction photodetector chip and its fabrication method. Background Technology

[0002] Photodetectors are core devices that convert optical signals into electrical signals and are widely used in modern optoelectronic systems such as imaging, communication, sensing, and spectral analysis. However, traditional planar photodetectors have inherent drawbacks, such as long carrier transport paths and susceptibility to carrier recombination (i.e., signal loss along the way), which makes it difficult to further improve their response speed and photoelectric conversion efficiency, thus failing to meet the current application requirements for high-speed and high-sensitivity detection.

[0003] To address this challenge, researchers have turned to micro / nano structured photodetectors, particularly vertically oriented micropillar arrays. This structure offers three main advantages: high specific surface area enhances the interaction between light and materials; it can capture more light of different wavelengths, improving photon utilization; and it shortens the carrier extraction path, effectively reducing recombination losses. Therefore, it is considered an ideal structure for achieving higher-performance photodetectors.

[0004] Currently, there are two main types of fabrication methods, but both have significant shortcomings: one is the traditional semiconductor process based on photolithography and etching, which can fabricate high-precision, well-aligned arrays, but the equipment is expensive, the process is complex and time-consuming, and the processing environment is unfavorable to solution-based semiconductor materials, easily causing material damage and interface defects. The other type is based on self-assembly technology, which, although simple in process, makes it difficult to precisely control the shape and size of the micropillars, and it is also impossible to construct high-quality semiconductor heterojunctions along the axial direction, resulting in poor device consistency, low repeatability, and numerous interface defects, failing to meet the requirements of high-performance detection.

[0005] To meet the requirements of high-performance detection, the fabrication process of photodetectors needs to simultaneously achieve four goals: precise fabrication of micro- and nano-structures, compatibility with various solution-based materials, realization of high-quality axial heterojunctions, and support for low-cost, large-area fabrication.

[0006] Therefore, the industry urgently needs a new method for fabricating photodetector chips that can meet the above four objectives. Summary of the Invention

[0007] The technical problem this invention aims to solve is to address the shortcomings of existing technologies by providing a method for fabricating axial micropillar array heterojunction photodetector chips based on the organic combination of three steps: spin coating, template-assisted patterning, and sequential selective etching. This method achieves high-precision, high-quality, and large-area fabrication of p-n or p-i-n type axial heterojunctions under mild process conditions (without damaging solution-based materials), and is fully compatible with solution-based semiconductor materials. This process has three major advantages: it can fabricate micropillar arrays with high aspect ratios and good consistency without damaging sensitive materials; it achieves precise axial construction of heterojunctions on single micropillars through a "two-step spin coating + two-step etching" process, resulting in high interface quality; and it enables the fabrication of large-area, structurally complex, and high-performance photodetector chips in a low-cost manner compatible with conventional semiconductor processes. This opens up a new technical path for the integration of next-generation solution-based high-performance optoelectronic devices, demonstrating significant technological advancement and industrial application value.

[0008] To address the aforementioned technical problems, this invention discloses a method for fabricating an axial micropillar array heterojunction photodetector chip, comprising the following steps:

[0009] S1. Fabricate the bottom electrode on the pretreated substrate;

[0010] S2. A perovskite layer and an organic semiconductor layer are sequentially prepared on the surface of the bottom electrode by spin coating and annealing.

[0011] S3. A sacrificial layer and a UV adhesive layer are sequentially prepared on the surface of an organic semiconductor layer by spin coating;

[0012] S4. UV adhesive layer is imprinted through a polydimethylsiloxane template with a microporous array, and UV adhesive micropillar array is obtained after photocuring;

[0013] S5. Using a dry etching process with a UV adhesive micropillar array as a mask, the sacrificial layer is etched until the surface of the organic semiconductor layer is exposed, thus obtaining the sacrificial layer micropore array.

[0014] S6. Electron beam evaporation is used to deposit a metal layer on the entire surface of the structure; then the sacrificial layer micropore array is peeled off to obtain a metal lattice.

[0015] S7. Using a metal dot matrix as a mask, a two-step etching process is employed to remove the non-mask regions of the organic semiconductor layer and the perovskite layer, respectively, to form an axial heterojunction micropillar array; the metal dot matrix is ​​then removed using an etching solution to obtain the axial micropillar array heterojunction photodetector chip.

[0016] In S1, the substrate is glass or silicon wafer.

[0017] In S1, the pretreatment is a two-step cleaning method. The specific steps are: soaking in acetone and ultrasonic treatment, then repeating ultrasonic cleaning with ethanol, followed by drying with a nitrogen gun and placing it on a clean bench for later use.

[0018] In some embodiments of the present invention, in S1, the substrate is glass.

[0019] In S1, the bottom electrode is prepared by vacuum evaporation or magnetron sputtering.

[0020] In some embodiments of the present invention, in S1, the bottom electrode is prepared by vacuum evaporation.

[0021] In S2, the perovskite layer includes any one of p-type MAPbI3, Sb2Te3, Sb2Se3, Bi2Se3, Bi2Te3, and Sb2S3. The spin coating process is: 3000~5000 rpm for 30~60s; the annealing process is: 80~150℃ for 10~30min.

[0022] Optionally, the thickness of the perovskite layer is 100 nm to 1.5 μm.

[0023] In S2, the organic semiconductor layer includes any one of n-type PCBM, ICBA, PTCDI, and N2200, and its spin coating process is: rotation speed 3000~5000rpm, time 30~60s; its annealing process is: 60~120℃, time 5~10min.

[0024] Optionally, the thickness of the organic semiconductor layer is 100 nm to 1.5 μm.

[0025] In S3, the sacrificial layer is polymethyl methacrylate or polystyrene, which is prepared by spin coating. The specific process is: rotation speed 2000~4000rpm, time 30~60s; the UV adhesive layer is a silicone-containing UV-curable adhesive, which is prepared by spin coating. The specific process is: rotation speed 3000~5000rpm, time 30~60s.

[0026] In some embodiments of the present invention, the sacrificial layer is polymethyl methacrylate; the UV adhesive is SU-8 adhesive.

[0027] In S4, the photocuring process is as follows: wavelength 365nm, light intensity 10~100mW / cm², irradiation time 30~60s.

[0028] In S5, the dry etching process includes two dry etching processes: the first etching process is to remove the thin adhesive layer by etching with a mixture of oxygen plasma and trifluoromethane gas; the second etching process is to remove the sacrificial layer by etching with oxygen plasma.

[0029] In some embodiments of the present invention, in S5, the oxygen plasma and trifluoromethane mixed gas is used to etch and remove the thin adhesive layer. The specific process is as follows: flow rate ratio O2:CHF3=1:(2~5), flow rate 50sccm, vacuum degree 30Pa, etching for 60s; the oxygen plasma is used to etch and remove the sacrificial layer. The specific process is as follows: oxygen flow rate 50~100sccm, vacuum degree 30Pa, etching for 120s.

[0030] In S6, the metal layer is a Cr metal layer.

[0031] In S7, the first step of the two-step etching process removes the organic semiconductor layer. The specific etching process is as follows: etching with a CHF3 / O2 mixed gas, with a flow rate ratio of CHF3:O2=(2~4):1, ICP power of 500~800W, RF power of 100~200W, and vacuum degree of 1~5Pa. The second step of the etching process removes the perovskite layer. The specific etching process is as follows: etching with a Cl2 / BCl3 mixed gas, with a flow rate ratio of Cl2:BCl3=(1~3):1, ICP power of 400~700W, RF power of 80~150W, and vacuum degree of 1~5Pa.

[0032] In some embodiments of the present invention, in S7, the first step of the two-step etching removes the organic semiconductor layer. The specific etching process is as follows: etching with a CHF3 / O2 mixed gas, a flow rate ratio of CHF3:O2=4:1, an ICP power of 600W, an RF power of 100W, and a vacuum degree of 5Pa; the second step of the etching removes the perovskite layer. The specific etching process is as follows: etching with a Cl2 / BCl3 mixed gas, a flow rate ratio of Cl2:BCl3=3:1, an ICP power of 500W, an RF power of 80W, and a vacuum degree of 5Pa.

[0033] Furthermore, the axial micropillar array heterojunction photodetector chip prepared by the above method is also within the scope of protection of this invention.

[0034] The axial micropillars have a diameter of 400 nm to 2 μm and a height of 350 nm to 2.35 μm.

[0035] Specifically, the diameter of the axial micropillar is controlled by changing the PDMS template, and the height is controlled by controlling the thickness of the perovskite layer and the organic semiconductor layer.

[0036] Furthermore, the application of the axial micropillar array heterojunction photodetector chip prepared by the above method in any of the fields including imaging, communication, sensing or spectral analysis is also within the scope of protection of this invention.

[0037] Specifically, in some embodiments of the present invention, axial micropillar array heterojunction photodetector chips with different materials and sizes were successfully fabricated using the above-described preparation method. Characterization of their microstructures demonstrated that they all possessed good axial micropillar arrays and good interfacial contact between the perovskite layer and the organic semiconductor layer. Testing of the photoelectric response of the axial micropillar array heterojunction photodetector chips proved that the chips prepared in the embodiments of the present invention all exhibited good photoelectric responsivity and excellent photoelectric detection performance. Beneficial effects

[0038] 1. The invention has extremely strong process compatibility: the core semiconductor layer is prepared by spin coating, which can be perfectly adapted to emerging solution-based materials such as organic semiconductors, perovskites, colloidal quantum dots, and metal oxide semiconductors, without relying on expensive vacuum deposition equipment, thus greatly reducing manufacturing costs.

[0039] 2. The heterojunction of this invention has high quality: First, a complete and flat planar heterojunction (semiconductor A layer + semiconductor B layer) is formed by spin coating, and then it is patterned into micropillars by etching. This fundamentally avoids the problems of interface defects and uneven material filling that may occur when preparing micropillars first and then filling the second material, ensuring that the heterojunction interface is tightly bonded and has excellent crystallinity.

[0040] 3. The structure of this invention is precise and controllable: By combining PDMS soft lithography (to achieve initial pattern transfer) with a metal Cr hard mask (to ensure etching accuracy), the diameter (400nm~2μm), height (350nm~2.35μm), and period (1.5~3 times the diameter of the micropillar) of the pillars can be precisely controlled, making it easy to fabricate large-area, highly ordered micropillar arrays with good device consistency.

[0041] 4. The device of this invention has excellent performance: The axial micropillar array heterojunction structure has three major performance advantages: huge heterojunction area (improving the efficiency of photogenerated carrier generation), high efficiency of light absorption (micropillar structure enhances light capture), and fast radial charge separation and collection (shortening the carrier transport path), which can significantly improve the responsivity and detectivity of the photodetector, while shortening the response time.

[0042] 5. This invention has a wide range of applications: This preparation method is not only applicable to photodetectors, but can also be extended to the preparation of various optoelectronic devices such as solar cells, light-emitting diodes (LEDs), and photoelectrochemical sensors, providing a general process solution for technological innovation in the optoelectronic field. Attached Figure Description

[0043] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments, and the advantages of the present invention in the above and / or other aspects will become clearer.

[0044] Figure 1The present invention provides a process flow diagram of the preparation method, wherein 1-1 is a PDMS template, 1-2 is a UV adhesive layer, 1-3 is a sacrificial layer, 1-4 is an organic semiconductor layer, 1-5 is a perovskite layer, 1-6 is a bottom electrode, 1-7 is a substrate, 1-8 is a metal layer, and 1-9 is an axial micropillar array heterojunction.

[0045] Figure 2 This is a performance characterization diagram of the axial micropillar array heterojunction photodetector chip constructed in Embodiment 1 of the present invention, wherein, Figure 2 In the image, 'a' represents the SEM image of the axial heterostructure micropillar array. Figure 2 In this context, 'b' represents the photoelectric detection performance of the axial micropillar array heterojunction photodetector.

[0046] Figure 3 This is a performance characterization diagram of the axial micropillar array heterojunction photodetector chip constructed in Embodiment 2 of the present invention, wherein, Figure 3 In the image, 'a' represents the SEM image of the axial heterostructure micropillar array. Figure 3 In this context, 'b' represents the photoelectric detection performance of the axial micropillar array heterojunction photodetector.

[0047] Figure 4 This is a performance characterization diagram of the axial micropillar array heterojunction photodetector chip constructed in Embodiment 3 of the present invention, wherein, Figure 4 In the image, 'a' represents the SEM image of the axial heterostructure micropillar array. Figure 4 In this context, 'b' represents the photoelectric detection performance of the axial micropillar array heterojunction photodetector.

[0048] Figure 5 This is a performance characterization diagram of the axial micropillar array heterojunction photodetector chip constructed in Embodiment 4 of the present invention, wherein, Figure 5 In the image, 'a' represents the SEM image of the axial heterostructure micropillar array. Figure 5 In this context, 'b' represents the photoelectric detection performance of the axial micropillar array heterojunction photodetector.

[0049] Figure 6 This is a performance characterization diagram of the axial micropillar array heterojunction photodetector chip constructed in Embodiment 5 of the present invention, wherein, Figure 6 In the image, 'a' represents the SEM image of the axial heterostructure micropillar array. Figure 6 In this context, 'b' represents the photoelectric detection performance of the axial micropillar array heterojunction photodetector.

[0050] Figure 7 This is a performance characterization diagram of the axial micropillar array heterojunction photodetector chip constructed in Embodiment 6 of the present invention, wherein, Figure 7 In the image, 'a' represents the SEM image of the axial heterostructure micropillar array. Figure 7 In this context, 'b' represents the photoelectric detection performance of the axial micropillar array heterojunction photodetector.

[0051] Figure 8 This is a performance characterization diagram of the axial micropillar array heterojunction photodetector chip constructed in Embodiment 7 of the present invention, wherein, Figure 8 In the image, 'a' represents the SEM image of the axial heterostructure micropillar array. Figure 8 In this context, 'b' represents the photoelectric detection performance of the axial micropillar array heterojunction photodetector. Detailed Implementation

[0052] Unless otherwise specified, the experimental methods described in the following examples are conventional methods; the reagents and materials described are commercially available unless otherwise specified.

[0053] This invention provides a method for fabricating an axial micropillar array photodetector chip based on a perovskite / organic semiconductor heterojunction. Figure 1 A flowchart of the preparation process of the method of the present invention is provided, wherein, Figure 1 In the diagram, 1-1 is the PDMS template, 1-2 is the UV adhesive layer, 1-3 is the sacrificial layer, 1-4 is the organic semiconductor layer (semiconductor B layer, upper layer of the micropillars), 1-5 is the perovskite layer (semiconductor A layer, lower layer of the micropillars), 1-6 is the bottom electrode, 1-7 is the substrate, 1-8 is the metal layer (mask, to be removed later), and 1-9 is the axial micropillar array heterojunction (core functional region). The specific fabrication steps are as follows:

[0054] 1. Substrate preparation and bottom electrode fabrication:

[0055] The substrate can be glass or silicon wafer. First, the substrate surface is cleaned in two steps: first, soak it in acetone and sonicate it (to remove surface oil and organic impurities), then repeat the sonic cleaning with ethanol (to remove residual acetone and fine particles), and finally dry it with a nitrogen gun and place it on a clean bench for later use.

[0056] Then, vacuum evaporation, magnetron sputtering and other processes are used to deposit the bottom electrode on the cleaned substrate surface. The bottom electrode can be an ITO transparent conductive film or a metal electrode (such as Au, Ag, etc.). The electrode thickness needs to be controlled according to the conductivity requirements of the device, generally controlled between 50 and 200 nm, to ensure uniform electrode coverage and no pinhole defects.

[0057] 2. Fabrication of the perovskite layer and the organic semiconductor layer:

[0058] The perovskite layer material can be selected from p-type MAPbI3, Sb2Te3, Sb2Se3, Bi2Se3, Bi2Te3, Sb2S3, etc. A perovskite layer is deposited on the bottom electrode surface via spin coating followed by annealing. The spin coating parameters are: rotation speed 3000~5000 rpm, time 30~60 s; annealing parameters are: 80~150℃, time 10~30 min. The final perovskite layer thickness is 100 nm~1.5 μm. High-speed rotation ensures uniform spreading of the solution into a film. During annealing, residual solvent within the film is gradually removed, while the crystallization of the semiconductor material is promoted, ultimately forming a perovskite layer with uniform thickness, a smooth surface, and high crystallinity.

[0059] The organic semiconductor layer can be made of materials such as n-type PCBM, ICBA, PTCDI, and N2200. The organic semiconductor layer is coated on the surface of the perovskite layer by spin coating and annealing. The spin coating parameters are: rotation speed 3000~5000 rpm, time 30~60s; annealing parameters are: 60~120℃, time 5~10min. The final thickness of the organic semiconductor layer is 100nm~1.5μm.

[0060] It should be noted that the materials chosen for the perovskite layer and the organic semiconductor layer are not limited to those described above. However, they must possess different conductivity types. Specifically, it can be a combination of p-type and n-type (such as p-type Sb₂Te₃ + n-type PCBM), or one of them can be an intrinsic semiconductor (i-type, with no obvious conductivity polarity), forming a pin structure. The core of material selection is to ensure that a pn heterojunction or pin junction can be formed at the interface between the perovskite layer and the organic semiconductor layer. This is the core structural basis for the separation of photogenerated carriers under subsequent optical signal irradiation. Without this junction, carriers easily recombine, and an effective electrical signal cannot be formed.

[0061] 3. Preparation of sacrificial layer and UV adhesive layer

[0062] The surface of the organic semiconductor layer needs to be spin-coated with two layers of functional materials in sequence, and the order and process parameters must be strictly controlled. Specifically, the first layer is a sacrificial layer and the second layer is a UV adhesive layer (patterning layer).

[0063] The sacrificial layer can be polymethyl methacrylate (PMMA) or polystyrene (PS). The spin coating parameters are: rotation speed 2000~4000 rpm, time 30~60s, to form a uniform film layer.

[0064] The UV adhesive layer uses a silicon-containing UV-curable adhesive (Si-UV adhesive). The spin coating parameters are: rotation speed 3000~5000rpm, time 30~60s, to form a film layer with uniform thickness. This layer is the core carrier for subsequent micropillar array patterns.

[0065] 4. Micro-pillar array pattern transfer:

[0066] The micropillar structure on the polydimethylsiloxane (PDMS) elastic pillar template is transferred onto the UV adhesive layer using a template replication method. The specific steps are as follows:

[0067] Template bonding: Take the pre-made PDMS template, with its cylindrical side facing down, and gently cover it on the surface of the UV adhesive layer;

[0068] Si-UV adhesive curing: The sample with the template attached is placed under a UV irradiator and UV light is irradiated from above the PDMS template (wavelength is usually 365nm, light intensity is 10~100mW / cm², irradiation time is 30~60s); the Si-UV adhesive undergoes a cross-linking reaction under UV light and gradually cures and hardens. Its surface will replicate the structure complementary to the PDMS template, that is, the positions where the template has micropillars, and the UV adhesive layer forms micropores, finally obtaining the preliminary pattern of the Si-UV adhesive micropore array.

[0069] Template removal: After the Si-UV adhesive has fully cured, gently lift one corner of the PDMS template and slowly peel it off from the surface of the UV adhesive layer; at this time, the surface of the UV adhesive layer shows a micro-pillar array, completing the pattern transfer and obtaining the Si-UV adhesive micro-pillar array.

[0070] 5. Patterned mask preparation:

[0071] The micropore pattern of the UV adhesive layer is transformed into a hard mask of the Cr metal layer through an etching and stripping process, providing precise positioning for subsequent micropillar etching. The specific steps are as follows:

[0072] Si-UV adhesive micropillar array mask forming: A dry etching process (the etching equipment is a plasma etching machine) is used, and a mixture of oxygen plasma and trifluoromethane (CHF3) gas is introduced (flow rate ratio O2:CHF3=1:(2~5)); during the etching process, the plasma only removes the thin adhesive layer remaining at the bottom of the Si-UV adhesive micropillar array until the surface of the sacrificial layer below is exposed, thus obtaining the Si-UV adhesive pillar array mask.

[0073] Patterning of the sacrificial layer: A dry etching process (the etching equipment is a plasma etching machine) is used, with only oxygen plasma (oxygen flow rate 50~100 sccm) introduced. The sacrificial layer below is etched through a Si-UV photoresist pillar array mask until the surface of the organic semiconductor layer is exposed, at which point the etching stops. At this point, the sacrificial layer forms a micro-hole array that is perfectly matched with the Si-UV photoresist micro-hole array, i.e., the sacrificial layer micro-hole array.

[0074] Metallic Cr deposition: The sample was transferred to a vacuum evaporator and a vertical evaporation process was used (evaporation rate 0.1~0.7 Å, vacuum degree 2×10⁻⁶). -6 ~3×10 -6Torr) deposits a layer of metallic chromium (Cr) on the entire surface of the structure (including the organic semiconductor layer at the bottom of the PMMA micropores), with the Cr layer thickness controlled at 30~100nm; due to the good etching resistance of Cr, it will be used as a hard mask in the future.

[0075] Lift-off to form a hard mask: The sample with the deposited Cr layer is immersed in an acetone solution and subjected to ultrasonic treatment (ultrasonic power 50~100W, time 5~10min); at this time, the acetone will dissolve the sacrificial layer, causing the Cr layer covering the surface of the sacrificial layer to fall off together with the UV adhesive mask (i.e., "lift-off effect"); finally, only a periodically distributed array of metal Cr dots is left on the surface of the organic semiconductor layer, each Cr dot corresponds to the position of a PMMA micropore, and this dot array is the hard mask for subsequent micropillar etching.

[0076] 6. Etching of micropillar array heterojunctions:

[0077] This step involves two selective etching processes to remove the unmasked regions of the organic semiconductor layer and the perovskite layer, respectively, to form an axial heterojunction micropillar array. The specific steps are as follows:

[0078] Step 1 Etching (Organic Semiconductor Layer): Place the sample with the Cr hard mask into an inductively coupled plasma (ICP) reactive ion etching machine, using the Cr lattice as the hard mask, and introduce a suitable etching gas, such as a CHF3 / O2 mixed gas for organic semiconductors, with a flow rate ratio of CHF3:O2=(2~4):1; set the etching parameters: ICP power 500~800W, RF power 100~200W, vacuum degree 1~5Pa, selectively etch the organic semiconductor layer areas not covered by Cr until the surface of the underlying perovskite layer is exposed.

[0079] The second step is etching (perovskite layer): Without removing the sample, the etching gas is changed, such as a Cl2 / BCl3 mixed gas for perovskite, with a flow rate ratio of Cl2:BCl3=(1~3):1. The etching parameters are adjusted: ICP power 400~700W, RF power 80~150W, vacuum degree 1~5Pa. The perovskite layer areas not covered by Cr are selectively etched. The final structure is: the Cr-covered area retains "lower perovskite pillars + organic semiconductor pillars", that is, an axial micropillar array, and an axial perovskite / organic semiconductor heterojunction (such as a pn junction) is formed at the interface between the perovskite layer and the organic semiconductor layer inside each micropillar.

[0080] 7. Device completed

[0081] The etched sample is taken out and immersed in a special Cr etching solution (such as cerium ammonium nitrate solution) at room temperature for 5-10 minutes until the surface metal Cr hard mask is completely dissolved. Then, the sample is rinsed with deionized water 3-5 times to remove residual etching solution and then dried with a nitrogen gun. At this point, the core structure of the axial micropillar array heterojunction photodetector chip has been fully fabricated.

[0082] The structure of the aforementioned axial micropillar array heterojunction photodetector chip, from bottom to top, is as follows:

[0083] Substrate: As the supporting substrate for the device, it needs to have good flatness and chemical stability (such as glass, silicon wafer).

[0084] Bottom electrode: Located on the upper surface of the substrate, it is responsible for collecting or injecting charge carriers and needs to have good conductivity and light transmittance (such as ITO).

[0085] Axial micropillar array: Located on the upper surface of the bottom electrode, it is the core functional area of ​​the device. Each micropillar consists of a lower first semiconductor pillar and an upper second semiconductor pillar, and an axial heterojunction is formed at the interface between the two. Example 1

[0086] 1. Preliminary preparations:

[0087] After cleaning, an ITO bottom electrode with a thickness of about 150 nm was prepared by electron beam evaporation. After evaporation, the electrode was annealed at 150°C for 30 minutes to enhance conductivity and adhesion.

[0088] 2. Spin coating of semiconductor layers:

[0089] A MAPbI3 perovskite precursor solution with a concentration of 40 wt% (the solvent is a mixture of N,N-dimethylformamide and dimethyl sulfoxide with a volume ratio of 4:1) was prepared and spin-coated on the surface of the ITO bottom electrode at a speed of 3000 rpm for 30 s, and then annealed on a hot stage at 100 °C for 30 min to form a p-type MAPbI3 perovskite layer (semiconductor A layer).

[0090] After the perovskite layer cools to room temperature, a 20 mg / mL PCBM chlorobenzene solution is prepared and spin-coated onto the surface of the perovskite layer at 3000 rpm for 40 seconds. Then, it is annealed on a hot stage at 80°C for 10 minutes to form an n-type PCBM organic semiconductor layer (semiconductor B layer). At this point, the two semiconductor layers form a pn planar heterojunction.

[0091] 3. Spin coating of sacrificial layers and patterned layers:

[0092] A PMMA toluene solution with a concentration of 80 mg / mL was prepared and spin-coated on the surface of the organic semiconductor layer at a speed of 3000 rpm for 30 seconds. Then, it was softened on a hot stage at 100°C for 5 minutes to form a PMMA layer (sacrificial layer).

[0093] Select a commercially available silicone-containing UV adhesive (such as SU-8 adhesive) and spin-coat it onto the PMMA layer surface at 3000 rpm for 30 seconds to form a UV adhesive layer (patterned layer), which is not cured at this time.

[0094] 4. Soft lithography patterning:

[0095] Select a pre-made PDMS elastic template (micropillar diameter 500nm, period 1000nm, height 300nm), place its micropore array face down on the surface of the UV adhesive layer, and hold for 30 seconds;

[0096] A UV lamp with a wavelength of 365nm and a power of 100mW / cm² was used to irradiate the PDMS template from above for 60 seconds to cure the Si-UV adhesive.

[0097] Slowly peel off the PDMS template, and a Si-UV adhesive micropillar array with a diameter of 500 nm and a period of 1000 nm is formed on the surface of the Si-UV adhesive layer.

[0098] 5. Metal mask formation:

[0099] An oxygen plasma etching instrument was used with a power of 100W, a mixture of oxygen plasma and trifluoromethane (CHF3) gas, a flow rate ratio of O2:CHF3=1:(2~5), a flow rate of 50sccm, a vacuum degree of 30Pa, and an etching time of 60 seconds to remove residual adhesive at the bottom of the Si-UV adhesive pillars, thereby obtaining a Si-UV adhesive pillar array mask.

[0100] Replace the etching gas with oxygen plasma at a flow rate of 50-100 sccm and continue etching for 120 seconds to transfer the Si-UV adhesive pillar array mask pattern to the PMMA layer until the surface of the underlying organic semiconductor layer is exposed. Stop etching to form a PMMA micro-hole array.

[0101] Electron beam evaporation technology was used to deposit a 50nm thick Cr layer on the entire surface of the structure.

[0102] The sample was immersed in acetone solution and sonicated for 5 minutes to peel off the PMMA and UV adhesive with Cr layer, leaving only a periodic array of metal Cr dots on the surface of the organic semiconductor layer. This array is the hard mask for subsequent micropillar etching.

[0103] 6. Micropillar etching:

[0104] Step 1 ICP etching: Use CHF3 / O2 mixed gas with a flow rate ratio of CHF3:O2=4:1. Set the ICP power to 600W, RF power to 100W, gas flow rate to 30sccm, and vacuum to 5Pa. Etch the exposed organic semiconductor layer and observe the color change of the sample in real time (the organic semiconductor layer is black, and the perovskite layer is brownish-black). Stop etching when the color turns brownish-black.

[0105] The second step is ICP etching: the gas is replaced with a Cl2 / BCl3 mixed gas with a flow rate ratio of Cl2:BCl3=3:1. The ICP power is set to 500W, the RF power to 80W, the gas flow rate to 25sccm, and the vacuum degree to 5Pa. The exposed perovskite layer is etched, and the etching is stopped when the bottom electrode (ITO, transparent) is exposed. At this time, an axial heterostructure microjunction pillar array of "perovskite (bottom layer) / organic semiconductor (top layer)" is formed.

[0106] 7. Follow-up processing:

[0107] The sample is immersed in a Cr etching solution (such as cerium ammonium nitrate solution) for 10 minutes. The remaining Cr mask is then removed to obtain the axial micropillar array heterojunction photodetector chip.

[0108] Performance testing:

[0109] The axial micropillar array heterojunction photodetector chip constructed in this embodiment was characterized by scanning electron microscopy, and the photoelectric response of the device was tested using a standard sunlight simulator (AM 1.5G, 100mW / cm²).

[0110] Figure 2 This section describes the performance characterization of the axial micropillar array heterojunction photodetector chip constructed in this embodiment, wherein... Figure 2 In the diagram, 'a' represents the characterization of the axial heterostructure micropillar array constructed in this embodiment. Figure 2 In this context, 'b' represents the photoelectric detection performance. (From...) Figure 2 As can be seen, the axial heterostructure pillar array is uniform and consistent, with a clearly visible p-type and n-type semiconductor interface layer. The axial micropillars have a diameter of 500 nm and a height of 650 nm, with the PCBM micropillars having a height of 350 nm and the MAPbI3 micropillars having a height of 300 nm. This proves that the technical route of this embodiment has successfully fabricated an axial heterostructure pillar array. The device achieves a photoresponsivity of 0.64 A / W at a wavelength of 500 nm, exhibiting excellent photoelectric detection performance. Example 2

[0111] The difference between this embodiment and Embodiment 1 is that the perovskite layer material is changed from p-type MAPbI3 to p-type Sb2Te3, while the rest of the process is the same.

[0112] Performance testing:

[0113] The axial micropillar array heterojunction photodetector chip constructed in this embodiment was characterized by scanning electron microscopy, and the photoelectric response of the device was tested using a standard sunlight simulator (AM 1.5G, 100mW / cm²).

[0114] Figure 3 This section describes the performance characterization of the axial micropillar array heterojunction photodetector chip constructed in this embodiment, wherein... Figure 3 In the diagram, 'a' represents the characterization of the axial heterogeneous microstructure column array constructed in this embodiment. Figure 3 In this context, 'b' represents the photoelectric detection performance. (From...) Figure 3 As can be seen, the axial micropillar array structure is uniform with a clear interface. The axial micropillars have a diameter of 500 nm and a height of 450 nm, with the PCBM micropillars having a height of 300 nm and the Sb₂Te₃ micropillars having a height of 150 nm. Optoelectronic performance testing shows a responsivity of 0.52 A / W at a wavelength of 500 nm, indicating good device performance. Example 3

[0115] The difference between this embodiment and Embodiment 1 is that the PDMS template is replaced with a template with a column diameter of 2μm, a period of 4μm, and a height of 2μm, and the perovskite layer material is replaced with p-type MAPbI3 and p-type Sb2Se3.

[0116] Performance testing:

[0117] The axial micropillar array heterojunction photodetector chip constructed in this embodiment was characterized by scanning electron microscopy, and the photoelectric response of the device was tested using a standard sunlight simulator (AM 1.5G, 100mW / cm²).

[0118] Figure 4 This section describes the performance characterization of the axial micropillar array heterojunction photodetector chip constructed in this embodiment, wherein... Figure 4 In the diagram, 'a' represents the characterization of the axial heterogeneous microstructure column array constructed in this embodiment. Figure 4 In this context, 'b' represents the photoelectric detection performance. (From...) Figure 4 As can be seen, the axial micropillar array structure is uniform, with an axial micropillar diameter of 2 μm and a height of 2.35 μm. Specifically, the PCBM micropillars are 1.5 μm high, and the Sb₂Se₃ micropillars are 0.85 μm high. Photoelectric performance testing shows a photoresponsivity of 0.43 A / W at 500 nm, demonstrating excellent photoelectric detection performance. Example 4

[0119] The difference between this embodiment and Embodiment 1 is that the PDMS template is replaced with a template with a column diameter of 400 nm, a period of 600 nm, and a height of 400 nm, and the perovskite layer material is replaced with p-type MAPbI3 and p-type Bi2Se3.

[0120] Performance testing:

[0121] The axial micropillar array heterojunction photodetector chip constructed in this embodiment was characterized by scanning electron microscopy, and the photoelectric response of the device was tested using a standard sunlight simulator (AM 1.5G, 100mW / cm²).

[0122] Figure 5 This section describes the performance characterization of the axial micropillar array heterojunction photodetector chip constructed in this embodiment, wherein... Figure 5 In the diagram, 'a' represents the characterization of the axial heterogeneous microstructure column array constructed in this embodiment. Figure 5 In this context, 'b' represents the photoelectric detection performance. (From...) Figure 5 As can be seen, the axial micropillar array structure is uniform with a clear interface. The axial micropillars have a diameter of 400 nm and a height of 570 nm, with the PCBM micropillars having a height of 250 nm and the Bi₂Se₃ micropillars having a height of 320 nm. Photoelectric performance testing shows a responsivity of 0.59 A / W at 500 nm, demonstrating excellent performance. Example 5

[0123] The difference between this embodiment and Embodiment 1 is that the perovskite layer material is changed from p-type MAPbI3 to Sb2S3.

[0124] Performance testing:

[0125] The axial micropillar array heterojunction photodetector chip constructed in this embodiment was characterized by scanning electron microscopy, and the photoelectric response of the device was tested using a standard sunlight simulator (AM 1.5G, 100mW / cm²).

[0126] Figure 6 This section describes the performance characterization of the axial micropillar array heterojunction photodetector chip constructed in this embodiment, wherein... Figure 6 In the diagram, 'a' represents the characterization of the axial heterogeneous microstructure column array constructed in this embodiment. Figure 6 In this context, 'b' represents the photoelectric detection performance. (From...) Figure 6 As can be seen, the axial micropillar array structure is uniform, with axial micropillars having a diameter of 500 nm and a height of 350 nm. Among them, the PCBM micropillars have a height of 200 nm, and the Sb2S3 micropillars have a height of 150 nm. Photoelectric performance testing shows that it has an A / W of 0.58 at 500 nm, which is excellent. Example 6

[0127] The difference between this embodiment and Embodiment 1 is that the organic semiconductor layer material is replaced by ICBA instead of n-type PCBM.

[0128] Performance testing:

[0129] The axial micropillar array heterojunction photodetector chip constructed in this embodiment was characterized by scanning electron microscopy, and the photoelectric response of the device was tested using a standard sunlight simulator (AM 1.5G, 100mW / cm²).

[0130] Figure 7 This section describes the performance characterization of the axial micropillar array heterojunction photodetector chip constructed in this embodiment, wherein... Figure 7 In the diagram, 'a' represents the characterization of the axial heterogeneous microstructure column array constructed in this embodiment. Figure 7 In this context, 'b' represents the photoelectric detection performance. (From...) Figure 7 As can be seen, the axial micropillar array structure is consistent, with axial micropillars having a diameter of 500 nm and a height of 660 nm. Among them, the ICBA micropillars are 330 nm high, and the MAPbI3 micropillars are 330 nm high. Photoelectric performance testing shows a responsivity of 0.60 A / W at 500 nm, demonstrating excellent performance. Example 7

[0131] The difference between this embodiment and Embodiment 1 is that the organic semiconductor layer material is replaced by PTCDI instead of n-type PCBM.

[0132] Performance testing:

[0133] The axial micropillar array heterojunction photodetector chip constructed in this embodiment was characterized by scanning electron microscopy, and the photoelectric response of the device was tested using a standard sunlight simulator (AM 1.5G, 100mW / cm²).

[0134] Figure 8 This section describes the performance characterization of the axial micropillar array heterojunction photodetector chip constructed in this embodiment, wherein... Figure 8 In the diagram, 'a' represents the characterization of the axial heterogeneous microstructure column array constructed in this embodiment. Figure 8 In this context, 'b' represents the photoelectric detection performance. (From...) Figure 8 As can be seen, the axial micropillar array structure is uniform, with axial micropillars having a diameter of 500 nm and a height of 420 nm. Among them, the PTCDI micropillars have a height of 220 nm, and the MAPbI3 micropillars have a height of 200 nm. Photoelectric performance testing shows that the responsivity at 500 nm is 0.46 A / W, which is good.

[0135] This invention provides an axial micropillar array heterojunction photodetector chip and its fabrication method. Many methods and approaches exist for implementing this technical solution; the above description is merely a preferred embodiment of the invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of this invention, and these improvements and modifications should also be considered within the scope of protection of this invention. All components not explicitly stated in this embodiment can be implemented using existing technologies.

Claims

1. A method for fabricating an axial micropillar array heterojunction photodetector chip, characterized in that, Includes the following steps: S1. Fabricate the bottom electrode on the pretreated substrate; S2. A perovskite layer and an organic semiconductor layer are sequentially prepared on the surface of the bottom electrode by spin coating and annealing. S3. A sacrificial layer and a UV adhesive layer are sequentially prepared on the surface of an organic semiconductor layer by spin coating; S4. UV adhesive layer is imprinted through a polydimethylsiloxane template with a microporous array, and UV adhesive micropillar array is obtained after photocuring; S5. Using a UV adhesive micropillar array as a mask, the sacrificial layer is etched through a dry etching process until the surface of the organic semiconductor layer is exposed, thus obtaining the sacrificial layer micropore array. S6. Electron beam evaporation technology is used to deposit a metal layer on the entire structure surface; Subsequently, the sacrificial layer microporous array was peeled off to obtain the metal lattice; S7. Using a metal dot matrix as a mask, a two-step etching process is used to remove the unmasked areas of the organic semiconductor layer and the perovskite layer, respectively, to form an axial heterojunction micropillar array. The axial micropillar array heterojunction photodetector chip is obtained by removing the metal dot matrix using an etching solution.

2. The preparation method according to claim 1, characterized in that, In S2, the perovskite layer includes any one of p-type MAPbI3, Sb2Te3, Sb2Se3, Bi2Se3, Bi2Te3, and Sb2S3. The spin coating process is: rotation speed 3000~5000rpm, time 30~60s; the annealing process is: 80~150℃, time 10~30min.

3. The preparation method according to claim 1, characterized in that, In S2, the organic semiconductor layer includes any one of n-type PCBM, ICBA, PTCDI, and N2200, and its spin coating process is: rotation speed 3000~5000rpm, time 30~60s; its annealing process is: 60~120℃, time 5~10min.

4. The preparation method according to claim 1, characterized in that, In S3, the sacrificial layer is polymethyl methacrylate or polystyrene, which is prepared by spin coating. The specific process is: rotation speed 2000~4000rpm, time 30~60s; the UV adhesive layer is a silicone-containing UV-curable adhesive, which is prepared by spin coating. The specific process is: rotation speed 3000~5000rpm, time 30~60s.

5. The preparation method according to claim 1, characterized in that, In S5, the dry etching process includes two dry etching processes. The first etching process is to remove the thin adhesive layer by etching with a mixture of oxygen plasma and trifluoromethane gas. The second etching process is to remove the sacrificial layer by etching with oxygen plasma.

6. The preparation method according to claim 1, characterized in that, In S6, the metal layer is a Cr metal layer.

7. The preparation method according to claim 1, characterized in that, In S7, the first step of the two-step etching removes the organic semiconductor layer. The specific etching process is as follows: etching with a CHF3 / O2 mixed gas, with a flow rate ratio of CHF3:O2=(2~4):1, ICP power of 500~800W, RF power of 100~200W, and vacuum degree of 1~5Pa; the second step of the etching removes the perovskite layer. The specific etching process is as follows: etching with a Cl2 / BCl3 mixed gas, with a flow rate ratio of Cl2:BCl3=(1~3):1, ICP power of 400~700W, RF power of 80~150W, and vacuum degree of 1~5Pa.

8. An axial micropillar array heterojunction photodetector chip prepared by the preparation method according to any one of claims 1 to 7.

9. The axial micropillar array heterojunction photodetector chip according to claim 8, characterized in that, The diameter of the axial micropillar is 400 nm to 2 μm, and the height is 350 nm to 2.35 μm.

10. The application of the axial micropillar array heterojunction photodetector chip of claim 8 in any of the fields including imaging, communication, sensing or spectral analysis.

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