Variable link width in two directions for master band chip module connection

Abstract

Aspects relate to variable link widths in two directions for master band chip module connections. In one aspect, different sets of data lines are active with respect to a transmit data line and a receive data line. In one example, a method includes transmitting, over a sideband, an enable request to operate a master band of a die-to-die connection from a module of a first die to a module partner of a second die, the die-to-die connection connecting the first die module to the second die module partner at a specified link width, the specified link width has a specified set of data lines of the primary band. An enable response to operate the primary band at the specified link width is received from the module partner over the sideband, and in response to receiving the enable response, data is communicated with the module partner over the primary band using the specified link width.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority to pending U.S. nonprovisional application No. 18 / 306,034, filed April 24, 2023, which has been assigned to the assignee of this application and is expressly incorporated herein by reference, as fully set forth below and for all applicable purposes. Technical Field

[0003] All aspects of this disclosure relate to data communication between integrated circuit chip modules in general, and specifically to operations performed via a mainband connection having variable link width in both directions. Background Technology

[0004] As integrated circuit (IC) chips become increasingly smaller, it has become possible to package multiple chips into a single package. Each chip can be optimized for the cost, materials, manufacturing process, and size best suited for a specific function. In such a package, the central processing unit (CPU) can be manufactured separately from graphics processors, dedicated processors, volatile memory, non-volatile memory, input / output controllers, or other components. Different components can be packaged together to meet different needs without redesigning any of the individual components. By placing these different chips into a single package, the entire system, including the package, can be made smaller. Similar principles apply to printed circuit board systems and subsystems. Furthermore, connections between different chips can be made faster and at a lower cost. In some cases, smaller chips (e.g., memory, dedicated processors, or interfaces) are referred to as chiplets; however, any chip can be called a chiplet.

[0005] The Universal Chipset Interconnect High Speed ​​(UCIe) specification version 1.0 (UCIe 1.0) defines the physical parameters and protocols for data transfer between chips or between two chipsets. Connections can be direct or via packages. Interconnects can be within a single package or across circuit boards between two different packages. UCIe 1.0 is designed to support interoperability between chipsets from different manufacturers and designers. A UCIe 1.0 interconnect includes a MainBand as the primary data transfer connection and a SideBand as the primary initialization and control connection. A series of state transitions are defined to allow the interconnect to move from SideBand initialization to MainBand initialization to link initialization to an active state, and back to standby and reset states.

[0006] The standard package version of UCIe 1.0 uses a MainBand with 16 data channels and two clock channels. This standard package version is designed for connectors with larger bump pitch (e.g., 100-130 microns) and longer distances (e.g., 10-25 mm), and may be found with two packages connected on a circuit board. The advanced package version of UCIe 1.0 uses a MainBand with 64 data channels, two clock channels, and an additional redundant clock channel. This advanced package version is designed for connectors with smaller bump pitch (e.g., 25-55 microns) and shorter distances (e.g., less than 2 mm), and may be found within the package. New applications for each version and new versions can be developed over time. Summary of the Invention

[0007] The following content presents an overview of one or more embodiments to provide a basic understanding of such embodiments. This overview is not an exhaustive summary of all anticipated embodiments, nor is it intended to identify key or essential elements of all embodiments, nor to depict the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed descriptions that follow.

[0008] In one example, a method includes: transmitting an enable request via a sideband from a module of a first die to a module partner of a second die to operate a main band of a die-to-die connection, the die-to-die connection connecting the first die module to the second die module partner with a specified link width having a specified set of data lines of the main band. Receiving an enable response via the sideband from the module partner to operate the main band with the specified link width, and in response to receiving the enable response, communicating data with the module partner via the main band using the specified link width.

[0009] In another example, a non-transitory computer-readable medium has instructions stored therein for causing a processor of an interconnect link to perform the operations described above.

[0010] In another example, an apparatus includes: a sideband transmitter for a first die module, configured to transmit an enable request to a second die module partner via a die-to-die connected sideband, the sideband requesting operation of the die-to-die connected main band at a specified link width, the specified link width having a specified set of data lines of the main band. A sideband receiver for the module is configured to receive an enable response from the module partner via the sideband, the main band requesting operation of the main band at the specified link width, and a main band transmitter is configured to, in response to receiving the enable response, transmit data to the module partner via the main band using the specified link width.

[0011] To achieve the foregoing and related objectives, one or more embodiments include the features fully described below and specifically pointed out in the claims. The following description and accompanying figures illustrate certain exemplary aspects of one or more embodiments in detail. However, these aspects are merely indications of a number of ways in which the principles of the various embodiments may be employed, and the described embodiments are intended to cover all such aspects and their equivalents. Attached Figure Description

[0012] Figure 1 This is a block diagram of modules and module partners that are coupled together using die-to-die connections, applicable to various aspects of this disclosure.

[0013] Figure 1 This is a block diagram applicable to all aspects of this disclosure of a module and module partner with 16 data channels having a fault receive data line and die-to-die connections coupled together.

[0014] Figure 2 This is a block diagram of a module and module partner with 16 data channels, including a fault transmit data line and nine disable data lines, coupled together in a die-to-die connection, applicable to all aspects of this disclosure.

[0015] Figure 3 This is a block diagram applicable to all aspects of this disclosure of a module and module partner with 16 data channels having 12 disabled receive data lines coupled together in a die-to-die connection.

[0016] Figure 4 This is a block diagram of a module and module partner with 16 data channels coupled together via die-to-die connections, incorporating half of the data channels being disabled, applicable to various aspects of this disclosure.

[0017] Figure 5 This is a block diagram of a module and module partner with 64 data channels having one fault transmit data line and 31 disabled transmit data lines coupled together in die-to-die connection, applicable to all aspects of this disclosure.

[0018] Figure 6 This is a diagram of the connection operation state machine according to various aspects of this disclosure.

[0019] Figure 7 This is a diagram of the master-band initialization state machine based on various aspects of this disclosure.

[0020] Figure 8 It is a signaling diagram of the modules and module partners between the various aspects of this disclosure for initializing the main band messages with the selected link width.

[0021] Figure 9It is a signaling diagram of messages between modules and module partners for changing the width of the mainband data link, according to various aspects of this disclosure.

[0022] Figure 10 This is a signaling diagram of messages between modules and module partners for repairing the mainband after a data line failure, according to various aspects of this disclosure.

[0023] Figure 11 It is a block diagram of a modular die according to various aspects of this disclosure.

[0024] Figure 12 This is a flowchart illustrating various aspects of operating die-to-die connections with variable link width according to various aspects of this disclosure. Detailed Implementation

[0025] The detailed descriptions following, illustrated with reference to the accompanying drawings, are intended as descriptions of various configurations and are not intended to represent the only configurations in which the concepts described herein can be practiced. To provide a comprehensive understanding of the various concepts, the detailed descriptions include specific details. However, these concepts can be practiced without these specific details. In some instances, to avoid ambiguity regarding such concepts, well-known structures and components are shown in block diagram form.

[0026] The term "die-to-die connection" as used in this document can refer to a connection between any two dies (including chips or chiplets). A die can be considered any integrated circuit formed on a wafer and then cut, removed, or otherwise extracted from the wafer. The wafer can be silicon, glass, gallium nitride, or any other suitable material used to form the integrated circuit. For a die-to-die connection, each die includes a module. As in UCIe 1.0, a module includes a die-to-die adapter processor, PHY (physical) logic, and a PHY interface. The interface includes a transmitter and a receiver for each line. A die can have multiple modules that can be coupled to modules of different dies or to the same die. Although examples are presented in the context of UCIe 1.0, this interface specification is not required. The die-to-die connections described in this document can also be used to connect two packages across a printed circuit board.

[0027] Die-to-die connections can provide bidirectional mainband connections with high data rates by using multiple data channels. Each channel has transmit and receive data lines. However, high data rates can consume power and generate heat that is not always necessary. Instead of intermittently operating the mainband connection, a method is described for allowing the mainband connection to operate at variable data rates, i.e., different numbers of data channels can be active at different times to adapt to different situations. The mainband interconnect between two chips can also be configured with different numbers of data lines in each direction. The transmit set and the receive set of lines can be set independently of each other via sideband requests and responses. The number of lines can be set to meet different data rate requirements in each direction. Reducing the number of lines reduces the power consumed by the mainband. The number of lines can be set to avoid using a faulty line only in one direction or using a different faulty line in each direction. The described method can be applied to UCIe MainBand interconnects or other mainband interconnects between IC chip modules with multiple data lines. In this description, a sideband connection is used to initialize the mainband connection. Furthermore, parameters, configuration registers, signaling, and other features can be adapted for variable link width operation.

[0028] Figure 1 This is a block diagram of a first die 101 and a second die 102 coupled together using a 16-channel die-to-die connection 100 (e.g., UCIe standard package interconnect). The die-to-die connection 100 has a fault receive data line 142. Each die may have many other components (not shown) to generate, process, store, or transmit data, or supply or regulate power, or perform operational, managerial, or administrative functions, depending on the nature of the die. The first die 101 has a module 103, and the second die 102 has a module partner 104. Module 103 and module partner 104 may have the same or different structures and may include additional components (not shown), including interfaces, adapters, logic, buffers, etc. Connection 100 has a main band 130 and a side band 136.

[0029] The connection has a main band 130 and a sideband 136. The main band has a transmitting section 132 as viewed from module 103 and a receiving section 134 as viewed from module 103. The sideband 136 also has transmitting and receiving sections, each with a sideband data line and a sideband clock line. The connection is symmetrical because module 103 has a main band transmitter 110, while module partner 104 has a main band transmitter 122. Both transmitters perform the same functions and operations in opposite directions using the same protocol. Similarly, module 103 has a main band receiver 112, and module partner 104 has a main band receiver 120. This description relates to the modules and their construction and operation, but the description applies equally to module partner 104 in the same manner. Repair or training can be initiated on either side, and parameter and configuration changes can be initiated on either side. Module 103 has a sideband transmitter 114 and a sideband receiver 116. Module partner 104 also has a sideband receiver 124 and a transmitter 126.

[0030] UCIe 1.0 features a layered protocol with a physical layer and die-to-die adapters. The physical layer can consist of all types of current packaging options from different manufacturers and manufacturing processes. Examples include 2D packaging, 2.5D packaging, 3D packaging, and other methods such as silicon bridges, embedded multi-die interconnect bridges (EMIB), interposer-based chip-on-substrate (CoWoS) and fan-out chip-on-substrate (FOCoS) interposer packages, as well as any other connections between two dies or two packages on the same substrate. Optical or electrical connections can be made between packages and other components. UCIe may be extended in future revisions to connect dies or packages across rack-based components.

[0031] UCIe 1.0 uses a protocol layer that runs on top of the physical layer, and this protocol layer shares many characteristics with Peripheral Component Interconnect High Speed ​​(PCIe), Compute High Speed ​​Link (CXL), and other pre-existing protocols. The PCIe protocol offers broad interoperability and flexibility. The CXL protocol provides low-latency and high-throughput connections. UCIe 1.0 can be extended in future revisions to include other protocols and further modifications beyond PCIe and CXL.

[0032] In UCIe 1.0, whenever a faulty channel is identified, link degradation can be selected to repair the link and thus avoid the faulty channel. When link degradation is selected during link training, it affects both the transmit and receive lines of each affected channel. Therefore, a faulty line in one direction will disable the corresponding functional line in the other direction as well. This reduces the data rate in both directions, rather than just in the direction with the fault.

[0033] When many data channels are present, such as in a UCIe Advanced Package with 64 bidirectional data channels, a significant amount of power is required to maintain the channels even when they are not in use. UCIe 1.0 provides several low-power or standby states, but these states prevent the full utilization of the data channels. In some cases, the die may have different data rate requirements for transmission than for reception. While one direction may benefit from all 64 channels, the other direction may not be fully utilized. By allowing different link widths in each direction, some data lines in one direction can be de-energized or placed in standby mode, even if corresponding lines in opposite directions are fully utilized. This helps reduce the power consumption for the off or standby lines.

[0034] The structures and methods presented in this paper are described within the context of UCIe 1.0, but can be adapted to future versions of UCIe under any name and other connection configurations with multiple clock channels. Figure 1 In this configuration, the main band 130 has two clock channels that operate at the same frequency at different stages. There is one clock P line and one clock N line in the main band transmit section 132, and one clock P line and one clock N line in the main band receive section 134. In UCIe 1.0, this is the MainBand connection. The two transmit lines of the clock channel are sometimes referred to as TCLKP and TCLKN, while the two receive lines of the clock channel are sometimes referred to as RCLKP and RCLKN. The 16 transmit data channels each have data lines in the transmit section 132 and data lines in the receive section 134, with 16 lines in each direction. The main band connection also has active lines and track lines in each direction.

[0035] In the transmitting section 132, all 16 transmit data lines are active. These lines are labeled 0-15. In the receiving section 134, receive data line 0 is faulty, but receive data lines 1-15 are active. If both lines of a channel need to be active for the channel to function, transmit data line 0 in the transmitting section will be disabled to provide 15 bidirectional data channels. By supporting a different number of transmit data lines than the number of receive data lines, all 16 transmit data lines can be used even when receive data line 0 in the receiving section is faulty. Receive data line 0 is provided as an example. Any one or more data lines in either direction may fail, and the main band can be reconfigured using the available functional data lines in each direction.

[0036] Figure 2This is a block diagram of a first die 201 and a second die 202 coupled together using a connection 200 (such as a die-to-die connection 200, e.g., a UCIe 1.0 standard package interconnect). In this example, the die-to-die connection 200 has one fail transmit data line 242 and nine disable data lines 244. Module 203 of the first die 201 has a transmitter 210 for the main band, which is connected to the transmit section 232 of the main band 230. The transmit section 232 includes 16 transmit lines, a clock P line, a clock N line, an active line, and a track line. The transmit section 232 is coupled to a module partner receiver 220 for the main band. The module partner receiver 220 is part of a module partner 204 of the second die 202. Module 203 has a main band receiver 212 connected to the receive section 234 of the main band 230. The receive section 234 includes 16 receive lines, a clock P line, a clock N line, an active line, and a track line. The receiving section 234 is coupled to the main band transmitter 222 of the module partner 204.

[0037] Module 203 also includes a sideband transmitter 214, which is coupled to a sideband receiver 224 of module partner 204 via a sideband 236 of die-to-die connection 200. Module 203 also includes a sideband receiver 216, which is coupled to a sideband transmitter 226 of module partner 204 via a sideband 236 of die-to-die connection 200. The sideband has a sideband data line and a sideband clock line in each direction. In UCIe 1.0, the sideband has only one bidirectional clock channel.

[0038] As shown in the figure, transmit data line 8 242 within the transmit section 232 of the main band 230 is faulty. This is indicated by the truncated arrow indicating that it does not reach the receiver. This has disabled functional transmit data lines 9-15 244 depending on how channel repair is performed. The disabled lines are indicated by the dashed arrows from module transmitter 210 to module partner receiver 220. Transmit data lines 0-7 are active and operational. This is indicated by the solid arrows from the transmitter to the receiver. The receive section 234 of the main band 230 is fully operational, with all receive data lines 0-15 active and operational. This is permitted when module 203 and module partner 204 are configured to allow different transmit and receive link widths. Transmit data line 8 242 is provided as an example; any one or more transmit and receive data lines may fail. The main band 230 can be reconfigured in each direction using the available functional lines in different ways to provide a higher data rate in one direction when the functional lines are permitted.

[0039] Considering the conditions of the lines in the transmitting section 232, the module transmitter 210 can disable faulty lines 242 and 8. Furthermore, lines 9-15 and 244 can also be disabled. At the module partner receiver 220, unused lines, faulty data lines 242, and disabled data lines 244 can be tri-state. This reduces crosstalk on the data lines. In this configuration, line 8, used for faulty lines, is tri-state. Lines 0-7 are the designated set of data lines for the transmitting section 232 of the main band 230. Lines 9-15 are receive lines that do not belong to the designated set of data lines and are tri-state.

[0040] Figure 3 This is a block diagram of a first die 301 having module 303 and a second die 302 having module partner 304, the first die and the second die being coupled together via a 16-channel die-to-die connection 300 (e.g., UCIe 1.0 standard package interconnect). In this example, the die-to-die connection 300 has 12 disable receive data lines 342, 344. Module 303 has a main band transmitter 310 connected to a transmit section 332 of the main band 330. The transmit section 332 includes 16 transmit lines, a clock P line, a clock N line, a valid line, and a track line. The transmit section 332 is coupled to a main band receiver 320 of module partner 304. Module 303 has a main band receiver 312 connected to a receive section 334 of the main band 330. The receive section 334 includes 16 transmit lines, a clock P line, a clock N line, a valid line, and a track line. The receiving section 334 is coupled to the main band transmitter 322 of the module partner 304.

[0041] Module 303 also includes a sideband transmitter 314, which is coupled to a sideband receiver 324 of module partner 304 via a sideband 336 through a die-to-die connection 300. Module 303 also includes a sideband receiver 316, which is coupled to a sideband transmitter 326 of module partner 304 via a sideband 336 through a die-to-die connection 300. The sideband has a sideband data line and a sideband clock line in each direction. In UCIe 1.0, the sideband has only one bidirectional clock channel.

[0042] As shown in the figure, the first 12 receive data lines 342, 0-11, within the receive section 334 of the main band 330 are disabled. These channels may be functional lines disabled due to lack of need. The last 4 receive data lines 344 of the 16 data lines in the receive section 334 of the main band are operational. This reduces the power consumption of the receive section 334 of the main band 330 by more than half. Simultaneously, all 16 data lines 0-15 of the transmit section 332 of the main band 330 are operational. Module 303 or an upstream component can be configured to adjust the number of disabled lines in each direction to meet requirements. The upstream component can be configured to send a command to the module to change the number of disabled lines in the transmit or receive direction. In some examples, module 303 or module partner 304 may be of a type with different data rate requirements in a particular direction. For example, the sensor may have a higher transmit rate than the receive rate. The main band 330 can be configured according to the nature of module 303 or module partner 304.

[0043] Figure 4 This is a block diagram of a first die 401 having module 403 and a second die 402 having module partner 404, the first die and the second die being coupled together via a 16-channel die-to-die connection 400 (e.g., UCIe 1.0 standard package interconnect). The die-to-die connection has eight disabled data channels. Module 403 has a main band transmitter 410 connected to a transmit section 432 of main band 430. Transmit section 432 includes a data channel with 16 transmit lines, a clock P line, a clock N line, a valid line, and a track line. Transmit section 432 is coupled to a main band receiver 420 of module partner 404. Module 403 has a main band receiver 412 connected to a receive section 434 of main band 430. Receiver section 434 includes a data channel with 16 transmit lines, a clock P line, a clock N line, a valid line, and a track line. Receiver section 434 is coupled to a main band transmitter 422 of module partner 404.

[0044] Module 403 also includes a sideband transmitter 414, which is coupled to a sideband receiver 424 of module partner 404 via a sideband 436 of die-to-die connection 400. Module 403 also includes a sideband receiver 416, which is coupled to the sideband transmitter 426 of module partner 404 via a sideband 436 of die-to-die connection 400. The sidebands have sideband data lines and sideband clock lines in each direction.

[0045] As shown in the figure, the last 8 transmit data lines 444, 8-15 within the transmit section 432 of the main band 430 are disabled. The last 8 receive data lines 448, 8-15 within the receive section 434 of the main band 430 are unused and can be tri-state. At the module partner, the last 8 lines 444 leading to the main band receiver 420 are tri-state, and the last 8 lines 448 of the main band transmitter 422 are disabled. This disables the last 8 data channels, which is half of the 16 available data channels. The first 8 transmit data lines 442, 0-7 and the first 8 receive lines 446, 0-7 remain active and operational. This reduces the power consumption of the main band data channels by almost half. Module 403 or upstream components can be configured to adjust the number of disabled lines in each direction to meet service requirements. In this example, the data link width in the receive and transmit directions is kept symmetrical for the matched data rate in each direction.

[0046] Figure 5 This is a block diagram of a first die 501 having module 503 and a second die 502 having module partner 504, the first die and the second die being coupled together via a 64-channel die-to-die connection 500 (e.g., UCIe Advanced Package Interconnect). The die-to-die connection 500 has one fail transmit data line and 31 disable transmit data lines. Module 503 has a master band transmitter 510 connected to a transmit section 532 of master band 530. Transmit section 532 includes 64 transmit data lines, a clock P line, a clock N line, an active line, and a track line. Advanced Package master band transmit section 532 also includes a redundant clock line (RD clock) and four redundant data lines (RD data). The redundant lines are configured for use in the event of a failure of one or more of the primary data or clock lines. Transmit section 532 is coupled to a master band receiver 520 of module partner 504. Module 503 has a master band receiver 512 connected to a receive section 534 of master band 530. The receiver section 534 includes 64 receive data lines, a clock P line, a clock N line, an active line, a track line, a redundant clock line, and 4 redundant data lines. The receiver section 534 is coupled to the main band transmitter 522 of module partner 504.

[0047] A bidirectional redundant clock channel is provided as a recovery mechanism in case of a failure in one of the clock channels. A failure on either clock channel P or N will result in the configuration of a redundant clock channel to replace the failed clock channel. The module also has a sideband transmitter 514, which is coupled to a sideband receiver 524 of the module partner 504 via a sideband 536 of a die-to-die connection 500. The sideband 536 can be used with… Figures 1 to 4The sideband examples are the same or similar. Module 503 has a sideband receiver 516, which is coupled to the sideband transmitter 526 of module partner 504 via a sideband 536 of die-to-die connection 500. The sideband has a bidirectional data channel and a bidirectional clock channel.

[0048] In this example, transmit data line 0 is faulty. Furthermore, transmit data lines 1-31 have been disabled to reduce the data link width to 32 active transmit data lines instead of the original 64. Receive data lines remain unchanged. This example is provided to illustrate a variation where functional lines can be disabled even when faulty lines are present. Faulty and disabled lines may also be present, or alternatively, in the receive section 534 of the main band 530. Specific lines are provided as examples, and different lines may be affected. Furthermore, this example uses a die-to-die connection applicable to 16 data channels, and... Figures 1 to 4 Any of the examples in the examples can be applied to this 64-channel die-to-die connection.

[0049] Figure 6 This is a state machine diagram of state machine 600 based on some aspects of the connection operation state machine. The state machine is related to the link layer form of the physical layer connection (e.g., 100, 500 described above). As described above, the same state machine can be used in UCIe advanced mode or standard mode or other configurations with adaptation to accommodate channel differences. State machine 600 starts from reset state 602, which can be obtained at startup or upon recovery from a deep sleep or low power state (e.g., L2 state 614), or upon recovery from a fault. Reset state 602 can also be entered via commands from higher-level layers of the die (e.g., commands for switching to different master band link widths).

[0050] The state machine transitions from reset state 602 to sideband initialization state 604. The sideband is the low-speed, high-reliability portion of the die-to-die connection. It is configured to be easily initialized even in the presence of other faults or challenging environmental conditions. After sideband initialization state 604, the state machine can proceed to mainband initialization state 606. The mainband initialization state includes a variable link width parameter substate 620. In some aspects, different link widths can be specified for the mainband's transmit and receive lines. In other aspects, different link widths can be specified for both the mainband's transmit and receive lines. These can be initialized using mainband initialization (MBINIT) in the mainband initialization state. The specified link width can be exchanged as a parameter in a sideband message and can be stored in a link configuration register.

[0051] After completing the main band initialization state 606 (including the variable link width parameter sub-state 620), state machine 600 advances to the link initialization state 610. Link initialization state 610 refers to the connection between modules and their partners. In some examples, only connections within a specified link width that were trained in the main band training state 608 and initialized in the link initialization state 610 are considered. If a link with 64 data channels has... Figure 5 If the specified link width for the 16 data channels is used, then the main band training state 608 and link initialization state 610 will complete much faster. After link initialization state 610, the state machine moves to active state 612 for data communication between modules and module partners. The state machine remains in active state 612 until an event requires a transition.

[0052] One type of transition is to PHY retraining state 616. PHY retraining state 616 allows the PHY layer of the connection to be retrained in case of errors or changes in the environment or conditions on the connection. As an example, the mechanism for reconfiguring the number of active data lines or the selection of those active data lines in the transmit or receive direction will transition to PHY retraining state 616 during active state 612. A new configuration of the active data lines can be trained in PHY retraining state 616. After PHY retraining state 616, the state machine returns to master band training state 608 to train the new master band configuration, then returns to link initialization state 610, and finally returns to active state 612, which has been recovered from PHY retraining state 616.

[0053] Another type of transition is to L1 / L2 state 614. L1 / L2 state 614 includes two different low-power or standby conditions to accommodate inactivity on die-to-die connections. To reduce power consumption, heat generation, and / or wear on dies or connection components, state machine 600 can transition to L1 standby, which disables many components connected, especially those across the mainband section. State machine 600 transitions from L1 standby in L1 / L2 state 614 to mainband training state 608. From mainband training state 608, the state machine transitions to link initialization state 610 and returns to active state 612. L2 standby is a deeper standby involving more components, including clock shutdown to save more power. Starting from L2 standby, state machine 600 transitions from L1 / L2 state 614 to reset state 602. From reset state 602, the complete process of state machine transitions is executed to reach active state 612. There may be more or fewer standby or low-power states than L1 standby and L2 standby to suit different specific implementations.

[0054] Another state is the training error state 618, which is reached as a transition from the reset state 602. This state is dead and results in an inoperable connection. If the module is restarted, it re-enters the reset state 602 and may be able to initialize or return to the training error state 618.

[0055] Using state machine 600, different link widths are entered or exited using variable link width parameter sub-state 620. Variable link width parameter sub-state 620 can be entered as part of main band initialization state 606. When the link width of the connected main band portion changes, the main band connection is initialized for the new link width in main band initialization state 606, then trained for the new link width in main band training state 608, and then state machine 600 transitions to link initialization state 610 and activity state 612.

[0056] From reset state 602, the system enters the variable link width parameter substate 620. In some cases, a die-to-die connection is being initiated, and as the state machine progresses through the mainband initialization state, the connection can be initialized through all states using the default link width or a specified link width different from the default link width. In some cases, one or more data lines may fail; in this case, the state machine returns to reset state 602 to identify the fault and initialize the mainband connection using one or more functional data lines. In some cases, higher layers of the module command a transition to a different link width for receive data lines, transmit data lines, or both due to service, performance, thermal, or other conditions. State machine 600 can return to state 602 via the L2 standby transition under L1 / L2 state 614.

[0057] Figure 7 Based on several aspects, the master band initialization state machine 700 provides additional details regarding the master band initialization state 606. The master band initialization state machine 700 transitions from the master band initialization state to parameter state 702, during which parameters for die-to-die connection operations are shared between the module and its module partners. Next, the link width selection state 704 includes selecting the link width for the transmit and receive data lines for the active state. The link width selection state 704 also includes setting parameters in the link configuration register to support the selected mode.

[0058] In the link width selection state, you can choose... Figures 1 to 5 Any data line configuration or other configuration. The illustrated configuration is provided as an example, and other configurations are possible. After link width selection state 704, proceed to calibration state 706 to calibrate the link to use the selected clock and data channel.

[0059] The clock state 708 is fixed to follow the calibration state 706, and training patterns can be transferred and received between modules and module partners to enable clock connections between the test module and module partners.

[0060] The valid state 710 is used to train the valid channel for framing data on the data line. The valid signal is a type of clock signal. In UCIe 1.0, the valid signal marks the beginning and middle of data packets on the data line. For each 8-bit data packet with an 8-unit interval (UI), the valid signal is asserted for the first 4 UIs and deasserted for the second 4 UIs. It is asserted again at the beginning of the next 8-bit packet.

[0061] Reversing the master tape state 712 allows testing the master tape to determine whether the reversal should be applied to the data channels connected to the master tape. Using the reversal, channel 15 or channel 63 becomes channel 0, and the channel designation continues counting up to channel 0, which becomes channel 15 or channel 63.

[0062] Repairing the main band state 714 is the training state for main band data communication, where known patterns are sent on the data channels to test the correct operation of each data channel. Each data channel is tested on both the transmit and receive data lines. When a faulty data line is found in either direction via Repairing the Main Band State 714, the link width can be modified to eliminate the faulty data line.

[0063] In UCIe 1.0, utilizing correct and valid framing on valid channels and the forwarding clock, the UCIe module tests the data channels in the repair mainband state while transmitting 128 iterations of the per-channel ID pattern (LSB priority) on all N MainBand data channels. N is 68 (64 data + 4 RD) for Advanced Encapsulation interfaces and 16 for Standard Encapsulation interfaces. The UCIe module partner performs per-channel comparisons on its receivers on all N channels. A channel detection is considered successful if at least 16 consecutive iterations of the per-channel ID pattern are detected. The UCIe module partner records the detection results on its receiver lines for channel fault detection. After transmitting 128 iterations of the per-channel ID pattern, the UCIe module stops transmitting patterns and transmits an MBINIT.REVERSALMB result req sideband message to obtain the recorded results. The UCIe module partner stops comparing and responds with an MBINIT.REVERSALMB result resp sideband message with N bits per channel result (68 for Advanced Encapsulation interfaces and 16 for Standard Encapsulation interfaces).

[0064] After completing the main band initialization state machine 700, the link training state machine then transitions from the main band initialization state 606 to the main band training state 608, as follows: Figure 6 As shown.

[0065] Figure 8 This is a signaling diagram based on some aspects of the messages between the first die module 802 and the second die module partner 804 for initializing the main band with the selected link width. When the die-to-die adapter processor... Figure 6 When the module moves from reset state 602, signaling 800 can be used. This can occur, for example, during startup or during a transition from L2 state 614. Signaling begins after sideband initialization is performed. The module and its partner transmit a message indicating sideband initialization is complete (812). This corresponds to... Figure 6 The sideband initialization state 604 ends. Module 802 then sends a main band initialization parameter request 814 to module partner 804. Module partner 804 responds with a main band initialization parameter response 816. These are also achieved through the initialized sideband exchange. Module 802 and module partner 804 perform this handshake to determine whether variable link width is supported. These parameters may include variable link width support parameters. The parameters can then be stored in the link configuration register.

[0066] After parameter exchange, perform mainband clock training 198 across mainband and mainband data line training 820 across mainband.

[0067] UCIe 1.0 provides a more concrete example of parameter exchange. An exchange called MBINIT.PARAM exists. Parameters used to implement variable link width can be exchanged during this exchange or during different operations. In UCIe 1.0, for both standard and advanced encapsulation, the MainBand initialization request message is called the MBINIT.PARAM configuration request. This is a sideband request to exchange parameters with a UCIe module partner. This request includes parameters. The response from the module partner is called MBINIT.PARAM configuration resp, and is also a sideband message. When variable link width is supported, another parameter can be added to the same sideband message. This parameter is referred to herein as VB_sup, the support parameter, where a value of "0" or low indicates that variable link width is not supported, and a value of "1" or high indicates that variable link width is supported.

[0068] The transmitter request module partner in the sideband support request also supports variable link width, with additional support parameters. The module partner responds with the support parameter VB_sup, which is set to high or low to indicate whether the module partner supports variable link width. If both the request and response contain a parameter set to high, variable link width is supported, and the parameter is stored in the link configuration register. The support parameter VB_sup can be referred to by any other name. In some examples, the module and module partner are configured to support variable link width without a handshake to transmit and receive parameters via the sideband request and response shown in the figure.

[0069] Administrators, implementers, manufacturers, suppliers, local or remote controllers, or another entity may choose to allow die-to-die connections to operate with variable link width. In some aspects, this is achieved by setting parameters in the main band configuration register (e.g., the link configuration register) to allow variable link width operation. Parameters can be added to a UCIe 1.0 register called MainBandconfig_reg. Alternatively, a different configuration register may be used. During the main band parameter initialization phase, which includes main band initialization parameter request 812 and main band initialization parameter response 816, module 802 and module partner 804 will determine whether variable link width is supported on both the module and module partner via a sideband handshake. This can be done based on support parameters.

[0070] Following the link width initialization process, mainband clock training 818 can begin. This process may include initialization requests and responses, followed by a clock repair training pattern that is bidirectional over the mainband connection and follows a known pattern, enabling the transmitter and receiver at each end to detect and train against the clock signal. Any other suitable clock training process can be used. After mainband clock training 818, mainband data line training 820 can follow. Mainband data line training can also be bidirectional over all enabled data lines of the mainband.

[0071] At 828, the module selects a link width or receives a selection of the link width from a higher-level component. This can be in response to a detected data channel failure, a command from a higher level, anticipated data service requirements, or for any other reason. The module then begins the link width configuration process 806. Module 802 transmits a send link width request 830 to module partner 804. The send link width request is an enable request to the module partner to operate the main band with the specified send link width. The specified send link width includes a specified set of transmit data lines with the main band. The request may include send enable parameters and send link width parameters. This is transmitted via sideband. The send link width request is then responded to with a send link width response 832, which may also include send enable parameters and link width parameters. The module then transmits a receive link width request 834. The receive link width request is an enable request to the module partner to operate the main band with the specified receive link width. The specified receive link width includes a specified set of receive data lines with the main band. The request may include receive enable parameters and receive link width parameters. The request is responded to by a receive link width response 836, which may also include receive enable parameters and receive link width parameters.

[0072] In this example, the transmit link width request 830 and the receive link width request 834 are indicated as separate requests. However, these can be combined into a single link width request for the transmit data line and also for the receive data line. A single link width request can indicate different link widths for transmit and receive, or a single link width for both transmit and receive.

[0073] Upon completion of transmit link width request 830 and receive link width request 834, the master band for the new transmit and receive link widths has been configured at both module 802 and module partner 804. Then, signaling proceeds to link initialization 822. This corresponds to... Figure 6 The link initialization state is 610. Then, signaling proceeds to mainband communication 824. This corresponds to... Figure 6 The activity state is 612. In the example, main band clock training 818 and main band data line training 820 are instead executed after the link width configuration process. This allows training to be performed only on a specified set of data lines within a specified link width.

[0074] Table 1 is an example of a portion of a link configuration register (referred to herein as config_reg), which can be configured to support variable link widths for the main band (e.g., a high-level packaged MainBand or a standard packaged MainBand). More registers can be added to accommodate further link variations and other connectivity configurations. In some respects, the value in each position is set to zero by default and at startup. During the main band initialization state 606 described above, and specifically during the variable link width parameter sub-state 620, a sideband support request is transmitted to the module partner to support variable link widths for the main band. This is part of the main band initialization parameter request 814 and may include support parameters. Upon receiving a sideband support response from the module partner (represented as main band initialization parameter response 816, which may include support parameters), support bits can be added to the configuration register.

[0075] Table 1 shows the support bits TxD_sup for the transmitting side and RxD_sup for the receiving side. In the example, when both are "1" or high, both dies support the specified link width for the main band's transmit data lines and a separate specified link width for the receive data lines. In the example, when both are "0" or low, neither dies supports the specified link width for the transmit data lines or the specified link width for the receive data lines. In the example, when TxD_sup is high and RxD_sup is low, both dies support variable link widths, except that the specified set of transmit data lines must equal the specified set of receive data lines. In other words, the data channel width can vary, but the number of lines in each direction remains constant.

[0076] Upon receiving a sideband enable response (shown as transmit link width response 832 and receive link width response 836) from the module partner, the remaining link configuration parameters in Table 1 can be set for the transmit and receive lines, respectively. Specifically, Tx_VB1 and Tx_VB0 are transmit link width parameters, and TxD_en is a transmit enable parameter. These can be set based on transmit link width response 836. Rx_VB1 and Rx_VB0 are receive link width parameters, and RxD_en is a receive enable parameter, which can also be set based on receive link width response 836.

[0077] Tx_config_reg Tx_VB1 Tx_VB0 TxD_en TxD_sup Rx_config_reg Rx_VB1 Rx_VB0 RxD_en RxD_sup

[0078] Table 1

[0079] When the TxD_en bit (transmit enable parameter) is set to "1" or high, the main band connection operates with a variable transmit data link width. The link width is specified by the other two parameters as shown in Table 2. Similarly, when the RxD_en bit (receive enable parameter) is set to "1" or high, the main band connection operates with a variable receive data link width.

[0080] Table 2 is an example of a link width selection table configured to provide a specified data link width in the transmit data lines using Tx_VB1 and Tx_VB0. Similarly, the specified data link width in the receive direction is provided by a combination of Rx_VB1 and Rx_VB0. In this example, 2 bits provide four possible options: 64, 32, 16, and 8 active lines. These are only applicable to 64-channel master bands, such as UCIe Advanced Packaging. For 16-channel master bands, different options can be used, such as 16, 8, 4, and 2 lines. More or fewer bits can be used to represent more or fewer data line selections for the data line set in Table 2. In the example, the Tx_VB2 bit is also used to allow 8 possible data line selections instead of 4, as shown in the figure.

[0081] Tx_VB1 Tx_VB0 Data bandwidth Rx_VB1 Rx_VB0 0 0 64 activity lines 0 0 0 1 8 activity lines 0 1 1 0 16 activity lines 1 0 1 1 32 activity lines 1 1

[0082] Table 2

[0083] Figure 9 This is a signaling diagram between module 902 and module partner 904 for messages used to change the mainband data link width. Doing so can reduce power, reduce data rate, or gain other benefits. This occurs when the die-to-die adapter processor moves from active state 612 to PHY retraining state 616. Figure 6 Signaling 900 can be used during the main band training state 608. Signaling can also be used for the transition from active state 614 to main band training state 608 via L1 state 614. Signaling begins after sideband initialization is performed. The module and module partner have already initialized main band data communication 922. In this example, module 902 and module partner 904 have performed a parameter handshake to determine whether variable link width is supported.

[0084] A local or remote controller or another entity determines that the die-to-die connection should be changed to a different link width. In response to this determination or command, module 902 determines to change the link width 928. The module then begins the link width configuration process 906. Module 902 transmits a send link width request 930 to module partner 904. The send link width request is an enable request to the module partner to operate the main band with the specified send link width. The send link width request is then responded to with a send link width response 932. The module then transmits a receive link width request 934. The receive link width request 934 is an enable request to the module partner to operate the main band with the specified receive link width. This request is responded to with a receive link width response 936. If no such response is found, main band data communication 922 may continue.

[0085] In some examples, only the transmit link width is changed. In this case, a receive link width request 934 is not required, and a receive link width response 936 is not received. In some examples, only the receive link width is changed. In this case, a transmit link width request 930 is not required, and a transmit link width response 932 is not received. In some examples, both the transmit and receive link widths will be changed to the same link width. In this case, only one link width request may be needed. A sideband enable request to operate the main band with a specified link width can be used in any of these examples and is used to independently change the link width in both directions.

[0086] The specified set of transmit data lines and the specified set of receive data lines can be included in the request and response using parameters such as Tx_VB, Tx_VB0, Rx_VB1, and Rx_VB0, or any other suitable information parameters. The process continues with optional mainband training of the specified set of data lines, then link initialization at 908, and mainband data communication 910 using the newly specified transmit link width and specified receive link width. In some examples, mainband training has already been performed for the original mainband data communication 922, and it is not necessary to repeat mainband training, therefore this operation is not performed.

[0087] Figure 10 This is a signaling diagram between module 1002 and module partner 1004 for repairing the mainband after a data line failure. The signaling diagram shows the process from die-to-die adapter processor moving from active state 612 to PHY retraining state 616 and then... Figure 6 When the main band training state is 608, signaling 1000 can be used. Signaling begins after sideband initialization is performed. The module and module partner have already initialized main band data communication 1012. In this example, module 1002 and module partner 1004 have performed a parameter handshake to determine whether variable link width is supported.

[0088] Module 1002 has determined that a data line in the main band 1028 is faulty. In response to this determination or command, module 1002 determines to change the link width to exclude the faulty data line. Module 1002 then begins the link width configuration process 1006. Module 1002 transmits a transmit link width request 1030 to module partner 1004 via a sideband. The transmit link width request is an enable request to the module partner to operate the main band with a specified transmit link width to exclude any faulty transmit data lines. The request for transmit link width is then responded to via a sideband with a transmit link width response 1032. The module then transmits a receive link width request 1034 via a sideband. The receive link width request 1034 is an enable request to the module partner to operate the main band with a specified receive link width to exclude any faulty receive transmit lines. If a faulty transmit data line exists that is different from the faulty receive data line, the different line can be excluded by specifying a different set of transmit data lines from the specified set of receive data lines. The receive link width request 1034 is responded to via a sideband by the receive link width response 1036.

[0089] Following the link width configuration process, mainband clock training 1014 can begin. This process may include initialization requests and responses, followed by a clock repair training pattern that is bidirectional over the mainband connection and follows a known pattern, enabling the transmitter and receiver at each end to detect and train against the clock signal. Any other suitable clock training process can be used. After mainband clock training 1014, mainband data line training 1016 can occur. Mainband data line training can also be bidirectional over all enabled data lines in the mainband. Then, the signal proceeds to link initialization 1018, followed by mainband data communication 1020 using the new link width.

[0090] Figure 11 This is a block diagram of an example of a hardware implementation of die 1100 (e.g., a central processing unit, graphics processing unit, dedicated processor, volatile memory, non-volatile memory, input / output controller, or any other suitable component having a die-to-die connection 1110 with sidebands and a mainband). In this example, the die has a processor 1120 and a memory 1105 for performing the main operations of the die. The die has a module 1114 for supporting the die-to-die connection 1110 with die-to-die adapter processor 1104, computer-readable medium 1106, PHY logic 1112, PHY receive block 1116, and PHY transmit block 1118. Die-to-die adapter processor 1104 performs the operations described above to serve the die-to-die connection 1110 between die 1100 and one or more other dies (not shown).

[0091] According to various aspects of this disclosure, module 1114 can be used to implement elements, any part of elements, or any combination of elements. Examples of module 1114 include microprocessors, microcontrollers, digital signal processors (DSPs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuitry, and other suitable hardware configured to control die-to-die connections 1110 and clock modes as described throughout this disclosure. In various examples, die 1100 can be configured to perform any one or more of the functions described herein. The die contains other components (not shown) configured to perform other functions of the die, as applicable to the type of die.

[0092] In this example, the module has a processor 1120, a memory 1105, and a computer-readable medium 1106 for performing the main operations of the module. A die-to-die adapter processor 1104 performs the operations described above to serve an interconnect 1102 between module 1114 and module partner 1004 or another module. According to various aspects of this disclosure, module 1114 may be used to implement elements or any part of elements or any combination of elements. Examples of processors include central processing units, graphics processors, dedicated processors, memory controllers, and input / output controllers. Examples of die-to-die adapter processor 1104 include microprocessors, microcontrollers, digital signal processors (DSPs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuitry, and other suitable hardware configured to control die-to-die connections and clock modes as described throughout this disclosure. In various examples, module 1114 may be configured to perform any one or more of the functions described herein. The module contains other components (not shown) configured to perform other functions of the module, as applicable to the type of die.

[0093] In this example, die 1100 can be implemented using a bus architecture (typically represented by bus 1102). Bus 1102 may include any number of interconnect buses and bridges, depending on module 1114, the specific application of die 1100, and overall design constraints. Bus 1102 communicatively couples together various circuits including processor 1120, die-to-die adapter processor 1104, memory 1105, and computer-readable medium (typically represented by computer-readable medium 1106) storing instructions thereon. Bus 1102 may also link various other circuits, such as timing sources, peripherals, data buffers, modules, power management circuitry, and other processing cores, which are not further described. Bus interface 1108 provides an interface between bus 1102 and other optional external interfaces, such as control interface 1130 and data interface 1132. Processor 1120 is at a higher level relative to die-to-die adapter processor 1104 and is coupled to die-to-die adapter processor via bus 1102. Processor 1120 may communicate operation, management, or management control with die-to-die adapter processor 1104, or die-to-die adapter processor 1104 may operate autonomously. In some examples, the die-to-die adapter receives a request to reduce the data rate of the main band from a higher layer (e.g., processor 1120).

[0094] Control interface 1130 can be used to provide a communication interface or component for communicating with various other devices and equipment (e.g., other devices housed within the same package or system) via an internal bus or external transmission medium, such as command and control interfaces for power regulation, power-on testing, and other purposes. Data interface 1132 can be used to provide data connections to other types of components within the package or system, in addition to die-to-die connection 1110. Control interface 1130 and data interface 1132 can be connected to higher layers to receive reset and configuration commands that can switch the die-to-die processor to single-clock mode.

[0095] Module 1114 includes a PHY receive block 1116 corresponding to the sideband and mainband receivers described above, and a PHY transmit block 1118 corresponding to the sideband and mainband transmitters described above. PHY transmit block 1116 and PHY receive block 1118 are coupled to a die-to-die connection 1110, which corresponds to the physical portions of the sideband 136 and mainband 130 channels described above, these channels being coupled to a first die 101 and a second die 102 via pins on corresponding die connectors. The module also includes PHY logic 1112, which may include link logic to control data applied to each line and the state machine described above, under the control of a die-to-die adapter processor. PHY logic 1112 may also include a clock generator coupled to a clock source to generate the sideband and mainband clock signals as described above.

[0096] The die-to-die adapter processor 1104 is responsible for managing the PHY logic 1112 and interface processing, including executing software stored on the computer-readable medium 1106. When executed by the die-to-die adapter processor 1104, the software causes module 1114 to perform various functions described below for any particular device. The computer-readable medium 1106 and memory 1105 can also be used to store data manipulated by the die-to-die adapter processor 1104 during software execution.

[0097] The die-to-die adapter processor 1104 may be part of one or more other processor cores (not shown) of the processor 1120 or die 1100, and performs operations by means of the processor core executing software stored in the computer-readable medium 1106, or the die-to-die adapter processor 1104 may be independent of any other processing resources of the die 1100 to execute software stored on the computer-readable medium 1106 using its own processing resources. Software should be broadly interpreted as instructions, instruction sets, code, code segments, program code, programs, subroutines, software dies, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description languages, or others. The software may reside on the computer-readable medium 1106. The die-to-die adapter processor 1104 controls operations performed by a state machine, such as... Figure 5 and Figure 6 Those operations, and cause signaling diagrams 800, 900, and 1000, and cause the clock repair training pattern to be sent and received.

[0098] Computer-readable medium 1106 may be a non-transitory computer-readable medium. By way of example, non-transitory computer-readable media include magnetic storage devices, flash memory devices, random access memory (RAM), read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), registers, and any other suitable medium for storing software and / or instructions accessible and readable by a controller. Computer-readable medium 1106 may reside in another portion of module 1114 or die 1100. Computer-readable medium 1106 may be embodied in firmware for the operation of a state machine or parameters of an ASIC. Those skilled in the art will recognize that the optimal implementation of the functionality described throughout this disclosure depends on the specific application and the overall design constraints imposed on the system.

[0099] Die 1100 may be configured to perform any one or more of the operations described herein. In some aspects of this disclosure, such as the die-to-die adapter processor 1104 utilized in die 1100, circuitry configured for various functions may be included.

[0100] The die-to-die adapter processor 1104 is coupled to memory 1105 via bus 1122. Memory 1105 includes parameter and configuration registers 1115, which may include parameters for different link widths of the data channels as shown in Tables 1 and 2. It may also store any other parameter and configuration values, including those for mainband operation or CXL operation in PCIe.

[0101] The die-to-die adapter processor 1104 may include variable link width support circuitry 1141 to request and receive responses for transmitting a variable link width supporting the main data communication band using a module partner and setting support parameters in the link configuration register of parameter and configuration register 1115. Variable link width support circuitry 1141 may include one or more hardware components providing a physical structure that performs various processes related to transmitting requests and receiving responses for supporting variable link width using a module partner and setting support parameters. Variable link width support circuitry 1141 may include components for transmitting support requests to a module partner, components for receiving support responses for supporting the variable link width of the main band from the module partner via sidebands, and components for setting support parameters in the link configuration register of parameter and configuration register 1115. Variable link width support circuitry 1141 may be further configured to execute variable link width support instructions 1151 included on computer-readable medium 1106 to implement the variable link width support described herein.

[0102] The die-to-die adapter processor 1104 may include a variable link width enable circuit 1142 configured to transmit and receive enable requests to and from a module partner via a sideband. The enable request operates the main band at a specified link width, where the specified link width has a specified set of data lines of the main band, as discussed herein. The variable link width enable circuit 1142 may include functionality for enabling the specified link width in response to a command or table inference from, for example, Table 2, and for transmitting and receiving requests and responses to enable the specified link width. The variable link width enable circuit may also set parameters in a link configuration register for operating at the specified link width. The variable link width enable circuit 1142 may be further configured to execute variable link width enable instructions 1152 included on the computer-readable medium 1106 to implement one or more of the functions described herein.

[0103] Module 1114 and die-to-die adapter processor 1104 may include link initialization circuitry 1143 configured to perform operations as discussed herein to initialize the main band with a specified transmit link width and a specified receive link width. Link initialization circuitry 1143 may include functionality for initializing the link, and may also include functionality for main band clock training and main band data line training. Link initialization circuitry 1143 may include functionality for initializing the main band link with a specified link width. Link initialization circuitry 1143 may be further configured to execute link initialization instructions 1153 included on computer-readable medium 1106 to implement one or more of the functions described herein.

[0104] The die-to-die adapter processor 1104 may include data communication circuitry 1144 configured to communicate data with another module via a masterband connection of die-to-die connection 1110 using an initial masterband with a specified link width, as discussed herein. Data communication circuitry 1144 may include functionality for communicating data with another module via a masterband connection using a specified link width. Data communication circuitry 1144 may also have parameters set in a link configuration register for operating different link widths. Data communication circuitry 1144 may be further configured to execute data communication instructions 1154 included on computer-readable medium 1106 to implement one or more of the functions described herein.

[0105] The circuit architecture described in this article can be implemented on one or more ICs, chips, chiplets, modules, interposers, packages, system printed circuit boards (PCBs), etc. The circuit architecture described in this article can also be manufactured using various process technologies, such as complementary metal-oxide-semiconductor (CMOS), NMOS, PMOS, bipolar junction transistors (BJTs), bipolar CMOS (BiCMOS), silicon-germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), silicon-on-insulator (SOI), etc.

[0106] Figure 12 This is an example of using link width and die-to-die connections (such as...) Figures 1 to 5 A flowchart illustrating an example of a method used in conjunction with the connection (of the method). This method can be used in... Figure 11 die to die adapter processor 1104 or other circuits and such as in Figure 11 This is executed within the software described in the context of [the software described]. Optionally, method 1200 begins at block 1202, where a support request for a variable link width supporting the main band is transmitted to the module partner via a sideband. The transmission of the support request may be performed during main band initialization. Alternatively, the die may be configured to support variable link width without any handshake of support parameters.

[0107] In response to the request message, the module partner may transmit a response. Method 1200 continues in block 1204, wherein optionally, a support response for a variable link width supporting the main band is received from the module partner via a sideband.

[0108] In block 1206, an enable request for operating the main band at a specified link width is transmitted to the module partner via a sideband. This specified link width has a specified set of data lines for the main band. Then, at block 1208, the module partner can execute an enable response for operating the main band at a specified link width, received from the module partner via a sideband. The enable request may include a single specified transmit link width for both transmit and receive lines. In some aspects, the enable request may have a specified set of transmit data lines and a specified receive link width, which has a specified set of receive data lines. In some aspects, a request to reduce the data rate of the main band is received from an upstream component. The transmission enable request is executed in response to the request to reduce the data rate.

[0109] In block 1210, optionally, the action of storing a transmit link width parameter indicating the transmit link width in the link configuration register is performed. In block 1212, optionally, the action of storing a receive link width parameter indicating the receive link width in the link configuration register is performed. In some aspects, only a single link width is stored for both transmit and receive.

[0110] After supporting variable link width, enabling variable link width, and specifying the link width, the master band operates with the specified link width. In box 1216, data is communicated with module partners via the master band using the specified link width.

[0111] As used herein, “or” is intended to be interpreted as inclusive unless otherwise explicitly stated. For example, “a or b” could include only a, only b, or a combination of a and b. As used herein, phrases referring to “at least one of” or “one or more of” a list of items refer to any combination of those items, including a single member. For example, “at least one of a, b, or c” is intended to cover examples such as only a, only b, only c, a combination of a and b, a combination of a and c, a combination of b and c, and a combination of a and b with c.

[0112] The various exemplary components, logic components, logic blocks, modules, circuits, operations, and algorithmic processes described in conjunction with the specific embodiments disclosed herein can be implemented as electronic hardware, firmware, software, or a combination of hardware, firmware, or software, including the structures disclosed in this specification and their structural equivalents. This interchangeability of hardware, firmware, and software has been generally described in terms of its functionality and exemplified in the various exemplary components, blocks, modules, circuits, and processes described above. Whether such functionality is implemented in hardware, firmware, or software depends on the specific application and the design constraints imposed on the overall system.

[0113] The various exemplary logic blocks, modules, and circuits described in conjunction with the exemplary aspects disclosed herein can be implemented or executed using a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic component, discrete hardware component, or any combination thereof. The general-purpose processor may be a microprocessor, but in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0114] In one or more exemplary aspects, the described functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functionality may be stored as one or more instructions or code stored on a computer-readable medium or transmitted as one or more instructions or code stored on a computer-readable medium. A computer-readable medium includes both computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one place to another. A storage medium may be any available medium accessible to a computer. By way of example and not limitation, such a computer-readable medium may include RAM, ROM, EEPROM, CD-ROM, or other optical disk storage devices or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and is accessible to a computer. Combinations of the above should also be included within the scope of computer-readable media.

[0115] The following provides an overview of various embodiments of this disclosure.

[0116] Example 1: A method comprising: transmitting, via a sideband, an enable request for operating a main band of a die-to-die connection from a module of a first die to a module partner of a second die, the die-to-die connection connecting the first die module to the second die module partner with a specified link width having a specified set of data lines of the main band; receiving, via the sideband, an enable response for operating the main band with the specified link width from the module partner; and, in response to receiving the enable response, communicating data with the module partner via the main band using the specified link width.

[0117] Example 2: According to the method described in Example 1, transmitting the enable request includes: transmitting an enable request that includes specifying a transmit link width and specifying a receive link width, wherein the specified transmit link width has a specified set of transmit data lines and the specified receive link width has a specified set of receive data lines.

[0118] Example 3: According to the method described in Example 2, the method further includes: storing a transmit link width parameter indicating the specified transmit link width in the link configuration register, and storing a receive link width parameter indicating the specified receive link width in the link configuration register.

[0119] Example 4: The method described in Example 2 or 3, wherein the specified transmit link width is different from the specified receive link width.

[0120] Example 5: The method according to any one or more of the above embodiments further includes: training the main band by training the specified set of data lines in the specified link width.

[0121] Example 6: The method according to any one or more of the above embodiments, the method further includes: disabling the data lines of the main band that are not in the specified set of data lines.

[0122] Example 7: According to the method described in Example 6, the method further includes: setting the receiving line of the main band that is not in the specified set of data lines to a tri-state.

[0123] Example 8: The method according to any one or more of the above embodiments, the method further comprising: receiving a request from an upstream component to reduce the data rate of the main band, wherein transmitting the enable request is performed in response to the request to reduce the data rate.

[0124] Example 9: The method according to any one or more of the above embodiments, the method further comprising: transmitting a request for support of the variable link width of the main band to the module partner via the sideband before transmitting the enable request; and receiving a support response from the module partner for support of the variable link width of the main band.

[0125] Example 10: According to the method of Example 9, transmitting the support request includes transmitting the support request during main band initialization.

[0126] Example 11: The method according to any one or more of the above embodiments, wherein transmitting the enable request includes: transmitting enable parameters and link width parameters, and the method further includes: storing the enable parameters and the link width parameters in a link configuration register.

[0127] Example 12: The method according to any one or more of the above embodiments, the method further comprising: initializing the main band and the module partner using a second link width before transmitting the enable request; transmitting data through the main band and the module partner using the second link width; and detecting a faulty data line during the transmission of the data using the second link width.

[0128] Example 13: According to the method of Example 12, wherein transmitting the data using the specified link width includes: transmitting the data at half the data rate at which the data is transmitted using the second link width.

[0129] Example 14: The method described in Example 13, wherein the specified link width excludes the faulty data line.

[0130] Example 15: The method according to any one or more of the above embodiments, the method further includes: detecting a faulty transmit data line of the main band; transmitting a second enable request to the module partner to operate the main band with a second specified transmit link width, the second specified transmit link width excluding the faulty data line; and transmitting data to the module partner through the main band with the second specified transmit link width and the specified receive link width.

[0131] Example 16: A non-transitory computer-readable medium storing instructions for causing a processor of a die to perform operations including: transmitting via a sideband an enable request for operating a main band of a die-to-die connection from a module of a first die to a module partner of a second die, the die-to-die connection connecting the first die module to the second die module partner with a specified link width having a specified set of data lines of the main band; receiving via the sideband an enable response for operating the main band with the specified link width from the module partner; and in response to receiving the enable response, communicating data with the module partner via the main band using the specified link width.

[0132] Example 17: According to the medium described in Example 16, transmitting the enable request includes: transmitting an enable request that includes a specified transmit link width and a specified receive link width, wherein the specified transmit link width has a specified set of transmit data lines and the specified receive link width has a specified set of receive data lines.

[0133] Example 18: According to the medium described in Example 16 or 17, the operation further includes: receiving a request from an upstream component to reduce the data rate of the main band, and wherein transmitting the enable request is performed in response to the request to reduce the data rate.

[0134] Example 19: The medium according to any one or more of Examples 16 to 18, wherein the transmission of the enable request is performed in response to the detection of a faulty data line during data communication via the main band.

[0135] Example 20: An apparatus comprising: a sideband transmitter for a first die module, the sideband transmitter being configured to transmit, via a die-to-die connected sideband, an enable request to operate the die-to-die connected main band at a specified link width to a second die module partner, the specified link width having a specified set of data lines of the main band; a sideband receiver for the module, the sideband receiver being configured to receive, via the sideband, an enable response to operate the main band at the specified link width from the module partner; and a main band transmitter, the main band transmitter being configured to, in response to receiving the enable response, transmit data via the specified link width to the module partner using the main band.

[0136] Example 21: According to the apparatus of Example 20, wherein the sideband transmitter is further configured to transmit a support request for a variable link width supporting the main band to the module partner, and wherein the sideband receiver is further configured to receive a support response for the variable link width supporting the main band from the module partner before transmitting the enable request from the sideband transmitter.

[0137] Example 22: The apparatus according to Example 20 or 21 further includes a link configuration register and a die-to-die adapter processor, wherein the die-to-die adapter processor is configured to store in the link configuration register a transmit link width parameter indicating a specified transmit link width and a receive link width parameter indicating a specified receive link width.

[0138] It should be understood that this disclosure is not limited to the exemplary terms used above to describe various aspects of this disclosure. For example, die-to-die connection may also be referred to as interconnect, bus, link, or another term.

[0139] Although the foregoing examples using UCIe 1.0 have discussed various aspects of this disclosure, it should be understood that this disclosure is not limited to these examples and can be used with other standards.

[0140] The use of designations such as "first," "second," etc., to refer to elements in this document generally does not limit the number or order of those elements. Rather, these designations are used here as a convenient way to distinguish two or more elements or instances of elements. Thus, a reference to the first element and the second element does not imply that only two elements can be used, or that the first element must precede the second element.

[0141] In this disclosure, the term "exemplary" is used to mean "serving as an example, instance, or illustration." Any specific implementation or aspect described herein as "exemplary" is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term "aspect" does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term "coupling" is used herein to refer to direct or indirect electrical coupling or other communication coupling between two structures. Furthermore, the term "about" means within ten percent of the stated value.

[0142] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method, the method comprising: A mainband enable request for a die-to-die connection is transmitted from the module of the first die to the module partner of the second die via a sideband, the die-to-die connection connecting the first die module to the second die module partner with a specified link width having a specified set of data lines of the mainband; Receive an enable response from the module partner via the sideband, allowing the main band to operate at the specified link width; as well as In response to receiving the enable response, data is transmitted to the module partner via the main band using the specified link width.

2. The method of claim 1, wherein transmitting the enable request comprises: The transmission includes an enable request specifying a transmit link width and a receive link width, wherein the specified transmit link width has a specified set of transmit data lines and the specified receive link width has a specified set of receive data lines.

3. The method according to claim 2, further comprising: The link configuration register stores a transmit link width parameter indicating the specified transmit link width, and the link configuration register also stores a receive link width parameter indicating the specified receive link width.

4. The method according to claim 2, wherein the specified transmit link width is different from the specified receive link width.

5. The method according to claim 1, further comprising: The main band is trained by training the specified set of data lines within the specified link width.

6. The method according to claim 1, further comprising: Disable the main band data lines that are not in the specified set of data lines.

7. The method according to claim 6, further comprising: Set the receive line of the main band that is not in the specified set of data lines to tri-state.

8. The method according to claim 1, further comprising: A request to reduce the data rate of the main band is received from an upstream component, and the enable request is transmitted in response to the request to reduce the data rate.

9. The method according to claim 1, further comprising: Before transmitting the enable request, a request to support the variable link width of the main band is transmitted to the module partner via the sideband; as well as Receive a support response from the module partner that supports the variable link width of the main band.

10. The method of claim 9, wherein transmitting the support request comprises: The support request is transmitted during mainband initialization.

11. The method of claim 1, wherein transmitting the enable request comprises: The method of transmitting enable parameters and link width parameters further includes storing the enable parameters and link width parameters in a link configuration register.

12. The method according to claim 1, further comprising: Before sending the enable request: Initialize the main band and the module partner using the second link width; The second link width is used to transmit data with the module partner via the main band; as well as A faulty data line is detected while the data is being transmitted using the second link width.

13. The method of claim 12, wherein conveying the data using the specified link width comprises: The data is transmitted at half the data rate using the second link width.

14. The method of claim 13, wherein the specified link width excludes the faulty data line.

15. The method according to claim 1, further comprising: Detect faulty data transmission lines of the main unit; A second enable request is transmitted to the module partner to operate the main band with a second specified transmit link width, the second specified transmit link width excluding the faulty data line; and Data is transmitted to the module partner via the main band using the second specified transmit link width and the specified receive link width.

16. A non-transitory computer-readable medium storing instructions for causing a processor of a die to perform operations including: A mainband enable request for a die-to-die connection is transmitted from the module of the first die to the module partner of the second die via a sideband, the die-to-die connection connecting the first die module to the second die module partner with a specified link width having a specified set of data lines of the mainband; Receive an enable response from the module partner via the sideband, allowing the main band to operate at the specified link width; as well as In response to receiving the enable response, data is transmitted to the module partner via the main band using the specified link width.

17. The medium of claim 16, wherein transmitting the enable request comprises: The transmission includes an enable request specifying a transmit link width and a receive link width, wherein the specified transmit link width has a specified set of transmit data lines and the specified receive link width has a specified set of receive data lines.

18. The medium according to claim 16, further comprising: A request to reduce the data rate of the main band is received from an upstream component, and the enable request is transmitted in response to the request to reduce the data rate.

19. The medium of claim 16, wherein transmitting the enable request is performed in response to the detection of a faulty data line during data communication via the main band.

20. An apparatus comprising: A sideband transmitter of a first die module, the sideband transmitter being configured to transmit an enable request for the main band of the second die module to a module partner of the second die via a sideband connected to the die-to-die connection, the enable request for the main band connected to the die-to-die connection being operated at a specified link width, the specified link width having a specified set of data lines of the main band; The module's sideband receiver is configured to receive, via the sideband, an enable response from the module partner to operate the main band at the specified link width; as well as A mainband transmitter, configured to transmit data to the module partner via the mainband using the specified link width in response to receiving the enable response.

21. The apparatus of claim 20, wherein the sideband transmitter is further configured to transmit a support request for a variable link width supporting the main band to the module partner, and wherein the sideband receiver is further configured to receive a support response for the variable link width supporting the main band from the module partner before transmitting the enable request from the sideband transmitter.

22. The apparatus of claim 20, further comprising a link configuration register and a die-to-die adapter processor, wherein the die-to-die adapter processor is configured to store in the link configuration register a transmit link width parameter indicating a transmit link width and a receive link width parameter indicating a receive link width.

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