Semiconductor device and method for manufacturing semiconductor device
By introducing void structures between the wirings of semiconductor components and in the resin film, the problem of increased capacitance between wirings is solved, achieving high-speed operation and warpage suppression. It is suitable for logic circuits, memory, image sensors, and interpolators.
Patent Information
- Application Number
- CN202480019558.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-03-24
- Filing Date
- 2024-01-26
- Publication Date
- 2025-11-11
AI Technical Summary
In the existing technology, with the advancement of miniaturization, the inter-wire capacitance in semiconductor devices increases, resulting in increased wiring delay and making it difficult to achieve high-speed operation.
Voids are introduced between the wirings of semiconductor components and in the insulating and protective films to cover the side and top surfaces of the wirings, thereby reducing the dielectric constant and the capacitance between the wirings. In addition, multiple layers of voids are deployed in the resin film to relieve stress and suppress warping.
By introducing a void structure, the capacitance between wirings is effectively reduced, the resin volume is reduced, and stress is alleviated, thereby enabling high-speed operation and warpage suppression of semiconductor devices.
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Figure CN120937137A_ABST
Abstract
Description
Technical Field
[0001] This technology relates to semiconductor devices. Specifically, this technology relates to semiconductor devices forming multiple wirings and methods for manufacturing semiconductor devices. Background Technology
[0002] Conventionally, in wafer-level chip-scale packages (WCSPs), wiring, such as rewiring, is used to electrically connect semiconductor devices to external terminals. When multiple wirings are formed, potential inter-wiring capacitance is generated between them. With the advancement of miniaturization, inter-wiring capacitance increases. Since wiring delay increases with increasing inter-wiring capacitance, reducing inter-wiring capacitance is important for achieving high-speed operation. Therefore, a semiconductor device that provides gaps between multiple wirings has been proposed (see, for example, Patent Document 1).
[0003] Citation List
[0004] Patent documents
[0005] Patent Document 1: Japanese Patent Application Publication No. H7-335747 Summary of the Invention
[0006] The problem to be solved by the present invention
[0007] In the aforementioned conventional techniques, inter-wire capacitance is reduced by providing gaps between multiple wires. However, in the aforementioned semiconductor devices, it is difficult to further reduce inter-wire capacitance.
[0008] This technology was developed in view of this situation, and its purpose is to reduce the inter-wire capacitance in semiconductor devices with multiple wires.
[0009] Solution to the problem
[0010] This technology aims to solve the above-mentioned problems, and its first aspect is a semiconductor device and a method for manufacturing a semiconductor device. The semiconductor device includes: a semiconductor substrate; an insulating film covering a predetermined surface of the semiconductor substrate; a protective film covering the insulating film; a predetermined number of wirings formed in the protective film; and covering gaps, including gaps in the protective film covering each wiring.
[0011] Furthermore, in the first aspect, it may also include voids within the insulating film, which include voids formed in the insulating film.
[0012] Furthermore, in the first aspect, a protective film void may also be included, the protective film void comprising a void formed in the protective film, the protective film comprising: a first protective film covering an insulating film; and a second protective film covering the first protective film, and the protective film void may be formed in the first protective film.
[0013] Furthermore, in the first aspect, an external connection terminal connected to the wiring may also be included, and the gaps in the insulating film and the gaps in the protective film may be deployed to avoid the vicinity of the external connection terminal.
[0014] Furthermore, in the first aspect, the voids within the insulating film and the voids within the protective film can be positioned to avoid the vicinity of the ends of the semiconductor element.
[0015] Furthermore, in the first aspect, the voids within the insulating film and the voids within the protective film can be preferentially deployed in the central portion of the semiconductor element.
[0016] Furthermore, in the first aspect, the predetermined number of wires may include a pair of wires with different potentials, and the covering gap may cover each of the pair of wires.
[0017] Furthermore, in the first aspect, when viewed from a direction perpendicular to the predetermined surface, the covering gap can extend along the wiring.
[0018] Furthermore, in the first aspect, the contact surface of the wiring can contact the insulating film, and when viewed from a direction parallel to the predetermined surface, the covering gap can cover the portion other than the contact surface.
[0019] Furthermore, in the first aspect, when viewed from a direction perpendicular to the predetermined surface, the covering gap can have any of the following shapes: rectangular, circular, and elliptical.
[0020] Furthermore, in the first aspect, the material of the insulating film may include any one of polyimide, silicone, acrylic, epoxy resin, and spin-on carbon (SOC) material.
[0021] Furthermore, in the first aspect, the semiconductor element may include any one of a logic circuit, a memory, an image sensor, and an interposer. Attached Figure Description
[0022] Figure 1 This is a cross-sectional view illustrating an example configuration of semiconductor elements in a first embodiment of the present technology.
[0023] Figure 2 These are examples of cross-sectional and plan views of a semiconductor element in the first embodiment of this technology.
[0024] Figure 3 This is a plan view illustrating an example of the layout of the gaps in the first embodiment of the present technology.
[0025] Figure 4 This is a view used to describe a manufacturing method for forming a pattern up to rewiring in a first embodiment of the present technology.
[0026] Figure 5 This is a view used to describe a manufacturing method for forming a protective resin film in a first embodiment of the present technology.
[0027] Figure 6 This is a view used to describe the manufacturing method up to curing in the first embodiment of the present technology.
[0028] Figure 7 This is an example of a plan view of a grayscale mask in the first embodiment of this technology.
[0029] Figure 8 This is another example of a plan view of a grayscale mask in the first embodiment of this technology.
[0030] Figure 9 This is a view used to illustrate the relationship between transmittance and the shape of the voids in a first embodiment of the present technology.
[0031] Figure 10 This is a flowchart illustrating an example of a method for manufacturing a semiconductor element in a first embodiment of the present technology.
[0032] Figure 11 This is a cross-sectional view illustrating an example configuration of semiconductor elements in a second embodiment of the present technology.
[0033] Figure 12 This is a view used to describe a manufacturing method for forming voids in a photosensitive insulating resin film according to a second embodiment of the present technology.
[0034] Figure 13 This is a view used to describe the manufacturing method up to Cu plating in a second embodiment of the present technology.
[0035] Figure 14 This is a view used to describe the manufacturing method up to photolithography in a second embodiment of the present technology.
[0036] Figure 15 This is a view used to describe a manufacturing method for forming a pattern up to rewiring in a second embodiment of the present technology.
[0037] Figure 16 This is a view used to describe a manufacturing method up to the formation of external connection terminals in a second embodiment of the present technology.
[0038] Figure 17 This is a block diagram illustrating a schematic configuration example of a vehicle control system.
[0039] Figure 18 This is an explanatory diagram illustrating an example of the mounting position of the imaging unit. Detailed Implementation
[0040] The following describes how this technology is implemented (hereinafter referred to as embodiments). The description will be given in the following order.
[0041] 1. First embodiment (example of wiring covered by gaps)
[0042] 2. Second embodiment (example where wiring is covered by gaps and the gaps are deployed in resin)
[0043] 3. Examples of applications of moving objects
[0044] <1. First Embodiment>
[0045] [Semiconductor Component Configuration Example]
[0046] Figure 1 This is a cross-sectional view illustrating an example configuration of a semiconductor element 100 in a first embodiment of the present technology. The semiconductor element 100 is a semiconductor element provided in a wafer-level chip-scale package (WCSP) or the like, and includes a protective resin film 110, a photosensitive insulating resin film 120, a semiconductor substrate 130, a wiring layer 140, and a through electrode 150. Examples of the semiconductor element 100 include logic circuits, memory, image sensors, and interpolators.
[0047] A wiring layer 140 is formed on one of the two surfaces of the semiconductor substrate 130. Hereinafter, the surface on which the wiring layer 140 is formed is defined as the "front surface," and the surface opposite the front surface is defined as the "rear surface." Furthermore, the direction from the front surface to the rear surface is defined as the "upward" direction. The front surface can also be referred to as the lower surface, and the rear surface can also be referred to as the upper surface. Built-in components 141, a predetermined number of wirings 142, and pads 143 are disposed in the wiring layer 140.
[0048] In the following text, the axis perpendicular to the front surface of the semiconductor substrate 130 is defined as the "Z-axis," and a predetermined axis parallel to the front surface of the semiconductor substrate 130 is defined as the "X-axis." The axis perpendicular to the X-axis and Y-axis is defined as the "Y-axis." This figure is a cross-sectional view taken from the Y-axis direction.
[0049] A photosensitive insulating resin film 120 covers the rear surface (in other words, the upper surface) of the semiconductor substrate 130. As the photosensitive insulating resin film 120, a photoresist of a negatively developed (NTD) type thermosetting organic film is used. Furthermore, as the material of the photosensitive insulating resin film 120, materials such as polyimide, silicone, acrylic, epoxy resin, or spin-on carbon (SOC) are used. Note that the photosensitive insulating resin film 120 is an example of the insulating film described in the claims.
[0050] The through electrode 150 is an electrode that penetrates the photosensitive insulating resin film 120 and the semiconductor substrate 130 and is connected to the pad 143. The through electrode 150 includes, for example, a through hole and wiring along the side surface of the through hole. Furthermore, the interior of the through electrode 150 is a cavity.
[0051] A protective resin film 110 covers the upper surface of the photosensitive insulating resin film 120. As the protective resin film 110, an NTD-type thermosetting organic film photoresist is used. Note that the protective resin film 110 is an example of the protective film described in the claims.
[0052] Furthermore, a predetermined number of redistribution layers 111 are formed along the upper surface of the photosensitive insulating resin film 120 in the protective resin film 110. The protective resin film 110 may also be referred to as a redistribution layer (RDL). Examples of materials for the redistribution layers 111 include titanium (Ti), copper (Cu), tantalum (Ta), nickel (Ni), tungsten (W), ruthenium (Ru), and cobalt (Co). Note that the redistribution layers 111 are examples of the wiring described in the claims.
[0053] Furthermore, each of the rewiring 111 is covered by a gap 161. Note that the gap 161 is an example of a covered gap described in the claims.
[0054] Furthermore, external connection terminals 112 (such as bumps) for connection to the outside are deployed in the protective resin film 110. The external connection terminals 112 are connected to one end of any rewiring 111, and the other end of the rewiring 111 is connected to the through electrode 150. Built-in components 141 in the wiring layer 140 are electrically connected to the external connection terminals 112 via the rewiring 111 and the through electrode 150.
[0055] Here, the inter-wire capacitance C between a pair of adjacent rewirings 111 in a predetermined number of rewirings 111 is represented by the following expression.
[0056] C = εS / d... Expression 1
[0057] In the above expressions, the unit of inter-wiring capacitance C is, for example, farads (F). The dielectric constant is represented by ε, and its unit is, for example, farads per meter (F / m). The area of the rewired side surface is represented by S, and its unit is, for example, square meters (m²). 2 The spacing between wirings is denoted by d, and its unit is, for example, meters (m).
[0058] According to the above expression, as miniaturization progresses, the spacing d decreases, and the inter-wire capacitance increases. However, since wiring delay increases with the increase in inter-wire capacitance, it is important to reduce the inter-wire capacitance in order to achieve high-speed operation.
[0059] Figure 2 These are examples of cross-sectional and planar views of the semiconductor element 100 in the first embodiment of this technology. Figure 2 In this context, 'a' represents the distance along the X-axis when viewed from the X-axis direction. Figure 1 A cross-sectional view of semiconductor device 100, cut by alternating long and short dashed lines. Figure 2 In the figure, b is a plan view of the semiconductor element 100 taken along the alternating long and short dashed lines in a when viewed from the Z-axis direction.
[0060] As shown in Figure a, multiple rewiring schemes 111, such as rewiring schemes 111-1, 111-2, and 111-3, are routed within the protective resin film 110. Each of these rewiring schemes is covered by a gap 161. The gaps 161 covering the rewiring schemes 111-1, 111-2, and 111-3 are defined as gaps 161-1, 161-2, and 161-3, respectively.
[0061] Assume each rewiring 111 is routed along the X-axis. In this case, when viewed from the X-axis direction, a cross-section of the rewiring 111 is observed. In the cross-section, the lower surface of the rewiring 111 is in seamless contact with the photosensitive insulating resin film 120, and its upper and side surfaces are covered by voids 161.
[0062] Here, the dielectric constant ε in Expression 1 is represented by the following expression.
[0063] ε=ε0ε r ...expression 2
[0064] In the above expression, ε0 is the vacuum permittivity, and ε r It is the relative permittivity.
[0065] For example, the relative permittivity ε of the resin constituting the protective resin film 110 r The relative permittivity ε of air is approximately 3. r The value is 1. Therefore, according to Expression 2, in the configuration where the upper and side surfaces of the rewiring 111 are covered by gaps 161, the dielectric constant ε is less than the dielectric constant in the case without gaps 161. When the dielectric constant ε decreases, according to Expression 1, the inter-wire capacitance decreases.
[0066] As described in Patent Document 1, the inter-wire capacitance can also be reduced by deploying gaps between the wires. However, as shown in Figure a, compared to Patent Document 1, the inter-wire capacitance can be reduced by covering the upper surface with gaps 161 except for the side surfaces.
[0067] Furthermore, there is a concern that the protective resin film 110 may dent if the size of the gap 161 is too large. Therefore, the height h of the gap 161 from the boundary between the protective resin film 110 and the photosensitive insulating resin film 120 is preferably about 2 / 3 of the film thickness D of the protective resin film 110. Note that the height h can also be adjusted correspondingly to the wiring width w of the rewiring 111. For example, if the wiring width w is less than a predetermined value, then the height h can exceed 2 / 3 of the film thickness D, and if the wiring width w is equal to or greater than the predetermined value, then the height h can be equal to or less than 2 / 3 of the film thickness D.
[0068] Furthermore, preferably, the gap 161 covers each of a pair of adjacent rewiring 111 with different potentials. On the other hand, each of a pair of adjacent rewiring 111 with the same potential is not necessarily covered by the gap 161.
[0069] Furthermore, as shown in Figure b, the rerouting 111-3 is connected to pad 113. Additionally, when viewed from the Z-axis direction, each of the gaps 161-1, 161-2, and 161-3 extends along its corresponding rerouting 111.
[0070] Note that, as Figure 3 As shown in Figure a, gap 161 can be divided into multiple sections, each with a different coverage area. For example, gap 161-1 can be divided into three gaps: gap 161-1a, gap 161-1b, and gap 161-1c.
[0071] Furthermore, in Figure a, the shape of each portion obtained by dividing the gap 161 is rectangular, but it can also be circular or elliptical as shown in Figure b. Circular or elliptical gaps 161 can also be represented as holes. Additionally, rectangular gaps 161 can also be represented as grooves.
[0072] [Semiconductor device manufacturing methods]
[0073] Then, refer to Figures 4 to 6 To describe the manufacturing method of semiconductor element 100.
[0074] First, such as Figure 4 As shown in Figure a, a photosensitive insulating resin film 120 is formed on the back surface of the semiconductor substrate 130 by spin coating or the like. After forming a desired pattern on the back surface using photolithography, high-temperature curing is performed.
[0075] Next, as shown in Figure b, Cu and the like are deposited as seed 200 on the upper surface of the photosensitive insulating resin film 120 by sputtering.
[0076] Next, as shown in c in the figure, photoresist 201 is applied, and a pattern for rewiring 111 is formed by photolithography.
[0077] Then, as Figure 5 As shown in a, Cu is plated by electroplating or electroless plating.
[0078] Next, as shown in Figure b, the photoresist 201 is stripped, and the seed 200 is removed by wet etching. This arrangement forms the rewiring 111.
[0079] Next, as shown in figure c, a protective resin film 110 is formed by spin coating or the like.
[0080] Then, as Figure 6 As shown in Figure a, photolithography is performed on the protective resin film 110 using a grayscale mask (not shown), where the exposure is set to a relatively high level. As described above, the protective resin film 110 is an NTD-type resin. In this NTD-type resin, when light is irradiated with a high exposure, a cross-linking reaction is promoted in the upper part of the resin, and contraction occurs in the direction of closure (direction of the arrow) of the upper part of the portion that has opened due to exposure. At this time, since the dissolved substances are discharged due to development, adjustments are performed to prevent complete closure.
[0081] Next, as shown in b in the figure, the thermosetting protective resin film 110 is cured at high temperature. At this time, the upper part of the opening is closed by reflow, and a void 161 is formed.
[0082] Figure 7 This is an example of a plan view of a grayscale mask 300 in the first embodiment of this technology. In this figure, a illustrates... Figure 6 A grayscale mask 300 is used in step a. A rectangular exposure area 310 is formed in the grayscale mask 300. In the exposure area 310, striped transparent portions and striped light-blocking portions are arranged alternately to form a striped pattern. The white portions in the figure are transparent portions and are made of glass or the like. The gray portions are light-blocking portions and are made of chromium (Cr) or the like.
[0083] The transmittance of the exposure area 310 can be adjusted by changing the width of the stripes in the exposure area 310.
[0084] For example, such as Figure 7 As shown in b, by making the width of the stripes narrower than that in a, the transmittance can be lower than that in a. Therefore, the exposure can be adjusted by changing the transmittance according to the pattern of the exposure area 310 of the grayscale mask 300.
[0085] Note that, as Figure 8As shown in a, the shape of the exposure area 310 is not limited to a rectangle, but can also be a circle, etc.
[0086] Furthermore, as shown in Figure b, the pattern of the exposure area 310 is not limited to a stripe shape, but can also be a grid shape. Even in the case of a grid shape, as shown in Figure c, the shape of the exposure area 310 is not limited to a rectangle, but can also be a circle, etc.
[0087] Figure 9 This is a view used to illustrate the relationship between transmittance and the shape of the voids in a first embodiment of the present technology. In this figure, a is an example of a photograph obtained by imaging a cross-section of the semiconductor element 100 before exposure using a scanning electron microscope (SEM).
[0088] In this figure, b is an example of a photograph obtained by SEM imaging of the cross-section when the transmittance of the grayscale mask 300 is adjusted to 75% and an exposure is performed. In this figure, c is an example of a photograph obtained by SEM imaging of the cross-section when the transmittance of the grayscale mask 300 is adjusted to 50% and an exposure is performed. In this figure, d is an example of a photograph obtained by SEM imaging of the cross-section when the transmittance of the grayscale mask 300 is adjusted to 30% and an exposure is performed.
[0089] As shown in figures b, c, and d, the size of the pore 161 can be changed by adjusting the transmittance.
[0090] Figure 10 This is a flowchart illustrating an example of a method for manufacturing a semiconductor element 100 in the first embodiment of the present technology. A photosensitive insulating resin film 120 is formed on the back surface of a semiconductor substrate 130, a desired pattern is formed by photolithography, and high-temperature curing is performed (step S901). Next, a seed 200 is deposited on the upper surface of the photosensitive insulating resin film 120 by sputtering (step S902). Next, a pattern for redistribution 111 is formed by photolithography (step S903).
[0091] Then, Cu is plated (step S904), and the photoresist 201 and seed 200 are removed (step S905). Next, a protective resin film 110 is formed (step S906).
[0092] Then, photolithography is performed using a grayscale mask (not shown) (step S907), and high-temperature curing is performed (step S908).
[0093] Therefore, according to the first embodiment of this technology, since a gap 161 covering the rewiring 111 is formed, the inter-wiring capacitance can be reduced.
[0094] <2. Second Embodiment>
[0095] In the first embodiment described above, a gap 161 is formed covering the redistribution 111. However, in some cases, the gap 161 alone is insufficient to sufficiently suppress warping of the semiconductor element 100. As described above, the photosensitive insulating resin film 120, the redistribution 111, and the protective resin film 110 are deployed between the semiconductor substrate 130 and the external connection terminal 112. In this case, due to the expansion and contraction of resins such as the photosensitive insulating resin film 120 and metals such as the redistribution 111, stress may be applied to the semiconductor substrate 130, and the semiconductor element 100 and the wafer including the semiconductor element 100 may warp. The effects of warping are particularly significant in large-diameter semiconductor elements 100, and stress relief is important for suppressing warping. The semiconductor element 100 of the second embodiment differs from that of the semiconductor element 100 of the first embodiment in that a gap is added to the photosensitive insulating resin film 120, etc., to relieve stress.
[0096] Figure 11 This is a cross-sectional view illustrating an example configuration of the semiconductor element 100 in a second embodiment of the present technology. The semiconductor element 100 in the second embodiment differs from the semiconductor element 100 in the first embodiment in that the protective resin film 110 has two layers and further forms voids 162 and 163.
[0097] In the two layers of the protective resin film 110, the upper layer is defined as protective resin film 110-2, and the lower layer is defined as protective resin film 110-1. A redistribution 111 and an external connection terminal 112 are formed on the upper protective resin film 110-2. A redistribution 114 is formed on the lower protective resin film 110-1, and the redistribution 114 is electrically connected to the upper redistribution 111 via a through electrode 151.
[0098] Void 162 is formed in the lower protective resin film 110-1. Note that protective resin film 110-1 is an example of the first protective film described in the claims, and protective resin film 110-2 is an example of the second protective film described in the claims. Void 162 is an example of an internal void in the protective film described in the claims.
[0099] Furthermore, voids 163 are formed in the photosensitive insulating resin film 120. Note that voids 163 are examples of voids within the insulating film described in the claims.
[0100] Note that in this figure, gaps 162 and 163 are deployed in both the protective resin film 110-1 and the photosensitive insulating resin film 120. However, it is also possible to deploy only one of gaps 162 and 163 in either the protective resin film 110-1 or the photosensitive insulating resin film 120.
[0101] As shown in the figure, by deploying voids 162 and 163 in the protective resin film 110-1 and the photosensitive insulating resin film 120, the volume of the resin can be reduced and stress can be alleviated. This arrangement can suppress warping of the semiconductor element 100 and the wafer.
[0102] There are no restrictions on the placement of gaps 162 and 163. However, for example, it is preferable to place gaps 162 and 163 in the central portion of the semiconductor element 100 or wafer where localized stress may be applied. Note that it is preferable not to form gaps 162 or 163 near the lower portion of the external connection terminal 112 where external stress is applied. Furthermore, it is preferable not to form gaps 162 or 163 near the ends of the semiconductor element 100 (e.g., coordinate X0). This is because stress is applied to the ends when the semiconductor element 100 is cut from the wafer, and this arrangement prevents the ends from denting due to stress.
[0103] Valves 162 and 163 are also formed by photolithography using a grayscale mask 300, as in the first embodiment. By selectively changing the transmittance of the grayscale mask 300, gaps 162, etc., can be formed simultaneously at multiple portions with different steps. For example, in this figure, gaps 162 are formed simultaneously in each of the upper and other portions of the rewiring 114.
[0104] Then, refer to Figures 12 to 16 A method for manufacturing the semiconductor element 100 in the second embodiment is described.
[0105] First, such as Figure 12 As shown in Figure a, a photosensitive insulating resin film 120 is formed on the back surface of the semiconductor substrate 130 by spin coating or the like. Next, as shown in Figure b, photolithography is performed using a grayscale mask (not shown), where the exposure is set to a relatively high level. Next, as shown in Figure c, high-temperature curing is performed, and voids 163 are formed in the photosensitive insulating resin film 120 by reflow.
[0106] Then, as Figure 13 As shown in Figure a, Cu, etc., are deposited as seed 200 on the upper surface of the photosensitive insulating resin film 120 by sputtering. Next, as shown in Figure b, a photoresist 201 is applied, and a pattern for the redistribution 114 on the underside is formed by photolithography. Next, as shown in Figure c, Cu is plated by electroplating or electroless plating.
[0107] Then, as Figure 14 As shown in Figure a, the photoresist 201 is stripped, and the seed 200 is removed by wet etching. This arrangement forms the rewiring 114. As shown in Figure b, a protective resin film 110-1 is formed on the upper surface of the photosensitive insulating resin film 120 by spin coating or the like. Next, as shown in Figure c, photolithography is performed using a grayscale mask (not shown), where the exposure is set to a relatively high level.
[0108] Then, as Figure 15 As shown in Figure a, high-temperature curing is performed, and voids 162 are formed in the protective resin film 110-1 by reflow. Next, as shown in Figure b, Cu or the like is deposited as a seed 202 on the upper surface of the protective resin film 110-1 by sputtering. Next, as shown in Figure c, photoresist 203 is applied, and a pattern of the redistribution 111 on the upper side is formed by photolithography.
[0109] Then, as Figure 16 As shown in Figure a, the photoresist 203 is stripped, and the seed 202 is removed by wet etching. This arrangement forms the upper rewiring 111. Next, as shown in Figure b, a protective resin film 110-2 is formed on the upper surface of the protective resin film 110-1 by spin coating or the like. Furthermore, voids 161 are formed by photolithography using a grayscale mask (not shown) and high-temperature curing. Next, as shown in Figure c, external connection terminals 112 are formed.
[0110] Therefore, according to the second embodiment of this technology, stress can be reduced because voids 162 and 163 are deployed in the protective resin film 110-2 and the photosensitive insulating resin film 120. This arrangement can suppress warping of the semiconductor element 100 and the wafer.
[0111] <3. Application Examples of Moving Bodies>
[0112] The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein can be implemented as a device included in any type of mobile body, such as a car, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility device, airplane, drone, ship, robot, etc.
[0113] Figure 17 This is a block diagram illustrating a schematic configuration example of a vehicle control system that can be applied to a mobile body control system according to the technology disclosed herein.
[0114] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 17 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a main system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. Furthermore, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are illustrated as part of the functional configuration of the integrated control unit 12050.
[0115] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system in accordance with various programs. For example, the drive system control unit 12010 is used as a control device for drive force generating devices (such as internal combustion engines, drive motors, etc.) that generate vehicle driving force, drive force transmission mechanisms that transmit driving force to the wheels, steering mechanisms that adjust the vehicle's steering angle, and braking devices that generate vehicle braking force.
[0116] The main system control unit 12020 controls the operation of various devices provided to the vehicle body in accordance with various programs. For example, the main system control unit 12020 is used as a control device for keyless entry systems, smart key systems, power windows, or various lights (such as headlights, reversing lights, brake lights, turn signals, fog lights, etc.). In this case, radio waves transmitted from the moving device or signals from various switches, as a substitute for a key, can be input to the main system control unit 12020. The main system control unit 12020 receives these input radio waves or signals and controls the vehicle's door locking devices, power windows, lights, etc.
[0117] The exterior information detection unit 12030 detects information about the exterior of the vehicle, including the vehicle control system 12000. For example, the exterior information detection unit 12030 is connected to the imaging unit 12031. The exterior information detection unit 12030 causes the imaging unit 12031 to image an image of the exterior of the vehicle and receives the image. Based on the received image, the exterior information detection unit 12030 can perform processing such as detecting objects like people, vehicles, obstacles, signs, features on the road surface, etc., or processing such as detecting the distance to objects.
[0118] Imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. Imaging unit 12031 can output the electrical signal as an image, or it can output the electrical signal as information about the measured distance. Furthermore, the light received by imaging unit 12031 can be visible light, or it can be invisible light such as infrared light.
[0119] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 that detects the driver's state. The driver state detection unit 12041 includes, for example, a camera that images the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or the driver's level of concentration, or it can determine whether the driver is dozing off.
[0120] The microcomputer 12051 can calculate control target values for the drive force generation device, steering mechanism, or braking device based on information about the vehicle's interior or exterior, and output control commands to the drive system control unit 12010. This information is obtained by the external information detection unit 12030 or the internal information detection unit 12040. For example, the microcomputer 12051 can perform cooperative control to realize the functions of an advanced driver assistance system (ADAS), including collision avoidance or shock absorption, following distance-based driving, speed maintenance driving, collision warning, lane departure warning, etc.
[0121] Furthermore, the microcomputer 12051 can perform coordinated control based on information about the vehicle's external or internal components to enable automatic driving by controlling the drive force generation device, steering mechanism, braking device, etc., so that the vehicle can drive automatically without relying on the operation of a driver, etc. The above information is obtained by the external information detection unit 12030 or the internal information detection unit 12040.
[0122] Furthermore, the microcomputer 12051 can output control commands to the main system control unit 12020 based on information about the vehicle's exterior obtained by the external information detection unit 12030. For example, the microcomputer 12051 can perform coordinated control corresponding to the position of the vehicle ahead or oncoming vehicle detected by the external information detection unit 12030, to prevent glare by controlling the headlights to switch from high beams to low beams.
[0123] The sound / image output unit 12052 transmits at least one output signal of sound and image to an output device capable of notifying vehicle occupants or the outside of the vehicle in a visual or audible manner. Figure 17 In the example shown, an audio speaker 12061, a display unit 12062, and a dashboard 12063 are illustrated as output devices. The display unit 12062 may include, for example, at least one of a vehicle-mounted display and a head-up display.
[0124] Figure 18 This is a diagram illustrating an example of the mounting position of the imaging unit 12031.
[0125] exist Figure 18 In this, imaging units 12101, 12102, 12103, 12104 and 12105 are included as imaging unit 12031.
[0126] Imaging units 12101, 12102, 12103, 12104, and 12105 are provided at locations such as the front of the vehicle 12100, side mirrors, rear bumper, rear door, and the upper part of the windshield inside the vehicle. Imaging unit 12101 at the front of the vehicle and imaging unit 12105 at the upper part of the windshield inside the vehicle primarily acquire images of the front of the vehicle 12100. Imaging units 12102 and 12103 at the side mirrors primarily acquire images of the sides of the vehicle 12100. Imaging unit 12104 at the rear bumper or rear door primarily acquires images of the rear of the vehicle 12100. Imaging unit 12105 at the upper part of the windshield inside the vehicle is mainly used to detect vehicles, pedestrians, obstacles, signals, traffic signs, lanes, etc., ahead.
[0127] Note that, Figure 18 An example of the imaging range of imaging units 12101 to 12104 is illustrated. Imaging range 12111 represents the imaging range provided by imaging unit 12101 at the front of the vehicle. Imaging ranges 12112 and 12113 represent the imaging ranges provided by imaging units 12102 and 12103 at the side mirrors, respectively. Imaging range 12114 represents the imaging range provided by imaging unit 12104 at the rear bumper or rear door. For example, by overlaying the image data captured by imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 when viewed from above is obtained.
[0128] At least one of the imaging units 12101 to 12104 may have the function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.
[0129] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging range 12111 to 12114 and the time change of that distance (relative speed to the vehicle 12100) based on distance information obtained from the imaging units 12101 to 12104. This allows it to extract the nearest three-dimensional object, particularly one existing on the vehicle 12100's travel path and traveling in substantially the same direction as the vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h), as the vehicle ahead. Furthermore, the microcomputer 12051 can preset a following distance to be maintained with the vehicle ahead and execute automatic braking control (including stop-and-go control), automatic acceleration control (including start-and-go control), etc. Therefore, cooperative control aimed at autonomous driving can be performed, enabling the vehicle to drive automatically without relying on the operation of a driver or similar personnel.
[0130] For example, the microcomputer 12051 can classify three-dimensional object data about three-dimensional objects into three-dimensional object data of two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around vehicle 12100 as obstacles that the driver of vehicle 12100 can visually recognize and obstacles that the driver of vehicle 12100 cannot visually recognize. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. If the collision risk is equal to or higher than a set value and there is therefore a possibility of collision, the microcomputer 12051 outputs a warning to the driver via audio speaker 12061 or display unit 12062, and performs forced deceleration or evasive steering via drive system control unit 12010. Thus, the microcomputer 12051 can assist driving to avoid collisions.
[0131] At least one of the imaging units 12101 to 12104 can be an infrared camera that detects infrared light. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian exists in the imaging images of the imaging units 12101 to 12104. This pedestrian identification is performed, for example, by a process of extracting feature points from the imaging images of the imaging units 12101 to 12104, which are infrared cameras, and by a process of determining whether it is a pedestrian by performing pattern matching processing on a series of feature points representing the outline of an object. When the microcomputer 12051 determines that a pedestrian exists in the imaging images of the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 to display a square outline for emphasis, superimposed on the identified pedestrian. The sound / image output unit 12052 can also control the display unit 12062 to display an icon or the like representing a pedestrian at a desired location.
[0132] Examples of vehicle control systems to which the technology according to this disclosure can be applied have been described above. The technology according to this disclosure can be applied to, for example, the imaging unit 12031 in the configuration described above. Specifically, Figure 1 The semiconductor element 100 can be applied to the imaging unit 12031. By applying the technology according to this disclosure to the imaging unit 12031, the inter-wire capacitance can be reduced and high-speed operation can be performed.
[0133] It should be noted that the above embodiments illustrate examples of implementing this technology, and the corresponding matters in the embodiments correspond to the corresponding matters specifically describing the invention in the claims. Similarly, the corresponding matters specifically describing the invention in the claims correspond to the corresponding matters of the same name in the embodiments of this technology. It should be noted that this technology is not limited to these embodiments, and can be implemented by applying various modifications to the embodiments without departing from the scope of this technology.
[0134] It should be noted that the effects described in this manual are merely examples and not limitations, and other effects can also be achieved.
[0135] Note that this technology can also have the following configurations.
[0136] (1) A semiconductor element, comprising:
[0137] Semiconductor substrate;
[0138] An insulating film covering a predetermined surface of a semiconductor substrate;
[0139] Protective film, covering the insulating film;
[0140] A predetermined number of wirings formed in the protective film; and
[0141] Covering gaps, including covering the gaps in each wire within the protective film.
[0142] (2) The semiconductor device according to (1) further includes
[0143] Voids within the insulating film include voids formed within the insulating film.
[0144] (3) The semiconductor device according to (2) further includes
[0145] Pore within the protective film, including voids formed within the protective film.
[0146] The protective film includes:
[0147] The first protective film covering the insulating film; and
[0148] A second protective film covering the first protective film, and
[0149] Voids are formed within the first protective film.
[0150] (4) The semiconductor device according to (3) further includes
[0151] External connection terminals connected to the wiring.
[0152] The gaps within the insulating film and the protective film are positioned to avoid the vicinity of external connection terminals.
[0153] (5) The semiconductor element according to (3) or (4), wherein
[0154] The voids in the insulating film and the voids in the protective film are positioned to avoid the vicinity of the ends of the semiconductor element.
[0155] (6) The semiconductor element according to any one of (3) to (5), wherein
[0156] The voids in the insulating film and the voids in the protective film are preferentially deployed in the central part of the semiconductor device.
[0157] (7) The semiconductor element according to any one of (1) to (6), wherein
[0158] The predetermined number of wires includes a pair of wires with different potentials, and
[0159] The coverage gap covers each of the pair of wires.
[0160] (8) The semiconductor element according to any one of (1) to (7), wherein
[0161] When viewed from a direction perpendicular to the predetermined surface, the covering gap extends along the wiring.
[0162] (9) The semiconductor element according to any one of (1) to (8), wherein
[0163] The contact surface of the wiring contacts the insulating film, and
[0164] When viewed from a direction parallel to the predetermined surface, the covering gap covers all parts except the contact surface.
[0165] (10) The semiconductor element according to any one of (1) to (9), wherein
[0166] When viewed from a direction perpendicular to the predetermined surface, the covering gap can have any of the following shapes: rectangular, circular, and elliptical.
[0167] (11) The semiconductor element according to any one of (1) to (10), wherein
[0168] The insulating film can be made of any of the following materials: polyimide, silicone, acrylic, epoxy resin, and spin-on carbon (SOC).
[0169] (12) The semiconductor element according to any one of (1) to (11), wherein
[0170] Semiconductor components include any of the following: logic circuits, memory, image sensors, and interpolators.
[0171] (13) A method for manufacturing a semiconductor device, the method comprising:
[0172] An insulating film forming process that forms an insulating film on a predetermined surface of a semiconductor substrate;
[0173] A wiring process that produces a predetermined number of wires;
[0174] The protective film forming process that forms a protective film to protect each wiring; and
[0175] A gap forming process is performed in the protective film to form a covering gap that covers each wire.
[0176] (14) The manufacturing method according to (13), wherein
[0177] The protective film includes negatively modifiable (NTD) type thermosetting photoresist, and
[0178] The void formation process includes:
[0179] A photolithography process is performed on the protective film using a predetermined gray-toned mask; and
[0180] A curing process is performed on the protective film.
[0181] Reference Symbol List
[0182] 100 semiconductor devices
[0183] 110, 110-1, 110-2 protective resin films
[0184] Rewiring of 111, 111-1, 111-2, 111-3, and 114
[0185] 112 External connection terminal
[0186] 113 pads
[0187] 120 Photosensitive Insulating Resin Film
[0188] 130 Semiconductor substrate
[0189] 140 wiring layer
[0190] 141 Built-in components
[0191] 142 Wiring
[0192] 143 pads
[0193] 150, 151 through electrodes
[0194] Gap 161, 161-1, 161-1a, 161-1b, 161-1c, 161-2, 161-3, 162, 163
[0195] 200, 202 seeds
[0196] 201, 203 Photoresist
[0197] 300 grayscale mask
[0198] 310 Exposure Area
[0199] 12031 Imaging Unit
Claims
1. A semiconductor element, comprising: Semiconductor substrate; An insulating film covering a predetermined surface of the semiconductor substrate; A protective film covers the insulating film; A predetermined number of wires are formed in the protective film; as well as Covering gaps, including gaps in the protective film that cover each wire.
2. The semiconductor device according to claim 1, further comprising: Voids within the insulating film include voids formed in the insulating film.
3. The semiconductor device according to claim 2, further comprising: Voids within the protective film, including voids formed within the protective film. in, The protective film includes: A first protective film covering the insulating film; and A second protective film covering the first protective film, and The voids in the protective film are formed in the first protective film.
4. The semiconductor device according to claim 3, further comprising: External connection terminals connected to the wiring. in, The gaps within the insulating film and the gaps within the protective film are positioned to avoid the vicinity of the external connection terminals.
5. The semiconductor device according to claim 3, wherein The gaps in the insulating film and the gaps in the protective film are positioned to avoid the vicinity of the ends of the semiconductor element.
6. The semiconductor device according to claim 3, wherein The voids in the insulating film and the voids in the protective film are preferentially deployed in the central portion of the semiconductor element.
7. The semiconductor device according to claim 1, wherein The predetermined number of wires includes a pair of wires with different potentials, and The coverage gap covers each of the pair of wires.
8. The semiconductor device according to claim 1, wherein When viewed from a direction perpendicular to the predetermined surface, the covering gap extends along the wiring.
9. The semiconductor device according to claim 1, wherein The contact surface of the wiring contacts the insulating film, and When viewed from a direction parallel to the predetermined surface, the covering gap covers the portion other than the contact surface.
10. The semiconductor device according to claim 1, wherein When viewed from a direction perpendicular to the predetermined surface, the covering gap has any one of a rectangular shape, a circular shape, or an elliptical shape.
11. The semiconductor device according to claim 1, wherein The insulating film is made of any one of polyimide, silicone, acrylic, epoxy resin, and spin-coated carbon (SOC) materials.
12. The semiconductor device according to claim 1, wherein The semiconductor element includes any one of logic circuits, memory, image sensors, and interpolators.
13. A method for manufacturing a semiconductor device, the method comprising: An insulating film forming process that forms an insulating film on a predetermined surface of a semiconductor substrate; A wiring process that produces a predetermined number of wires; The protective film forming process, which forms a protective film to protect each wire; as well as A gap forming process is performed in the protective film to form a covering gap that covers each wire.
14. The manufacturing method according to claim 13, wherein The protective film comprises a negatively modifiable (NTD) type thermosetting photoresist, and The void formation process includes: A photolithography process is performed on the protective film using a predetermined gray-toned mask; as well as A curing process is performed on the protective film.