Antenna tuner

Abstract

An apparatus includes a power amplifier, a first inductor coupled to the power amplifier, a second inductor magnetically coupled with the first inductor, and an impedance matching circuit having a first terminal and a second terminal, where the first terminal is coupled to the second inductor and the second terminal is coupled to an antenna port. The impedance matching circuit includes a third inductor coupled between the first terminal and the second terminal, and one or more capacitors coupled to the third inductor, wherein the third inductor overlaps the first inductor and the second inductor.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to non-provisional patent application serial number 18 / 189,561, filed March 24, 2023, with the United States Patent and Trademark Office, the entire contents of which are incorporated herein by reference as fully set forth herein and for all applicable purposes. Technical Field

[0003] Various aspects of this disclosure generally relate to wireless communications, and more specifically, to impedance matching in wireless devices. Background Technology

[0004] Wireless devices may include transceivers for transmitting and / or receiving signals via one or more antennas. Good impedance matching between the transceiver and one / or more antennas is desirable to facilitate efficient power transfer between the transceiver and one / or more antennas. Summary of the Invention

[0005] The following provides a brief overview of one or more implementations to offer a basic understanding of such implementations. This overview is not a comprehensive summary of all anticipated implementations, but rather aims to neither identify key or essential elements of all implementations nor define the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed descriptions that follow.

[0006] A first aspect relates to an apparatus. The apparatus includes a power amplifier, a first inductor coupled to the power amplifier, a second inductor magnetically coupled to the first inductor, and an impedance matching circuit having a first terminal and a second terminal, wherein the first terminal is coupled to the second inductor and the second terminal is coupled to an antenna port. The impedance matching circuit includes a third inductor coupled between the first and second terminals, and one or more capacitors coupled to the third inductor, wherein the third inductor overlaps with the first and second inductors.

[0007] The second aspect relates to an apparatus. The apparatus includes a power amplifier, a low-noise amplifier, a first inductor coupled to the power amplifier, a second inductor magnetically coupled to the first inductor, and a third inductor coupled to the low-noise amplifier, wherein the third inductor is magnetically coupled to the second inductor. The apparatus also includes an impedance matching circuit having a first terminal and a second terminal, wherein the first terminal is coupled to the second inductor and the second terminal is coupled to an antenna port. The impedance matching circuit includes a fourth inductor coupled between the first and second terminals, and one or more capacitors coupled to the fourth inductor.

[0008] The third aspect relates to a method for antenna tuning. The method includes: magnetically coupling a radio frequency (RF) signal from a first inductor to a second inductor, and using an impedance matching circuit to tune the impedance of the antenna as seen at the second inductor, the impedance matching circuit including a third inductor overlapping the first and second inductors, and one or more capacitors coupled to the third inductor. The method also includes: propagating the RF signal from the impedance matching circuit to the antenna.

[0009] The fourth aspect relates to an apparatus. The apparatus includes a power amplifier, a first inductor coupled to the power amplifier, a second inductor magnetically coupled to the first inductor, and an impedance matching circuit having a first terminal and a second terminal, wherein the first terminal is coupled to the second inductor and the second terminal is coupled to an antenna port. The impedance matching circuit includes a third inductor magnetically coupled to the first and second inductors and coupled between the first and second terminals, and one or more capacitors coupled to the third inductor.

[0010] The fifth aspect relates to an apparatus for antenna tuning. The apparatus includes: a unit for magnetically coupling a radio frequency (RF) signal from a first inductor to a second inductor; and a unit for tuning the impedance of an antenna as seen at the second inductor, the unit for tuning the antenna impedance including a third inductor overlapping the first and second inductors. The method further includes: a unit for propagating the RF signal from the unit for tuning the antenna impedance to the antenna. Attached Figure Description

[0011] Figure 1 It is a diagram of an environment including an electronic device containing a transceiver, based on certain aspects of this disclosure.

[0012] Figure 2 This is an exploded perspective view illustrating exemplary components of an electronic device according to certain aspects of this disclosure.

[0013] Figure 3 Examples of electronic devices including transceivers and antennas are shown in accordance with certain aspects of this disclosure.

[0014] Figure 4 An example of a transceiver including a power amplifier and a transformer is shown, according to certain aspects of this disclosure.

[0015] Figure 5 An example of a tunable capacitor coupled in parallel with an inductor of a transformer, according to certain aspects of this disclosure, is shown.

[0016] Figure 6 Examples of transceivers including power amplifiers, low-noise amplifiers, and transformers are shown in accordance with certain aspects of this disclosure.

[0017] Figure 7 An example of an impedance matching circuit comprising an inductor, a first capacitor, and a second capacitor, according to certain aspects of this disclosure, is shown.

[0018] Figure 8A It shows that the system is configured to control separately based on certain aspects. Figure 7 An example of a control circuit for the first and second capacitors.

[0019] Figure 8B This illustrates certain aspects of the content of this disclosure. Figure 8A An exemplary implementation of the first and second capacitors.

[0020] Figure 9A A top view shows an exemplary layout of an inductor for an impedance matching circuit according to certain aspects of this disclosure.

[0021] Figure 9B Some aspects of this disclosure are shown. Figure 9A The inductor in which the inductor was removed Figure 9A The bridge of the inductor shown.

[0022] Figure 9C Some aspects of this disclosure are shown. Figure 9A An example of current flow in an inductor.

[0023] Figure 9D Some aspects of this disclosure are shown. Figure 9A Another example of current flow in an inductor.

[0024] Figure 10 It shows one of the aspects according to certain aspects Figure 9A A top view of an example where the inductor overlaps with the first and second inductors.

[0025] Figure 11 Examples of a first inductor comprising two loops and a second inductor comprising two loops are shown according to various aspects of this disclosure.

[0026] Figure 12A A top view of another exemplary layout of an inductor according to certain aspects of this disclosure is shown.

[0027] Figure 12B Some aspects of this disclosure are shown. Figure 12A The inductor in which the inductor was removed Figure 12A The bridge of the inductor shown.

[0028] Figure 13An example of a structure comprising multiple inductors according to certain aspects of this disclosure is shown.

[0029] Figure 14 Another example of a structure comprising multiple inductors according to certain aspects of this disclosure is shown.

[0030] Figure 15 This is a flowchart illustrating an example of a method for antenna tuning according to certain aspects of this disclosure. Detailed Implementation

[0031] The specific embodiments described below with reference to the accompanying drawings are intended as descriptions of various configurations and are not intended to represent only configurations in which the concepts described herein can be implemented. Specific details are included in the specific embodiments for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts can be implemented without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0032] Figure 1 This is a diagram of an environment 100 including electronic device 102, which includes a transceiver 196. In environment 100, electronic device 102 communicates with base station 104 via wireless link 106. As shown, electronic device 102 is depicted as a smartphone. However, electronic device 102 can be implemented as any suitable computing device or other electronic device, such as a cellular base station, broadband router, access point, cellular phone or mobile phone, gaming device, navigation device, media device, laptop computer, desktop computer, tablet computer, server computer, network-connected storage (NAS) device, smart appliance, vehicle-based communication system, Internet of Things (IoT) device, sensor or security device, asset tracker, etc.

[0033] Base station 104 communicates with electronic device 102 via wireless link 106, which can be implemented as any suitable type of wireless link. Although base station 104 is depicted as a base station tower of a cellular radio network, base station 104 can represent or be implemented as another device, such as a satellite, terrestrial broadcast tower, access point, peer device, mesh network node, or another electronic device as described above. Wireless link 106 may include a downlink transmitting data and / or control information from base station 104 to electronic device 102. Wireless link 106 may also include an uplink transmitting data and / or control information from electronic device 102 to base station 104. Wireless link 106 can be implemented using any suitable communication protocol or standard (e.g., 3GPP LTE, 3GPP NR5G, IEEE 802.11, IEEE 802.1, Bluetooth, etc.).

[0034] Electronic device 102 includes a processor 180 and a memory 182. The memory 182 may be or form part of a computer-readable storage medium. The processor 180 may include any type of processor, such as an application processor or a multi-core processor, configured to execute processor-executable instructions (e.g., code) stored in the memory 182. The memory 182 may include any suitable type of data storage medium, such as volatile memory (e.g., random access memory (RAM)), non-volatile memory (e.g., flash memory), optical media, magnetic media (e.g., magnetic disk or magnetic tape), etc. In the context of this disclosure, the memory 182 is implemented to store instructions 184, data 186, and other information of electronic device 102, and therefore, when configured as a computer-readable storage medium or part thereof, the memory 182 does not include transiently propagated signals or carrier waves.

[0035] Electronic device 102 may also include input / output (I / O) port 190. I / O port 190 enables data exchange or interaction with other devices, networks, or users, or between components of the device.

[0036] Electronic device 102 may also include a signal processor (SP) 192 (e.g., a digital signal processor (DSP)). The signal processor 192 functions similarly to a processor and may be able to execute instructions and / or process information in conjunction with memory 182.

[0037] For communication purposes, electronic device 102 also includes a modem 194, a transceiver 196, and one or more antennas. Transceiver 196 uses radio frequency (RF) signals to provide connectivity to the appropriate network and other connected electronic devices. Transceiver 196 can facilitate communication over any suitable type of wireless network, such as a wireless local area network (LAN) (WLAN), peer-to-peer (P2P) network, mesh network, cellular network, wireless wide area network (WWAN), navigation network (e.g., North American Global Positioning System (GPS) or another Global Navigation Satellite System (GNSS)), and / or wireless personal area network (WPAN)).

[0038] Figure 2 An example is shown in which the electronic device 102 is implemented as a mobile device (e.g., a smartphone). However, as referenced above... Figure 1 The electronic device 102 discussed is not limited to mobile devices.

[0039] exist Figure 2 In the example shown, electronic device 102 includes a top cover 202, a display layer 206, a substrate 208 (e.g., a printed circuit board (PCB), plastic laminate, ceramic, any combination thereof, etc.), and a bottom cover 210. In this example, the top cover 202 includes a screen 216. The top cover 202 and the bottom cover 210 provide a housing for electronic device 102, which holds the display layer 206, the substrate 208 (e.g., a PCB), and other components of electronic device 102 that may or may not be on the substrate 208. Figure 2 (Not shown in the image). The housing can be substantially rectangular, such as... Figure 2 The example shown is illustrated in the figure. However, it should be understood that the housing can have other shapes. It should also be understood that in some implementations, the housing can be configured to bend or fold. In addition, it should be understood that the substrate 208 (e.g., PCB) is not limited to Figure 2 The exemplary dimensions and / or shapes are shown.

[0040] Figure 3 An example is shown in which electronic device 102 includes a transceiver 196, a memory 182, and antennas 320-1 to 320-N. Electronic device 102 also includes a baseband processor 330 coupled to the transceiver 196 and the memory 182. The baseband processor 330 may be as described above. Figure 1The modem 194, signal processor 192, and / or processor 180 discussed are part of this discussion. Transceiver 196 may be coupled to baseband processor 330 via one or more signal lines. For example, in some implementations, transceiver 196 may be coupled to baseband processor 330 via multiple signal lines arranged in parallel. Transceiver 196, memory 182, baseband processor 330, antennas 320-1 to 320-N, or any combination thereof, may be mounted, formed in, and / or embedded in substrate 208 (e.g., PCB). For example, in some implementations, transceiver 196 may be integrated on multiple chips in a multi-chip module.

[0041] Transceiver 196 can be coupled to each of antennas 320-1 to 320-N via corresponding transmission lines 310-1 to 310-N. Transmission lines may also be referred to as feed lines or other terms. In some aspects, transmission lines 310-1 to 310-N can be implemented using metal traces formed on and / or embedded in substrate 208 (e.g., a PCB). In some implementations, transceiver 196 can be integrated on one or more chips mounted on substrate 208, and antennas 320-1 to 320-N can be external to one or more chips (e.g., off-chip).

[0042] Each of antennas 320-1 to 320-N can be implemented using a patch antenna, a dipole antenna, or another type of antenna. Antennas 320-1 to 320-N may also be referred to as antenna elements or another term. In some implementations, antennas 320-1 to 320-N can be arranged in a one-dimensional array, a two-dimensional array, a three-dimensional array, or another configuration. In some implementations, one or more of antennas 320-1 to 320-N can be integrated onto an antenna module, which can be mounted on substrate 208 or on another surface of electronic device 102. In some implementations, two or more of antennas 320-1 to 320-N can be oriented in different directions to provide wireless transmission and / or reception in different directions.

[0043] Transceiver 196 can be configured to transmit one or more RF signals via one or more of antennas 320-1 to 320-N (e.g., to base station 104). Transceiver 196 can also be configured to receive one or more RF signals via one or more of antennas 320-1 to 320-N (e.g., from base station 104). Transceiver 196 can use one or more wireless communication technologies to transmit and / or receive RF signals, including but not limited to third-generation (3G) technologies (e.g., CDMA), fourth-generation (4G) technologies (also known as Long Term Evolution (LTE)), fifth-generation (5G) technologies, one or more technologies based on one or more IEEE 802.11 protocols (e.g., IEEE 802.11ac, IEEE 802.11n, IEEE 802.11ad, IEEE 802.11ax, IEEE 802.11ay, etc.), and / or one or more other technologies. The RF signals can be in the millimeter-wave (mmW) band and / or another band. Examples of mmW bands include those used in the fifth-generation standard.

[0044] To transmit data and / or control information (e.g., to base station 104), baseband processor 330 may process the data and / or control information into one or more baseband signals. The processing performed by baseband processor 330 may include decoding and / or modulation. Transceiver 196 receives one or more baseband signals and processes them into one or more RF signals for transmission via one or more of antennas 320-1 to 320-N. The processing performed by transceiver 196 may include filtering, up-conversion, power amplification, phase shifting, or any combination thereof. In some aspects, transceiver 196 may first up-convert one or more baseband signals into one or more intermediate frequency (IF) signals, and then up-convert one or more IF signals into one or more RF signals.

[0045] In order to receive data and / or control information (e.g., from base station 104), transceiver 196 receives one or more RF signals carrying data and / or control information via one or more of antennas 320-1 to 320-N. Transceiver 196 can then process the one or more RF signals into one or more baseband signals. Processing performed by transceiver 196 may include low-noise amplification, down-conversion, phase shifting, filtering, or any combination thereof. In some aspects, transceiver 196 may first down-convert one or more RF signals into one or more IF signals, and then down-convert one or more IF signals into one or more baseband signals. Baseband processor 330 receives one or more baseband signals and processes them to recover data and / or control information. Processing performed by baseband processor 330 may include decoding and / or demodulation.

[0046] Figure 4 An example of a portion of a transceiver 196 according to certain aspects is shown. In this example, the transceiver 196 includes a power amplifier (PA) 410 and a transformer 420. Figure 4 As shown, transformer 420 is coupled to antenna 320 via transmission line 310. Antenna 320 can be... Figure 3 Any one of the antennas 320-1 to 320-N shown. In some implementations, the transformer 420 is integrated on a chip, and the antenna 320 is external to the chip (i.e., off-chip). In this example, the transformer 420 may be coupled to the transmission line 310 via an antenna port. The antenna port 450 may include pads on the chip. The pads may be coupled to the transmission line 310 via bumps (e.g., not shown) and / or another conductor. The transformer 420 may be coupled to the antenna port 450 via metal wiring on the chip. However, it should be understood that this disclosure is not limited to this example. In other examples, the antenna 320 may be configured on a chip or share a substrate or other common structure for supporting the power amplifier 410 and the antenna 320 (e.g., integrated together in a module).

[0047] Although Figure 4 The diagram shows a PA410 and a transformer 420, but it should be understood that transceiver 196 may include multiple PAs and transformers. For example, transceiver 196 may include components for... Figure 3 The corresponding PA and corresponding transformer for each antenna in the antennas 320-1 to 320-N shown, or for each antenna in a subset of antennas 320-1 to 320-N.

[0048] PA 410 is configured to amplify RF signals for transmission via antenna 320. Figure 4 In the example shown, PA410 is a differential PA having input 412 and differential outputs including a first output 416 and a second output 418. In this example, PA 410 is configured to receive an RF signal at input 412 (e.g., from a mixer or other circuit), amplify the RF signal, and output the amplified RF signal at the differential output. In this example, the amplified RF signal may be a differential RF signal including a first RF signal at the first output 416 and a second signal RF at the second output 418. Input 412 may be a single-ended input or a differential input.

[0049] exist Figure 4In the example shown, transformer 420 includes a first inductor 430 and a second inductor 440 that are magnetically (i.e., inductively) coupled to each other. The first inductor 430 is coupled between a first output 416 and a second output 418 of PA 410, and the second inductor 440 is coupled between antenna 320 and ground (or a reference potential). Because the first inductor 430 and the second inductor 440 are magnetically coupled, transformer 420 transfers power from PA 410 to antenna 320. In some aspects, transformer 420 is configured to convert a differential RF signal at the first inductor 430 into a single-ended RF signal at the second inductor 440 for transmission via antenna 320.

[0050] It should be understood that transmitter 196 may include Figure 4 One or more additional components not explicitly shown in the document. For example, Figure 5 An example is shown in which transceiver 196 also includes a tunable capacitor 510 coupled in parallel with the first inductor 430. In this example, the first inductor 430 and the tunable capacitor 510 provide a load at the output of PA410 using a tunable resonant frequency to increase the gain at the desired frequency. In this example, the center tap (not shown) of the first inductor 430 can be coupled to a common-mode voltage. However, it should be understood that this disclosure is not limited to this example.

[0051] Figure 6 An example is shown in which transceiver 196 also includes a low-noise amplifier (LNA) 610 according to certain aspects. LNA 610 has an input 612 and an output 614. LNA 610 is configured to receive an RF signal from antenna 320 at input 612, amplify the RF signal, and output the amplified RF signal at output 614. Output 614 of LNA 610 can be coupled to a mixer (not shown), a filter (not shown), and / or another component of transceiver 196 for downconversion.

[0052] In this example, transformer 420 also includes a third inductor 620 coupled between input 612 of LNA 610 and ground (or some reference potential). The third inductor 620 is magnetically (i.e., inductively grounded) coupled to the second inductor 440. Because the second inductor 440 and the third inductor 620 are magnetically coupled, transformer 420 transfers power from the RF signal received from antenna 320 to input 612 of LNA 610. This allows LNA 610 to receive and amplify the RF signal received by antenna 320. Therefore, in this example, transformer 420 magnetically (i.e., inductively grounded) couples PA 410 to antenna 320 and magnetically (i.e., inductively grounded) couples antenna 320 to LNA 610.

[0053] In this example, transformer 420 can also be referred to as a three-coil transformer because it includes three inductors. However, it should be understood that transformer 420 is not limited to this example, and in other implementations, transformer 420 may include one or more additional inductors.

[0054] A challenge in using transceiver 196 is that the impedance of antenna 320 may vary (e.g., due to environmental changes). For example, antenna impedance can change based on how the user holds electronic device 102, due to crosstalk between antenna 320 and other active antennas (e.g., one or more of the other antennas in antennas 320-1 to 320-N), due to changes in frequency band, etc. Furthermore, antenna impedance may be affected by the geometry and / or composition of the housing used to house antenna 320, the position and / or orientation of antenna 320 within the housing, etc.

[0055] Antenna impedance variations can increase impedance mismatch between transceiver 196 and antenna 320, which reduces the efficiency of power transfer between antenna 320 and transceiver 196. Due to the reduced power transfer, the output power of PA 410 needs to be increased to achieve a given transmit power at antenna 320, which increases power consumption and reduces power efficiency. The increased impedance mismatch can also increase the noise figure of LNA 610.

[0056] To address this problem, aspects of this disclosure provide a tunable impedance matching circuit (e.g., an antenna tuning circuit system) configured to tune the impedance seen at transceiver 196 to maintain good impedance matching across variations in antenna impedance, as discussed further below.

[0057] Figure 7 An example is shown in which the electronic device 102 also includes an impedance matching circuit 710 coupled between the transformer 420 and the antenna 320. In this example, the impedance matching circuit 710 has a first terminal 712 coupled to a second inductor 440 of the transformer 420, and a second terminal 714 coupled to the antenna 320 (e.g., via the antenna port 450 and the transmission line 310).

[0058] Impedance matching circuit 710 can be configured to tune the impedance seen at first terminal 712 (labeled "Z") to maintain good impedance matching across impedance variations of antenna 320. For example, good impedance matching can be achieved when the impedance seen at first terminal 712 is approximately equal to the target impedance (e.g., 50 ohms). In this example, impedance matching circuit 710 can tune the impedance Z seen at first terminal 712 to maintain impedance Z near the target impedance (e.g., 50 ohms). Good impedance matching improves the efficiency of power transfer between transceiver 196 and antenna 320 for better overall system efficiency. It should be understood that impedance matching circuit 710 does not need to provide perfect impedance matching.

[0059] In this example, the impedance matching circuit 710 includes an inductor 720, a first capacitor 730, and a second capacitor 740. In this example, the inductor 720 is coupled between a first terminal 712 and a second terminal 714. The first capacitor 730 is coupled between the second terminal 714 and ground (or a reference potential), and the second capacitor 740 is coupled between the first terminal 712 and ground (or a reference potential). In this example, the inductor 720, the first capacitor 730, and the second capacitor 740 are arranged to form a pi impedance matching network.

[0060] Other types of impedance matching networks are possible, such as L-type impedance matching networks and T-type impedance matching networks. Regarding L-type impedance matching networks, pi-type impedance matching networks provide impedance tuning over a wider range than L-type impedance matching networks. T-type impedance matching networks use series tunable capacitors. However, series tunable capacitors may require strong drain and source wiring for the switching transistors used in the tunable capacitors to handle the high currents (e.g., hundreds of milliamps) for high-power applications. Strong drain and source wiring reduces the off-impedance of the switching transistors and makes the capacitors more difficult to tune. In contrast, pi-type impedance matching networks use series inductors (e.g., inductor 720), which can be more easily designed to handle the high currents for high-power applications.

[0061] In some aspects, the first capacitor 730 has a first tunable capacitor C1, and the second capacitor 740 has a second capacitor C2. In these aspects, the impedance Z seen at the first terminal 712 can be tuned by tuning the first capacitor C1 and / or the second capacitor C2. For example, if the antenna impedance is low, the second capacitor C2 of the second capacitor 740 can be tuned to bring the impedance Z close to the target impedance for good impedance matching. If the antenna impedance is high, the first capacitor C1 of the first capacitor 730 can be tuned to bring the impedance Z close to the target impedance (e.g., 50Ω) for good impedance matching.

[0062] In some respects, inductor 720, first capacitor 730, and second capacitor 740 can be integrated on the same chip as inductors 430, 440, and 620. The advantage of integrating inductor 720 on-chip is that no additional pads and / or bumps are required to couple inductor 720 to capacitors 730 and 740. In contrast, external inductors for inductor 720 may require additional pads and / or bumps on substrate 208, as well as additional metal wiring, for coupling the two ends of inductor 720 to capacitors 730 and 740.

[0063] Figure 8A An example is shown in which the first capacitor C1 of the first capacitor 730 and the second capacitor C2 of the second capacitor 740 are controlled by the control circuit 810. In this example, the first capacitor 730 is configured to set the first capacitor C1 based on a first control signal (labeled "Ctrl1") from the control circuit 810, and the second capacitor 740 is configured to set the second capacitor C2 based on a second control signal (labeled "Ctrl2") from the control circuit 810.

[0064] In some respects, each of the first capacitor 730 and the second capacitor 740 can be implemented using a corresponding digitally programmable capacitor. In this example, the first control signal may include a first digital signal that digitally sets (i.e., programs) the first capacitor C1. Figure 8B In some implementations shown, the first capacitor 730 includes a first group of switchable capacitors 820-1 to 820-n, wherein a first digital signal sets the first capacitor C1 by controlling which of the switchable capacitors 820-1 to 820-n in the first group are turned on. In some aspects, the first digital signal includes a digital code, which includes bits in which the bit value of each bit controls whether the corresponding switchable capacitor in the first group of switchable capacitors 820-1 to 820-n is turned on or off. Figure 8BIn the example shown, switchable capacitors 820-1 to 820-n are coupled in parallel, and each of the switchable capacitors 820-1 to 820-n includes corresponding capacitors 832-1 to 832-n and 834-1 to 834-n coupled in series, as well as corresponding switches 830-1 to 830-n (e.g., switching transistors). In this example, a first digital signal turns on the switchable capacitor (i.e., one of the corresponding switches 830-1 to 830-n) by turning on the corresponding switch (i.e., one of the corresponding switches 830-1 to 830-n), and turns off the switchable capacitor by turning off the corresponding switch.

[0065] Additionally, in this example, the second control signal may include a second digital signal that digitally sets (i.e., programs) the second capacitor C2. Figure 8B In some implementations shown, the second capacitor 740 includes a second group of switchable capacitors 840-1 to 840-n, wherein a second digital signal sets the second capacitor C2 by controlling which of the switchable capacitors 840-1 to 840-n in the second group are turned on. In some aspects, the second digital signal includes a digital code comprising bits in which the bit value of each bit controls whether the corresponding switchable capacitor in the second group of switchable capacitors 840-1 to 840-n is turned on or off. Figure 8B In the example shown, switchable capacitors 840-1 to 840-n are coupled in parallel, and each of the switchable capacitors 840-1 to 840-n includes corresponding capacitors 852-1 to 852-n and 854-1 to 854-n coupled in series, as well as corresponding switches 850-1 to 850-n (e.g., switching transistors). In this example, a second digital signal turns on the switchable capacitor (i.e., one of the corresponding switches 850-1 to 850-n) by turning on the corresponding switch (i.e., one of the corresponding switches 850-1 to 850-n), and turns off the switchable capacitor by turning off the corresponding switch.

[0066] It should be understood that the switchable capacitors 820-1 to 820-n and 840-1 to 840-n are not limited to Figure 8B The examples show the arrangement and / or number of capacitors and switches. Typically, switchable capacitors consist of one or more capacitors coupled in series and one or more switches.

[0067] In some aspects, control circuitry 810 can store capacitance settings for capacitors 730 and 740 for different use cases affecting the impedance of antenna 320 of electronic device 102. The capacitance settings for different use cases can be stored (i.e., loaded) in a register or another type of memory. The capacitance settings for each use case may include settings for a first capacitor C1 and a setting for a second capacitor C2 that provide good impedance matching for the use case. In this example, control circuitry 810 can determine the current use case of electronic device 102 and set the first capacitor C1 and the second capacitor C2 based on the stored settings for the determined use case.

[0068] In an example where the first control signal for the first capacitor 730 includes a first digital signal, the setting of the first capacitor C1 for each use case can be specified by a corresponding digital code, wherein the bit value of the corresponding digital code controls which switchable capacitors 820-1 to 820-n in the first group are turned on. Similarly, in an example where the second control signal for the second capacitor 740 includes a second digital signal, the setting of the second capacitor C2 for each use case can be specified by a corresponding digital code, wherein the bit value of the corresponding digital code controls which switchable capacitors 840-1 to 840-n in the second group are turned on. In this example, for each use case, the control circuit 810 can store a corresponding pair of digital codes (i.e., a digital code for the first capacitor C1 and a digital code for the second capacitor C2). In operation, the control circuit 810 can determine the current use case of the electronic device 102 and set the first capacitor C1 and the second capacitor C2 based on the stored digital codes for the determined use case.

[0069] In some implementations, transceiver 196 may support beamforming to transmit RF signals in any of a plurality of beam directions using all antennas 320-1 to 320-N or a subset of antennas 320-1 to 320-N. In this example, the impedance of antenna 320 may be different for different beam directions (e.g., due to different transmit power at different angles for different beam directions). In this example, for each beam direction, control circuitry 810 may store a corresponding capacitance setting for a first capacitor C1 and a corresponding setting for a second capacitor C2 that provides good impedance matching for the beam direction. For an example where capacitors 730 and 740 are digitally tuned (i.e., programmed), the capacitance settings for capacitors C1 and C2 may be specified by a corresponding pair of digital codes. In operation, control circuitry 810 may determine the current beam direction and set the first capacitor C1 and the second capacitor C2 based on the stored capacitance settings (e.g., digital codes) for the determined beam direction.

[0070] In some aspects, the beam direction can be controlled by a beamformer (not shown) in transceiver 196. In these aspects, control circuitry 810 can receive a signal from the beamformer indicating the current beam direction and determine the current beam direction based on the received signal.

[0071] In some implementations, transceiver 196 may support an adaptive power control scheme in which a power coupler (not shown) or a PA drain detector is used to detect the power delivered to antenna 320, and the power controller adjusts the output power of PA 410 based on the detected power. In this example, control circuitry 810 can use the detected power to tune first capacitor C1 and second capacitor C2 to find a capacitance setting for first capacitor C1 and second capacitor C2 that results in the highest power (e.g., average power) delivered to antenna 320 based on the detected power. In this example, higher power indicates higher efficiency of power transmission to antenna 320, and therefore indicates better impedance matching.

[0072] In the example where inductor 720 is integrated on the chip, it is desirable for inductor 720 to have very low magnetic coupling with inductors 430, 440, and 620. This is because large magnetic coupling between inductor 720 and inductors 430, 440, and 620 could have a significant impact on the characteristics of transformer 420 and could complicate the design of transformer 420 to account for the magnetic coupling with inductor 720. One way to reduce the magnetic coupling between inductor 720 and inductors 430, 440, and 620 is to position inductor 720 away from inductors 430, 440, and 620 on the chip. However, this method would likely require a large additional area on the chip to accommodate inductor 720. To address this issue, various aspects of this disclosure provide inductor designs for inductor 720 that allow inductor 720 to fully or substantially overlap with inductors 430, 440, and 620 of transformer 420 to achieve high area efficiency, while maintaining very low magnetic coupling between inductor 720 and inductors 430, 440, and 620, as discussed further below.

[0073] Figure 9AA top view of an exemplary layout of an inductor 720 according to certain aspects is shown. In this example, the inductor 720 includes an 8-shaped conductor path 905 forming a first loop 910 and a second loop 915. In some implementations, the 8-shaped conductor path 905 may be formed by two or more metal layers on a chip (e.g., using photolithography and etching processes). The 8-shaped conductor path 905 may also be referred to as a figure-eight conductor path or another term. As discussed further below, the 8-shaped conductor path 905 substantially reduces the magnetic coupling between the inductor 720 and one or more other inductors overlapping the inductor 720 (e.g., one or more of inductors 430, 440, and 620).

[0074] In this example, conductor path 905 includes a first portion 920, a second portion 925, and a bridge 928 coupling the first portion 920 and the second portion 925. Bridge 928 allows conductor path 905 to intersect itself to form an 8 shape (also known as a figure-eight). In one example, the first portion 920 and the second portion 925 may be formed by a first metal layer on the chip (e.g., using photolithography and etching processes), and bridge 928 may be formed by a second metal layer on the chip (e.g., using photolithography and etching processes). The second metal layer may be located above or below the first metal layer on the chip.

[0075] exist Figure 9A In the example shown, the second metal layer is located above the first metal layer. Therefore, in this example, the bridge 928 crosses above the second portion 925 of the conductor path 905. However, it should be understood that in other implementations, the second metal layer may be located below the first metal layer, in which case the bridge 928 crosses below the second portion 925 of the conductor path 905. Figure 9B A view of inductor 720 without bridge 928 is shown. In this example, inductor 720 includes a first portion 920 of conductor path 905 coupled to bridge 928. Figure 9A (shown in the figure) One or more vias 950 and one or more vias 955 that couple the second portion 925 of the conductor path 905 to the bridge 928.

[0076] In this example, inductor 720 has a first terminal 930 and a second terminal 935. The first terminal 930 can be coupled to a first terminal 712 of impedance matching circuit 710 (e.g., via on-chip metal wiring), and the second terminal 935 can be coupled to a second terminal 714 of impedance matching circuit 710 (e.g., via on-chip metal wiring), and vice versa. Figure 9A As shown, the first terminal 930 can be located at one end of the conductor path 905, and the second terminal 935 can be located at the other end of the conductor path 905.

[0077] As discussed above, the 8-shaped conductor path 905 of inductor 720 in this example substantially reduces magnetic coupling between inductor 720 and one or more other inductors overlapping inductor 720 (e.g., one or more of inductors 430, 440, and 620). This is because, when current flows into inductor 720, the 8-shaped conductor path 905 causes the current to flow in opposite directions in the first loop 910 and the second loop 915, which generates a magnetic flux in the first loop 910 and a magnetic flux of opposite polarity in the second loop 915. The opposite polarity of the magnetic flux in the first loop 910 and the magnetic flux in the second loop 915 substantially reduces magnetic coupling from inductor 720 to one or more other inductors overlapping inductor 720 (e.g., one or more of inductors 430, 440, and 620).

[0078] The current flow in the first loop 910 of inductor 720 is in the opposite direction to the current flow in the second loop 915. Figure 9C and Figure 9D As shown in the image. Figure 9C An example is shown in which current flows into the first terminal 930 of inductor 720. The direction of current flow in conductor path 905 is indicated by arrows. In this example, the current flows counterclockwise in the first loop 910 and clockwise in the second loop 915. Therefore, the magnetic field of the magnetic flux in the first loop 910 points out of the page, and the magnetic field of the magnetic flux in the second loop 915 points in into the page.

[0079] Figure 9D An example is shown in which current flows into the second terminal 935 of inductor 720. The direction of current flow in conductor path 905 is indicated by arrows. In this example, the current flows clockwise in the first loop 910 and counterclockwise in the second loop 915. Therefore, the magnetic field of the magnetic flux in the first loop 910 points inwards, and the magnetic field of the magnetic flux in the second loop 915 points outwards.

[0080] exist Figure 9C and Figure 9D In both cases shown, the current flows in opposite directions in the first loop 910 and the second loop 915, which generates magnetic flux in the first loop 910 and magnetic flux with opposite polarity in the second loop 915.

[0081] Figure 10A top view shows an exemplary layout of inductor 720, first inductor 430, and second inductor 440 according to certain aspects of this disclosure. In this example, the first inductor 430 is implemented using a loop inductor having a first terminal 1010 and a second terminal 1020. The first terminal 1010 and the second terminal 1020 may be coupled between outputs 416 and 418 of PA-410 (e.g., via metal wiring on the chip). Additionally, in this example, the second inductor 440 is implemented using a loop inductor having a first terminal 1030 and a second terminal 1040. The first terminal 1030 may be coupled to a first terminal 712 of impedance matching circuit 710, and the second terminal 1040 may be coupled to ground (or a reference potential), or vice versa.

[0082] exist Figure 10 In the example shown, loop 1025 of the second inductor 440 is located within loop 1015 of the first inductor 430 to enhance the magnetic coupling between the first inductor 430 and the second inductor 440. In this example, the first inductor 430 and the second inductor 440 may be formed from the same metal layer on the chip (e.g., using photolithography and etching processes). However, it should be understood that this disclosure is not limited to this example. For example, in other implementations, the first inductor 430 and the second inductor 440 may be formed from different metal layers.

[0083] Inductor 720 overlaps with the first inductor 430 and the second inductor 440. As used herein, an inductor may overlap with another inductor when the region within the loop of the inductor overlaps with that of the other inductor. Figure 10 In the example shown, inductor 720 overlaps with the regions within loops 1015 and 1025 of the first inductor 430 and the second inductor 440. Therefore, in this example, inductor 720 does not occupy additional area on the chip, thus improving area efficiency. As described above, the current in inductor 720 generates magnetic flux within the first loop 910 and generates magnetic flux of opposite polarity within the second loop 915. Due to their opposite polarity, the magnetic flux of the first loop 910 cancels out the magnetic flux of the second loop 915 within loops 1015 and 1025 of inductors 430 and 440, which substantially reduces the magnetic coupling from inductor 720 to inductors 430 and 440. Therefore, inductor 720 is weakly magnetically coupled to the first inductor 430 and the second inductor 440. In some respects, the first loop 910 and the second loop 915 of inductor 720 may completely overlap with the regions within loops 1015 and 1025 of inductors 430 and 440.

[0084] The first portion 920 and the second portion 925 of the conductor path 905 of the inductor 720 may be formed from the same metal layer as the inductors 430 and 440, or the first portion 920 and the second portion 925 of the conductor path 905 of the inductor 720 may be formed from different metal layers on the chip.

[0085] exist Figure 10 In the example shown, each of inductors 430 and 440 has a single loop. However, it should be understood that this disclosure is not limited to this example. For example, in some implementations, the first inductor 430 may include two or more loops, and / or the second inductor 440 may include two or more loops.

[0086] In this regard, Figure 11 An example is shown in which a first inductor 430 includes two loops coupled in parallel and a second inductor 440 includes two loops coupled in parallel. More specifically, in this example, the first inductor 430 includes a first loop 1120 (e.g., an output loop) and a second loop 1125 (e.g., an internal loop) within the first loop 1120. The first inductor 430 also includes a first bridge 1130 coupling a first end of the first loop 1120 to a first end of the second loop 1125, and a second bridge 1135 coupling a second end of the first loop 1120 to a second end of the second loop 1125. Figure 11 As shown, in this example, the first terminal 1010 is located at the first bridge 1130, and the second terminal 1020 is located at the second bridge 1135.

[0087] In this example, the second inductor 440 includes a first loop 1140 (e.g., an output loop) and a second loop 1145 (e.g., an internal loop) within the first loop 1140. The second inductor 440 also includes a first bridge 1150 coupling a first end of the first loop 1140 to a first end of the second loop 1145, and a second bridge 1155 coupling a second end of the first loop 1140 to a second end of the second loop 1145. Figure 11 As shown, in this example, the first terminal 1030 is located at the first bridge 1150, and the second terminal 1040 is located at the second bridge 1155.

[0088] exist Figure 11 In the example shown, the first loop 1140 of the second inductor 440 is located between the first loop 1120 and the second loop 1125 of the first inductor 430, and the second loop 1125 of the first inductor 430 is located between the first loop 1140 and the second loop 1145 of the second inductor 440. This feature enhances the magnetic coupling between the first inductor 430 and the second inductor 440. Figure 11In the example shown, the first bridge 1130 and the second bridge 1135 of the first inductor 430 pass through the first loop 1140 of the second inductor 440, and the first bridge 1150 and the second bridge 1155 of the second inductor 440 pass through the first loop 1120 and the second loop 1125 of the first inductor 430.

[0089] It should be understood that the content of this disclosure is not limited to... Figure 11 The example shown. For example, besides Figure 11 In addition to the loop shown, the first inductor 430 and the second inductor 440 may each include one or more additional loops.

[0090] Figure 12A A top view of an exemplary layout of a third inductor 620 according to certain aspects is shown. In this example, the third inductor 620 has an outer loop 1210 and an inner loop 1215. The third inductor 620 may also include a bridge 1228 coupling a first portion 1220 and a second portion 1225 of the third inductor 620. The bridge 1228 allows the third inductor 620 to cross itself. In one example, the first portion 1220 and the second portion 1225 may be formed by a first metal layer on the chip (e.g., using photolithography and etching processes), and the bridge 1228 may be formed by a second metal layer on the chip (e.g., using photolithography and etching processes). The second metal layer may be located above or below the first metal layer.

[0091] exist Figure 12A In the example shown, the second metal layer is located above the first metal layer. Therefore, in this example, the bridge 1228 crosses above the first portion 1220 of the third inductor 620. However, it should be understood that in other implementations, the second metal layer may be located below the first metal layer, in which case the bridge 1228 crosses below the first portion 1220 of the third inductor 620. Figure 12B A view of a third inductor 620 without bridge 1228 is shown. In this example, inductor 620 includes a first portion 1220 of the third inductor 620 coupled to bridge 1228. Figure 12A (shown in the figure) One or more vias 1250 and one or more vias 1255 that couple the second portion 1225 of the third inductor 620 to the bridge 1228.

[0092] In this example, the third inductor 620 has a first terminal 1230 and a second terminal 1235. The first terminal 1230 may be coupled to the input 612 of the LNA 610 (e.g., through metal wiring on the chip), and the second terminal 1235 may be coupled to ground (or a reference potential), or vice versa.

[0093] Figure 13An example is shown in Figure 12, where a third inductor 620 is located within loops 1140 and 1145 of the second inductor 440 to enhance the magnetic coupling from the second inductor 440 to the third inductor 620. The magnetic coupling between the second inductor 440 and the third inductor 620 facilitates the transmission of RF signal power from the antenna 320 to the LNA 610. In this example, the first inductor 430, the second inductor 440, and the third inductor 760 form a three-coil structure 1310.

[0094] Figure 14 The inductor 720 is shown with Figure 13 The example shown is a three-coil structure 1310 overlapped to form a four-coil structure 1410. In this example, inductor 720 and... Figure 13 The three-coil structure 1310 shown overlaps. As a result, in this example, the inductor 720 does not require additional chip area.

[0095] As described above, the current in inductor 720 generates magnetic flux in the first loop 910 and magnetic flux with opposite polarity in the second loop 915. Due to their opposite polarity, the magnetic flux in the first loop 910 cancels out the magnetic flux in the second loop 915 within the loops of inductors 430, 440, and 620, which substantially reduces the magnetic coupling from inductor 720 to inductors 430, 440, and 620.

[0096] exist Figure 14 In the example shown, the first loop 910 and the second loop 915 of inductor 720 overlap with the regions within loops 1120 and 1125 of the first inductor 430, and with the regions within loops 1140 and 1145 of the second inductor 440. The first loop 910 and the second loop 915 of inductor 720 also overlap with the regions within the loops of the third inductor 620.

[0097] although Figure 14 An example is shown in which each of inductors 430, 440, and 620 includes two loops; however, it should be understood that this disclosure is not limited to this example. For example, in other implementations, one or more of inductors 430, 440, and 620 may each include a single loop, or one or more of inductors 430, 440, and 620 may each include three or more loops.

[0098] It should be understood that the inductor 720 is not limited to one 8-shaped conductor path, and the inductor 720 may include two or more 8-shaped conductor paths (e.g., series and / or parallel coupling).

[0099] Figure 15A flowchart illustrating an example of a method 1500 for antenna tuning according to certain aspects of this disclosure is shown.

[0100] At block 1510, a radio frequency (RF) signal is magnetically coupled from the first inductor to the second inductor. For example, transformer 420 can magnetically couple an RF signal from the first inductor (e.g., first inductor 430) to the second inductor (e.g., second inductor 440). The RF signal can originate from a power amplifier (e.g., PA 410) coupled to the first inductor.

[0101] At block 1520, an impedance matching circuit is used to tune the impedance of the antenna as seen at the second inductor. This impedance matching circuit includes a third inductor overlapping the first and second inductors, and one or more capacitors coupled to the third inductor. The impedance matching circuit may correspond to impedance matching circuit 710. In some aspects, tuning the antenna impedance includes tuning the capacitance of one or more capacitors (e.g., the first capacitor 730 and / or the second capacitor 740). Tuning the capacitance may be performed by control circuitry 810.

[0102] At block 1530, the RF signal is propagated from the impedance matching circuit to the antenna. For example, transmission line 310 can propagate the RF to the antenna (e.g., antenna 320).

[0103] In some aspects, the third inductor includes a first loop and a second loop, and method 1500 further includes generating a magnetic flux in the first loop and generating a magnetic flux of opposite polarity in the second loop. The first loop may correspond to a first loop 910, and the second loop may correspond to a second loop 915.

[0104] The control circuit 810 may be implemented using a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete hardware components (e.g., logic gates), or any combination thereof, designed to perform the functions described herein. The processor may perform the functions described herein by executing software that includes code for performing the functions. The software may be stored on a computer-readable storage medium, such as RAM, ROM, EEPROM, optical disk, and / or magnetic disk.

[0105] It should be understood that inductors can be physically implemented on a chip with multiple inductors having series and / or parallel coupling.

[0106] It should be understood that this disclosure is not limited to the exemplary terms used above to describe various aspects of this disclosure. For example, an inductor in a transformer may also be referred to as a winding or another term. Furthermore, it should be understood that an inductor may be referred to as a coil even when it is not physically implemented using a coil. It should also be understood that magnetic coupling may also be referred to as inductive coupling or another term. A tunable capacitor may also be referred to as a variable capacitor, a programmable capacitor, or another term. An impedance matching circuit may also be referred to as an impedance matching network, an impedance tuning circuit, an antenna tuner, or another term.

[0107] Examples of implementation methods are described in the following numbered clauses:

[0108] 1. An apparatus comprising:

[0109] Power amplifier;

[0110] A first inductor coupled to the power amplifier;

[0111] A second inductor, which is magnetically coupled to the first inductor;

[0112] An impedance matching circuit has a first terminal and a second terminal, wherein the first terminal is coupled to a second inductor and the second terminal is coupled to an antenna port, and the impedance matching circuit includes:

[0113] A third inductor coupled between the first terminal and the second terminal, wherein the third inductor overlaps with the first inductor and the second inductor; and

[0114] One or more capacitors coupled to the third inductor.

[0115] 2. The apparatus according to Clause 1, wherein the third inductor includes an 8-shaped conductor path forming the first loop and the second loop.

[0116] 3. The apparatus according to Clause 2, wherein:

[0117] The first inductor includes one or more loops; and

[0118] The first and second loops of the third inductor overlap with the regions within one or more loops of the first inductor.

[0119] 4. The apparatus according to clause 2 or 3, wherein:

[0120] The second inductor includes one or more loops; and

[0121] The first and second loops of the third inductor overlap with the regions within one or more loops of the second inductor.

[0122] 5. The apparatus according to any one of clauses 2 to 4, wherein the third inductor is configured to generate magnetic flux in the first loop and to generate magnetic flux of opposite polarity in the second loop.

[0123] 6. The device according to any one of clauses 2 to 5, wherein the conductor path comprises a first portion, a second portion, and a bridge, wherein the bridge couples the first portion and the second portion, and the bridge passes through the second portion.

[0124] 7. The apparatus according to Clause 1, wherein the third inductor comprises a first loop and a second loop.

[0125] 8. The apparatus according to Clause 7, wherein:

[0126] The first inductor includes one or more loops; and

[0127] The first and second loops of the third inductor overlap with the regions within one or more loops of the first inductor.

[0128] 9. The apparatus according to clause 7 or 8, wherein:

[0129] The second inductor includes one or more loops; and

[0130] The first and second loops of the third inductor overlap with the regions within one or more loops of the second inductor.

[0131] 10. The apparatus according to any one of clauses 7 to 9, wherein the third inductor is configured to generate magnetic flux in the first loop and to generate magnetic flux of opposite polarity in the second loop.

[0132] 11. The apparatus according to any one of clauses 1 to 10, wherein the one or more capacitors comprise a first capacitor having a first tunable capacitance and a second capacitor having a second tunable capacitance.

[0133] 12. The apparatus according to Clause 11, wherein the first tunable capacitor is digitally programmable and the second tunable capacitor is digitally programmable.

[0134] 13. The apparatus according to any one of clauses 1 to 12, wherein the antenna port is coupled to an antenna.

[0135] 14. The apparatus according to Clause 13, wherein the antenna is in an antenna array.

[0136] 15. The apparatus according to any one of clauses 1 to 14, wherein the second inductor is coupled between the first terminal of the impedance matching circuit and ground.

[0137] 16. The apparatus according to any one of clauses 1 to 15, wherein the power amplifier has a first output and a second output, and the first inductor is coupled between the first output and the second output of the power amplifier.

[0138] 17. The apparatus according to any one of clauses 1 to 16, wherein the one or more capacitors include a first capacitor coupled to the first terminal and a second capacitor coupled to the second terminal.

[0139] 18. The apparatus according to Clause 17, wherein the first capacitor is coupled between the first terminal and ground, and the second capacitor is coupled between the second terminal and the ground.

[0140] 19. An apparatus comprising:

[0141] Power amplifier;

[0142] Low-noise amplifier;

[0143] A first inductor coupled to the power amplifier;

[0144] A second inductor, which is magnetically coupled to the first inductor;

[0145] A third inductor is coupled to the low-noise amplifier, wherein the third inductor is magnetically coupled to the second inductor;

[0146] An impedance matching circuit has a first terminal and a second terminal, wherein the first terminal is coupled to a second inductor and the second terminal is coupled to an antenna port, and the impedance matching circuit includes:

[0147] A fourth inductor coupled between the first terminal and the second terminal; and

[0148] One or more capacitors coupled to the fourth inductor.

[0149] 20. The apparatus according to Clause 19, wherein the fourth inductor includes an 8-shaped conductor path forming the first loop and the second loop.

[0150] 21. The apparatus according to Clause 20, wherein:

[0151] The first inductor includes one or more loops; and

[0152] The first and second loops of the fourth inductor overlap with the regions within one or more loops of the first inductor.

[0153] 22. The apparatus according to clause 20 or 21, wherein:

[0154] The second inductor includes one or more loops; and

[0155] The first and second loops of the fourth inductor overlap with the regions within one or more loops of the second inductor.

[0156] 23. The apparatus according to any one of clauses 20 to 22, wherein:

[0157] The third inductor includes one or more loops; and

[0158] The first and second loops of the fourth inductor overlap with the regions within one or more loops of the third inductor.

[0159] 24. The apparatus according to any one of clauses 20 to 23, wherein the first loop and the second loop of the fourth inductor overlap with the first inductor, the second inductor and the third inductor.

[0160] 25. The apparatus according to any one of clauses 20 to 24, wherein the fourth inductor is configured to generate magnetic flux in the first loop and to generate magnetic flux of opposite polarity in the second loop.

[0161] 26. The device according to any one of clauses 20 to 25, wherein the conductor path comprises a first portion, a second portion, and a bridge, wherein the bridge couples the first portion and the second portion, and the bridge passes through the second portion.

[0162] 27. The apparatus according to Clause 19, wherein the fourth inductor includes a first loop and a second loop.

[0163] 28. The apparatus according to Clause 27, wherein:

[0164] The first inductor includes one or more loops; and

[0165] The first and second loops of the fourth inductor overlap with the regions within one or more loops of the first inductor.

[0166] 29. The apparatus according to clause 27 or 28, wherein:

[0167] The second inductor includes one or more loops; and

[0168] The first and second loops of the fourth inductor overlap with the regions within one or more loops of the second inductor.

[0169] 30. The apparatus according to any one of clauses 27 to 29, wherein:

[0170] The third inductor includes one or more loops; and

[0171] The first and second loops of the fourth inductor overlap with the regions within one or more loops of the third inductor.

[0172] 31. The apparatus according to any one of clauses 27 to 30, wherein the first loop and the second loop of the fourth inductor overlap with the first inductor, the second inductor and the third inductor.

[0173] 32. The apparatus according to any one of clauses 27 to 31, wherein the fourth inductor is configured to generate magnetic flux in the first loop and to generate magnetic flux of opposite polarity in the second loop.

[0174] 33. The apparatus according to any one of clauses 19 to 32, wherein the one or more capacitors comprise a first capacitor having a first tunable capacitance and a second capacitor having a second tunable capacitance.

[0175] 34. The apparatus according to any one of clauses 19 to 33, wherein the antenna port is coupled to an antenna.

[0176] 35. The apparatus according to clause 34, wherein the antenna is in an antenna array.

[0177] 36. The apparatus according to any one of clauses 19 to 35, wherein the second inductor is coupled between the first terminal of the impedance matching circuit and ground.

[0178] 37. The apparatus according to any one of clauses 19 to 36, wherein the third inductor is coupled between the input of the low-noise amplifier and ground.

[0179] 38. The apparatus according to any one of clauses 19 to 37, wherein the power amplifier has a first output and a second output, and the first inductor is coupled between the first output and the second output of the power amplifier.

[0180] 39. The apparatus according to any one of clauses 19 to 38, wherein the one or more capacitors include a first capacitor coupled to the first terminal and a second capacitor coupled to the second terminal.

[0181] 40. The apparatus according to Clause 39, wherein the first capacitor is coupled between the first terminal and ground, and the second capacitor is coupled between the second terminal and the ground.

[0182] 41. A method for antenna tuning, comprising:

[0183] The radio frequency (RF) signal is magnetically coupled from the first inductor to the second inductor;

[0184] The impedance of the antenna as seen at the second inductor is tuned using an impedance matching circuit coupled to the second inductor. The impedance matching circuit includes a third inductor overlapping the first and second inductors, and one or more capacitors coupled to the third inductor.

[0185] The RF signal is propagated from the impedance matching circuit to the antenna.

[0186] 42. The method according to Clause 41, wherein tuning the impedance of the antenna seen at the second inductor includes tuning the capacitance of the one or more capacitors.

[0187] 43. The method according to clause 41 or 42, wherein the third inductor includes a first loop and a second loop, and the method further includes: generating a magnetic flux in the first loop and generating a magnetic flux of opposite polarity in the second loop.

[0188] 44. The method according to any one of clauses 41 to 43, wherein the first loop and the second loop of the third inductor overlap with the regions within the one or more loops of the first inductor.

[0189] 45. The method according to any one of clauses 41 to 44, wherein the first loop and the second loop of the third inductor overlap with the regions within the one or more loops of the second inductor.

[0190] 46. ​​An apparatus comprising:

[0191] Power amplifier;

[0192] A first inductor coupled to the power amplifier;

[0193] A second inductor, which is magnetically coupled to the first inductor;

[0194] An impedance matching circuit has a first terminal and a second terminal, wherein the first terminal is coupled to a second inductor and the second terminal is coupled to an antenna port, and the impedance matching circuit includes:

[0195] A third inductor, magnetically coupled to the first and second inductors, and coupled between the first and second terminals; and

[0196] One or more capacitors coupled to the third inductor.

[0197] 47. An apparatus for antenna tuning, comprising:

[0198] A unit used to magnetically couple radio frequency (RF) signals from a first inductor to a second inductor;

[0199] A unit for tuning the impedance of the antenna as seen at the second inductor, the unit for tuning the antenna impedance including a third inductor overlapping the first inductor and the second inductor; and

[0200] A unit used to propagate the RF signal from a unit used to tune the antenna impedance to a unit of the antenna.

[0201] Within this disclosure, the term "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" is not necessarily to be construed as superior to or more advantageous than other aspects of this disclosure. Similarly, the term "aspect" does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. Unless preceded by the term "magnetically," the term "coupled" is used herein to refer to direct or indirect electrical coupling between two structures. It should also be understood that the term "grounded" can refer to DC ground or AC ground, and therefore the term "grounded" encompasses both possibilities. It should be understood that "input" can be one of a single-ended input, a differential input, or two differential inputs, and "output" can be one of a single-ended output, a differential output, or two differential outputs. The term "approximately" means within 10 percent of the value (i.e., between 90 percent and 110 percent of the value).

[0202] The foregoing description of this disclosure is provided to enable any person skilled in the art to implement or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: Power amplifier; A first inductor, which is coupled to the power amplifier; A second inductor, which is magnetically coupled to the first inductor; An impedance matching circuit has a first terminal and a second terminal, wherein the first terminal is coupled to a second inductor and the second terminal is coupled to an antenna port, and the impedance matching circuit includes: A third inductor, coupled between the first terminal and the second terminal, wherein the third inductor overlaps with the first inductor and the second inductor; and One or more capacitors coupled to the third inductor.

2. The apparatus according to claim 1, wherein, The third inductor includes an 8-shaped conductor path that forms the first loop and the second loop.

3. The apparatus according to claim 1, wherein, The third inductor includes a first loop and a second loop.

4. The apparatus according to claim 3, wherein: The first inductor includes one or more loops; and The first and second loops of the third inductor overlap with the regions within one or more loops of the first inductor.

5. The apparatus according to claim 3, wherein: The second inductor includes one or more loops; and The first and second loops of the third inductor overlap with the regions within one or more loops of the second inductor.

6. The apparatus according to claim 3, wherein, The third inductor is configured to generate magnetic flux in the first loop and magnetic flux with opposite polarity in the second loop.

7. The apparatus according to claim 1, wherein, The one or more capacitors include a first capacitor having a first tunable capacitance and a second capacitor having a second tunable capacitance.

8. The apparatus according to claim 1, wherein, The antenna port is coupled to the antenna.

9. The apparatus according to claim 1, wherein, The second inductor is coupled between the first terminal of the impedance matching circuit and ground.

10. The apparatus according to claim 1, wherein, The power amplifier has a first output and a second output, and the first inductor is coupled between the first output and the second output of the power amplifier.

11. The apparatus according to claim 1, wherein, The one or more capacitors include a first capacitor coupled to the first terminal and a second capacitor coupled to the second terminal.

12. The apparatus according to claim 11, wherein, The first capacitor is coupled between the first terminal and ground, and the second capacitor is coupled between the second terminal and ground.

13. An apparatus comprising: Power amplifier; Low-noise amplifier; A first inductor, which is coupled to the power amplifier; A second inductor, which is magnetically coupled to the first inductor; A third inductor is coupled to the low-noise amplifier, wherein the third inductor is magnetically coupled to the second inductor; An impedance matching circuit has a first terminal and a second terminal, wherein the first terminal is coupled to a second inductor and the second terminal is coupled to an antenna port, and the impedance matching circuit includes: A fourth inductor, coupled between the first terminal and the second terminal; and One or more capacitors coupled to the fourth inductor.

14. The apparatus according to claim 13, wherein, The fourth inductor includes an 8-shaped conductor path forming the first loop and the second loop.

15. The apparatus according to claim 13, wherein, The fourth inductor includes a first loop and a second loop.

16. The apparatus according to claim 15, wherein: The first inductor includes one or more loops; and The first and second loops of the fourth inductor overlap with the regions within one or more loops of the first inductor.

17. The apparatus according to claim 15, wherein: The second inductor includes one or more loops; and The first and second loops of the fourth inductor overlap with the regions within one or more loops of the second inductor.

18. The apparatus according to claim 15, wherein: The third inductor includes one or more loops; and The first and second loops of the fourth inductor overlap with the regions within one or more loops of the third inductor.

19. The apparatus according to claim 15, wherein, The first loop and the second loop of the fourth inductor overlap with the first inductor, the second inductor and the third inductor.

20. The apparatus according to claim 15, wherein, The fourth inductor is configured to generate magnetic flux in the first loop and magnetic flux with opposite polarity in the second loop.

21. The apparatus according to claim 13, wherein, The one or more capacitors include a first capacitor having a first tunable capacitance and a second capacitor having a second tunable capacitance.

22. The apparatus according to claim 13, wherein, The antenna port is coupled to the antenna.

23. The apparatus according to claim 13, wherein, The second inductor is coupled between the first terminal of the impedance matching circuit and ground.

24. The apparatus according to claim 13, wherein, The third inductor is coupled between the input of the low-noise amplifier and ground.

25. The apparatus according to claim 13, wherein, The power amplifier has a first output and a second output, and the first inductor is coupled between the first output and the second output of the power amplifier.

26. The apparatus according to claim 13, wherein, The one or more capacitors include a first capacitor coupled to the first terminal and a second capacitor coupled to the second terminal.

27. The apparatus according to claim 26, wherein, The first capacitor is coupled between the first terminal and ground, and the second capacitor is coupled between the second terminal and ground.

28. A method for antenna tuning, comprising: The radio frequency (RF) signal is magnetically coupled from the first inductor to the second inductor; The impedance of the antenna seen at the second inductor is tuned using an impedance matching circuit coupled to the second inductor, the impedance matching circuit including a third inductor overlapping the first inductor and the second inductor, and one or more capacitors coupled to the third inductor. as well as The RF signal is propagated from the impedance matching circuit to the antenna.

29. The method according to claim 28, wherein, Tuning the impedance of the antenna as seen at the second inductor includes tuning the capacitance of the one or more capacitors.

30. An apparatus comprising: Power amplifier; A first inductor, which is coupled to the power amplifier; A second inductor, which is magnetically coupled to the first inductor; An impedance matching circuit has a first terminal and a second terminal, wherein the first terminal is coupled to a second inductor and the second terminal is coupled to an antenna port, and the impedance matching circuit includes: A third inductor, magnetically coupled to the first and second inductors, and coupled between the first and second terminals; and One or more capacitors coupled to the third inductor.

Images