System, apparatus, method and non-transitory computer-readable storage device for deserialized and serialized data transfer

Abstract

A deserialization method and a serialization method for data transmission between chips involving an arrangement of analog front ends and digital signal processors for the deserialization method and the serialization method are disclosed. According to the present application, the processing in the digital domain may be performed by a chip having a smaller technology node geometry, while the processing in the analog domain may be performed by a chiplet suitable for analog components. And the heat generated by the AFE is isolated from the DSP. In addition, costs associated with development and manufacturing may be reduced.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit and priority of U.S. Nonprovisional Patent Application No. 18 / 124,101, filed March 21, 2023, entitled "Systems, Apparatuses, Methods, and Non-transitive Computer-Readable Storage Devices for De-serializing and Serializing Data Transmission," the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This application relates to modules, systems, and methods for deserializing and serializing data transmission, and more particularly to the arrangement of components of a serializer-deserializer (SerDes) for data transmission. Background Technology

[0004] SerDes is a technology widely used in high-speed communication systems. With the increase in data transmission rates, the demand for SerDes technology has emerged, and traditional parallel communication methods have become insufficient. SerDes technology achieves efficient data transmission over serial communication links by converting parallel data into a serial stream that can be transmitted on a single channel, and then converting the serial data back into parallel form at the receiving end.

[0005] In recent years, with the rise of data-intensive applications such as cloud computing, big data, and the Internet of Things, the demand for SerDes technology has grown exponentially. Therefore, SerDes technology is currently being used in various applications, including high-speed networks, data centers, and consumer electronics.

[0006] Although existing technologies have achieved serialization and deserialization, they are not good in terms of efficiency, cost, and performance. Additional, alternative, and / or improved SerDes technologies would be beneficial. Summary of the Invention

[0007] According to this application, a deserialization method is disclosed, comprising: an analog front end (AFE) receiver receiving an analog signal from a signaling channel in a serial stream; the receiver converting the received analog signal into a digital signal; a digital signal processor (DSP) connected to the AFE via a parallel digital interface processing the converted digital signal from the receiver of the AFE; the DSP transmitting the processed digital signal to a digital core integrated circuit (IC), wherein the DSP and the digital core IC are embedded in a digital core die, the AFE is embedded in a small chip separate from the digital core die, and the deserialization method is executed sequentially in the AFE and the DSP.

[0008] In one embodiment of the deserialization method, the digital core die can be manufactured using a process with a technology node geometry smaller than that of the chiplet.

[0009] In another embodiment of the deserialization method, the AFE and the DSP can form a SerDes.

[0010] According to this application, a serialization method is disclosed, comprising: a DSP receiving a digital signal from a digital core IC; the DSP processing the received digital signal; a transmitter connected to an AFE of the DSP via a parallel digital interface converting the processed digital signal into an analog signal; the transmitter transmitting the converted analog signal to a signaling channel in a serial stream manner, wherein the DSP and the digital core IC are embedded in a digital core die, the AFE is embedded in a small chip separate from the digital core die, and the serialization method is executed sequentially in the DSP and the AFE.

[0011] In one embodiment of the serialization method, the digital core die can be manufactured using a process with a technology node geometry smaller than that of the chiplet.

[0012] In another embodiment of the serialization method, the AFE and the DSP can form a SerDes.

[0013] According to this application, a data transmission module is disclosed, including an analog circuit breaker (AFE) and a digital signal generator (DSP). The AFE includes: a receiver for receiving an input analog signal from a serial stream from a signaling channel and converting the input analog signal into an input digital signal; and a transmitter for converting an output digital signal into an output analog signal and transmitting the output analog signal from the serial stream to the signaling channel. The DSP is connected to the AFE via a parallel digital interface and is used to process the input digital signal from the receiver of the AFE and transmit the processed input digital signal to a digital core IC, or to process the output digital signal from the digital core IC and transmit the processed output digital signal to the transmitter of the AFE. The DSP and the digital core IC are embedded in a digital core die, and the AFE is embedded in a small chip separate from the digital core die.

[0014] In one embodiment of the module, the digital core die can be manufactured using a process with a technology node geometry smaller than that of the chiplet.

[0015] In another embodiment of the module, the module may be SerDes.

[0016] According to this application, a data transmission system is disclosed, comprising: a plurality of chiplets; a digital core die separate from the plurality of chiplets; and a plurality of modules. Each of the plurality of modules includes an analog front-end (AFE) and a digital signal processor (DSP). The AFE includes: a receiver for receiving an input analog signal from a serial stream from a signaling channel and converting the input analog signal into an input digital signal; and a transmitter for converting an output digital signal into an output analog signal and transmitting the output analog signal from the serial stream to the signaling channel. The AFE is embedded in one of the plurality of chiplets. The DSP is connected to the AFE via a parallel digital interface and is used to process the input digital signal from the receiver of the AFE and transmit the processed input digital signal to the digital core IC, or to process the output digital signal from the digital core IC and transmit the processed output digital signal to the transmitter of the AFE. The DSP and the digital core IC are embedded in the digital core die.

[0017] In one embodiment of the system, the digital core die may be manufactured using a process with a technology node geometry smaller than that of the chiplet.

[0018] In another embodiment of the system, each of the plurality of chiplets may include a plurality of AFEs.

[0019] In another embodiment of the system, each of the plurality of modules may be a SerDes, and the digital core IC is a digital processing unit, which includes one of the following: application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), central processing unit (CPU), network processing unit (NPU), graphics processing unit (GPU), tensor processing unit (TPU), or switch fabric unit (SFU).

[0020] In another embodiment of the system, the digital core die and the plurality of chips can be stacked on top of each other.

[0021] In another embodiment of the system, for each of the plurality of modules, the DSP in the digital core die is aligned with the AFE in one of the plurality of chiplets; for each of the plurality of modules, the parallel digital interface between the DSP and the AFE is in the form of through silicon via (TSV), bonded metallization, or a combination thereof.

[0022] In another embodiment of the system, the system may further include a second die, with the plurality of chiplets arranged around the second die; the digital core die is stacked on top of the second die and the plurality of chiplets.

[0023] In another embodiment of the system, the plurality of chips may be arranged in a matrix; the digital core die may be stacked on top of the plurality of chips.

[0024] In another embodiment of the system, the system may further include a printed circuit board (PCB) and an interpolation layer on the PCB, the interpolation layer enabling the serial stream to be routed from the AFE to the signaling channel or from the signaling channel to the AFE via the PCB.

[0025] In another embodiment of the system, the plurality of small chips may be arranged to surround the digital core die.

[0026] In another embodiment of the system, the system may further include a PCB and an interpolation layer on the PCB, the interpolation layer enabling the parallel digital interface to route between the AFE in at least one of the plurality of chiplets and the corresponding DSP in the digital core die.

[0027] According to this application, a non-transitory computer-readable storage device is disclosed, including computer-executable instructions, wherein the instructions, when executed, cause one or more circuits to perform a deserialization method or serialization method as described herein.

[0028] According to embodiments of this application, the arrangement of the AFE and the DSP can be improved so that processing in the digital domain can be performed by a chip with a smaller technology node geometry, while processing in the analog domain can be performed by a small chip suitable for analog components. The heat generated by the AFE is isolated from the DSP. Furthermore, development and manufacturing costs can be reduced. Attached Figure Description

[0029] Other features and advantages of this application will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0030] Figure 1 A block diagram illustrating the arrangement of core ICs and chiplets for serialization and deserialization processes, provided for embodiments of this application;

[0031] Figure 2 A side sectional view of the components describing the arrangement of the AFE and DSP of the SerDes provided for embodiments of this application;

[0032] Figure 3 Provided for embodiments of this application Figure 2 The top sectional view depicting the underlying components as seen from the horizontal plane indicated by the dotted line A-A' in the figure;

[0033] Figure 4 Provided for embodiments of this application Figure 2 The top section view depicting the top-level component as seen from the horizontal plane indicated by the dotted line B-B' in the figure;

[0034] Figure 5 A side sectional view of the components describing the arrangement of the AFE and DSP of the SerDes provided for embodiments of this application;

[0035] Figure 6 Provided for embodiments of this application Figure 5 The top sectional view depicting the underlying components as seen from the horizontal plane indicated by the dotted line A-A' in the figure;

[0036] Figure 7 Provided for embodiments of this application Figure 5 The top section view depicting the top-level component as seen from the horizontal plane indicated by the dotted line B-B' in the figure;

[0037] Figure 8 A side sectional view of the components describing the arrangement of the AFE and DSP of the SerDes provided for embodiments of this application;

[0038] Figure 9 Provided for embodiments of this application Figure 8 The top sectional view of the component as seen from the horizontal plane indicated by the dotted line A-A' in the figure;

[0039] Figure 10 A flowchart of a deserialization method provided for embodiments of this application;

[0040] Figure 11 A flowchart describing a serialization method provided for embodiments of this application. Detailed Implementation

[0041] A serializer-deserializer (SerDes) is an integrated circuit (IC) used to convert parallel data into serial data or vice versa. The term "SerDes" is often used to refer to a transmitter (serializer) and receiver (deserializer) working together as a single IC. Of course, the serializer and deserializer can also be implemented as separate circuits (such as separate ICs).

[0042] SerDes typically include parallel inputs and serial outputs on the transmitter or serializer side, and serial inputs and parallel outputs on the receiver or deserializer side. Parallel data is converted into a serial stream by the transmitter and then transmitted through a signaling channel, such as a conductor (e.g., copper cable) or optical fiber, or any other physical medium for transmitting electrical signals. The receiver receives the serial stream and converts it back into parallel data.

[0043] SerDes can be used in a variety of applications, including high-speed data communications such as Ethernet, SONET / SDH, and PCI Express, as well as video and imaging systems such as HDMI, DisplayPort, and Camera Link.

[0044] The analog front end (AFE) is part of SerDes and is used to perform analog signal processing functions. The AFE is responsible for regulating input / output signals, ensuring that input and output signals are at the correct voltage levels, and maintaining signal integrity on the signaling path. The specific components of the AFE can vary depending on the SerDes design, but it typically includes a transmitter module, a receiver module, a power supply module, and an on-chip termination module.

[0045] The transmitter module is responsible for converting parallel input data into a serial output signal. The transmitter module may include a voltage-controlled oscillator (VCO) and a phase-locked loop (PLL) for generating a serial clock signal, a digital-to-analog converter (DAC) for converting digital signals to analog signals, and a parallel-to-serial converter (P / S) for converting parallel input data into a serial stream.

[0046] The receiver module is responsible for converting serial input signals into parallel output data. The receiver module may include clock and data recovery (CDR) circuitry for extracting clock signals from the input data stream, an analog-to-digital converter (ADC) for converting analog signals to digital signals, a serial-to-parallel converter (S / P) for converting serial input data to parallel output data, and an equalizer circuit.

[0047] The power module is responsible for providing the necessary voltage levels to the AFE and the rest of the SerDes. The on-chip termination module is responsible for matching the impedance of the SerDes to the external transmission lines to minimize reflections and signal loss.

[0048] In SerDes, the digital signal processor (DSP) is a microcontroller or microprocessor specifically designed to perform digital signal processing tasks. In a SerDes system, the DSP is responsible for controlling and monitoring the operation of the SerDes. The DSP can perform tasks such as clock and data recovery, signal equalization, and error correction. The DSP can also be used to monitor the performance of the communication link and adjust SerDes parameters to optimize link performance. Furthermore, by using techniques such as forward error correction (FEC) or interleaving, errors in the transmitted data can be detected and corrected.

[0049] In this application, a chip or chiplet refers to a physically separated die that may include one or more ICs for implementing one or more functions. A chip is a monolithic semiconductor material on which one or more integrated circuits are formed. It includes transistors, diodes, and other components required to perform a specific function or set of functions. On the other hand, a chiplet is a small piece of semiconductor material containing a specific set of transistors, diodes, and other components. Chipslets are designed to be combined with other chiplets to form larger, more complex ICs. Chips that are much larger than chiplets can perform many (or very powerful) functions, and are therefore more expensive, making it difficult to achieve flexibility and scalability. Chipslets are small and typically perform only a few (or simple / less powerful / limited) functions, and are therefore inexpensive, can be easily combined, and have better flexibility and scalability.

[0050] Compared to traditional monolithic ICs, chiplet-based designs offer greater flexibility and scalability because they support the integration of different chiplets with varying functions and / or technologies onto a single package or substrate. This allows for more efficient resource utilization and lower costs. Chipslets can be used to improve system performance and power efficiency by supporting different parts of the system for optimized performance and power characteristics. Chipslets are also more adaptable to different manufacturing processes, which can improve manufacturing yields.

[0051] SerDes can be implemented as chiplets to perform serialization and deserialization processes. These chiplets are designed to combine with other chiplets to form larger, more complex ICs. Compared to traditional single-chip ICs, this approach offers greater flexibility and scalability, more efficient resource utilization, and lower costs.

[0052] SerDes can also be embedded in larger ICs that contain other functional blocks, such as microcontrollers, memory, or other digital logic. This approach supports the integration of multiple functional blocks on a single chip. This type of integration is commonly used in SoC designs, where multiple functional blocks are integrated on a single chip.

[0053] In the semiconductor industry, a technology node, or technology node geometry, refers to the size of the smallest feature that can be manufactured on a chip or chiplet using specific manufacturing processes. As technology advances, the size of features such as electronic components shrinks, resulting in more transistors on a chip, which in turn improves performance and reduces power consumption. Technology node geometries are typically measured in nanometers (nm).

[0054] Technology nodes are closely related to Moore's Law because the regular "node shrinkage" within technology nodes is a key driver of the increase in the number of transistors on a chip and the corresponding increase in computing power. As the feature size of technology nodes decreases, more transistors can be installed on the chip. This can improve performance and reduce power consumption. In recent years, feature sizes have continued to shrink, and the most advanced technology nodes are currently less than five (5) nm.

[0055] SerDes can be implemented as chiplets, which are sequentially connected to another, more powerful IC on the core die. These chiplets can be, for example, a central processing unit (CPU), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), network processing unit (NPU), graphics processing unit (GPU), tensor processing unit (TPU), switch fabric unit (SFU), or any other digital processing unit, for performing digital computations or processing. This arrangement has two main drawbacks. First, when the SerDes' DSP requires heavy processing, the chiplets implementing the SerDes need to be supplemented with even smaller SerDes or host SerDes on both the chiplet and the core die. These host SerDes are typically unaffected by the DSP and are only responsible for transmitting data signals between the chiplet and the core die. This is to achieve high-bandwidth data transmission with a limited number of physical connections between the chiplet and the core die. However, using additional host SerDes leads to wasted area in both chiplets and the core die, reduces IC performance in the core die, and increases manufacturing costs. Secondly, chiplets typically have larger technology node geometries compared to the core die, thus limiting DSP performance in SerDes.

[0056] Alternatively, SerDes can be embedded within the core die. However, this arrangement also has drawbacks. First, a significant area of ​​the core die may be occupied by SerDes, impacting the performance of other circuitry on the core die (e.g., CPU, ASIC, or FPGA). Second, the AFE portion of SerDes typically generates more heat, and the temperature on the core die can be higher compared to an arrangement where SerDes is implemented as a chiplet physically separated from the core die. Furthermore, designing the analog portion of SerDes requires extensive trial and error, and the placement of SerDes within a core die at advanced technology nodes increases development costs. Additionally, the analog portion of SerDes is generally unsuitable for embedding in chips designed for digital processing.

[0057] Figure 1 The arrangement of core ICs and chiplets for serialization and deserialization processes provided by embodiments of this application is described. System 100 is a standalone electronic component provided by embodiments of this application, typically packaged in a package as an IC chip. Typically, such an electronic component is electrically connected to other electronic components to exchange data, thereby enabling the performance of complex operations. For example, System 100 may have the functionality of an ASIC module, capable of connecting to other modules to form a powerful computing or processing component.

[0058] In this embodiment, system 100 includes a digital core die 110 and a chiplet 120 connected to the digital core die 110. This connection supports digital data transfer between the digital core die 110 and the chiplet 120. A “die” refers to a monolithic semiconductor material, such as silicon, on which an integrated circuit is fabricated. The IC manufacturing process involves depositing various material layers and patterns on a flat semiconductor material (die) and then dicing it into individual segments, each segment containing at least one complete IC. For example, the digital core die 110 in this embodiment can constitute a monolithic IC. Therefore, the technology node geometry is constant on the same digital core die, and smaller technology node geometries, such as five (5) nm, four (4) nm, three (3) nm, or smaller, generally perform well in digital applications due to higher density and lower power consumption. On the other hand, the chiplet 120 is a single component physically separate from the digital core die 110, thus allowing the use of older technologies for components embedded in the chiplet 120.

[0059] The digital core die 110 includes a core IC 111 and a DSP 112 connected to the core IC 111. In this example, the core IC 111 is used for digital processing and can be in the form of an ASIC or an FPGA. The DSP 112, embedded in the same digital core die 110 as the core IC 111, is used to process signals received from chiplet 120. Chiplet 120 includes a receiver 121 and a transmitter 122. In this embodiment, the combination of DSP 112 (embedded in the digital core die 110) and receiver 121 and transmitter 122 (embedded in chiplet 120) serves as a SerDes. DSP 112 serves as the DSP of the SerDes, and receiver 121 and transmitter 122 serve as the AFE of the SerDes.

[0060] Upon receiving a signal for processing by the core IC 111, the receiver 121 first receives the analog signal from an external chip (not shown) via signaling channel 140. After necessary processing, such as analog-to-digital conversion occurring in chip 120, the digital signal is output to the DSP 112 via parallel digital interface 130. Therefore, the DSP 112 can perform tasks such as clock and data recovery, signal equalization, and error correction on the digital signal. After the DSP 112 performs these tasks, the processed digital signal is transmitted to the core IC 111 via internal connection 113.

[0061] When a signal processed by the core IC 111 needs to be transmitted to an external chip (not shown), the DSP 112 receives the digital signal from the core IC 111 via internal connection 113, and then performs tasks such as pre-distortion processing of the digital signal to compensate for possible losses during analog transmission. The digital signal is then output to the transmitter 122 embedded in the chiplet 120 via the parallel digital interface 130. Before the converted signal is finally output as a serial stream through the signaling channel 140, the transmitter 122 performs necessary processing, such as digital-to-analog conversion.

[0062] In this embodiment, receiver 121 and DSP 112 form the receive path of the SerDes, and DSP 112 and transmitter 122 form the transmit path of the SerDes. DSP 112 is physically located separately from receiver 121 and transmitter 122, allowing it to be embedded in the same chip as the core IC 111, utilizing a smaller technology node geometry for digital processing. Therefore, compared to a scenario where both the DSP and AFE are embedded in the same chiplet, the DSP 112 utilizes a more advanced chip, resulting in faster processing speeds and lower heat generation. Independent embedding of the AFE in the chiplet is also advantageous, as analog circuit designs typically require higher currents, leading to higher temperatures within the chiplet. This arrangement of separating the AFE from the DSP minimizes heat radiation towards the digital core die 110. Furthermore, AFE design requires significant trial and error, so a chiplet containing only the analog portion of the SerDes offers the advantage of significantly reduced design costs. Additionally, the chiplet can utilize a larger technology node geometry, which significantly reduces costs compared to the smaller technology node geometries used for manufacturing digital circuits. Compared to conventional methods, all the above results give advantages to the embodiments of this application, in which the analog portion (i.e., AFE) and digital portion (i.e., DSP) of the SerDes are embedded in a single chip / chiplet.

[0063] Figure 2 A side sectional view of the components describing the arrangement of the AFE and DSP of the SerDes provided for embodiments of this application. Figure 3 For this embodiment, from Figure 2 The top section view depicting the underlying components is shown on the horizontal plane indicated by the dotted line A-A'. Figure 4 For this embodiment, from Figure 2 The top section view depicting the top-level component, as seen from the horizontal plane indicated by the dotted line B-B'; in the following text, Figures 2 to 4 Together they are described to illustrate the working principle and application concept of this embodiment.

[0064] like Figure 2 As shown, component 200 according to an embodiment of this application relates to three-dimensional (3D) stacking. 3D stacking is a technique for vertically stacking two or more layers of ICs to increase the amount of available space. By stacking multiple layers, chip designers can achieve higher performance and integration density than traditional two-dimensional (2D) architectures. This technique also helps to reduce chip size and lower power consumption by enabling shorter interconnects between different layers.

[0065] In this embodiment, the top layer having the first digital core die 210 is stacked on top of the bottom layer having the second die 220 and a plurality of chiplets 250 surrounding the second die 220, as shown below. Figure 3 As shown. The first digital core die 210 may be a single chip having a core IC (not shown) and a plurality of DSPs 211 embedded therein. The core IC is connected to the plurality of DSPs 211 via internal interconnects (not shown) for digital processing of signals received from the DSPs 211. The second die 220 may be a single chip having another IC (not shown) embedded therein for another operation. Each chiplet in the chiplet 250 includes at least one AFE 251 embedded therein. At least one AFE 251 in one chiplet of the chiplet 250 may be aligned with a corresponding DSP of one of the DSPs 211 embedded in the first digital core die 210, such as Figures 2 to 4 As shown, this is to achieve a short path between one AFE in AFE251 and the corresponding DSP 211.

[0066] The parallel digital interface 203 between the top layer of the first digital core die 210, the bottom layer of the second die 220, and the multiple chiplets 250 can take various suitable forms, such as through-silicon vias (TSVs), interpolation layers, and / or bonding metallization, for high-bandwidth digital data transmission. The required bandwidth is determined by the application. For example, in high-speed optical communication, data rates can range from several Gbps to 100 Gbps or even higher, requiring corresponding bandwidth. A TSV is a cylindrical hole drilled into a silicon wafer to connect different layers in a stack. Interpolation layers are thin layers of insulating material placed between different layers in a stack. They contain metal wires that serve as electrical interconnects between layers and are filled with metal conductors to provide electrical connections between layers. Bond metallization can be achieved through microbumps. Microbumps are small bumps made of metals such as copper, formed on the surface of each layer, and serve as interconnects between layers. It should be understood that, although... Figure 2 The parallel digital interface 203 in the example shown uses a microbump design, but other forms of connection are also easily implemented. TSV can also be used in this example to electrically connect the bottom of the first digital core die 210 to the AFE 251 located at the bottom of the chiplet 250.

[0067] A stack comprising a first digital core die 210, a second die 220, and a plurality of chiplets 250 is fixed on a substrate 230. The substrate 230 can be an organic or inorganic substrate, which facilitates signal routing into or out of the stack. The chips or silicon dies can be attached to the substrate in various ways. For example, wire bonding can be used, involving attaching metal wires to pads on the silicon die and to the substrate using processes called ball bonding or wedge bonding. Alternatively, flip-chip bonding can be used, involving directly attaching pads on the silicon die to the substrate using a layer of metal bumps. In this embodiment, the secondary interconnect 202 is located between the bottom of the plurality of chiplets 250 and the top of the substrate 230 in the form of flip-chip bonding, but it should be understood that other forms of connection are also readily achievable.

[0068] The stack and substrate 230 are packaged into package 240. As an independent electronic device, package 240 can be further connected to printed circuit board (PCB) 260 via bonding methods such as flip-chip bonding or surface-mount technology (SMT). These methods refer to placing the package on the surface of the PCB and directly soldering it to pads on the PCB. In this embodiment, the primary interconnect 201 is located between the bottom of substrate 230 and the top of PCB 260 in the form of flip-chip bonding; however, it should be understood that other forms of connection are also easily implemented. When the package is mounted on PCB 260, a route from AFE 251 in chiplet 250 to the signaling channel (not shown) is formed through the primary interconnect 201, secondary interconnect 202, and traces (not shown) within substrate 230 and PCB 260. Input / output (I / O) routing is... Figure 2 The dashed lines are used to represent this schematically.

[0069] When component 200 is used for the deserialization process, it receives the input analog signal from the signaling channel on the receiver side of AFE 251 and converts the analog signal received by the receiver of AFE 251 into a digital signal. The deserialization process is performed sequentially in one or more AFE 251s and one or more DSP 211s. The analog-to-digital conversion can be performed by the internal ADC module in AFE 251, so the output of AFE 251 for the input signal is in the digital domain. After the signal is transmitted to DSP 211 (embedded in the first digital core die 210) through parallel digital interface 203, DSP 211 processes the signal by performing tasks such as clock and data recovery, signal equalization, and error correction. Then, the processed digital signal is transmitted through internal connections to the core IC in the same first digital core die 210.

[0070] When component 200 is used for the serialization process, it receives the output digital signal from the core IC in the same first digital core die 210 and processes the received signal, for example, by pre-distorting the signal to compensate for potential losses during data transmission in the analog domain. The serialization process is performed sequentially in one or more DSPs 211 and one or more AFEs 251. After the signal is transmitted to the AFE 251 (embedded in chiplet 250) via parallel digital interface 203, the DAC in the AFE 251 converts the processed digital signal into an analog signal. The converted analog signal is then transmitted as a serial stream to the signaling channel and finally to an external electronic device located locally or remotely relative to component 200.

[0071] In this embodiment, the AFE 251 in chiplet 250 and the DSP 211 in the first digital core die 210 are physically separated and connected via a parallel digital interface 203. The first digital core die 210 is typically manufactured using a process with a smaller technology node geometry than that of chiplet 250. Typically, the technology node geometry of the first digital core die 210 can be 5 nm, 4 nm, 3 nm, or smaller, while the technology node geometry of the chiplet can be 7 nm, 8 nm, or larger. This approach avoids embedding the AFE and DSP in the same chip or chiplet, thus enabling a more advantageous arrangement of the AFE and DSP within the SerDes. Therefore, the analog and digital domains of a single SerDes are separated, with the AFE utilizing older, lower-cost, and lower-density technologies better suited to the analog domain, and the DSP utilizing more advanced digital processing technologies. Furthermore, the heat generated by the AFE, which typically degrades DSP performance, is essentially isolated through physical separation.

[0072] It should be understood that, despite Figure 2 The diagram shows a first digital core die 210 on top of a second die 220 and a plurality of chiplets 250, but in some other embodiments, the first digital core die may be placed below the second die 220 and the plurality of chiplets 250. There may be one or more additional layers in the stack for additional one or more functions. Furthermore, although in Figures 2 to 4 The diagram shows AFE 251 and DSP 211 placed in the outer periphery of their respective layers, but AFE 251 and DSP 211 can also be placed in different locations.

[0073] Figure 5 A side sectional view of the components describing the arrangement of the AFE and DSP of the SerDes, provided for another embodiment of this application. Figure 6 For this embodiment, from Figure 5 The top section view depicting the underlying components is shown on the horizontal plane indicated by the dotted line A-A'. Figure 7 For this embodiment, from Figure 5 The dotted-line B-B' in the figure shows a top section view depicting the top-level component on the horizontal plane indicated by the horizontal plane. In the following text, Figures 5 to 7 Together they are described to illustrate the working principle and application concept of this embodiment.

[0074] like Figure 5 As shown, component 300 according to another embodiment of this application relates to 3D stacking. In this embodiment, a digital core die 310 is stacked on top of a plurality of chiplets 350 distributed in a matrix, as... Figure 6 As shown. The digital core die 310 can be a single chip having a core IC (not shown) and multiple DSPs 311 embedded therein. The core IC is connected to the multiple DSPs 311 via internal connections (not shown) for digital processing of signals received from the DSPs 311. Each chiplet 350 includes at least one AFE 351 embedded therein. At least one AFE 351 of one chiplet 350 can be aligned with a corresponding DSP of one of the DSPs 311 embedded in the digital core die 310, such as... Figures 5 to 7 As shown, this is to achieve a short path between one AFE in AFE 351 and the corresponding DSP 311.

[0075] The parallel digital interface 304 between the digital core die 310 and the multiple chiplets 350 can take various suitable forms, such as through-silicon vias (TSVs), interpolation layers, and / or bonded metallization, for high-bandwidth digital data transmission. The required bandwidth is determined by the application. For example, in high-speed optical communication, data rates can range from several Gbps to 100 Gbps or even higher, requiring corresponding bandwidth. It should be understood that, although... Figure 5 The parallel digital interface 304 in the example shown uses microbumps, but other forms of connection are also easily implemented. TSV can also be used in this example to electrically connect the bottom of the digital core die 310 to the AFE 351 located at the bottom of the chiplet 350.

[0076] A stack including a digital core die 310 and multiple chiplets 350 is fixed on an interpolation layer 320, which in turn is fixed on a substrate 330. The interpolation layer 320 is a thin layer of insulating material containing metal wires that serve as electrical interconnects between the matrix of chiplets 350 and the substrate 330. The interpolation layer 320 is also filled with metal conductors to form electrical connections between the matrix of chiplets 350 and the substrate 330. The substrate 330 can be an organic or inorganic substrate, which facilitates signal routing into or out of the stack. In this embodiment, a tertiary interconnect 303 is located between the bottom of the multiple chiplets 350 and the top of the interpolation layer 320, and a secondary interconnect 302 is located between the bottom of the interpolation layer 320 and the top of the substrate 330, both using flip-chip bonding. However, it should be understood that other forms of interconnection are also easily implemented.

[0077] The stack of a digital core die 310 and multiple chiplets 350, an interpolation layer 320, and a substrate 230 are packaged into a package 340 as a separate electronic device that can be further connected to a PCB 360 via bonding methods such as flip-chip bonding or SMT. In this embodiment, the primary interconnect 301 is located between the bottom of the substrate 330 and the top of the PCB 360 in the form of flip-chip bonding, but it should be understood that other forms of connection are also readily achievable. When the package is mounted on the PCB 360, a route from the AFE 351 in the chiplet 350 to the signaling channel (not shown) is formed through the primary interconnect 301, secondary interconnect 302, tertiary interconnect 303, and traces (not shown) in the interpolation layer 320, substrate 330, and PCB 360. Input / output (I / O) routing is... Figure 5 The dashed lines are used to represent this schematically.

[0078] When component 300 is used for the deserialization process, it receives the input analog signal from the signaling channel on the receiver side of AFE 351 and converts the analog signal received by the receiver of AFE 351 into a digital signal. The deserialization process is performed sequentially in one or more AFE 351s and one or more DSP 311s. The analog-to-digital conversion can be performed by the internal ADC module in AFE 351, so the output of AFE 351 for the input signal is in the digital domain. After the signal is transmitted to DSP 311 (embedded in digital core die 310) through parallel digital interface 304, DSP 311 processes the signal by performing tasks such as clock and data recovery, signal equalization, and error correction. Then, the processed digital signal is transmitted through internal connections to the core IC in the same digital core die 310.

[0079] When component 300 is used for the serialization process, it receives the output digital signal from the core IC in the same digital core die 310 and processes the received signal, for example, by pre-distorting the signal to compensate for potential losses during data transmission in the analog domain. The serialization process is performed sequentially in one or more DSPs 311 and one or more AFEs 351. After the signal is transmitted to the AFE 351 (embedded in chiplet 350) via parallel digital interface 303, the DAC in the AFE 351 converts the processed digital signal into an analog signal. The converted analog signal is then transmitted as a serial stream to the signaling channel and finally to an external electronic device located locally or remotely relative to component 300.

[0080] In this embodiment, the AFE 351 in the chiplet 350 and the DSP 311 in the digital core die 310 are physically separated and connected via a parallel digital interface 304. The digital core die 310 is typically manufactured using a process with a smaller technology node geometry than the chiplet 350. Typically, the technology node geometry of the digital core die 310 can be 5 nm, 4 nm, 3 nm, or smaller, while the technology node geometry of the chiplet can be 7 nm, 8 nm, or larger. This approach avoids embedding the AFE and DSP in the same chip or chiplet, thus enabling a more advantageous arrangement of the AFE and DSP within the SerDes. Therefore, the analog and digital domains of a single SerDes are separated, with the AFE utilizing older, lower-cost, and lower-density technologies better suited to the analog domain, and the DSP utilizing more advanced digital processing technologies. Furthermore, the heat generated by the AFE, which typically degrades DSP performance, is essentially isolated through physical separation.

[0081] It should be understood that, despite Figure 5 The diagram shows a digital core die 310 on top of multiple chiplets 350, but in some other embodiments, the digital core die may be placed below the multiple chiplets 350. There may be one or more additional layers in the stack for additional one or more functions. Furthermore, although in Figures 5 to 7 The diagram shows the AFE 351 and DSP 311 placed in their respective layers in a matrix form, but the AFE 351 and DSP 311 can also be placed in different forms.

[0082] Figure 8 A side sectional view of the components describing the arrangement of the AFE and DSP of the SerDes, provided for yet another embodiment of this application. Figure 9 For this embodiment, from Figure 8 The top section view of the component as seen from the horizontal plane indicated by the dashed line A-A'. In the following text, Figure 8 and Figure 9Together they are described to illustrate the working principle and application concept of this embodiment.

[0083] like Figure 8 As shown, component 400 according to another embodiment of this application relates to 2.5D stacking. "2.5D stacking" refers to stacking semiconductor dies in a package, with interconnections between the dies achieved through a system of microbumps and interpolation layers, rather than traditional wire bonding. In this embodiment, the digital core die 410 is surrounded by a plurality of main chiplets 450 and a plurality of auxiliary chiplets 460, as... Figure 9 As shown. The digital core die 410 can be a single chip having a core IC (not shown) and multiple DSPs 411 embedded therein. The core IC is connected to the multiple DSPs 411 via internal connections (not shown) for digital processing of signals received from the DSPs 411. Each chiplet in the main chiplet 450 includes at least one main AFE 451 embedded therein, and each auxiliary chiplet in the auxiliary chiplet 460 includes at least one auxiliary AFE 461 embedded therein.

[0084] The interconnection between the digital core die 410 and the main chiplet 450 or auxiliary chiplet 460 can employ various suitable forms for high-bandwidth digital data transmission. For example, such as... Figure 8 As shown, the digital core die 410 and the auxiliary chiplet 460 are located on an interpolation layer 420, which includes traces supporting digital data transfer between the DSP 411 and the auxiliary AFE 451 with sufficiently high bandwidth. The interpolation layer 420 and the main chiplet 450 are located on a substrate 430, which also includes traces supporting digital data transfer between the DSP 411 and the main AFE 461 with sufficiently high bandwidth. It should be understood that... Figure 8 In the example shown, although microbumps are used for the secondary interconnect 402 between the substrate 430 and the interpolation layer 420, the main parallel digital interface 403 between the main chiplet 450 and the substrate 430, the auxiliary parallel digital interface 404 between the auxiliary chiplet 460 and the interpolation layer 420, and the core parallel digital interface 405 between the digital core die 410 and the interpolation layer 420, other forms of connections are also easily implemented.

[0085] Substrate 430 can be an organic or inorganic substrate, which facilitates signal routing into or out of the main AFE 451 or auxiliary AFE 461. In this embodiment, the secondary interconnect 402 is located between the bottom of the interpolation layer 420 and the top of the substrate 430 in the form of flip-chip bonding, but it should be understood that other forms of interconnection are also readily achievable.

[0086] The digital core die 410, interpolation layer 420, main chiplet 450, and auxiliary chiplet 460 are packaged as independent electronic devices in a package 440, which can be further connected to a PCB 470 via flip-chip bonding or SMT bonding methods. In this embodiment, the primary interconnect 401 is located between the bottom of the substrate 430 and the top of the PCB 470 in the form of flip-chip bonding, but it should be understood that other forms of connection are also easily implemented. When the package is mounted on the PCB 470, a route is formed from the main AFE 451 and auxiliary AFE 461 in the main chiplet 450 and auxiliary chiplet 460 to the signaling channel (not shown) through the primary interconnect 401, secondary interconnect 402, main parallel digital interface 403, auxiliary parallel digital interface 404, and traces (not shown) within the interpolation layer 420, substrate 430, and PCB 470.

[0087] When component 400 is used for the deserialization process, it receives the input analog signal from the signaling channel on the receiver side of at least one of the main AFE 451 and auxiliary AFE 461, and converts the received analog signal into a digital signal. The deserialization process is performed sequentially in one or more main AFEs 451 and auxiliary AFEs 461 and one or more DSPs 411. The analog-to-digital conversion can be performed by the internal ADC modules in the main AFEs 451 and auxiliary AFEs 461, so the outputs of the main AFEs 451 and auxiliary AFEs 461 to the input signal are in the digital domain. After the signal is transmitted to the DSP 411 embedded in the digital core die 410, the DSP 411 processes the signal by performing tasks such as clock and data recovery, signal equalization, and error correction. The processed digital signal is then transmitted to the core IC in the same digital core die 410 via internal connections.

[0088] When component 400 is used for the serialization process, it receives the output digital signal from the core IC in the same digital core die 410 and processes the received signal, for example, by pre-distorting the signal to compensate for potential losses during data transmission in the analog domain. The serialization process is performed sequentially in one or more DSPs 411 and one or more main AFEs 451 and auxiliary AFEs 461. After the signal is transmitted to the main AFEs 451 and auxiliary AFEs 461 embedded in the main chiplet 450 and auxiliary chiplet 460, the DACs in the main AFEs 451 and auxiliary AFEs 461 convert the processed digital signal into an analog signal. The converted analog signal is then transmitted as a serial stream to the signaling channel and finally to an external electronic device located locally or remotely relative to component 400.

[0089] In this embodiment, the main AFE 451 and auxiliary AFE 461 (located in the main chiplet 450 and auxiliary chiplet 460, respectively) and the DSP 411 (located in the digital core die 410) are physically separated. The digital core die 410 can typically be manufactured using a process with a smaller technology node geometry than that of the main chiplet 450 and auxiliary chiplet 460. Typically, the technology node geometry of the digital core die 410 can be 5 nm, 4 nm, 3 nm, or smaller, while the technology node geometry of the chiplets 450 and 460 can be 7 nm, 8 nm, or larger. This approach avoids embedding the AFE and DSP in the same chip or chiplet, thus enabling a favorable arrangement of the AFE and DSP in the SerDes. Therefore, the analog and digital domains of a single SerDes are separated, with the AFE utilizing older, lower-cost, and lower-density technologies that are better suited to the analog domain, and the DSP utilizing more advanced digital processing technologies. Furthermore, the heat generated by the AFE, which typically degrades DSP performance, is essentially isolated through physical separation.

[0090] It should be understood that, despite Figure 8 The illustration shows some small chips placed on an interpolation layer with a digital core die, while other small chips are placed on a substrate. However, in some other embodiments, all small chips may be placed on the interpolation layer. Alternatively, all small chips and the digital core die may be placed on the substrate without using an interpolation layer. One or more chips or small chips may be additionally placed or stacked for one or more additional functions.

[0091] Figure 10 A flowchart describing a deserialization method 500 provided for embodiments of this application is shown. According to the embodiments presented herein, the deserialization method 500 can be performed in one or more AFEs and one or more DSPs. The deserialization method 500 begins at step 501: the receiver of the AFE receives an analog signal from a signaling channel in a serial stream. Then, in step 502, the method 500 includes a process where the receiver converts the received analog signal into a digital signal. In step 503, the method 500 includes a process where a DSP connected to the AFE via a parallel digital interface processes the converted digital signal from the receiver of the AFE. Finally, the method 500 ends at step 504: the DSP transmits the processed digital signal to a digital core IC. For the deserialization method 500 according to this application, the DSP and digital core IC are embedded in a digital core die, and the AFE is embedded in a chiplet separate from the digital core die.

[0092] Figure 11A flowchart describing a serialization method 600 provided for embodiments of this application is shown. According to the embodiments provided herein, the serialization method 600 can be executed in one or more DSPs and one or more AFEs. The serialization method 600 begins at step 601: the DSP receives a digital signal from a digital core IC. Then, in step 602, the method 600 includes a process where the DSP processes the received digital signal. In step 603, the method 600 includes a process where a transmitter of the AFE connected to the DSP via a parallel digital interface converts the processed digital signal into an analog signal. Finally, the method 600 ends at step 604: the transmitter transmits the converted analog signal in the serial stream to a signaling channel. For the deserialization method 600 according to this application, the DSP and digital core IC are embedded in the digital core die, and the AFE is embedded in a chiplet separate from the digital core die.

[0093] Those skilled in the art will understand that Figures 1 to 11 The modules, systems, and components shown may include components not shown in the figures. For the sake of simplicity and clarity, the elements in the figures are not necessarily to scale, but are merely schematic and not intended to limit the structure of the elements. It will be apparent to those skilled in the art that many variations and modifications can be made without departing from the scope of this specification.

[0094] The foregoing description of embodiments, with reference to processes, sequences, and block diagrams of methods, apparatuses, systems, and computer program products, illustrates the architecture, functionality, and operation of various embodiments. For example, each block of the processes and block diagrams, and each operation in the sequence diagrams, may represent a module, segment, or portion of code comprising one or more executable instructions for implementing one or more specified actions. In some alternative embodiments, the execution order of one or more actions marked in the block or operation may differ from the order marked in those diagrams. For example, in some embodiments, two blocks or operations shown consecutively may be executed nearly simultaneously, or sometimes, blocks or operations may be executed in reverse order, depending on the functionality involved. Some specific examples have been mentioned above, but these examples are not necessarily the only examples. Each block of the processes and block diagrams, and each operation in the sequence diagrams, as well as combinations of these blocks and operations, may be implemented by a dedicated hardware-based system performing the specified function or action, or by a combination of dedicated hardware and computer instructions.

[0095] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. Therefore, the singular forms “a” and “described” as used herein are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term “comprising” as used herein indicates the presence of one or more features, integers, steps, operations, elements, and components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and combinations. The use of directional terms such as “top,” “bottom,” “up,” “down,” “vertical,” and “lateral” in the following description is for the purpose of providing relative reference only and is not intended to suggest how any item should be positioned during use, how it should be installed in an assembly, or any limitations relative to the environment. Furthermore, unless otherwise stated, the term “connect” and its variations, such as “connected,” “connects,” and “connecting,” as used herein are intended to include both indirect and direct connections. For example, if a first device is connected to a second device, the coupling can be via a direct connection or an indirect connection via other devices and connections. Similarly, if a first device is communicatively connected to a second device, the communication can be via a direct connection or an indirect connection via other devices and connections. Then, when the terms “approximately” and “about” are used in relation to numerical values, they are intended to include a variation of plus or minus 10% of the number.

[0096] The use of “at least one of X, Y, and Z,” “at least one of X, Y, or Z,” “at least one or more of X, Y, and Z,” “at least one or more of X, Y, and / or Z,” or “at least one of X, Y, and / or Z” is intended to include a single item (e.g., only X, or only Y, or only Z) and multiple items (e.g., {X and Y}, {X and Z}, {Y and Z}, or {X, Y, and Z}). The phrase “at least one” and similar phrases are not intended to convey the requirement that every possible item must exist, although every possible item may exist.

[0097] It is conceivable that any aspect or any part of any embodiment discussed in this specification may be implemented or combined with any other aspect or any part of any embodiment discussed in this specification, provided that such parts are not mutually exclusive.

[0098] While every effort has been made to provide a detailed and accurate description of the disclosure herein, it should be noted that the scope of this disclosure is not limited to the exact configurations and embodiments described. The description provided is intended to illustrate the principles of this application and not to limit it to the specific embodiments shown. The scope of this application is defined by the appended claims, their equivalents, and their potential applications in other fields.

Claims

1. A deserialization method, characterized in that, include: The receiver of the analog front end (AFE) receives analog signals from the serial stream through the signaling channel; The receiver converts the received analog signal into a digital signal; The digital signal processor (DSP) connected to the AFE via a parallel digital interface processes the converted digital signal from the receiver of the AFE. The DSP transmits the processed digital signal to the integrated circuit (IC). The DSP and the digital core IC are embedded in the digital core die, and the AFE is embedded in a small chip separate from the digital core die. The deserialization method is executed sequentially in the AFE and the DSP.

2. The deserialization method according to claim 1, characterized in that, The digital core die is manufactured using a process with a smaller technology node geometry than the chip's technology node geometry.

3. The deserialization method according to claim 1 or 2, characterized in that, The AFE and the DSP form a serializer-deserializer (SerDes).

4. A serialization method, characterized in that, include: A digital signal processor (DSP) receives digital signals from a digital core integrated circuit (IC). The DSP processes the received digital signal; The transmitter, connected to the analog front end (AFE) of the DSP via a parallel digital interface, converts the processed digital signal into an analog signal. The transmitter transmits the converted analog signal from the serial stream to the signaling channel. The DSP and the digital core IC are embedded in the digital core die, and the AFE is embedded in a small chip separate from the digital core die. The serialization method is executed sequentially in the DSP and the AFE.

5. The serialization method according to claim 4, characterized in that, The digital core die is manufactured using a process with a smaller technology node geometry than the chip's technology node geometry.

6. The serialization method according to claim 4 or 5, characterized in that, The AFE and the DSP form a serializer-deserializer (SerDes).

7. A data transmission module, characterized in that, include: An analog front end (AFE) includes: a receiver for receiving an input analog signal from a serial stream from a signaling channel and converting the input analog signal into an input digital signal; and a transmitter for converting an output digital signal into an output analog signal and transmitting the output analog signal from the serial stream to the signaling channel. A digital signal processor (DSP), connected to the AFE via a parallel digital interface, is used to process the input digital signal from the receiver of the AFE and transmit the processed input digital signal to the integrated circuit (IC), or to process the output digital signal from the IC and transmit the processed output digital signal to the transmitter of the AFE. The DSP and the digital core IC are embedded in the digital core die, while the AFE is embedded in a small chip separate from the digital core die.

8. The module according to claim 7, characterized in that, The digital core die is manufactured using a process with a smaller technology node geometry than the chip's technology node geometry.

9. The module according to claim 7 or 8, characterized in that, The module is a serializer-deserializer (SerDes).

10. A data transmission system, characterized in that, include: Multiple small chips; The digital core die is separate from the plurality of small chips; Multiple modules, each module includes: An analog front end (AFE) includes: a receiver for receiving an input analog signal from a serial stream from a signaling channel and converting the input analog signal into an input digital signal; and a transmitter for converting an output digital signal into an output analog signal and transmitting the output analog signal from the serial stream to the signaling channel. The AFE is embedded in one of the plurality of chiplets. A digital signal processor (DSP) is connected to the AFE via a parallel digital interface. It is used to process the input digital signal from the receiver of the AFE and transmit the processed input digital signal to the integrated circuit (IC), or to process the output digital signal from the IC and transmit the processed output digital signal to the transmitter of the AFE. The DSP and the IC are embedded in the IC die.

11. The system according to claim 10, characterized in that, The digital core die is manufactured using a process with a smaller technology node geometry than the chip's technology node geometry.

12. The system according to claim 10 or 11, characterized in that, Each of the plurality of chiplets includes a plurality of AFEs.

13. The system according to claim 10, characterized in that, Each of the plurality of modules is a serializer-deserializer (SerDes), and the digital core IC is a digital processing unit, including one of the following: application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), central processing unit (CPU), network processing unit (NPU), graphics processing unit (GPU), tensor processing unit (TPU), or switch fabric unit (SFU).

14. The system according to claim 10 or 11, characterized in that, The digital core die and the multiple small chips are stacked on top of each other.

15. The system according to claim 14, characterized in that, For each of the plurality of modules, the DSP in the digital core die is aligned with the AFE in one of the plurality of chiplets; For each of the plurality of modules, the parallel digital interface between the DSP and the AFE is in the form of through silicon via (TSV), bonded metallization, or a combination thereof.

16. The system according to claim 15, characterized in that, The system also includes a second die, with the plurality of small chips arranged around the second die; The digital core die is stacked on top of the second die and the plurality of small chips.

17. The system according to claim 15 or 16, characterized in that, The multiple small chips are arranged in a matrix; The digital core die is stacked on top of the multiple small chips.

18. The system according to claim 17, characterized in that, It also includes a printed circuit board (PCB) and an interpolation layer on the PCB, the interpolation layer enabling the serial stream to be routed from the AFE to the signaling channel or from the signaling channel to the AFE via the PCB.

19. The system according to claim 15 or 16, characterized in that, The plurality of small chips are arranged around the digital core die.

20. The system according to claim 19, characterized in that, It also includes a PCB and an interpolation layer on the PCB, the interpolation layer enabling the parallel digital interface to route between the AFE in at least one of the plurality of chiplets and the corresponding DSP in the digital core die.

21. A non-transitory computer-readable storage device, characterized in that, It includes computer-executable instructions that, when executed, cause one or more circuits to perform the method according to any one of claims 1 to 6.

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