Imaging device

Abstract

[Problem] To provide an imaging device capable of suppressing more noise. [Solution] This imaging device is provided with: a plurality of photoelectric conversion elements that are arranged in a first direction and a second direction that intersect each other, and that respectively store charges corresponding to the amount of incident light; a plurality of pixel circuits that respectively generate analog pixel signals corresponding to the charges stored in the plurality of photoelectric conversion elements; a signal line that transmits the analog pixel signals output from the two or more pixel circuits arranged in the second direction; and a clipping circuit that clips a voltage of the signal line to a predetermined lower limit voltage level using a power supply voltage line of any one of the two or more pixel circuits connected to the signal line.

Description

Technical Field

[0001] This invention relates to a camera device. Background Technology

[0002] Imaging devices that perform imaging using a rolling shutter method have a stacked structure that bonds multiple semiconductor dies, a technique known to exist (see Patent Document 1). Patent Document 1 discloses an image sensor device constructed using a three-layer substrate comprising a first semiconductor die, a second semiconductor die, and a third semiconductor die. In Patent Document 1, the comparator in the AD conversion circuit is divided into a first part and a second part, the first part being formed on the first semiconductor die together with a photodetector, and the second part being formed on the second semiconductor die. List of cited references Patent documents

[0003] Patent Document 1: U.S. Patent Application Publication No. 2020 / 0258926 Summary of the Invention The technical problem that the invention aims to solve

[0004] Pixel signals in the imaging device are supplied to the analog-to-digital (AD) converter circuit via vertical signal lines over a distance of at most from one end of the pixel array in the column direction to the other. The pixel signals transmitted via the vertical signal lines are analog signals, have a wide signal bandwidth, and are susceptible to noise.

[0005] Patent Document 1 discloses a structure in which a digital pixel is composed of a photodetector, a comparator, and a storage circuit, and the digital pixels are arranged in a matrix array. Note that the storage circuit is formed on a second semiconductor die.

[0006] In Patent Document 1, the digital pixels store codes supplied for each column based on the output of the first part of the comparator in a storage circuit, and read out and output the codes stored in the storage circuit in response to a read signal. Therefore, since the pixel readout is performed row by row, it can be said that this is unsuitable for rolling shutter methods that require faster readout.

[0007] This invention provides a camera device that is compatible with the rolling shutter method and can better suppress noise. Solutions to technical problems

[0008] To address the above problems, according to one aspect of the present invention, a camera device is provided, comprising: Multiple photoelectric conversion elements are arranged in a first direction and a second direction that intersect each other, and accumulate charge according to the amount of incident light; Multiple pixel circuits that generate analog pixel signals based on the charge accumulated in the multiple photoelectric conversion elements; Signal lines that transmit the analog pixel signals output from two or more of the pixel circuits arranged in the second direction; and A chopping circuit uses the power supply voltage line of any one of the two or more pixel circuits connected to the signal line to chopping the voltage of the signal line to a predetermined lower limit voltage level.

[0009] The camera device may also include: A conversion circuit that performs analog-to-digital conversion on the analog pixel signals transmitted through the signal lines. The conversion circuit includes The first circuit connected to the signal line, and The second circuit is connected to the output node of the first circuit, and The first circuit includes the choke circuit.

[0010] The conversion circuit may include a current source that generates the current flowing through the signal line and the current flowing through the chopping circuit.

[0011] The first circuit can compare the analog pixel signal with a reference signal, and The second circuit can compare the output signal of the first circuit with a threshold.

[0012] The first circuit may include: A first-stage comparator that compares the analog pixel signal with the reference signal. The cutoff circuit may include: The first transistor and the second transistor are connected from the same source between the power supply voltage line and the reference voltage line of the first stage comparator. The first transistor can be turned on when a first signal indicating a cutoff to the lower limit voltage level reaches a predetermined level, and The second transistor can be turned on when the second signal indicating the selection of the first circuit reaches a predetermined level.

[0013] The first circuit may include a first input node connected to the power supply voltage line and a second input node connected to the signal line.

[0014] The camera device may further include: A first semiconductor layer, wherein the plurality of photoelectric conversion elements and the plurality of pixel circuits are arranged; A second semiconductor layer is stacked on top of the first semiconductor layer, and the first circuit is disposed therein; A first bonding member, which bonds the first semiconductor layer and the second semiconductor layer, and is connected to the first input node; and The second bonding member bonds the first semiconductor layer and the second semiconductor layer, and is connected to the second input node.

[0015] The signal line may include: Multiple segmented signal lines segmented along the second direction, The output nodes of the two or more pixel circuits arranged along the second direction can be respectively connected to the plurality of segmentation signal lines. The chopping circuit can be configured for each of the plurality of segmentation signal lines, and by using the power supply voltage line connected to any of the two or more pixel circuits of the corresponding segmentation signal line, the voltage of the corresponding segmentation signal line can be chopping to the predetermined lower limit voltage level. The conversion circuit can perform analog-to-digital conversion on the analog pixel signals transmitted through the multiple segmented signal lines.

[0016] The conversion circuit may include: The plurality of first circuits connected to the plurality of segmented signal lines, and The second circuit is connected to the output nodes of the plurality of first circuits, and Each of the plurality of first circuits may include the chopping circuit.

[0017] According to another aspect of the present invention, a camera device is provided, comprising: Multiple photoelectric conversion elements are arranged in a first direction and a second direction that intersect each other, and accumulate charge according to the amount of incident light; Multiple pixel circuits that generate analog pixel signals based on the charge accumulated in the multiple photoelectric conversion elements; Signal lines that transmit the analog pixel signals output from two or more of the pixel circuits arranged in the second direction; and A conversion circuit that performs analog-to-digital conversion on the analog pixel signals transmitted through the signal lines. The signal line includes multiple segmented signal lines divided along the second direction. The conversion circuit includes Multiple first circuits connected to the multiple segmented signal lines, and A second circuit connected to the output nodes of the plurality of first circuits, and The output nodes of the plurality of first circuits are divided into two or more groups, and each group is connected to the second circuit.

[0018] The conversion circuit may include a first selector that connects any one of the two or more groups to the second circuit.

[0019] The camera device may further include: The second selector, for each of the two or more groups, selects any one of the output nodes of the first circuit belonging to the group, and The output node of the first circuit selected by the first selector and the second selector can be connected to the second circuit.

[0020] The camera device may further include: A pre-charge circuit that pre-charges the output node of the first circuit that is not selected by the second selector.

[0021] The camera device may further include: A first semiconductor layer, wherein the plurality of photoelectric conversion elements and the plurality of pixel circuits are arranged; A second semiconductor layer, stacked on top of the first semiconductor layer, wherein the plurality of first circuits are arranged; and A third semiconductor layer, stacked on top of the second semiconductor layer, wherein the second circuit is disposed. The first selector, the second selector, and the pre-charge circuit can be arranged in the second semiconductor layer.

[0022] The camera device may further include: A first semiconductor layer, wherein the plurality of photoelectric conversion elements and the plurality of pixel circuits are arranged; A second semiconductor layer, stacked on top of the first semiconductor layer, wherein the plurality of first circuits are arranged; and A third semiconductor layer is stacked on top of the second semiconductor layer, and the second circuit is disposed therein. The first selector, the second selector, and the pre-charge circuit may be arranged in the second semiconductor layer or the third semiconductor layer.

[0023] The camera device may further include: A chopping circuit is provided for each of the plurality of segmentation signal lines, and uses the power supply voltage line connected to any one of the two or more pixel circuits of the corresponding segmentation signal line to chopping the voltage of the corresponding segmentation signal line to a predetermined lower limit voltage level.

[0024] Each of the plurality of first circuits may include a voltage setting circuit that sets the corresponding segmented signal line to a predetermined voltage level when the first circuit is not connected to the second circuit.

[0025] According to another aspect of this disclosure, a camera device is provided, comprising: Multiple photoelectric conversion elements are arranged in a first direction and a second direction that intersect each other, and accumulate charge according to the amount of incident light; Multiple pixel circuits that generate analog pixel signals based on the charge accumulated in the multiple photoelectric conversion elements; Signal lines that transmit analog pixel signals output from two or more pixel circuits arranged in the second direction; and A conversion circuit that performs analog-to-digital conversion on the analog pixel signals transmitted through the signal lines. The signal line includes multiple segmented signal lines divided along the second direction. The conversion circuit includes Multiple first circuits connected to the multiple segmented signal lines, and A second circuit connected to the output nodes of the plurality of first circuits, and Each of the plurality of first circuits includes a voltage setting circuit that sets the corresponding segmented signal line to a predetermined voltage level when the first circuit is not connected to the second circuit.

[0026] The voltage setting circuit may include a pseudo-source follower circuit, which has the same circuit configuration as the amplifying transistor and the selection transistor constituting the source follower circuit in the pixel circuit. The pseudo-source follower circuit can set the corresponding segmented signal line to the predetermined voltage level. Attached Figure Description

[0027] Figure 1 This is a block diagram illustrating the construction of an example of an electronic device commonly applicable to various implementation schemes. Figure 2 This is a block diagram illustrating the construction of an example camera device according to various embodiments of the present invention. Figure 3 This is a schematic diagram illustrating the signal processing of pixel signals in the prior art. Figure 4A This is a diagram illustrating an example of a camera device formed according to various embodiments using a stacked CIS with a two-layer structure. Figure 4BThis is a diagram illustrating an example of a camera device formed according to various embodiments using a stacked CIS with a three-layer structure. Figure 5 This is a schematic diagram showing the structure of an example of a camera device according to an embodiment. Figure 6 This is a schematic diagram illustrating the signal processing of pixel signals according to various embodiments. Figure 7 This is a schematic diagram illustrating an example of a pixel array being divided into multiple regions in the vertical direction. Figure 8 This is a schematic diagram illustrating the signal processing of pixel signals according to the fourth embodiment. Figure 9 This is a schematic diagram illustrating the segmentation of VSL according to the fourth embodiment. Figure 10 This is a circuit diagram of the periphery of the first-stage comparator of the camera device according to the first embodiment. Figure 11 This is a diagram illustrating the operation of a clip circuit. Figure 12 This is a diagram showing the voltage waveform of the divided VSL when the divided VSL is truncated. Figure 13 It is a diagram showing how the voltage level of the power supply voltage line of the pixel circuit fluctuates due to pixel differences. Figure 14 It is based on the circuit diagram surrounding the chopping circuit of a comparative example. Figure 15 This is a diagram showing the construction of a pixel array section according to a comparative example. Figure 16 This is a diagram showing the voltage waveform of the vertical signal line when it is truncated. Figure 17 It is a diagram showing how the voltage level of the power supply voltage line of the pixel circuit fluctuates due to pixel differences. Figure 18 This is a circuit diagram of the periphery of the first-stage comparator of the camera device according to a first variation of the first embodiment. Figure 19 This is a circuit diagram of the periphery of the first-stage comparator of the camera device according to a second variation of the first embodiment. Figure 20 This is a circuit diagram of the periphery of the first-stage comparator of the camera device according to the third variation of the first embodiment. Figure 21 This is a block diagram illustrating a schematic construction of a comparator according to a first embodiment. Figure 22 This is a block diagram illustrating a schematic construction of a comparator according to a second embodiment. Figure 23 This is a block diagram illustrating a schematic construction of a comparator according to a first variation of the second embodiment. Figure 24 This is a block diagram illustrating a schematic construction of a comparator according to a second variation of the second embodiment. Figure 25 This is a circuit diagram of the periphery of the first-stage comparator of the camera device according to the second embodiment. Figure 26 This is a circuit diagram of the periphery of the first-stage comparator of the camera device according to a variation of the second embodiment. Figure 27 This is a circuit diagram of the periphery of the first-stage comparator of the camera device according to the third embodiment. Figure 28 It shows Figure 27 The diagram shows the voltage waveform of the segmented VSL and the current waveform of the power supply voltage line flowing through the pixel circuit. Figure 29 This is a circuit diagram of the first-stage comparator of a camera device based on a comparative example. Figure 30 It shows Figure 29 The diagram shows the voltage waveform of the segmented VSL and the current waveform of the power supply voltage line flowing through the pixel circuit. Figure 31 It is a circuit diagram of the periphery of the first-stage comparator of a camera device having the characteristic functions according to the first to third embodiments. Figure 32A This is a schematic diagram showing the cross-sectional structure of an example of a camera device according to the first example of the fourth embodiment. Figure 32B This is a schematic diagram showing the cross-sectional structure of an example of a camera device according to the first example of the fourth embodiment. Figure 33 This is a block diagram illustrating an example of a schematic construction of a vehicle control system. Figure 34 This is an explanatory diagram showing an example of the installation location of the vehicle exterior information detection unit and the camera unit. Detailed Implementation

[0028] The following description, with reference to the accompanying drawings, will illustrate an embodiment of the camera device. Although the main components of the camera device will be described primarily below, the camera device may have components and functions not shown or described. The following description does not exclude components and functions not shown or described.

[0029] (Applicable in all implementation schemes to electronic devices) Figure 1 This is a block diagram illustrating the construction of an example of an electronic device commonly applicable to various implementation schemes. Figure 1 In this context, the electronic device 1000 includes an optical system 1002, a control unit 1003, an imaging device 1004, an image processing unit 1005, a memory 1006, a recording unit 1007, a display unit 1008, an interface (I / F) unit 1009, and an input device 1012. Examples of the electronic device 1000 include digital cameras, digital video cameras, and mobile phones or smartphones with video recording capabilities. Furthermore, surveillance cameras, vehicle-mounted cameras, or medical cameras can also be used as the electronic device 1000.

[0030] The imaging device 1004 includes, for example, a plurality of photoelectric conversion elements arranged in a matrix array. The photoelectric conversion elements convert received light into electrical charge through photoelectric conversion. The imaging device 1004 includes a drive circuit for driving the plurality of photoelectric conversion elements, a signal processing circuit for reading the charge from each of the plurality of photoelectric conversion elements and generating image data based on the read charge, and a power supply circuit for supplying power to the drive circuit.

[0031] The optical system 1002 includes a main lens comprising one or more lenses and a mechanism for driving the main lens, and forms an image of the subject light (incident light) from the subject on the light-receiving surface of the imaging device 1004 through the main lens. Furthermore, the optical system 1002 also includes an autofocus mechanism for adjusting the focus according to a control signal and a zoom mechanism for changing the zoom ratio according to a control signal. Additionally, the electronic device 1000 allows the optical system 1002 to be attachable and detachable, thereby allowing it to be replaced by another optical system 1002.

[0032] The image processing unit 1005 performs predetermined image processing on the pixel data output from the imaging device 1004. For example, the image processing unit 1005 is connected to a memory 1006, such as a frame memory, and writes the image data output from the imaging device 1004 into the memory 1006. The image processing unit 1005 performs predetermined image processing on the pixel data written to the memory 1006, and then writes the image-processed pixel data back into the memory 1006. Note that the memory 1006 is capable of storing one frame of pixel data as image data.

[0033] For example, the recording unit 1007 is a non-volatile memory such as flash memory or a hard disk drive, and stores the image data output from the image processing unit 1005 in a non-volatile manner. The display unit 1008 includes, for example, a display device such as a liquid crystal display (LCD) and a drive circuit for driving the display device, and can display images based on the image data output from the image processing unit 1005. The I / F unit 1009 is an interface for transmitting the image data output from the image processing unit 1005 to an external device. For example, a Universal Serial Bus (USB) can be used as the I / F unit 1009. The present invention is not limited thereto, and the I / F unit 1009 can be an interface that can be connected to a network via wired or wireless communication.

[0034] Input device 1012 includes operating components for receiving user input. In the case of electronic device 1000, such as a digital camera, digital camcorder, or mobile phone or smartphone with video recording function, input device 1012 may include a shutter button for commanding video recording device 1004 to take a picture, or operating components for implementing the shutter button function.

[0035] The control unit 1003 includes, for example, a processor such as a central processing unit (CPU), a read-only memory (ROM), and a random access memory (RAM), and controls the overall operation of the electronic device 1000 by using the RAM as working memory according to a program pre-stored in the ROM. For example, the control unit 1003 can control the operation of the electronic device 1000 based on user input received through the input device 1012. Furthermore, the control unit 1003 can control the autofocus mechanism of the optical system 1002 based on the image processing results of the image processing unit 1005.

[0036] (This applies to all camera devices used in the various implementation schemes) Figure 2 This is a block diagram illustrating examples of the construction of a camera device 1004 according to various embodiments of the present invention. Figure 2 In this device, the imaging apparatus 1004 includes a vertical scanning circuit 12, a timing control unit 13, a digital-to-analog converter (DAC) 14, a pixel array unit 11, a column signal processing unit 15, and a horizontal scanning circuit 16. The imaging apparatus 1004 can be configured as a CMOS image sensor (CIS) in which these components are integrally formed using complementary metal-oxide-semiconductor (CMOS).

[0037] In the pixel array section 11, a plurality of pixels 10 are arranged in a matrix array. In the following text, the pixel array section 11 will be referred to as... Figure 2 The horizontal direction is defined as rows, and the vertical direction is defined as columns.

[0038] In the pixel array section 11, each pixel 10 includes: a photoelectric conversion element that generates charge in response to received light; and a pixel circuit that outputs a pixel signal based on the charge generated by the photoelectric conversion element. The vertical scanning circuit 12 drives each pixel 10 included in the pixel array section 11 row by row to output a pixel signal from each pixel 10. At this time, the vertical scanning circuit 12 drives each pixel 10 sequentially in row order to output a pixel signal. That is, the vertical scanning circuit 12 serves as a readout control circuit that controls the readout of charge from the photoelectric conversion element and the output of the pixel signal.

[0039] The timing control unit 13 controls the operating timing of each of the vertical scanning circuit 12, DAC 14, column signal processing unit 15, and horizontal scanning circuit 16 in sync with the vertical synchronization signal VSYNC. The vertical synchronization signal VSYNC is a periodic signal having a predetermined frequency (e.g., 60 Hz) that indicates the imaging timing.

[0040] DAC 14 generates a predetermined reference signal through digital-to-analog (DA) conversion. For example, a sawtooth ramp (RAMP) signal is used as the reference signal. The reference signal is supplied to the DAC 14 by the neodymium signal processing unit 15.

[0041] The column signal processing unit 15 receives analog pixel signals output from the pixel 10 via vertical signal lines (VSLs) provided for each column in the pixel array unit 11. The column signal processing unit 15 performs signal processing such as analog-to-digital (AD) conversion and correlated double sampling (CDS) processing on a column-by-column basis for the pixel signals. The column signal processing unit 15 outputs processed digital pixel signals (pixel data). The pixel data output from the column signal processing unit 15 is supplied to the image processing unit 1005.

[0042] For example, the horizontal scanning circuit 16 controls the column signal processing unit 15 to output pixel data from the column signal processing unit 15 sequentially row by row in the column direction.

[0043] (Existing technology processing flow) The following section will illustrate the existing technology for signal processing of pixel signals. Figure 3 This is a schematic diagram illustrating the signal processing of pixel signals using existing techniques. Figure 3 In this context, comparator 20, counter 30, and logic circuit 40 are included, for example... Figure 2 The signal processing unit 15 in the column.

[0044] The analog pixel signal output from pixel 10 is supplied to comparator 20. Furthermore, a RAMP signal, serving as a reference signal, is supplied to comparator 20 from DAC 14. For example, the RAMP signal is a signal whose level (voltage value) gradually decreases over time, for example, according to a predetermined clock pulse. Comparator 20 compares the pixel signal with the RAMP signal and supplies the comparison result to counter 30. For example, if the level of the RAMP signal is higher than the level of the pixel signal, comparator 20 outputs a high-level differential signal to counter 30. On the other hand, if the level of the RAMP signal becomes the same as, equal to, or lower than the level of the pixel signal, comparator 20 inverts its output and outputs a low-level differential signal to counter 30.

[0045] Based on the differential signal input from comparator 20, during each of the P-phase (preset phase) and D-phase (data phase) periods, counter 30 counts the time from the start of the voltage drop of the ramp signal RAMP until the level of the ramp signal RAMP becomes the same as, equal to, or lower than the level of the pixel signal, and outputs each count result to logic circuit 40. Note that the P-phase period is used to detect the reset level of the pixel signal in CDS processing, and the D-phase period is used to detect the signal level of the pixel signal in CDS processing.

[0046] The logic circuit 40 performs CDS processing and AD conversion processing based on the counting results of the P-phase period and the D-phase period input from the counter 30, and generates and outputs digital pixel signals (pixel data).

[0047] (Structure of the camera device applicable to each implementation scheme) Next, the structure of the camera device applicable to each embodiment will be illustrated schematically. The camera device 1004 according to the embodiment can be formed with a stacked structure of multiple layers of semiconductor chips.

[0048] As an example, the camera device 1004 can be formed into a two-layer structure with semiconductor chips stacked in two layers. Figure 4A This is a diagram illustrating an example of a camera device 1004 formed according to various embodiments using a stacked CIS with a two-layer structure. Figure 4A In the structure, the pixel section 2010 is formed on the first layer semiconductor chip, and the memory + logic section 2011 is formed on the second layer semiconductor chip.

[0049] The pixel unit 2010 includes at least a pixel array unit 11. The memory and logic unit 2011 may include, for example, a vertical scanning circuit 12, a timing control unit 13, a DAC 14, a column signal processing unit 15, a horizontal scanning circuit 16, and an interface for communication between the imaging device 1004 and an external device. Furthermore, the memory and logic unit 2011 may also include, for example, a memory for storing pixel data output from the column signal processing unit 15.

[0050] like Figure 4A As shown on the right, the camera device 1004 is constructed as a solid-state camera element 2000a by bonding the first and second semiconductor chips while they are in electrical contact with each other.

[0051] As another example, the camera device 1004 can be formed into a three-layer structure with semiconductor chips stacked in three layers. Figure 4B This is a diagram illustrating an example of a camera device 1004 formed according to various embodiments using a stacked CIS with a three-layer structure. Figure 4B In this structure, the pixel unit 2010 is formed on the first semiconductor chip, the memory unit 2012 is formed on the second semiconductor chip, and the logic unit 2011' is formed on the third semiconductor chip. In this case, the logic unit 2011' may include, for example, a vertical scanning circuit 12, a timing control unit 13, a DAC 14, a column signal processing unit 15, a horizontal scanning circuit 16, and an interface for communication between the imaging device 1004 and an external device. Furthermore, the memory unit 2012 may also include, for example, a memory for storing pixel data output from the column signal processing unit 15.

[0052] like Figure 4B As shown on the right, the camera device 1004 is constructed as a solid-state camera element 2000b by bonding the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip while they are in electrical contact with each other.

[0053] (Based on the structure of each implementation plan) The structure of each implementation scheme will be explained next. Figure 5 This is a schematic diagram illustrating an example structure of a camera device 1004 according to an embodiment. Figure 5 In the example, the camera device 1004 adopts a reference... Figure 4A The solid-state imaging element 2000a has a two-layer structure. Here, in the case of a back-illuminated image sensor, a photoelectric conversion element is formed on the first layer 2010a of the substrate, and a pixel circuit that converts the charge generated by the photoelectric conversion element into a pixel signal and outputs the pixel signal is formed on the second layer 2010b of the substrate. The first layer 2010a and the second layer 2010b constitute the pixel section 2010.

[0054] exist Figure 5 In this configuration, photoelectric conversion units 100 are arranged in a matrix array on the first layer 2010a, each including a photoelectric conversion element and a transistor for controlling the readout of charge from the photoelectric conversion element. Circuit units 101 are arranged in a matrix array on the second layer 2010b, corresponding to the photoelectric conversion units 100 on the first layer 2010a, each including a pixel circuit for converting the charge read from the photoelectric conversion unit 200 into a pixel signal. More specifically, the circuit units 101 are electrically connected between the first layer 2010a and the second layer 2010b, and are arranged in a one-to-one relationship with the photoelectric conversion units 100 located on the first layer 2010a.

[0055] Furthermore, in various embodiments, the circuit section 101 (represented in the figures as pixel-CMP(1)) includes a portion of the comparator 20. That is, in various embodiments, the comparator 20 is constructed by dividing it into at least two parts: a first circuit (represented as CMP(1)) and second and third circuits (represented as CMP(2),(3)). The pixel signal is directly supplied from the pixel circuit to the first circuit, and the output of the first circuit is supplied to the second and third circuits. The first circuit includes, for example, circuitry that compares the pixel signal output from the pixel circuit with the RAMP signal supplied from the DAC 14.

[0056] exist Figure 5 In the memory + logic section 2011, there are vertical scan circuit 12, counter 30, logic circuit 40, peripheral circuit 50 and interface circuit 60 (also referred to as IF circuit in the figure).

[0057] The peripheral circuit 50 includes a DAC 14. Furthermore, the interface circuit 60 is an interface for transmitting and receiving signals between the imaging device 1004, which is a solid-state imaging element 2000a, and the outside world.

[0058] exist Figure 5 In the example, the vertical scanning circuit 12 is arranged along the column direction of the pixel array section 11 at one end (the right end in the example shown) of the row direction of the memory + logic section 2011. Furthermore, the interface circuit 60 is arranged along the column direction of the pixel array section 11 at the other end (the left end in the example shown) of the row direction of the memory + logic section 2011.

[0059] Furthermore, the memory + logic unit 2011 is provided with a second circuit 210 obtained through the segmentation comparator 20. Figure 5 In the example, the second circuit 210 is arranged at one end and the other end in the column direction along the row direction of the memory + logic section 2011. Figure 5 (At the top and bottom of the example). The second circuit 210 is provided for each of the pixel array sections 11. Figure 5 In the example, the second circuit 210 is disposed at both ends of the memory + logic section 2011 along the row direction of the pixel array section 11 in the column direction.

[0060] The second circuit 210 is shared by multiple circuit sections 101 arranged along a column in the second layer 2010b. For example, for each column, each second circuit 210 arranged at one end (e.g., the upper end in the figure) in the column direction of the memory + logic section 2011 is arranged in the half of the circuit section 101 in the second layer 2010b arranged at one end. Figure 5 The circuit section 101 (the upper half of the example) is shared. Similarly, for each column, the other end of the memory + logic section 2011 arranged in the column direction (e.g., Figure 5 The second circuits 210 at the lower end of the second layer 2010b are arranged in the circuit section 101 of the second layer 2010b on the other end side of the half-section ( Figure 5 The circuit section 101 (the lower half of the example) is shared.

[0061] Note that, as indicated by the arrow, each pixel 10 (each photoelectric conversion unit 100 and each circuit unit 101) is scanned along the column direction (i.e., along the vertical direction). The output from each pixel 10 (each circuit unit 101) is transferred to the memory + logic unit 2011 on a row-by-row basis.

[0062] Figure 6 This is a schematic diagram illustrating signal processing of pixel signals according to various embodiments. In various embodiments of the invention, the comparator 20 is divided into multiple circuits. Figure 6 In this example, comparator 20 is divided into three circuits: a first-stage comparator 201, an intermediate-stage comparator 202, and a final-stage comparator 203. The first-stage comparator 201 corresponds to the reference... Figure 5 The first circuit described includes, for example, circuitry that compares a pixel signal output from pixel 10 with a RAMP signal supplied from DAC 14. Intermediate stage comparator 202 and post-stage comparator 203 correspond to a reference. Figure 5 The second circuit is described, and the output of the first circuit is compared with a threshold. The intermediate stage comparator 202 and the subsequent stage comparator 203 can also be constructed as a single circuit.

[0063] (An example of dividing a pixel array into multiple regions) By dividing the pixel array section 11 into multiple regions in the vertical direction and transmitting pixel signals to each segmented region, the distance for transmitting pixel signals can be shortened. Figure 7 This is a schematic diagram showing an example of dividing the pixel array 11 into multiple regions in the vertical direction.

[0064] exist Figure 7 In the example, in the pixel unit 2010, the pixel array unit 11 is divided into four regions in the vertical direction: pixel regions 11Up1 and 11Up2, and pixel regions 11Dwn1 and 11Dwn2. In the pixel regions, pixel regions 11Up1 and 11Up2 are the upper first and second pixel regions, respectively, and pixel regions 11Dwn1 and 11Dwn2 are the lower first and second pixel regions, respectively.

[0065] In the memory + logic unit 2011, analog circuit 80Up1 and logic circuit 40Up1 are arranged at positions corresponding to pixel region 11Up1, and analog circuit 80Up2 and logic circuit 40Up2 are arranged at positions corresponding to pixel region 11Up2. Similarly, analog circuit 80Dwn1 and logic circuit 40Dwn1 are arranged at positions corresponding to pixel region 11Dwn1, and analog circuit 80Up2 and logic circuit 40Dwn2 are arranged at positions corresponding to pixel region 11Up2.

[0066] Note that each of the analog circuits 80Up1, 80Up2, 80Dwn1, and 80Dwn2 includes, for example, pixel circuits, comparator 20, and counter 30.

[0067] Pixel signals output from each pixel in pixel region 11Up1 are transmitted from the end of pixel region 11Up1 to memory + logic section 2011 via vertical signal lines within pixel region 11Up1, line by line, and are input to analog circuit 80Up1. The output of analog circuit 80Up1 is input to logic circuit 40Up1. Similar processing applies to pixel regions 11Up2, 11Dwn1, and 11Dwn2.

[0068] use Figure 7 In this configuration, the pixel signal output from each pixel is transmitted over a distance of at most one-quarter of the distance between the two ends in the column direction of the pixel array 11. However, the fact that the pixel signal is transmitted through the vertical signal line remains unchanged from the existing configuration. Therefore, the parasitic capacitance of the shortened vertical signal line only affects the settling in each pixel 10 and is unlikely to lead to improvements in characteristics such as noise reduction.

[0069] On the other hand, in various embodiments of the present invention, since the distance for transmitting the charge generated in pixel 10 to the first-stage comparator 201 is extremely short, the settling time of pixel 10 can be shortened, and with this arrangement, the time for reading the charge from pixel 10 can be accelerated. Furthermore, since the vertical signal line, which becomes a large load, is connected to the output side of the first-stage comparator 201, the bandwidth of the signal transmitted to the vertical signal line can be reduced, and noise can be reduced.

[0070] In the above, the VSL is segmented vertically to reduce its load. However, even with an increased number of VSL segments, the wiring still needs to be routed to the input terminals of the ADC provided in the column signal processing unit 15, making it difficult to improve processing speed and achieve high frame rates. For example, in a two-layer stacked structure, the upper limit of the number of VSL segments is typically around two. Furthermore, since one ADC corresponds to multiple pixels, the load on the pixel switching unit becomes heavy.

[0071] Therefore, in the imaging device according to the present invention, in a three-layer structure including a first layer and a second layer of a first substrate and a second substrate, a first-stage comparator 201 is provided for each segmented region of the VSL in the intermediate layer (the second layer of the first substrate), and the output of the first-stage comparator 201 is switched by a selection switch and input to the intermediate-stage comparator 202. By adopting this structure, the VSL load is reduced by increasing the number of VSL segments, and the processing speed can be improved and a high frame rate can be achieved.

[0072] Furthermore, in the imaging device according to the present invention, multiple pixels (photoelectric conversion unit 100) are connected to a single first-stage comparator 201. That is, the imaging device is configured to switch connections at two points (i.e., between the pixel and the first-stage comparator 201, and between the first-stage comparator 201 and the intermediate-stage comparator 202). Therefore, the load at the pixel switching unit (i.e., VSL wiring) can be reduced.

[0073] Figure 8 This is a schematic diagram illustrating the signal processing of pixel signals by the camera device according to the present invention.

[0074] With the above Figure 6 Similarly, in Figure 8 In this circuit, comparator 20 includes a first-stage comparator 201, an intermediate-stage comparator 202, and a final-stage comparator 203. The output of the final-stage comparator 203 is input to counter 30, and the output of counter 30 is input to logic circuit 40. Furthermore, the RAMP signal output from DAC 14 is supplied to the first-stage comparator 201.

[0075] exist Figure 8 In the construction shown, the pixels 101, 102, ..., 10 are from N (N ≥ 1) pixels. N The pixel signals are input to the first-stage comparator 201. This includes the first-stage comparator 201 and pixels 101, 102, ..., 10... N M (M ≥ 2) pixels / first-stage comparator units 2501, 2502, ..., and 250 M The output is input to intermediate comparator 202.

[0076] Furthermore, among these components, including pixel / first-level comparator sections 2501, 2502, ..., and 250... M The individual pixels 101, 102, ..., and 10 N The first-stage comparators 201 are arranged on the first layer 2010a of the pixel unit 2010, and each first-stage comparator 201 is arranged on the second layer 2010b of the pixel unit 2010. The intermediate-stage comparators 202 and subsequent structures are arranged in the memory + logic unit 2011.

[0077] Figure 9 This is a schematic diagram illustrating the segmentation of the VSL in the imaging device according to the present invention. Note that in Figure 9 In the middle, the first-stage comparator 2011 to 201 M It is also illustrated as the first circuit CMP (1). In addition, the subsequent circuit 251 includes an intermediate stage comparator 202, a subsequent stage comparator 203 (the second and third circuits CMP (2) (3)) and a counter 30.

[0078] like Figure 9 As shown, VSL divides pixels 101 to 10 N Each of the pixels / first-stage comparator sections 2501, 2502, ..., 250... M The corresponding first comparator 2011 to 201 M Connection. That is, in the imaging device according to the present invention, for each of the first-stage comparators 2011 to 201 M Split VSL.

[0079] As described above, in the camera device according to the present invention, the signal path is from pixel 101 to 100. N Each of them is between the first-stage comparator 201 and the pixel / first-stage comparator section 2501 to 2502. M The switching between the two in each. Therefore, for the first-stage comparator 2011 to 201 M The VSLs were split among the components, and the load on the VSL wiring was reduced.

[0080] (First Implementation Plan) Semiconductor chips, such as the camera device 1004, need to be driven at low voltage. When the camera device 1004 is driven at low voltage, the signal amplitude on the vertical signal line VSL becomes smaller, and there are component differences between individual pixels. Therefore, it is difficult to design a current source to supply current to the vertical signal line VSL.

[0081] For example, the lower limit voltage of the vertical signal line VSL depends on the signal amplitude of the vertical signal line VSL, the electrical characteristics of the pixel transistor, the potential of the FD, and the component differences in the photoelectric conversion element, etc., and the design margin (also known as margin) allowed by the aforementioned current source becomes more stringent. The imaging device 1004 according to the first embodiment described below aims to solve the above problems.

[0082] Figure 10 This is a circuit diagram of the area surrounding the first-stage comparator 201 of the camera device 1004 according to the first embodiment. Figure 10 The imaging device 1004 shown illustrates an example of a three-layer structure. Pixel circuitry 10c is arranged on a first layer 2010a. The first circuitry 73 of comparator 20 is arranged on a second layer 2010b stacked below the first layer 2010a. The second circuitry 210 and the third circuitry 211 of comparator 20 are arranged on a third layer 2010c stacked below the second layer 2010b.

[0083] and Figure 9 Similarly, in Figure 10 In the example, the vertical signal line VSL is divided into multiple parts along the vertical direction (second direction). In the following text, each segmented vertical signal line VSL will be referred to as a "segmented VSL".

[0084] Two or more pixel circuits 10c arranged in the vertical direction (second direction) are connected to each segment VSL. In addition, the first circuit 73 in a comparator 20 is connected to each segment VSL.

[0085] Comparator 20 includes a plurality of first circuits 73, a second circuit 210, and a third circuit 211. The first circuit 73 includes a first-stage comparator 201, the second circuit 210 includes an intermediate-stage comparator 202, and the third circuit 211 includes a subsequent-stage comparator 203.

[0086] More specifically, the first circuit 73 includes a clip circuit 2, a first-stage comparator 201, and a current source. As described later, the current source may be arranged in the second circuit 210.

[0087] The chopping circuit 2 uses the power supply voltage line VDDH connected to one of the two or more pixel circuits 10c of the segmented VSL to chopping the voltage of the segmented VSL to a predetermined lower limit voltage level. By setting the chopping circuit 2, the voltage level of the segmented VSL will not fall below the predetermined lower limit voltage level, thus shortening the settling time of the segmented VSL. The chopping circuit 2 is set for each of the multiple segmented VSLs, and uses the power supply voltage line VDDH connected to one of the two or more pixel circuits of the corresponding segmented VSL to chopping the voltage of the corresponding segmented VSL to the predetermined lower limit voltage level.

[0088] The chopping circuit 2 includes two NMOS transistors 111 and 112, which are common-source connected between the power supply voltage line VDDH of the pixel circuit 10c connected to the VSL segment and the power supply line of the first circuit 73. A VCLP signal is input to the gate of NMOS transistor 111, and a CLPSEL signal is input to the gate of NMOS transistor 112. Figure 10 In the original text, VCLP and CLPSEL have suffixes, but these are omitted in the manual. The VCLP signal specifies the chopping voltage of the segmented VSL. When specifying the chopping voltage of the segmented VSL, the VCLP signal is set to the analog voltage of the specified lower limit voltage of the segmented VSL. When a specific segmented VSL is selected to be set to the lower limit voltage level, the CLPSEL signal goes high. The CLPSEL signal is set individually for each chopping circuit 2.

[0089] When both the VCLP and CLPSEL signals go high, transistors 111 and 112 are turned on, and current flows from the power supply voltage line VDDH connected to the pixel circuit 10c that divides the VSL to the chopping circuit 2.

[0090] like Figure 10 As shown, the output node of the chopping circuit 2 is connected to the input node of the first-stage comparator 201 and the current source 388. When both transistors 111 and 112 in the chopping circuit 2 are turned on, current flows from the power supply voltage line VDDH connected to the pixel circuit 10c of the segmented VSL through the chopping circuit 2 to the current source 388, and the segmented VSL is chopping down to a predetermined lower limit voltage level defined by transistor 111. Furthermore, when at least one transistor in the chopping circuit 2 is turned off, current from the power supply voltage line VDDH does not flow to the chopping circuit 2, and therefore the segmented VSL is not chopping down.

[0091] Figure 10 The first circuit 73 includes a first-stage comparator 201 configured as a differential comparator comprising an active load formed by PMOS transistors 310a and 310b and a differential pair formed by NMOS transistors 311a and 311b. In the first-stage comparator 201, a RAMP signal is supplied to the gate of the NMOS transistor 311b via a capacitor 342b. Furthermore, the gate of the NMOS transistor 311a is connected to the split VSL1 via the capacitor 342a and is also connected to the current source 388, and receives the pixel signal output from the pixel circuit 10c.

[0092] Furthermore, in the first-stage comparator 201, the drain and source of PMOS transistor 341a are connected to the drain and gate of NMOS transistor 311a, respectively. Similarly, the drain and source of PMOS transistor 341b are connected to the drain and gate of NMOS transistor 311b, respectively. PMOS transistors 341a and 341b are configured to perform an automatic zero-reset operation based on signal XAZ1.

[0093] Note that each of the signals TRG, RST, SEL, CMSEL and AZ (suffix omitted) is generated in the logic circuit 40 of the memory + logic section 2011 and is supplied to the first-stage comparator 2502 through the vertical scan circuit 12.

[0094] The second circuit 210 includes NMOS transistors 320, 382, ​​and 384, and a NAND circuit 387. The source of NMOS transistor 320 is connected to a power supply line, and its drain is connected to the drain of each of NMOS transistors 382 and 384, as well as an input node of the NAND circuit 387. The gate of NMOS transistor 320 is connected to the output node of the first circuit 73. The source of NMOS transistor 382 is grounded, and its gate is connected to the source of NMOS transistor 384. A binary signal VCO indicating the comparison result is output from the NAND circuit 387.

[0095] Figure 11 This is a diagram illustrating the operation of the chopping circuit 2. (As shown...) Figure 11 As shown, two or more pixel circuits 10c are connected to the segmentation VSL ( Figure 11 VSL1 in the first circuit 73 is connected to the cutoff circuit 2 in the first circuit 73.

[0096] like Figure 11 As shown, pixel circuits 10c are arranged in the first layer 2010a, while a first circuit 73 including a chopping circuit 2 is arranged in the second layer 2010b. The first layer 2010a and the second layer 2010b are joined, for example, by copper-copper connections (CCCs) 21a and 21b for signal transmission. The first layer 2010a and the second layer 2010b have two CCCs for each segmented VSL. One CCC 21a is used to supply pixel signals output from two or more pixel circuits 10c connected to the segmented VSL to the first circuit 73 of the second layer 2010b. The other CCC 21b is used to supply the power supply voltage line VDDH of any of the two or more pixel circuits 10c connected to the segmented VSL to the chopping circuit 2 of the second layer 2010b.

[0097] With the two transistors 111 and 112 in the chopping circuit 2 turned on, current flows from the power supply voltage line VDDH connected to the pixel circuit 10c of the segmented VSL through the chopping circuit 2 to the current source 388 (indicated by the arrow line y1), and the segmented VSL is chopping down to a predetermined lower limit voltage level.

[0098] When at least one of the two transistors 111 and 112 in the chopping circuit 2 is turned off, the current from the power supply voltage line VDDH does not flow to the chopping circuit 2. In this case, the pixel signal output from any pixel circuit 10c among the two or more pixel circuits 10c connected to the chopping VSL is input to the first circuit 73 through the split VSL and a CCC 21a, and the current flows from the output node of the pixel circuit 10c to the current source 388 (indicated by the arrow line y2).

[0099] Figure 12 This is a diagram showing the voltage waveform of VSL segmented in the case of VSL segmentation by chopping in the camera device 1004 according to the first embodiment. Figure 12 The waveform w1 of the reference signal (RAMP signal), the waveform w2 of VSL when the power supply voltage of the camera device 1004 is not reduced, and the waveform w3 of VSR when the power supply voltage is reduced are shown.

[0100] like Figure 12 As shown, by setting the chopping circuit 2, the voltage level of the VSL segment during chopping remains almost unchanged, whether the power supply voltage of the camera device 1004 decreases or not, and is almost unaffected by pixel differences. Therefore, even when the power supply voltage of the camera device 1004 decreases, the design margin of the current source 388 can be sufficiently ensured, reducing design costs and improving the reliability of the current source 388.

[0101] Figure 13 This is a graph showing how the voltage level of the power supply line VDDH of the pixel circuit 10c fluctuates due to pixel differences. Figure 13 In the diagram, the horizontal axis represents time, and the vertical axis represents voltage level. Figure 13 In the diagram, the time period from time t1 to time t2 represents the voltage level of the power supply line VDDH when the normal pixel signal is read out, and the time period after time t2 represents the voltage level of the power supply line VDDH when the signal is truncated. Figure 13 The waveform w4 of the power supply voltage line VDDH is shown when using the chopping circuit 2 according to the first embodiment. Figure 13As shown, during chopped-off operation, the fluctuations in the power supply voltage line VDDH caused by pixel differences become slightly larger than the fluctuations during pixel signal readout, but the voltage fluctuations are insufficient to affect the design margin of the current source 388.

[0102] As described above, in this embodiment, since the path of current flowing to current source 388 does not change much between the readout time of the pixel signal and the truncation time of the pixel signal, voltage fluctuations caused by pixel differences in the power supply voltage line VDDH during truncation can be reduced.

[0103] Figure 14 This is based on the circuit diagram surrounding the chopping circuit 2 of a comparative example. For example... Figure 14 As shown, according to a comparative example, the chopping circuit 2 is connected in parallel with two or more pixel circuits 10c connected to the vertical signal line VSL.

[0104] Figure 15 This diagram illustrates the construction of a pixel array section 11 according to a comparative example. The pixel array section 11 according to the comparative example includes a pixel region 10a1 in which a plurality of pixels 10 are arranged, and a chopping region 10a2 in which a plurality of chopping circuits 2 are arranged for each vertical signal line VSL. The chopping region 10a2 is, for example, arranged on the lower end side of the pixel array section 11.

[0105] According to a comparative example, the chopping circuit 2 is connected to each vertical signal line VSL in a manner independent of the multiple pixel circuits 10c connected to each vertical signal line VSL. The common power supply line VDDH is connected to the multiple pixel circuits 10c and the chopping circuit 2 connected to the same vertical signal line VSL, but the power supply line VDDH is wired over a long distance, thus adding wiring load corresponding to the pixel position. Figure 14 The current path flowing through the power supply voltage line VDDH during normal pixel signal readout (indicated by arrow y3) and the current path flowing through the power supply voltage line VDDH during chopped signaling (indicated by arrow y4) are shown.

[0106] As can be seen from arrows y3 and y4, the current path flowing through the power supply voltage line VDDH is different during the normal pixel signal readout time and the choke time, and the IR drop in the vertical signal line VSL varies significantly depending on the position of the pixel to be read out.

[0107] Figure 16 This is a diagram showing the voltage waveform of the vertical signal line VSL in a camera device 1004 according to a comparative example, when the vertical signal line VSL is truncated. Figure 16The waveforms w1 of the reference signal, w5 of the vertical signal line VSL when the power supply voltage of the imaging device 1004 is not reduced, and w6 of the vertical signal line VSL when the power supply voltage is reduced are shown. In a comparative example, since the current path flowing through the power supply voltage line VDDH is different during normal pixel signal readout and during clipping, the voltage level of the vertical signal line VSL varies significantly depending on the pixel position. In particular, when the power supply voltage of the pixel circuit 10c is reduced, the voltage fluctuation of the vertical signal line VSL due to pixel differences increases. Therefore, compared with the clipping circuit 2 of the first embodiment, the design margin of the current source 388 becomes significantly narrower, making the design of the current source 388 more difficult and reducing its reliability.

[0108] Figure 17 This is a graph showing how the voltage level of the power supply line VDDH of the pixel circuit 10c fluctuates due to pixel differences. Figure 17 In the diagram, the horizontal axis represents time, and the vertical axis represents voltage level. Figure 17 In the diagram, the time period from time t1 to time t2 represents the voltage level of the power supply line VDDH when the normal pixel signal is read out, and the time period after time t2 represents the voltage level of the power supply line VDDH when the signal is truncated. Figure 17 The waveform w7 of the power supply voltage line VDDH during normal pixel signal readout in a comparative example and the waveform 8 of the power supply voltage line VDDH during truncation in a comparative example are shown. Figure 13 The waveform w4 of the power supply voltage line VDD during chopped-off operation in the first embodiment shown.

[0109] from Figure 17 A comparison between waveforms w7 and w4 shows that in the imaging device 1004 according to a comparative example, the fluctuation of the power supply voltage line VDDH due to pixel differences during chopping is significantly greater than that in the imaging device 1004 according to the first embodiment. Therefore, in the imaging device 1004 according to a comparative example, the voltage fluctuations in the power supply voltage line VDDH and the vertical signal line VSL due to pixel differences are larger, making the stripes easily visible and degrading the image quality of the captured image.

[0110] As described above, since the chopping circuit 2 according to the first embodiment causes the current flowing through the power supply voltage line VDDH connected to the pixel circuit 10c of the corresponding segmented VSL to flow to the current source 388 through the chopping circuit 2, the current path flowing to the current source 388 will not be significantly different during chopping and during normal pixel signal readout, and even when the voltage is reduced, the pixel difference in the voltage level of the segmented VSL can be suppressed.

[0111] for Figure 10The circuit construction of the first-stage comparator 201 shown can be modified in various ways. Figure 18 This is a circuit diagram of the periphery of the first-stage comparator 201 of the camera device 1004 according to the first modification of the first embodiment.

[0112] exist Figure 18 In the first-stage comparator 201 shown, the readout operation of the photoelectric conversion element 300 in the pixel circuit 10c is controlled by signals TRG1, RST1, and SEL1. In the adjacent first-stage comparator 201, the readout operation of the photoelectric conversion element 300 is also controlled by signals TRG2, RST2, and SEL2 supplied from the vertical scanning circuit 12 in row units.

[0113] The first-stage comparator 201 is controlled by mutually inverted signals AZ1 and XAZ1, as well as signal NCLP, all of which are supplied to the first-stage comparator 201 row by row from the vertical scan circuit 12. Furthermore, the connection between the first-stage comparator 201 and the intermediate-stage comparator input line 440 is controlled by signal CMSEL1, which is supplied to the first-stage comparator 201 row by row from the vertical scan circuit 12.

[0114] The operation of the first-stage comparator 201 is controlled by mutually inverted signals AZ2 and XAZ2, as well as signal NCLP, all of which are supplied to the first-stage comparator 201 row by row from the vertical scan circuit 12. Furthermore, the connection between the input nodes of the first-stage comparator 201 and the intermediate-stage comparator 202 is controlled by signal CMSEL2, which is supplied to the first-stage comparator 201 row by row from the vertical scan circuit 12.

[0115] The input node of the intermediate stage comparator 202 is connected to the gate of the PMOS transistor 383 included in the second circuit 210, and is also connected to the current source 388.

[0116] Note that each of the signals TRG, RST, SEL, CMSEL, AZ and NCLP (suffix omitted) is generated in the logic circuit 40 of the memory + logic section 2011 and supplied to the first-stage comparators 201 and 250 through the vertical scan circuit 12.

[0117] The operation of the first-stage comparator 201 will be illustrated schematically. The first-stage comparator 201 performs an auto-zero (AZ) operation before the P-phase period. During the AZ operation, the switching circuit 341, including the PMOS transistor, is turned on by the signal XAZ1, the PMOS transistor 340 is set to a diode-connected state, the PMOS transistor 372 is turned off by the signal AZ1, which is the inverted signal of XAZ1, and the NMOS transistor 370 is also turned off by the signal XAZ1. On the other hand, the switching circuit 371 is turned on by both signals AZ1 and XAZ1.

[0118] For example, the pixel signal output from pixel circuit 10c is input to the drain of NMOS transistor 373 via PMOS transistor 340, which is configured as a diode, and through switching circuit 371. NMOS transistor 373 is turned on by signal NCLP, and the pixel signal input to the drain of NMOS transistor 373 is input to one end of switching circuit 328. When switching circuit 328 is turned on by signal CMSEL1, the pixel signal is supplied to input line 440 of intermediate stage comparator 202 via switching circuit 328, thereby connecting to current source 388. Therefore, first-stage comparator 201 is reset.

[0119] After the automatic zeroing operation ends, the switching circuits 341 and 371 are turned off by signals AZ1 and XAZ1. On the other hand, PMOS transistor 372 and NMOS transistor 370 are turned on by signals AZ1 and XAZ1, forming two current paths in the vertical direction shown in the figure.

[0120] In this state, based on the current of the VSL1 signal generated from the pixel signal output from the pixel circuit and the RAMP signal, the intermediate stage comparator 202 in the second circuit 210 performs a 0 / 1 determination based on the difference in the amount of current flowing through the two current paths.

[0121] Figure 18 The second circuit 210 shown includes PMOS transistors 380, 381 and 383, NMOS transistors 382 and 384, capacitors 385 and 386, and NAND circuit 387.

[0122] The input line 440 of the intermediate stage comparator 202 is connected to the gate of the PMOS transistor 383. The drain of the PMOS transistor 383 is connected to a first fixed potential, and its source is connected to the source of the NMOS transistor 382. The drain of the NMOS transistor 384 is connected to the drain of the NMOS transistor 382, ​​and the source of the NMOS transistor 384 is connected to the gate of the NMOS transistor. A signal AZ is input to the gate of the NMOS transistor 384. Furthermore, a signal V2ndSHIFT is input to the junction connecting the gate of the NMOS transistor 382 and the source of the NMOS transistor 384 via a capacitor 386. In this way, NMOS transistors 382 and 384 and capacitor 386 are used to construct a comparator that performs a comparison operation on the signal supplied from the input line 440 of the intermediate stage comparator 202.

[0123] On the other hand, a bias voltage BaisP is applied to the source of PMOS transistor 380, and the drain of PMOS transistor 380 is connected to the gate of PMOS transistor 381. One end of capacitor 385 is connected to a second fixed voltage, and the other end of capacitor 385 is connected to the junction point where the drain of PMOS transistor 380 and the gate of PMOS transistor 381 are connected. The source of PMOS transistor 381 is connected to the second fixed voltage, and its drain is connected to the drain of NMOS transistor 382.

[0124] The output signal is extracted from the connection point between the drains of PMOS transistor 381 and NMOS transistor 382 and input to one input terminal of NAND circuit 387. Signal STB is input to the other input terminal of NAND circuit 387. Signal STB is used as a masking signal to mask signals not needed for comparator operation. For example, signal STB is generated in logic circuit 40 of memory + logic section 2011. The output of NAND circuit 387 is the output signal from second circuit 210 (intermediate stage comparator 202).

[0125] The output of NAND circuit 387 is input to a counter. Note that the part following NAND circuit 387 can be a third circuit.

[0126] exist Figure 18 With the two transistors 111 and 112 in the chopping circuit 2 turned on, current flows from the power supply voltage line VDDH connected to the pixel circuit 10c that divides the VSL to the two transistors 111 and 112 in the chopping circuit 2. This current flows through the first-stage comparator 201 to the current source 388. Similarly, in... Figure 18 In the circuit configuration, since the current path through the power supply voltage line VDDH is not significantly different during normal pixel signal readout and during truncated signal processing, the IR drop of the segmented VSL due to pixel differences does not change significantly. Therefore, as... Figure 12 As shown, this ensures sufficient design margin for the current source.

[0127] Figure 10 and Figure 18An example is shown where the first circuit 73 of comparator 20 is arranged on the second layer 2010b, and the second circuit 210 and the third circuit 211 are arranged on the third layer 2010c. However, a portion of the first circuit 73 may be arranged on the third layer 2010c. For example, the first-stage comparator 201 in the first circuit 73 may be arranged on the third layer 2010c, and the remainder of the first circuit 73, including the chopping circuit 2, may be arranged on the first layer 2010b. Furthermore, the current source that generates the current flowing through the chopping circuit 2 may be arranged on either the second layer 2010b or the third layer 2010c. For example, only the chopping circuit 2 in the first circuit 73 may be arranged on the second layer 2010b, and the remainder of the first circuit 73 may be arranged on the third layer 2010c.

[0128] Figure 10 and Figure 18 An example of a first circuit 73 for connecting comparator 20 by dividing the vertical signal line VSL into multiple parts in the vertical direction is shown, but a construction in which the first circuit 73 for connecting comparator 20 is also possible without dividing the vertical signal line VSL is also possible.

[0129] Figure 19 This is a circuit diagram surrounding the first-stage comparator 201 of the camera device 1004 according to a second modification of the first embodiment. Figure 19 In this configuration, multiple pixel circuits 10c are connected to the vertical signal line, and a comparator 20 is also connected to the vertical signal line. More specifically, a comparator 20 is connected to N pixel circuits 10c that are connected to the vertical signal line VSL.

[0130] The first circuit 73 in comparator 20 includes a chopping circuit 2, a first-stage comparator 201, and a current source. Figure 19 The first-stage comparator 201 includes circuit construction and Figure 10 The first-stage comparator 201 in the model is constructed similarly to a differential comparator.

[0131] Also in Figure 19 In this circuit, since there is no significant difference between the current path from the power supply voltage line VDDH of the pixel circuit 10c when transistors 111 and 112 in the chopping circuit 2 are turned on and the current path through the vertical signal line when the normal pixel signal is read out, the difference in IR drop in the vertical signal line VSL due to pixel differences is reduced, thereby ensuring sufficient design margin of the current source.

[0132] Figure 20 This is a circuit diagram of the periphery of the first-stage comparator 201 of the camera device 1004 according to a third modification of the first embodiment. Figure 19 Similarly, multiple pixel circuits 10c are connected to Figure 20 The vertical signal line is connected to a comparator 20.

[0133] The first circuit 73 of comparator 20 includes a chopping circuit 2, a first-stage comparator 201, and a current source 388. Figure 20 The first-stage comparator 201 includes circuit construction and Figure 18 The circuit construction of the first-stage comparator 201 is similar to that of a differential comparator. Therefore, it is possible to obtain a circuit similar to... Figure 18 and Figure 19 The effect is similar to that of the camera device 1004 in the middle.

[0134] for Figure 19 and Figure 20 The imaging device 1004 shown, which connects multiple pixel circuits 10c and a comparator 20 to the vertical signal line, can be modified in various ways. For example, Figure 19 and Figure 20 An example is shown where the first circuit 73 of comparator 20 is arranged on the second layer 2010b, and the second circuit 210 and the third circuit 211 are arranged on the third layer 2010c. However, a portion of the first circuit 73 can also be arranged on the third layer 2010c. For example, the first-stage comparator 201 in the first circuit 73 can be arranged on the third layer 2010c, and the remainder of the first circuit 73, including the chopping circuit 2, can be arranged on the second layer 2010b. Furthermore, the current source that generates the current flowing through the chopping circuit 2 can be arranged on either the second layer 2010b or the third layer 2010c. For example, only the chopping circuit 2 in the first circuit 73 can be arranged on the second layer 2010b, and the remainder of the first circuit 73 can be arranged on the third layer 2010c.

[0135] As described above, in the first embodiment, since the chopping circuit 2 connected to the power supply voltage line VDDH of the pixel circuit 10c to be read is provided in the first circuit 73 of the comparator 20, there is no significant difference between the current path through the power supply voltage line VDDH during chopping and the current path through the vertical signal line (or segmented VSL) during normal pixel signal readout, and the difference in IR drop of the segmented VSL due to pixel differences is eliminated. Therefore, the design margin of the current source can be increased, the design of the current source can be facilitated, and the reliability of the current source can be improved.

[0136] (Second Implementation Plan) In the second embodiment, the load on the output node of the first circuit 73 of the comparator 20 is reduced.

[0137] like Figure 9As shown, by dividing the vertical signal line VSL into multiple segmented VSLs and connecting the first circuit 73 of comparator 20 to each segmented VSL, the load on the vertical signal line VSL can be reduced. However, although the number of first circuits 73 of comparator 20 is set to be equal to the number of segmented VSLs, there is only one second circuit 210. Therefore, the input load of the second circuit 210 is increased.

[0138] Figure 21 This is a block diagram illustrating a schematic construction of the comparator 20 according to the first embodiment. Figure 21 As shown, the comparator 20 according to the first embodiment includes a first-stage comparator 201 connected to a plurality of first circuits 73 of a plurality of split VSLs, a plurality of switches 328 connected to the output nodes of the plurality of first circuits 73, and a subsequent-stage circuit 251 including a second circuit 210 and a third circuit 211 connected to the switches 328.

[0139] Any one of the multiple switches 328 is turned on, and the corresponding output signal of the first circuit 73 is input to the second circuit 210. Since the multiple switches 328 are integrated into a single wiring harness and connected to the second circuit 210, the load on the wiring harness increases, and stabilization takes time, thus preventing an increase in the frame rate.

[0140] Figure 22 This is a block diagram illustrating a schematic construction of the comparator 20 according to the second embodiment. Figure 22 As shown, the comparator 20 according to the second embodiment is provided with a first selector 23, which divides the output wiring of the multiple first circuits 73 connected to the multiple split VSLs into multiple groups and selects one of the multiple groups. In addition, each group includes the output wiring of two or more first-stage comparators 201, and a second selector 24 is provided to select one of the output wiring of the two or more first-stage comparators 201 in each group.

[0141] like Figure 22 As shown, by placing a first selector 23 and a second selector 24 between multiple first-stage comparators 201 and a single second circuit 210 of comparator 20, the output signal of the first-stage comparator 201 selected by the first selector 23 and the second selector 24 is input to the second circuit 210. Since the first selector 23 divides the output nodes of the multiple first-stage comparators 201 into multiple groups, the load on the input wiring of the second circuit 210 can be reduced.

[0142] Figure 23 This is a block diagram illustrating a schematic construction of the comparator 20 according to a first variation of the second embodiment. Figure 23 Comparator 20, in addition to Figure 22 In addition to its structure, it also includes a pre-charging circuit 25.

[0143] The pre-charge circuit 25 includes a third selector 26 and a pre-charge voltage generator 27. The third selector 26 selects the output wiring of the first-stage comparator 201 that was not selected by the first selector 23. The pre-charge voltage generator 27 generates the pre-charge voltage.

[0144] In this way, the pre-charge circuit 25 pre-charges the output line of the first-stage comparator 201, which is not selected by the first selector 23, to a predetermined voltage level. By pre-charging the output line of the first-stage comparator 201, which is not selected by the first selector 23, when the first selector 23 later selects the pre-charged output line of the first-stage comparator 201, the output line of the first-stage comparator 201 can be quickly set to the required voltage level, which can shorten the settling time and improve the frame rate.

[0145] Figure 24 This is a block diagram illustrating a schematic construction of a comparator 20 according to a second variation of the second embodiment. Figure 24 Through from Figure 22 This is obtained by removing the first selector 23 from comparator 20. Figure 24 In comparator 20, the output wiring of multiple first-stage comparators 201 is divided into multiple groups, and a second circuit 210 is provided for each group. Therefore, Figure 24 The comparator 20 in the system includes a plurality of second circuits 210, the number of which is equal to the number of groups. One of the output wirings of the plurality of first-stage comparators 201 belonging to each group is selected by a second selector 24 and input to the corresponding second circuit 210.

[0146] exist Figure 24 In comparator 20, the first selector 23 can be omitted, and... Figure 22 In comparison, the number of second circuits 210 has been increased.

[0147] The following text will explain the relationship with Figure 23 The block diagram corresponds to a specific circuit example, but by changing a part of the circuit construction, the circuit diagram can be changed to be similar. Figure 22 or Figure 24 The corresponding circuit diagram for the block diagram section.

[0148] Figure 25 This is a circuit diagram surrounding the first-stage comparator 201 of the camera device 1004 according to the second embodiment. A first circuit 73 is provided for each of the multiple segmented VSLs. A second circuit 210 and a third circuit 211 are provided for the multiple first circuits 73 corresponding to the multiple segmented VSLs.

[0149] The first circuit 73 includes a first-stage comparator 201, a first selector 23, a second selector 24, and a pre-charge circuit 25. The first-stage comparator 201 and the second circuit 24 in the first circuit 73 have the same characteristics as... Figure 18 The circuit structure is similar to that in the previous circuit. The first circuit 73 is arranged on the second layer 2010b, and the second circuit 210 is arranged on the third layer 2010c.

[0150] Figure 25 An example is shown where the output wiring of the four first circuits 73 connected to the split VSL is divided into two groups. A first selector 23 selects one of the two groups. A second selector 24 includes transistors 328 connected to the output nodes of the respective first-stage comparators 201.

[0151] The second selector 24 selects either of the output signals from the two first circuits 73 belonging to each group, and causes the output signal to be input to the second selector 24.

[0152] The pre-charge circuit 25 includes a third selector 26 and a pre-charge voltage generator 27. The third selector 26 selects one of the output wirings of the first circuit 73 in each group. The third selector 26 selects whether to connect the source of the transistor 328 in each group to the output node of the pre-charge voltage generator 27.

[0153] The precharge voltage generator 27 includes a PMOS transistor 390, an NMOS transistor 391, and a current source 392 connected in series between the power supply line and the ground line. The drain and gate of the PMOS transistor 390 are shorted. An NCLP signal is input to the gate of the NMOS transistor 391. When precharging is performed, the NCLP signal goes high. When the NCLP signal goes high, the NMOS transistor 391 is turned on, and a precharge voltage is output from the source of the NMOS transistor 391. Note that the circuit configuration of the precharge voltage generator 27 is not limited to... Figure 25 The example shown.

[0154] exist Figure 25 In this circuit, the output wiring of the two first circuits 73 is grouped into one group, but the number of output wiring of the first circuits 73 constituting each group is arbitrary. Furthermore, the number of segments of the vertical signal line VSL is also arbitrary. Moreover, the circuit construction of the first-stage comparator 201 in the first circuit 73 is not limited to... Figure 25 As shown. For example, you can use Figure 10 The differential comparator circuit shown can be used, or any other circuit construction can be employed. Furthermore, the circuit construction of the second circuit 210 is not limited to... Figure 25 As shown, and for example, it could be Figure 10 The circuit configuration shown or any other suitable configuration.

[0155] Figure 26 This is a circuit diagram of the area surrounding the first-stage comparator 201 of the camera device 1004 according to a variation of the second embodiment. Figure 26 The circuit construction of the first-stage comparator 201 in the middle and Figure 25 The same as in [the previous sentence]. Figure 26 and Figure 25 The difference lies in that the first selector 23 and the pre-charge circuit 25 are moved from the first circuit 73 to the second circuit 210. Therefore, in Figure 26 In the middle, a second circuit 210, including a first selector 23 and a pre-charge circuit 25, is arranged on the third layer 2010c.

[0156] As described above, in the second embodiment, the output wiring of the plurality of first circuits 73 in comparator 20 is divided into multiple groups, and a first selector 23 is provided to select one group and a second selector 24 is provided to select one of the output wirings of the plurality of first circuits 73 in the selected group. Therefore, the load on the input wiring of the second circuit 210 can be reduced, the settling time can be shortened, and the frame rate can be improved.

[0157] Furthermore, in the second embodiment, since a pre-charge circuit 25 is provided to pre-charge the output wiring of the first circuit 73 in the unselected group, the output wiring of the first circuit 73 can be quickly set to the required voltage level when the unselected group is selected later, and the settling time can be further shortened.

[0158] (Third Implementation Plan) In the third embodiment, the unselected segment VSL is set to a predetermined voltage level.

[0159] When the vertical signal line VSL is divided into multiple segmented VSLs, and the multiple first circuits 73 of comparator 20 and the single second circuit 210 are configured for the multiple segmented VSLs, the output of one of the multiple first circuits 73 is input to the second circuit 210. In this case, when the segmented VSL connected to the remaining first circuits 73 is set to a high-impedance state, when the pixel signal of the segmented VSB in the high-impedance state is subsequently read out, the voltage level on the segmented VSL changes rapidly, and a large instantaneous current flows through the power line of the pixel circuit 10c, thus degrading the characteristics. Therefore, the imaging device 1004 according to the third embodiment is characterized by implementing a countermeasure against this problem.

[0160] Figure 27 This is a circuit diagram of the area surrounding the first-stage comparator 201 of the camera device 1004 according to the third embodiment. (e.g.) Figure 27As shown, the camera device 1004 according to the third embodiment includes a first circuit 73 for a comparator 20 for each of the plurality of segmented VSLs. A second circuit 210 of the comparator 20 is provided for the plurality of first circuits 73 corresponding to the plurality of segmented VSLs.

[0161] The first circuit 73 includes a first-stage comparator 201 and a voltage setting circuit 28. For example, the first-stage comparator 201 has a voltage setting circuit 28. Figure 18 The circuit construction of the first-stage comparator 202 in the third embodiment is the same. Note that the circuit construction of the first-stage comparator 201 in the third embodiment is not limited to... Figure 27 The circuit configuration shown, for example, could be with... Figure 10 The circuit construction is similar to the differential comparator circuit in the diagram, or it can be other circuit constructions.

[0162] The voltage setting circuit 28 includes a PMOS transistor 393 and an NMOS transistor 394 connected at a common source between the power supply line and the ground line. The power supply voltage of the power supply line is the same as the power supply voltage of the pixel circuit 10c. A DMYSF_SW1 signal is input to the gate of the PMOS transistor 393. A VANA signal is input to the gate of the NMOS transistor 394. The NMOS transistor 394 is a source follower circuit. Therefore, when the DMYSF_SW1 signal goes low, the PMOS transistor 393 turns on, and the power supply line becomes a voltage level corresponding to the voltage level of the VANA signal. The DMYSF_SW1 signal goes high only in any of the multiple first circuits 73 connected to the segmented VSL. That is, different DMYSF_SW signals are input to the multiple first circuits 73 connected to the segmented VSL. The voltage level of the VSL of the first circuit 73 can be adjusted by the voltage level of the VANA signal. As described above, the voltage setting circuit 28 includes a pseudo-source follower circuit having the same circuit configuration as the amplifying transistor 305 and the selecting transistor 306 that constitute the source follower circuit in the pixel circuit. The pseudo-source follower circuit sets the corresponding segment VSL to a predetermined voltage level.

[0163] Transistors 393 and 394 are source follower circuits with the same electrical characteristics as amplifying transistor 305 and selecting transistor 306 in pixel circuit 10c.

[0164] In the following text, among the multiple first circuits 73 connected to the multiple split VSLs, the first circuit 73 that supplies an output signal to the second circuit 210 is referred to as being in an active state, and the first circuit 73 that does not supply an output signal to the second circuit 210 is referred to as being in an inactive state.

[0165] In the camera device 1004 according to the third embodiment, since the voltage setting circuit 28 forces the segment VSL connected to the first circuit 73 in the inactive state to a predetermined voltage level, the voltage level of the segment VSL does not fluctuate significantly when the first circuit 73 changes from the inactive state to the active state, and a large instantaneous current does not flow through the power line of the pixel circuit 10c.

[0166] Figure 28 It shows Figure 27 The diagram shows the voltage waveform of the segmented VSL and the current waveform flowing through the power supply voltage line VDDH of the pixel circuit 10c. Figure 28 The time period before time t1 corresponds to the inactive state, and the time period after time t1 corresponds to the active state. Since the state changes from inactive to active at time t1, the voltage level of the split VSL fluctuates slightly, but the fluctuation is not large.

[0167] Figure 29 This is a circuit diagram of the first-stage comparator 201 of a comparative camera device 1004. The first circuit 73 of the comparative camera device 1004 is... Figure 28 The difference in the first circuit 73 of the camera device 1004 according to the third embodiment shown is that the voltage setting circuit 28 is not provided.

[0168] Figure 30 It shows Figure 29 The diagram shows the voltage waveform of the segmented VSL and the current waveform flowing through the power supply voltage line VDDH of the pixel circuit 10c. In the first circuit 73 according to a comparative example, when the state switches from the inactive state to the active state (time t1), a large instantaneous current flows through the power supply voltage line VDDH of the pixel circuit 10c, and the voltage level of the segmented VSL also fluctuates significantly instantaneously.

[0169] from Figure 30 and Figure 28 A comparison between the voltage and current waveforms shows that by setting the voltage setting circuit 28 in the first circuit 73, when the first circuit 73 switches from the inactive state to the active state, the instantaneous large current no longer flows through the power supply voltage line VDDH of the pixel circuit 10c, and the voltage fluctuation of the segmentation VSL can also be suppressed.

[0170] The features and functions of the camera device 1004 according to the first to third embodiments described above can be combined arbitrarily. Figure 31 This is a circuit diagram of the periphery of the first-stage comparator 201 of the camera device 1004 with characteristic functions according to the first to third embodiments.

[0171] Figure 31The first circuit 73 shown includes a first-stage comparator 201, a chopping circuit 2, a first selector 23, a second selector 24, a pre-charge circuit 25, and a voltage setting circuit 28.

[0172] Figure 31 The first-stage comparator 201 can have any circuit configuration other than the one shown. The circuit configuration of the second circuit 210 is also arbitrary.

[0173] As Figure 31 A variation could be conceived of replacing the chopping circuit 2 and the voltage setting circuit 28 with a first circuit 73 that does not include the first selector 23, the second selector 24, and the pre-charge circuit 25. Alternatively, a first circuit 73 could be conceived that includes any two of the chopping circuit 2, the first selection circuit, the second selection circuit, the pre-charge circuit 25, and the voltage setting circuit 28.

[0174] As described above, in the third embodiment, for the first circuit 73 in the inactive state among the multiple first circuits 73 connected to the multiple segmented VSLs, since the voltage setting circuit 28 sets the segmented VSL to a predetermined voltage level, when the state changes from inactive to active, a large instantaneous current will not flow through the power supply voltage line VDDH of the pixel circuit 10c, and voltage fluctuations of the segmented VSL can be suppressed.

[0175] (Fourth Implementation Plan) Next, a fourth embodiment of the present invention will be described. The fourth embodiment shows a specific structure when the imaging device 1004 described in the first to fourth embodiments is constructed as a solid-state imaging element 2000a.

[0176] (First example) Next, a first example of the fourth implementation scheme will be described. Figure 32A and Figure 32B This is a schematic diagram showing a cross-sectional structure of an example of a camera device 3001 according to a first example of a fourth embodiment. The camera device 3001 can be associated with the camera device 1004 described using the first to fourth embodiments.

[0177] (Stacked structure of solid-state imaging elements) like Figure 32A As shown, the camera device 3001 has a stacked structure in which a light-concentrating layer 3090, a first semiconductor layer 3020, a first wiring layer 3030, a second wiring layer 3040, a second semiconductor layer 3050, a third wiring layer 3060, a fourth wiring layer 3070 and a third semiconductor layer 3080 are stacked in sequence.

[0178] The light-concentrating layer 3090 has, for example, a stacked structure in which a color filter 3091 and an on-chip lens 3092 are sequentially stacked from the second surface S2 side of the first semiconductor layer 3020, but is not limited thereto. The first semiconductor layer 3020 has a photoelectric conversion region, which will be described later, and one surface is the first surface S1, and the other surface is the second surface S2, which serves as the light incident surface. A first wiring layer 3030 is stacked on the first surface S1 of the first semiconductor layer 3020. A second wiring layer 3040 is stacked on the surface of the first wiring layer 3030 opposite to the surface on the first semiconductor layer 3020 side. The second semiconductor layer 3050 includes a plurality of transistors, one surface of which is the third surface S3, and the other surface of which is the fourth surface S4, and the third surface S3 is stacked on the surface of the second wiring layer 3040 opposite to the surface on the first wiring layer 3030 side. A third wiring layer 3060 is stacked on the fourth surface S4 of the second semiconductor layer 3050. The fourth wiring layer 3070 is stacked on the surface of the third wiring layer 3060 opposite to the surface of the second semiconductor layer 3050. The fifth surface S5 of the third semiconductor layer 3080 is stacked on the surface of the fourth wiring layer 3070 opposite to the surface of the third wiring layer 3060.

[0179] Here, the first surface S1 of the first semiconductor layer 3020 can also be referred to as the device forming surface or the main surface, and the second surface S2 of the first semiconductor layer 3020 can also be referred to as the light incident surface or the back surface. Furthermore, the third surface S3 of the second semiconductor layer 3050 can also be referred to as the device forming surface or the main surface, and the fourth surface S4 of the second semiconductor layer 3050 can also be referred to as the back surface. Additionally, the fifth surface S5 of the third semiconductor layer 3080 can also be referred to as the device forming surface or the main surface, and the surface opposite to the fifth surface S5 can be referred to as the back surface.

[0180] Furthermore, the first semiconductor layer 3020 and the second semiconductor layer 3050 are bonded using a face-to-face (F2F) method (i.e., the component forming surfaces face each other) via the first wiring layer 3030 and the second wiring layer 3040. Additionally, the second semiconductor layer 3050 and the third semiconductor layer 3080 are bonded using a back-to-face (B2F) method via the third wiring layer 3060 and the fourth wiring layer 3070, i.e., the back side and the component forming surface face each other.

[0181] (First semiconductor layer) The first semiconductor layer 3020 includes a semiconductor substrate. The first semiconductor layer 3020 includes a single-crystal silicon substrate of a first conductivity type (e.g., p-type). Furthermore, for example, a bonding pad 3014 is provided in a region of the first semiconductor layer 3020 that overlaps with the peripheral region 3002B in a plan view. Then, in a region of the first semiconductor layer 3020 that overlaps with the pixel region, a photoelectric conversion region 3020a is provided for each pixel 3003. For example, an island-shaped photoelectric conversion region 3020a divided by an isolation region 3020b is provided for each pixel 3003. Note that the number of pixels 3003 is not limited to this. Figure 32A The quantity in.

[0182] Although not shown, the photoelectric conversion region 3020a includes a well region of a first conductivity type (e.g., p-type) and a semiconductor region (photoelectric conversion section) of a second conductivity type (e.g., n-type) buried in the well region. Figure 3 The photoelectric conversion element in the pixel 10 shown is constructed in the photoelectric conversion region 3020a of the photoelectric conversion section, which includes a well region and a first semiconductor layer 3020. Furthermore, although not limited thereto, the photoelectric conversion region 3020a may be provided with a charge storage region (not shown) as a semiconductor region of a second conductivity type (e.g., n-type) and a transistor T1.

[0183] Although not limited to this construction, the isolation portion 3020b has, for example, a trench structure in which an isolation groove is formed in the first semiconductor layer 3020 and an insulating film is embedded in the isolation groove. Figure 32A In the example shown, an insulating film and metal are embedded in the isolation groove.

[0184] (First wiring layer) The first wiring layer 3030 includes an insulating film 3031, wirings 3032, first connection pads 3033, and vias (contacts) 3034. As shown, wirings 3032 and first connection pads 3033 are stacked together, with the insulating film 3031 disposed between them. The first connection pads 3033 face the surface of the first wiring layer 3030 opposite to the side of the first semiconductor layer 3020. The vias 3034 connect the first semiconductor layer 3020 to the wirings 3032, connect the wirings 3032 to each other, and connect the wirings 3033 to the first connection pads 3033, etc. Furthermore, wirings 3032 and first connection pads 3033 are not limited to this; for example, they may contain copper and be formed using a damascene process.

[0185] (Second wiring layer) The second wiring layer 3040 includes an insulating film 3041, wirings 3042, second connection pads 3043, and vias (contacts) 3044. As shown, wirings 3042 and second connection pads 3043 are stacked together, with the insulating film 3041 disposed between them. The second connection pads 3043 face the surface of the second wiring layer 3040 on the side opposite to the second semiconductor layer 3050 and are bonded to the first connection pads 3033. The vias 3044 connect the second semiconductor layer 3050 to the wirings 3042, connect the wirings 3042 to each other, and connect the wirings 3042 to the second connection pads 3043, etc. Furthermore, the wirings 3042 and second connection pads 3043 are not limited to this; for example, they may contain copper and be formed using a damascene process.

[0186] (Second semiconductor layer) The second semiconductor layer 3050 includes a semiconductor substrate. However, it is not limited to this, but the second semiconductor layer 3050 includes a single-crystal silicon substrate. The second semiconductor layer 3050 exhibits a first conductivity type, for example, p-type. A plurality of transistors T2 are disposed in the second semiconductor layer 3050. More specifically, the transistors T2 are disposed in the region of the second semiconductor layer 3050 that overlaps with the pixel region. Note that, in the second semiconductor layer 3050, in order to distinguish the region overlapping with the pixel region in a planar view, the region overlapping with the peripheral region surrounding the pixel region, the region overlapping with the peripheral region 3002B, is referred to as the first region 3050a, and the region overlapping with the pixel region 3002A is referred to as the second region 3050b.

[0187] (First conductor and second conductor) The second semiconductor layer 3050 is provided with a first conductor 3051 and a second conductor 3052. More specifically, in the first region 3050a, a first conductor 3051 is provided, having a first width, containing a first material, and penetrating through the second semiconductor layer 3050 in the thickness direction. Then, in the second region 3050b, a second conductor 3052 is provided, having a second width less than the first width, containing a second material different from the first material, and penetrating through the second semiconductor layer 3050 in the thickness direction. The first conductor 3051 and the second conductor 3052 are conductors (electrodes) penetrating the semiconductor layer. In this embodiment, since the semiconductor layer contains silicon, the first conductor 3051 and the second conductor 3052 are through-silicon vias (TSVs).

[0188] Although not limited to this, the first conductor 3051 is used, for example, as a power line. Therefore, it is preferable that the first conductor 3051 has low resistance. Therefore, it is preferable to use a conductive material with low resistivity as the first material constituting the first conductor 3051. Here, copper is used as an example of such a conductive material. Furthermore, by increasing the first width, the resistance of the first conductor 3051 can be reduced. Since the arrangement density of components and wiring in the first region 3050a where the first conductor 3051 is provided is low, the first width can be increased.

[0189] Since the second conductor 3052 is disposed in the second region 3050b where multiple transistors T2 are disposed, in some cases, the second conductor 305 needs to be disposed in a narrow region between the transistors T2. Therefore, it is necessary to reduce the second width. When the second width is reduced, the aspect ratio of the second conductor 3052 increases. Although not limited to this, in some cases, the aspect ratio of the second conductor 3052 is, for example, 5 or more. With such an aspect ratio, it is difficult to embed the same material as the first material (here, for example, copper). Therefore, for holes with a high aspect ratio, it is preferable to use a conductive material with good embedding properties as the second material constituting the second conductor 3052. Examples of such conductive materials include high-melting-point metals. Examples of high-melting-point metals include tungsten (W), cobalt (Co), ruthenium (Ru), or a metallic material containing at least one of these materials. Here, tungsten is used as the second material.

[0190] like Figure 32B As shown, the first conductor 3051 has an end 3051a and an end 3051b in the through direction. The through direction refers to the direction in which the first conductor 3051 penetrates the second semiconductor layer 3050, and is also the thickness direction of the second semiconductor film 3050. The end 3051a of the first conductor 3051 is located in the third wiring layer 3060, and the end 3051b is located in the second wiring layer 3040. Since the first conductor 3051 has a tapered shape in the through direction, the diameter of the end 3051a is larger than the diameter of the end 3051b. Furthermore, the aforementioned first width corresponds, for example, to the larger dimension of the end of the first conductor 3051 in the through direction. More specifically, the first width corresponds to the larger of the dimensions of the end 3051a (here, diameter) and the end 3051b (here, diameter), that is, to the larger dimension of the end 3051a (here, diameter). Note that the term "diameter" refers to the distance between the side surfaces and is independent of the planar shape of the first conductor 3051. Furthermore, here, the diameter of end 3051a is denoted as diameter d1.

[0191] Similarly, the second conductor 3052 has ends 3052a and 3052b in the through direction. The through direction refers to the direction in which the second conductor 3052 penetrates the second semiconductor layer 3050, and is also the thickness direction of the second semiconductor layer 3050. End 3052a of the second conductor 3052 is located in the third wiring layer 3060, and end 3052b is located in the second wiring layer 3040. Since the second conductor 3052 has a tapered shape in the through direction, the diameter of end 3052b is larger than the diameter of end 3052a. Furthermore, the aforementioned second width corresponds, for example, to the larger dimension of the end of the second conductor 3052 in the through direction. More specifically, the second width corresponds to the larger of the dimensions of end 3052a (here, diameter) and end 3052b (here, diameter), that is, to the larger dimension of end 3052b (here, diameter). Note that the term "diameter" refers to the distance between the side surfaces and is independent of the planar shape of the second conductor 3052. Furthermore, the diameter of end 3052b is denoted as diameter d2. Also, the diameter d2 of end 3052b is smaller than the diameter d1 of end 3051a (d2 < d1).

[0192] Furthermore, one of the first conductor 3051 end 3051a with a first width and the second conductor 3052 end 3052b with a second width is located on the second wiring layer 3040, and the other is located on the third wiring layer 3060. Figure 32A In the example shown, end 3052b is located on the second wiring layer 3040, and end 3051a is located on the third wiring layer 3060.

[0193] The ends of the first conductor 3051 and the second conductor 3052 on one side are connected to different wirings belonging to a single metal layer, which is disposed in the wiring layer on the same side as the ends on said one side. More specifically, the ends 3051a of the first conductor 3051 on the third wiring layer 3060 side (one side) and the ends 3052a of the second conductor 3052 on the third wiring layer 3060 side (one side) are connected to wirings formed by dividing a single metal layer disposed in the third wiring layer 3060, which will be described later, or to wirings formed by embedding a metal film in a groove and removing excess portions of the metal film. More specifically, the single metal layer is the metal layer M1 of the third wiring layer 3060 described in the manufacturing method described later. The metal layer M1 is then divided to form a plurality of wirings 3062 belonging to the metal layer M1. Here, the wiring connected to end 3051a is referred to as wiring 3062a to distinguish it from other wirings, and the wiring connected to end 3052a is referred to as wiring 3062b to distinguish it from other wirings. Furthermore, the single metal layer is the metal layer closest to the second semiconductor layer 3050 among the wiring layers on the same side as the end on one side.

[0194] The first conductor 3051 is connected at its end 3051b on the side of the second wiring layer 3040 (the other side) and the second conductor 3052 is connected at its end 3052b on the side of the second wiring layer 3040 (the other side) to the wiring 3042 belonging to the metal layer M1 of the second wiring layer 3040.

[0195] (Third wiring layer) like Figure 32A and Figure 32B As shown, the third wiring layer 3060 includes an insulating film 3061, wiring 3062, a third connection pad 3063, a barrier insulating film 3064, and a silicon capping film 3065. As shown, wiring 3062 and the third connection pad 3063 are stacked together, with the insulating film 3061 disposed between them. The third connection pad 3063 faces the surface of the third wiring layer 3060 on the side opposite to the second semiconductor layer 3050 side. Wiring 3062 and the third connection pad 3063 are not limited to this; for example, they may contain copper and be formed using a damascene process.

[0196] like Figure 32B As shown, the third wiring layer 3060 includes a barrier insulating film 3064 disposed at a position in the thickness direction overlapping with the wiring 3062 belonging to the metal layer M1. The barrier insulating film 3064 has the function of preventing metal from diffusing from the side of the barrier insulating film 3064 opposite to the side of the second semiconductor layer 3050 to the side of the barrier insulating film 3064 opposite to the side of the second semiconductor layer 3050. More specifically, although not limited thereto, the barrier insulating film 3064 prevents metal (here, copper) formed on, for example, the wiring formed on the side of the barrier insulating film 3064 opposite to the side of the second semiconductor layer 3050 from diffusing toward the side of the barrier insulating film 3064 opposite to the side of the second semiconductor layer 3050. The barrier insulating film 3064 is a film with insulating properties, and may be, for example, a film containing silicon (Si) and nitrogen (N), a film containing silicon and carbon (C), or a SiCN film containing silicon, carbon, and nitrogen, but is not limited thereto. Here, it is assumed that the barrier insulating film 3064 is a SiCN film.

[0197] The silicon capping film 3065 is configured to prevent light reflection from the device and contains a high-melting-point oxide.

[0198] (Fourth wiring layer) like Figure 32AAs shown, the fourth wiring layer 3070 includes an insulating film 3071, wiring 3072, a fourth connection pad 3073, and a via (contact) 3074. As shown, wiring 3072 and the fourth connection pad 3073 are stacked, with the insulating film 3071 disposed between them. The fourth connection pad 3073 faces the surface of the fourth wiring layer 3070 on the side opposite to the third semiconductor layer 3080 and is bonded to the third connection pad 3063. The via 3074 connects the third semiconductor layer 3080 to wiring 3072, connects wiring 3072 to each other, and connects wiring 3072 to the fourth connection pad 3073, etc. Furthermore, wiring 3072 and the fourth connection pad 3073 are not limited to this, but may, for example, contain copper and be formed using a damascene process.

[0199] (Third semiconductor layer) The third semiconductor layer 3080 includes a semiconductor substrate. The third semiconductor layer 3080 includes a single-crystal silicon substrate of a first conductivity type (e.g., p-type). A plurality of transistors T3 are disposed in the third semiconductor layer 3080. More specifically, the transistors T3 are disposed in the region of the third semiconductor layer 3080 that overlaps with the pixel region 3002A and the peripheral region 3002B in a planar view.

[0200] In the above structure, the first semiconductor layer 3020 and the first wiring layer 3030 can be associated with the first layer 2010a of the substrate. The second semiconductor layer 3050 and the second wiring layer 3040 can be associated with the second layer 2010b of the substrate. Furthermore, the third semiconductor layer 3080 and the fourth wiring layer 3070 can be associated with the memory + logic section 2011.

[0201] <8. Examples of applications of moving bodies> The technology according to the present invention (the technology) can be applied to a variety of products. For example, the technology according to the present invention can also be implemented as a device installed on any type of mobile body such as automobiles, electric vehicles, hybrid vehicles, motorcycles, bicycles, personal mobile devices, airplanes, drones, ships, and robots.

[0202] Figure 33 This is a block diagram illustrating a schematic construction example of a vehicle control system, which is an example of a mobile body control system to which the technology according to the present invention can be applied.

[0203] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 33In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. Furthermore, as functional components of the integrated control unit 12050, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0204] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various types of programs. For example, the drive system control unit 12010 is used as a control device for devices such as an internal combustion engine or drive motor for generating vehicle driving force, a drive force transmission mechanism for transmitting driving force to the wheels, a steering mechanism for adjusting the vehicle's steering angle, and a braking device for generating vehicle braking force.

[0205] The body system control unit 12020 controls the operation of various types of devices installed on the vehicle body according to various types of programs. For example, the body system control unit 12020 is used as a control device for keyless entry systems, smart key systems, power windows, or various lights such as headlights, reversing lights, brake lights, turn signals, or fog lights. In this case, radio waves or signals of various types of switches sent from a keyless entry device can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signal inputs and controls the vehicle's door locks, power windows, lights, etc.

[0206] The exterior information detection unit 12030 detects information about the exterior of the vehicle, including information from the vehicle control system 12000. For example, the exterior information detection unit 12030 is connected to a camera unit 12031. The exterior information detection unit 12030 causes the camera unit 12031 to capture images of the exterior of the vehicle and receives the captured images. Based on the received images, the exterior information detection unit 12030 can perform detection processing for objects such as people, vehicles, obstacles, signs, or characters on the road surface, or it can perform processing to detect the distance to these objects.

[0207] The camera unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The camera unit 12031 can output an electrical signal as an image or as ranging information. In addition, the light received by the camera unit 12031 can be visible light or invisible light such as infrared light.

[0208] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected, for example, to a driver state detection unit 12041 that detects the driver's state. The driver state detection unit 12041 includes, for example, a camera that captures images of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level, or determine whether the driver is dozing off.

[0209] The microcomputer 12051 can calculate control target values ​​for the drive force generating device, steering mechanism, or braking device based on information about the exterior or interior of the vehicle obtained by the exterior information detection unit 12030 or the interior information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an advanced driver assistance system (ADAS), such as collision avoidance or impact mitigation, distance-based following, speed maintenance, collision warning, or lane departure warning.

[0210] Furthermore, by controlling the drive force generating device, steering mechanism, or braking device based on information about the exterior or interior of the vehicle obtained by the exterior information detection unit 12030 or the interior information detection unit 12040, the microcomputer 12051 can perform coordinated control aimed at achieving autonomous driving, etc., which enables the vehicle to drive autonomously without relying on the driver's operation.

[0211] Furthermore, based on information about the exterior of the vehicle obtained by the exterior information detection unit 12030, the microcomputer 12051 can output control commands to the body system control unit 12020. For example, the microcomputer 12051 can, for instance, perform coordinated control aimed at preventing glare by controlling the headlights to switch from high beam to low beam, based on the position of the vehicle ahead or oncoming vehicle detected by the exterior information detection unit 12030.

[0212] The audio-visual output unit 12052 sends an output signal of at least one of audio and visual information to an output device capable of visually or audibly notifying passengers of the vehicle or external to the vehicle. Figure 33 In the example, an audio speaker 12061, a display unit 12062, and a dashboard 12063 are shown as output devices. For example, the display unit 12062 may include at least one of an in-vehicle display and a head-up display.

[0213] Figure 34 This is a diagram showing an example of the mounting position of the camera unit 12031.

[0214] exist Figure 34 In the middle, the camera unit 12031 includes camera units 12101, 12102, 12103, 12104 and 12105.

[0215] Cameras 12101, 12102, 12103, 12104, and 12105 are installed, for example, at locations on the front nose, rearview mirrors, rear bumper, and rear door of vehicle 12100, as well as at the upper part of the windshield inside the passenger compartment. Camera 12101 at the front nose and camera 12105 at the upper part of the windshield inside the passenger compartment primarily acquire images of the front of vehicle 12100. Cameras 12102 and 12103 at the rearview mirrors primarily acquire images of the sides of vehicle 12100. Camera 12104 at the rear bumper or rear door primarily acquires images of the rear of vehicle 12100. Camera 12105 at the upper part of the windshield inside the passenger compartment is mainly used to detect vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes ahead.

[0216] Notice, Figure 34 Examples of the camera ranges of camera units 12101 to 12104 are shown. Camera range 12111 represents the camera range of camera unit 12101 located at the front nose. Camera ranges 12112 and 12113 represent the camera ranges of camera units 12102 and 12103 located at the rearview mirrors, respectively. Camera range 12114 represents the camera range of camera unit 12104 located at the rear bumper or rear door. For example, by overlaying image data captured by camera units 12101 to 12104, a bird's-eye view of the vehicle 12100 viewed from above is obtained.

[0217] At least one of the camera units 12101 to 12104 may have the function of obtaining distance information. For example, at least one of the camera units 12101 to 12104 may be a stereo camera composed of multiple camera elements, or may be a camera element having pixels for phase difference detection.

[0218] For example, based on distance information obtained from cameras 12101 to 12104, microcomputer 12051 can determine the distances to various three-dimensional objects within the camera ranges 12111 to 12114 and the time-varying distances (relative speeds to vehicle 12100), thereby extracting the closest three-dimensional object as the vehicle ahead. Specifically, this closest three-dimensional object exists on the driving path of vehicle 12100 and travels at a predetermined speed (e.g., equal to or greater than 0 km / h) in approximately the same direction as vehicle 12100. Furthermore, microcomputer 12051 can preset the vehicle-to-the-front distance to be maintained and execute automatic braking control (including stop-and-go control) or automatic acceleration control (including start-and-go control), etc. Therefore, it is possible to perform cooperative control such as autonomous driving, which aims to enable the vehicle to drive autonomously without driver intervention.

[0219] For example, based on distance information obtained from cameras 12101 to 12104, microcomputer 12501 can classify three-dimensional object data into three-dimensional object data for two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid obstacles. For example, microcomputer 12051 identifies obstacles around vehicle 12100 as obstacles that the driver of vehicle 12100 can visually recognize and obstacles that the driver of vehicle 12100 cannot visually recognize. Then, microcomputer 12051 determines a collision risk to indicate the risk of collision with each obstacle. If the collision risk is equal to or higher than a set value and there is a possibility of collision, microcomputer 12051 outputs a warning to the driver via audio speaker 12061 or display unit 12062, and performs forced deceleration or evasive steering via drive system control unit 12010. Therefore, microcomputer 12051 can assist driving to avoid collisions.

[0220] At least one of the camera units 12101 to 12104 can be an infrared camera that detects infrared light. The microcomputer 12051 can identify a pedestrian, for example, by determining whether a pedestrian exists in the captured images of the camera units 12101 to 12104. This pedestrian identification is performed, for example, by the following steps: extracting feature points from the captured images of the camera units 12101 to 12104, which are infrared cameras; and performing pattern matching processing on a series of feature points representing the outline of an object to determine whether it is a pedestrian. If the microcomputer 12051 determines that a pedestrian exists in the captured images of the camera units 12101 to 12104 and thus identifies the pedestrian, the audio-visual output unit 12052 controls the display unit 12062 so that a square outline for emphasis is displayed superimposed on the identified pedestrian. The audio-visual output unit 12052 can also control the display unit 12062 to display an icon or similar symbol representing a pedestrian at a desired location.

[0221] Examples of vehicle control systems to which the technology according to the present invention can be applied have been described above. The technology according to the present invention can be applied to the camera device 1004 in the above-described configuration. By applying the technology according to the present invention, the noise of the camera device 1004 can be further reduced.

[0222] Note that this technology can have the following configuration. (1) A camera device, comprising: Multiple photoelectric conversion elements are arranged in a first direction and a second direction that intersect each other, and accumulate charge according to the amount of incident light; Multiple pixel circuits that generate analog pixel signals based on the charge accumulated in the multiple photoelectric conversion elements; Signal lines that transmit the analog pixel signals output from two or more of the pixel circuits arranged in the second direction; and A chopping circuit uses the power supply voltage line of any one of the two or more pixel circuits connected to the signal line to chopping the voltage of the signal line to a predetermined lower limit voltage level. (2) The camera device according to (1) further includes: A conversion circuit that performs analog-to-digital conversion on the analog pixel signals transmitted through the signal lines. The conversion circuit includes The first circuit connected to the signal line, and The second circuit is connected to the output node of the first circuit, and The first circuit includes the choke circuit. (3) The camera device according to (2), wherein the conversion circuit includes a current source that generates current flowing through the signal line and current flowing through the chopping circuit. (4) The camera device according to (2) or (3), The first circuit compares the analog pixel signal with a reference signal, and The second circuit compares the output signal of the first circuit with a threshold. (5) The camera device according to (4), The first circuit includes a first-stage comparator that compares the analog pixel signal with the reference signal. The chopping circuit includes The first transistor and the second transistor are connected from the same source between the power supply voltage line and the reference voltage line of the first stage comparator. The first transistor turns on when a first signal indicating a cutoff to the lower limit voltage level reaches a predetermined level, and The second transistor turns on when the second signal indicating the selection of the first circuit reaches a predetermined level. (6) The camera device according to any one of (2) to (5), The first circuit includes a first input node connected to the power supply voltage line and a second input node connected to the signal line. (7) The camera device according to (6) further includes: A first semiconductor layer, wherein the plurality of photoelectric conversion elements and the plurality of pixel circuits are arranged; A second semiconductor layer is stacked on top of the first semiconductor layer, and the first circuit is disposed therein; A first bonding member, which bonds the first semiconductor layer and the second semiconductor layer, and is connected to the first input node; and The second bonding member bonds the first semiconductor layer and the second semiconductor layer, and is connected to the second input node. (8) The camera device according to any one of (2) to (7), The signal line includes multiple segmented signal lines divided along the second direction. The output nodes of the two or more pixel circuits arranged along the second direction are respectively connected to the plurality of segmentation signal lines. The chopping circuit is configured for each of the plurality of segmentation signal lines, and uses the power supply voltage line connected to any one of the two or more pixel circuits of the corresponding segmentation signal line to chop the voltage of the corresponding segmentation signal line to the predetermined lower limit voltage level. The conversion circuit performs analog-to-digital conversion on the analog pixel signals transmitted through the multiple segmented signal lines. (9) The camera device according to (8), The conversion circuit includes The plurality of first circuits connected to the plurality of segmented signal lines, and The second circuit is connected to the output nodes of the plurality of first circuits, and Each of the plurality of first circuits includes the chopping circuit. (10) A camera device, comprising: Multiple photoelectric conversion elements are arranged in a first direction and a second direction that intersect each other, and accumulate charge according to the amount of incident light; Multiple pixel circuits that generate analog pixel signals based on the charge accumulated in the multiple photoelectric conversion elements; Signal lines that transmit the analog pixel signals output from two or more of the pixel circuits arranged in the second direction; and A conversion circuit that performs analog-to-digital conversion on the analog pixel signals transmitted through the signal lines. The signal line includes multiple segmented signal lines divided along the second direction. The conversion circuit includes Multiple first circuits connected to the multiple segmented signal lines, and A second circuit connected to the output nodes of the plurality of first circuits, and The output nodes of the plurality of first circuits are divided into two or more groups, and each group is connected to the second circuit. (11) The camera device according to (10), The conversion circuit includes a first selector that connects any one of the two or more groups to the second circuit. (12) The camera device according to (11) further includes: The second selector, for each of the two or more groups, selects any one of the output nodes of the first circuit belonging to the group, and The output node of the first circuit, selected by the first selector and the second selector, is connected to the second circuit. (13) The camera device according to (12) further includes: A pre-charge circuit that pre-charges the output node of the first circuit that is not selected by the second selector. (14) The camera device according to (13) further includes: A first semiconductor layer, wherein the plurality of photoelectric conversion elements and the plurality of pixel circuits are arranged; A second semiconductor layer, stacked on top of the first semiconductor layer, wherein the plurality of first circuits are arranged; and A third semiconductor layer is stacked on top of the second semiconductor layer, and the second circuit is disposed therein. The first selector, the second selector, and the pre-charge circuit are arranged in the second semiconductor layer. (15) The camera device according to (13) further includes: A first semiconductor layer, wherein the plurality of photoelectric conversion elements and the plurality of pixel circuits are arranged; A second semiconductor layer, stacked on top of the first semiconductor layer, wherein the plurality of first circuits are arranged; and A third semiconductor layer is stacked on top of the second semiconductor layer, and the second circuit is disposed therein. The first selector, the second selector, and the pre-charge circuit are each arranged in the second semiconductor layer or the third semiconductor layer. (16) The camera device according to any one of (10) to (15) further comprises: A chopping circuit is provided for each of the plurality of segmentation signal lines, and uses the power supply voltage line connected to any one of the two or more pixel circuits of the corresponding segmentation signal line to chopping the voltage of the corresponding segmentation signal line to a predetermined lower limit voltage level. (17) The camera device according to any one of (10) to (16), Each of the plurality of first circuits includes a voltage setting circuit, which sets the corresponding segmentation signal line to a predetermined voltage level when the first circuit is not connected to the second circuit. (18) A camera device, comprising: Multiple photoelectric conversion elements are arranged in a first direction and a second direction that intersect each other, and accumulate charge according to the amount of incident light; Multiple pixel circuits that generate analog pixel signals based on the charge accumulated in the multiple photoelectric conversion elements; Signal lines that transmit analog pixel signals output from two or more pixel circuits arranged in the second direction; and A conversion circuit that performs analog-to-digital conversion on the analog pixel signals transmitted through the signal lines. The signal line includes multiple segmented signal lines divided along the second direction. The conversion circuit includes Multiple first circuits connected to the multiple segmented signal lines, and A second circuit connected to the output nodes of the plurality of first circuits, and Each of the plurality of first circuits includes a voltage setting circuit that sets the corresponding segmented signal line to a predetermined voltage level when the first circuit is not connected to the second circuit. (19) According to the camera device described in (18), The voltage setting circuit includes a pseudo-source follower circuit, which has the same circuit structure as the amplifying transistor and the selection transistor constituting the source follower circuit in the pixel circuit. The pseudo-source follower circuit sets the corresponding segmented signal line to the predetermined voltage level.

[0223] The present invention is not limited to the embodiments described above, but includes various modifications that can be conceived by those skilled in the art, and the effects of the present invention are not limited to the above description. That is, various additions, modifications, and partial deletions can be made without departing from the concept and spirit of the invention as defined in the claims and their equivalents. List of reference numerals

[0224] 2. Cutoff Circuit 10 pixels 10a1 pixel area 10a2 Cutoff Region 10c pixel circuit 11-pixel array 12 Vertical Scanning Circuit 13 Timing Control Department 15 signal processing units 16 Horizontal Scanning Circuit 20 comparators 23 First Selector 24 Second Selector 25 Pre-charge circuit 26 Third Selector 27 Precharge Voltage Generator 28 Voltage setting circuit 30 counter 40 Logic Circuits 50 Peripheral Circuits 60 Interface Circuit 73 First Circuit 100 Photoelectric Conversion Unit 210 Second Circuit 211 Third Circuit 251 power supply circuit 1005 Image Processing Department 1006 memory Records Department 1007 1008 Display Department 1009 Interface (I / F) Unit 1012 Input Device 2010a First Layer 2010b Second Layer 2010c Third Layer 2011 First-stage comparator 2011 Logic Department 2012 Memory Division 2501 pixels / First-stage comparator section 2501 M (M ≥ 2) pixels / first-stage comparator section 2502 pixels / First-stage comparator section 3001 Camera Device 3002A pixel area 3002B Peripheral Area

Claims

1. A camera device, comprising: Multiple photoelectric conversion elements are arranged in a first direction and a second direction that intersect each other, and accumulate charge according to the amount of incident light; Multiple pixel circuits that generate analog pixel signals based on the charge accumulated in the multiple photoelectric conversion elements; A signal line that transmits the analog pixel signals output from two or more of the pixel circuits arranged in the second direction; and A chopping circuit uses the power supply voltage line of any one of the two or more pixel circuits connected to the signal line to chopping the voltage of the signal line to a predetermined lower limit voltage level.

2. The camera device according to claim 1, further comprising: A conversion circuit that performs analog-to-digital conversion on the analog pixel signals transmitted through the signal lines. The conversion circuit includes The first circuit connected to the signal line, and The second circuit is connected to the output node of the first circuit, and The first circuit includes the choke circuit.

3. The camera device according to claim 2, wherein, The conversion circuit includes a current source that generates current flowing through the signal line and current flowing through the chopping circuit.

4. The camera device according to claim 2, in, The first circuit compares the analog pixel signal with a reference signal, and The second circuit compares the output signal of the first circuit with a threshold.

5. The camera device according to claim 4, in, The first circuit includes a first-stage comparator that compares the analog pixel signal with the reference signal. The chopping circuit includes The first transistor and the second transistor are connected from the same source between the power supply voltage line and the reference voltage line of the first stage comparator. The first transistor turns on when a first signal indicating a cutoff to the lower limit voltage level reaches a predetermined level, and The second transistor turns on when the second signal indicating the selection of the first circuit reaches a predetermined level.

6. The camera device according to claim 2, in, The first circuit includes a first input node connected to the power supply voltage line and a second input node connected to the signal line.

7. The camera device according to claim 6, further comprising: A first semiconductor layer, wherein the plurality of photoelectric conversion elements and the plurality of pixel circuits are arranged; A second semiconductor layer is stacked on top of the first semiconductor layer, and the first circuit is disposed therein; A first bonding member bonds the first semiconductor layer and the second semiconductor layer, and is connected to the first input node; and The second bonding member bonds the first semiconductor layer and the second semiconductor layer, and is connected to the second input node.

8. The camera device according to claim 2, in, The signal line includes multiple segmented signal lines divided along the second direction. The output nodes of the two or more pixel circuits arranged along the second direction are respectively connected to the plurality of segmentation signal lines. The chopping circuit is configured for each of the plurality of segmentation signal lines, and uses the power supply voltage line connected to any one of the two or more pixel circuits of the corresponding segmentation signal line to chop the voltage of the corresponding segmentation signal line to the predetermined lower limit voltage level. The conversion circuit performs analog-to-digital conversion on the analog pixel signals transmitted through the multiple segmented signal lines.

9. The camera device according to claim 8, in, The conversion circuit includes The plurality of first circuits connected to the plurality of segmented signal lines, and The second circuit is connected to the output nodes of the plurality of first circuits, and Each of the plurality of first circuits includes the chopping circuit.

10. A camera device comprising: Multiple photoelectric conversion elements are arranged in a first direction and a second direction that intersect each other, and accumulate charge according to the amount of incident light; Multiple pixel circuits that generate analog pixel signals based on the charge accumulated in the multiple photoelectric conversion elements; A signal line that transmits the analog pixel signals output from two or more of the pixel circuits arranged in the second direction; and A conversion circuit that performs analog-to-digital conversion on the analog pixel signals transmitted through the signal lines. The signal line includes multiple segmented signal lines divided along the second direction. The conversion circuit includes Multiple first circuits connected to the multiple segmented signal lines, and A second circuit connected to the output nodes of the plurality of first circuits, and The output nodes of the plurality of first circuits are divided into two or more groups, and each group is connected to the second circuit.

11. The camera device according to claim 10, in, The conversion circuit includes a first selector that connects any one of the two or more groups to the second circuit.

12. The camera device according to claim 11, further comprising: The second selector, for each of the two or more groups, selects any one of the output nodes of the first circuit belonging to the group, and The output node of the first circuit, selected by the first selector and the second selector, is connected to the second circuit.

13. The camera device according to claim 12, further comprising: A pre-charge circuit that pre-charges the output node of the first circuit that is not selected by the second selector.

14. The camera device according to claim 13, further comprising: A first semiconductor layer, wherein the plurality of photoelectric conversion elements and the plurality of pixel circuits are arranged; A second semiconductor layer is stacked on top of the first semiconductor layer, and the plurality of first circuits are arranged therein; and A third semiconductor layer is stacked on top of the second semiconductor layer, and the second circuit is disposed therein. The first selector, the second selector, and the pre-charge circuit are arranged in the second semiconductor layer.

15. The camera device according to claim 13, further comprising: A first semiconductor layer, wherein the plurality of photoelectric conversion elements and the plurality of pixel circuits are arranged; A second semiconductor layer is stacked on top of the first semiconductor layer, and the plurality of first circuits are arranged therein; and A third semiconductor layer is stacked on top of the second semiconductor layer, and the second circuit is disposed therein. The first selector, the second selector, and the pre-charge circuit are each arranged in the second semiconductor layer or the third semiconductor layer.

16. The camera device according to claim 10, further comprising: A chopping circuit is provided for each of the plurality of segmentation signal lines, and uses the power supply voltage line connected to any one of the two or more pixel circuits of the corresponding segmentation signal line to chopping the voltage of the corresponding segmentation signal line to a predetermined lower limit voltage level.

17. The camera device according to claim 10, in, Each of the plurality of first circuits includes a voltage setting circuit that sets the corresponding segmented signal line to a predetermined voltage level when the first circuit is not connected to the second circuit.

18. A camera device comprising: Multiple photoelectric conversion elements are arranged in a first direction and a second direction that intersect each other, and accumulate charge according to the amount of incident light; Multiple pixel circuits that generate analog pixel signals based on the charge accumulated in the multiple photoelectric conversion elements; A signal line that transmits the analog pixel signals output from two or more of the pixel circuits arranged in the second direction; and A conversion circuit that performs analog-to-digital conversion on the analog pixel signals transmitted through the signal lines. The signal line includes multiple segmented signal lines divided along the second direction. The conversion circuit includes Multiple first circuits connected to the multiple segmented signal lines, and A second circuit connected to the output nodes of the plurality of first circuits, and Each of the plurality of first circuits includes a voltage setting circuit that sets the corresponding segmented signal line to a predetermined voltage level when the first circuit is not connected to the second circuit.

19. The camera device according to claim 18, in, The voltage setting circuit includes a pseudo-source follower circuit, which has the same circuit configuration as the amplifying transistor and the selection transistor constituting the source follower circuit in the pixel circuit. The pseudo-source follower circuit sets the corresponding segmented signal line to the predetermined voltage level.

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