Multi-channel memory with serializer / deserializer

Abstract

A joint structure is disclosed. The bonding structure may include a carrier. The bonding structure may include a first memory cell disposed on a carrier having a first memory channel and a first plurality of memory dies directly hybrid bonded to each other. The bonding structure may also include a second memory cell having a second memory channel different from the first memory channel and a second plurality of memory dies directly hybrid bonded to each other. The second memory cells may be stacked on top of the first memory cells. The bonding structure may include a serializer-deserializer disposed in or on the carrier and electrically connected to a first memory channel of the first memory cell and a second memory channel of the second memory cell. The serializer-deserializer may have an external channel configured to electrically connect the bonding structure to the processor.

Description

Cross-reference to related applications

[0001] This application claims priority to U.S. Provisional Patent Application 63 / 487,824, filed March 1, 2023, entitled "Multichannel Memory with Serializer / Deserializer," the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to semiconductor device structures and methods. Some embodiments relate to multichannel memories. Background Technology

[0003] The methods described in this section are permissible but not necessarily methods that have been previously conceived or adopted. Therefore, unless otherwise stated, none of the methods described in this section should be assumed to be prior art simply because they are included in this section.

[0004] Multiple semiconductor components can be stacked in a variety of applications, such as high-bandwidth memory. Summary of the Invention

[0005] In order to summarize the advantages of this disclosure and its implementation relative to prior art, certain objects and advantages of this disclosure are described herein. Not all such objects or advantages can be achieved in any particular embodiment. Therefore, for example, those skilled in the art will recognize that the invention can be practiced or performed in a manner that achieves or optimizes one or more advantages taught herein, without necessarily achieving other objects or advantages as taught or suggested herein.

[0006] All of these embodiments are intended to be within the scope of the invention disclosed herein. These or other embodiments will become apparent to those skilled in the art from the following detailed description of preferred embodiments with reference to the accompanying drawings, and the invention is not limited to any particular preferred embodiment disclosed.

[0007] In one embodiment, a bonding structure may include: a carrier; a first memory cell disposed on the carrier, the first memory cell including a first memory channel, the first memory cell including a first plurality of memory dies directly coupled to each other; a second memory cell including a second memory channel different from the first memory channel, the second memory cell including a second plurality of memory dies directly coupled to each other, the second memory cell stacked on top of the first memory cell; and a serializer-deserializer disposed in or on the carrier and electrically connected to the first memory channel of the first memory cell and the second memory channel of the second memory cell, the serializer-deserializer having an external channel configured to electrically connect the bonding structure to a processor.

[0008] In some embodiments, the carrier includes a logic die. In some embodiments, the bonding structure includes a logic die, wherein the carrier includes an interpolation layer, and wherein the logic die is disposed between the first memory cell and the interpolation layer. In some embodiments, the bonding structure includes an encapsulation and a logic die; wherein the carrier includes a redistribution layer; wherein the logic die is disposed between the first memory cell and the redistribution layer; wherein the first memory cell, the second memory cell, the logic die, and the serializer-deserializer are partially enclosed within the encapsulation. In some embodiments, the bonding structure includes a logic die, wherein the carrier includes a printed circuit board, and wherein the logic die is disposed between the first memory cell and the printed circuit board.

[0009] In some embodiments, the first memory cell is directly co-conjugated to the second memory cell. In some embodiments, the first memory cell is directly co-conjugated to the carrier. In some embodiments, the serializer-deserializer is directly co-conjugated to the carrier.

[0010] In another embodiment, a structure may include: a first memory cell having a top surface and a bottom surface, the first memory cell including a first plurality of memory dies directly coupled to each other; a second memory cell having a top surface and a bottom surface, the second memory cell including a second plurality of memory dies directly coupled to each other; a logic die having a top surface and a bottom surface; and a serializer-deserializer having a top surface and a bottom surface, wherein the bottom surface of the second memory cell is disposed on the top surface of the first memory cell, wherein the bottom surface of the first memory cell is disposed on the top surface of the logic die, wherein the bottom surface of the serializer-deserializer is disposed on the top surface of the logic die, wherein the structure has a first number of internal channels electrically connecting the serializer-deserializer, the logic die, the first memory cell, and the second memory cell, wherein the structure has a second number of external channels configured to electrically connect the structure to a processor, wherein the first number is greater than the second number.

[0011] In some embodiments, the first number of internal channels is two, and the second number of external channels is one. In some embodiments, the technology described herein relates to a structure in which the first number of internal channels is four, and the second number of external channels is one. In some embodiments, the second memory cell is directly coupled to the first memory cell.

[0012] In some implementations, the first memory cell is directly coupled to the logic die. In some implementations, the serializer-deserializer is directly coupled to the logic die. In some implementations, a first internal channel is electrically connected to an active circuitry of the first memory cell, wherein a second internal channel is electrically connected to an active circuitry of the second memory cell, and wherein the second internal channel is not electrically connected to an active circuitry of the first memory cell.

[0013] In another embodiment, a structure may include: a first memory cell having a top surface and a bottom surface, the first memory cell including a first plurality of memory dies directly coupled to each other; a second memory cell having a top surface and a bottom surface, the second memory cell including a second plurality of memory dies directly coupled to each other; a logic die having a top surface and a bottom surface; an interpolation layer having a top surface and a bottom surface; and a serializer-deserializer having a top surface and a bottom surface; wherein the bottom surface of the second memory cell is disposed on the top surface of the first memory cell; wherein the bottom surface of the first memory cell is disposed on the top surface of the logic die; wherein the bottom surface of the logic die is disposed on the top surface of the interpolation layer; wherein the bottom surface of the serializer-deserializer is disposed on the top surface of the interpolation layer; wherein the structure has a first number of internal channels electrically connecting the serializer-deserializer, the logic die, the first memory cell, and the second memory cell; wherein the structure has a second number of external channels configured to electrically connect the structure to a processor; and wherein the first number is greater than the second number.

[0014] In some implementations, the first number of internal channels is two, and the second number of external channels is one. In some implementations, the first number of internal channels is four, and the second number of external channels is one.

[0015] In some embodiments, the second memory cell is directly co-conjugated to the first memory cell. In some embodiments, the first memory cell is directly co-conjugated to the logic die. In some embodiments, the serializer-deserializer is directly co-conjugated to the interpolation layer. In some embodiments, the logic die is directly co-conjugated to the interpolation layer.

[0016] In some embodiments, the first internal channel is electrically connected to the active circuitry of the first memory cell, wherein the second internal channel is electrically connected to the active circuitry of the second memory cell, and wherein the second internal channel is not electrically connected to the active circuitry of the first memory cell.

[0017] In another embodiment, a structure may include: a first memory cell having a top surface and a bottom surface, the first memory cell including a first plurality of memory dies directly coupled to each other; a second memory cell having a top surface and a bottom surface, the second memory cell including a second plurality of memory dies directly coupled to each other; a logic die having a top surface and a bottom surface; a redistribution layer; a serializer-deserializer having a top surface and a bottom surface; and an encapsulation; wherein the top surface of the second memory cell is disposed on the bottom surface of the first memory cell; wherein the top surface of the first memory cell is disposed on the bottom surface of the logic die; wherein the first memory cell and the second memory cell A logic die and a serializer-deserializer are at least partially enclosed within an enclosure; wherein the top surface of the logic die and the top surface of the serializer-deserializer are exposed; wherein a redistribution layer is formed over the top surface of the serializer-deserializer and the top surface of the logic die; wherein the redistribution layer electrically connects the serializer-deserializer and the logic die; wherein the redistribution layer is configured to electrically connect the serializer-deserializer to a processor; wherein the structure has a first number of internal channels electrically connecting the serializer-deserializer, the logic die, a first memory cell, and a second memory cell; and wherein the structure has a second number of external channels configured to electrically connect the structure to a processor; wherein the first number is greater than the second number.

[0018] In some embodiments, the first number of internal channels is two, and the second number of external channels is one. In some embodiments, the first number of internal channels is four, and the second number of external channels is one. In some embodiments, the second memory cell is directly coupled to the first memory cell. In some embodiments, the first memory cell is directly coupled to the logic die.

[0019] In some implementations, the redistribution layer is deposited. In some implementations, the redistribution layer is directly mixed and bonded to the logic die and the serializer-deserializer.

[0020] In some embodiments, the first internal channel is electrically connected to the active circuitry of the first memory cell, wherein the second internal channel is electrically connected to the active circuitry of the second memory cell, and wherein the second internal channel is not electrically connected to the active circuitry of the first memory cell.

[0021] In another embodiment, a structure may include: a first memory cell having a top surface and a bottom surface, the first memory cell including a first plurality of memory dies directly coupled to each other; a second memory cell having a top surface and a bottom surface, the second memory cell including a second plurality of memory dies directly coupled to each other; a logic die having a top surface and a bottom surface; a substrate; and a serializer-deserializer having a top surface and a bottom surface, wherein the bottom surface of the second memory cell is disposed on the top surface of the first memory cell, wherein the bottom surface of the first memory cell is disposed on the top surface of the logic die, wherein the top surface of the logic die is disposed on the bottom surface of the substrate, wherein the serializer-deserializer is embedded in the substrate, wherein the serializer-deserializer is electrically connected to the logic die, wherein the structure has a first number of internal channels electrically connecting the serializer-deserializer, the logic die, the first memory cell, and the second memory cell, wherein the structure has a second number of external channels configured to electrically connect the serializer-deserializer to a processor; wherein the first number is greater than the second number.

[0022] In some implementations, the first number of internal channels is two, and the second number of external channels is one. In some implementations, the first number of internal channels is four, and the second number of external channels is one.

[0023] In some implementations, the second memory cell is directly coupled to the first memory cell. In some implementations, the first memory cell is directly coupled to the logic die.

[0024] In some embodiments, a first internal channel is electrically connected to an active circuitry of a first memory cell, a second internal channel is electrically connected to an active circuitry of a second memory cell, and a second internal channel is not electrically connected to an active circuitry of the first memory cell. In some embodiments, the substrate includes a printed circuit board.

[0025] In another embodiment, a bonding structure may include: a carrier; a first memory cell disposed on the carrier, the first memory cell including a first memory channel and a first plurality of memory dies directly coupled to each other; a second memory cell including a second memory channel different from the first memory channel and a second plurality of memory dies directly coupled to each other, the second memory cell being stacked on top of the first memory cell; and a serializer-deserializer directly coupled to the carrier and electrically connected to the first memory channel of the first memory cell and the second memory channel of the second memory cell, the serializer-deserializer having an external channel configured to electrically connect the bonding structure to a processor.

[0026] In some embodiments, the bonding structure has a first number of internal channels electrically connecting a serializer-deserializer, a logic die, a first memory cell, and a second memory cell, wherein a second number of external channels are configured to electrically connect the structure to a processor, and wherein the first number is different from the second number.

[0027] In some embodiments, the carrier includes a logic die. In some embodiments, the bonding structure further includes a logic die; wherein the carrier includes an interpolation layer, and wherein the logic die is disposed between the first memory cell and the interpolation layer. In some embodiments, the bonding structure further includes an encapsulation; and a logic die, wherein the carrier includes a redistribution layer; wherein the logic die is disposed between the first memory cell and the redistribution layer; wherein the first memory cell, the second memory cell, the logic die, and the serializer-deserializer are partially enclosed within the encapsulation. In some embodiments, the bonding structure further includes a logic die; wherein the carrier includes a printed circuit board, and wherein the logic die is disposed between the first memory cell and the printed circuit board.

[0028] In some embodiments, the first memory cell is directly co-bonded to the second memory cell. In some embodiments, the first memory cell is directly co-bonded to the carrier.

[0029] In another embodiment, a bonding structure may include: a carrier; a first memory cell and a second memory cell, the first memory cell including a first memory channel, and the second memory cell including a second memory channel different from the first memory channel, wherein the second memory cell is stacked on top of the first memory cell, wherein the first memory cell and the second memory cell are disposed on the carrier, wherein the first memory cell includes a first plurality of memory dies directly coupled to each other, and wherein the second memory cell includes a second plurality of memory dies directly coupled to each other; and a serializer-deserializer disposed on or at least partially embedded in the carrier and electrically connected to the first memory channel of the first memory cell and the second memory channel of the second memory cell, the serializer-deserializer having an external channel configured to electrically connect the bonding structure to a processor.

[0030] In some embodiments, the bonding structure has a first number of internal channels electrically connecting the serializer-deserializer, the carrier, the first memory cell, and the second memory cell, wherein a second number of external channels are configured to electrically connect the structure to a processor, and wherein the first number is different from the second number. In some embodiments, the serializer-deserializer is directly and co-bonded to the carrier.

[0031] In some embodiments, the carrier includes a logic die. In some embodiments, the bonding structure further includes a logic die; wherein the carrier includes an interpolation layer, and wherein the logic die is disposed between the first memory cell and the interpolation layer. In some embodiments, the bonding structure further includes an encapsulation body; and a logic die; wherein the carrier includes a redistribution layer; wherein the logic die is disposed between the first memory cell and the redistribution layer; wherein the first memory cell, the second memory cell, the logic die, and the serializer-deserializer are partially enclosed within the encapsulation body. In some embodiments, the bonding structure further includes a logic die; wherein the carrier includes a printed circuit board, and wherein the logic die is disposed between the first memory cell and the printed circuit board.

[0032] In some embodiments, the first memory cell is directly co-bonded to the second memory cell. In some embodiments, the first memory cell is directly co-bonded to the carrier. Attached Figure Description

[0033] These or other features, aspects, and advantages of this disclosure have been described with reference to the accompanying drawings of certain embodiments, which are intended to illustrate but not limit the scope of this disclosure. It should be understood that the drawings, which are incorporated in and constitute a part of this specification, are for the purpose of illustrating the concepts disclosed herein and may not be to scale.

[0034] Figure 1 The illustration schematically depicts a prior art implementation of a high-bandwidth memory.

[0035] Figure 2 This illustration schematically depicts another prior art high-bandwidth memory implementation.

[0036] Figure 3 An example of a multichannel memory module is illustrated schematically.

[0037] Figures 4 to 5D The illustration schematically depicts an example of a multichannel memory utilizing a serializer-deserializer according to some embodiments.

[0038] Figures 6A to 6B The diagram schematically illustrates a direct bonding process according to some embodiments. Detailed Implementation

[0039] Although several embodiments, examples, and descriptions are disclosed below, those skilled in the art will understand that the invention described herein extends beyond the specific disclosed embodiments, examples, and descriptions, and includes other uses of the invention as well as obvious modifications and equivalents thereof. Embodiments are described with reference to the accompanying drawings, wherein the same reference numerals always refer to the same elements. The techniques used in the description presented herein are not intended to be interpreted in any limiting or restrictive manner, but merely because they are used in conjunction with the detailed description of some specific embodiments of the invention. Furthermore, embodiments may include several novel features. No single feature is solely responsible for its desired properties or is necessary for practicing the invention described herein.

[0040] There is a significant demand for higher memory bandwidth and larger memory capacity. Providing high-speed, high-bandwidth connections between memory and processors can be important for some applications. For example, when training artificial intelligence or machine learning models, performing complex graphics operations, or performing other data-intensive tasks, processors such as central processing units (CPUs), graphics processing units (GPUs), field-programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs) may spend a significant amount of idle time waiting for data, which can negatively impact performance and increase the time it takes to complete computational tasks.

[0041] Conventional high-bandwidth memory (HBM) implementations use stacked memory close to the processor. For example, memory dies (e.g., dynamic random-access memory (DRAM) dies) can be stacked and connected to the processor's (e.g., a GPU or CPU) memory controller via a carrier (e.g., a silicon interpolation layer). In some embodiments, the controller die may be present within the stack. A typical HBM stack may include multiple (e.g., four) DRAM dies and logic layers (e.g., controller dies). In some implementations, memory dies may be directly stacked on the processor and connected to the processor using through-silicon vias (TSVs).

[0042] Compared to standalone memory modules that are socketed or soldered to a PCB, HBM offers several advantages. For example, power consumption can be lower, the formation factor can be smaller, and bandwidth can be significantly higher. However, there are several drawbacks and limitations with current HBM implementations. For example, memory dies are typically manufactured separately, and contact pads are formed on the memory die. The size of the contact pads can be, for example, about 25 micrometers and can have a pitch of about 55 micrometers. These large feature sizes can limit the total number of interconnects that can be formed within a given area. Additionally, to achieve high bandwidth and low latency, positioning the memory die as close to the processor as possible can be important. For example, while socketed memory in a desktop or server may be several centimeters away from the processor, HBM modules are typically within a few millimeters of the processor, and greater distances can significantly degrade performance. These limitations can negatively impact both the capacity and available bandwidth of HBM.

[0043] Figure 1 The illustration shows a typical HBM 100 method in which stacked memory modules 102 (e.g., four stacked memory modules) are arranged around a processor 104 (e.g., a CPU or GPU). Figure 2 The illustration uses something similar to Figure 1 Another HBM 200 implementation of the method shown. However, in Figure 2 The embodiment shown has significant drawbacks. Although the number of memory modules 102 (i.e., memory stacks) is from Figures 1 to 2 Doubling the memory capacity, however, places the additional memory module 102 at a greater distance from the processor 104, negatively impacting performance. Therefore, a method is needed that can increase memory capacity while maintaining or even increasing performance.

[0044] Some embodiments described herein can significantly improve the bandwidth, capacity, or both of HBM. Advantageously, some embodiments described herein can improve bandwidth, capacity, or both without requiring a larger area, significantly increasing the distance between the processor and the memory die, and / or having a significant impact on power consumption.

[0045] One method allows HBM memory cells (e.g., a stack of four DRAM dies) to be vertically stacked on top of another cell, for example, as described in U.S. Patent Application No. 18 / 052,399, filed November 3, 2022, the entire contents of which are incorporated herein by reference in their entirety and for all purposes. Two or more memory cells can be stacked on top of each other to form a memory module. To accommodate a large number of input / output connections to support multiple memory cells in a single memory module, small contact and small pitch may be important. Therefore, instead of forming connections using fairly large metal bumps as is possible in conventional methods, a direct hybrid bonding as described in more detail herein can be used to bond and form electrical connections between components of the memory module.

[0046] Figure 3 An example embodiment of a memory module 302 (e.g., an HBM module) with two memory cells 306 is shown, each memory cell 306a, 306b including a plurality (e.g., four) of memory dies (e.g., DRAM dies) 308 that are co-conjugated and stacked on top of each other. Figure 3 As shown, memory cells 306 can be stacked on top of each other and can be stacked on logic layer 310. Memory module 302 can be electrically connected to processor 304 (e.g., CPU or GPU). This design can provide increased density and bandwidth, but it can take advantage of modifications to processor 304 because the number of input / output connections has been doubled (and possibly tripled, quadrupled, etc., depending on how many memory cells are stacked together to form a memory module).

[0047] In some embodiments, memory capacity can be preferably increased without requiring an increase in the number of input / output connections to the processor. This simplifies interconnection and reduces or eliminates the need to modify the processor design to accommodate a memory module with input / output connections different from more conventional HBM modules. Therefore, some implementations may use a serializer-deserializer (SerDes) in the location between processor 304 and memory 306. In some embodiments, the SerDes may be built into a multichannel memory module, although not all implementations may include a SerDes as part of the memory module. For processor 304, a multichannel memory module 302 appears and behaves as a conventional HBM module design with a single channel.

[0048] This approach offers several advantages. Besides presenting itself as a single module, the memory module 302 can be configured to utilize multiple internal channels to improve performance. For example, in a memory module 302 having two memory cells 306, there can be two internal channels 314, one connected to the first memory cell 306a and the other connected to the second memory cell 306b. In some embodiments, the module can be configured to write to and / or read from both memory cells simultaneously. Therefore, in the case of two memory cells 306, the module's internal bandwidth can be significantly increased, for example, approximately doubled.

[0049] Figure 4 The illustration shows an example multichannel memory module 402 according to some embodiments. Figure 4 In this embodiment, memory module 402 includes two memory cells 406 (e.g., a first memory cell 406a and a second memory cell 406b), each memory cell including four memory dies (e.g., DRAM dies) 408 that are co-conjugated with each other. The memory dies 408 may also be stacked on top of each other. The first memory cell 406a may include a top surface 430 and a bottom surface 432 opposite to the top surface 430. The second memory cell 406b may include a top surface 434 and a bottom surface 436 opposite to the top surface 434. The memory cells 406 may be vertically stacked on top of logic dies 410 (e.g., a memory controller configured to manage data flow to and from the memory cells). Logic dies 410 may include a top surface 438 and a bottom surface 440. In some embodiments, the bottom surface 436 of the second memory cell 406b may be disposed on the top surface 430 of the first memory cell 406a. Furthermore, the bottom surface 432 of the first memory cell 406a can be disposed on the top surface 438 of the logic die 410.

[0050] In the electrical path between memory cell 406 and processor 404, SerDes 412 may be included in memory module 402. SerDes 412 may receive signals (e.g., data) originating from both memory cells 406 and may combine the data into a single stream before sending the data to processor 404. In some embodiments, SerDes 412 may receive a single stream from processor 404, and memory controller 410 (e.g., Figure 4 The logic shown can be configured to segment data across memory cell 406. SerDes 412 may include a top surface 442 and a bottom surface 444 opposite to the top surface 442. In some embodiments, the bottom surface 444 of SerDes 412 may be disposed on the top surface 438 of the logic die 410.

[0051] Because a large number of interconnects exist in memory module 402, such as Figure 4 As shown, having small feature sizes (e.g., small contact pads and small pitch) may be important. For example, in Figure 4 In the configuration shown, there may be one external interconnect channel 414 (e.g., for connecting to a processor) and two internal channels 416 (e.g., one channel per memory cell). The number of interconnects may increase significantly as more memory cells are added. For example, there may be two internal channels for each external channel, or another ratio such as 4:1, 8:1, 16:1, 32:1, etc. Generally, the number of internal channels may be greater than the number of external channels. In some embodiments, direct hybrid bonding may be used to bond components of memory module 402 (e.g., to bond DRAM dies 408 to each other, to bond memory cells 406 to each other, to bond memory cells 406 to logic dies 410, to bond SerDes 412 to logic dies 410, etc.).

[0052] Various methods can be used to implement multichannel memory. Figures 5A to 5D The illustration shows an example implementation using a multichannel memory of the SerDes 512. Figure 5A In this configuration, memory cell 506 is stacked on top of logic die 510. SerDes 512 is attached (e.g., directly mixed-junction) to logic die 510, and signals between processor 504 and memory cell 506 pass through SerDes 512. Figure 5B In this memory module 502, memory module 502 may include memory cell 506 and logic die 510, and SerDes 512 may be disposed on interpolation layer 518 outside memory module package 520. Interpolation layer 518 may include a top surface 546 and a bottom surface 548 opposite to the top surface 546. Interpolation layer 518 may include any suitable type of interpolation layer, such as semiconductor or dielectric substrate, integrated device die or wafer, reconfigurable element (e.g., one or more encapsulated dies having routing and bonding layers formed thereon), package substrate having a direct bonding layer thereon, etc. Memory module 502 may be bonded (direct hybrid bonding) to interpolation layer 518. Bottom surface 540 of logic die 510 may be disposed on top surface 546 of interpolation layer. Additionally, bottom surface 544 of serializer-deserializer 512 may be disposed on top surface 548 of interpolation layer. Figures 5A to 5B In this context, the signal between the processor 504 and the memory unit 506 can pass through the SerDes 512.

[0053] Figure 5 illustrates an example of a fan-out package according to some embodiments. Unless otherwise noted, Figure 5C The components can be with Figures 5A to 5C Components with the same reference numerals are identical or substantially similar and can be assembled and / or operated in substantially similar manner. A fan-out package enables connectivity between memory cells and external interfaces such as processors. A fan-out configuration can be designed to optimize data transfer between memory cells and external memory controllers or host systems. Figure 5C In this configuration, the memory stack 522 (i.e., memory module) may include memory cells 506 and logic dies 510. The memory stack 522 may be embedded in an encapsulation 524. The SerDes 512 may also be embedded in the encapsulation 524. In various embodiments, the encapsulation 524 may include one or more dielectric layers, such as one or more inorganic dielectric layers (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.). In some embodiments, the encapsulation 524 may include an organic insulating material such as a molding compound or epoxy resin. A redistribution layer 526 may be formed (e.g., deposited) over the exposed surfaces of the SerDes 512 and the logic die 510, providing electrical connections between the SerDes 512 and the logic die 510, as well as external connections for interfacing with the processor 504. In some embodiments, the redistribution layer 526 may be deposited or directly hybridized (e.g., via a transfer bonding process). Figure 5D In this embodiment, the SerDes 512 can be embedded in a substrate 528 (e.g., a printed circuit board). The substrate 528 may include an organic, ceramic, or inorganic substrate having cavities thereon on which the SerDes element 512 can be disposed. A memory module 502, which may include a logic die 510 and a memory cell 506, may be electrically connected to the SerDes 512, and the SerDes 512 may be connected to a processor 504.

[0054] As mentioned above, using a serializer-deserializer (SerDes) at the location between any processor in the processor and the memory described herein can improve the performance of a multichannel memory module, since multichannel memory modules can emerge and behave as a conventional HBM module design with a single channel. The memory module can be configured to utilize multiple internal channels to improve performance. The memory module can write to and / or read from two or more memory cells simultaneously, thus increasing the internal bandwidth of the memory module. direct connection

[0055] The various embodiments disclosed herein relate to direct bonding structures in which two or more elements can be directly bonded to each other without an intermediate adhesive. Such processes and structures are referred to herein as "direct bonding" processes or "direct bonding" structures. Direct bonding can involve the bonding of one material on one element to one material on another element (also referred to herein as "uniform" direct bonding), where the materials on the different elements do not need to be identical without the use of conventional adhesive materials. Direct bonding can also involve the bonding of multiple materials on one element to multiple materials on another element (e.g., hybrid bonding).

[0056] In some embodiments (not shown), each bonding layer has one material. In these uniform direct bonding processes, only one material on each element is directly bonded. Example uniform direct bonding processes include ZIBOND commercially available from Adeia of San Jose, CA. ® The materials of the opposing bonding layers on different components can be the same or different, and can include elemental or compound materials. For example, in some embodiments, without patterning with conductive features (e.g., without pads), the non-conductive bonding layer can be a blanket deposited on a portion of the substrate. In other embodiments, the bonding layers can be patterned on one or two components and can be the same or different from each other, but without adhesive, a material from each component bonds directly across the surface of the components (or across the surface of the smaller component if the components are of different sizes). In another embodiment of uniform direct bonding, one or both layers of the non-conductive bonding layers can include one or more conductive features, but the conductive features are not involved in the bonding. For example, in some embodiments, opposing non-conductive layers can be uniformly and directly bonded to each other, but after bonding, a through-substrate via (TSV) can subsequently be formed through one component to provide electrical communication to other components.

[0057] In various embodiments, bonding layers 608a and / or 608b may comprise non-conductive materials such as dielectric materials or undoped semiconductor materials such as undoped silicon, which may comprise natural oxides. Suitable dielectric bonding surfaces or materials for direct bonding include, but are not limited to, inorganic dielectrics such as silicon oxide, silicon nitride, or silicon oxynitride, or may comprise carbon such as silicon carbide, silicon oxycarbonitride, low-k dielectrics, SiCOH dielectrics, silicon carbonitride, or diamond carbon, or materials comprising a diamond surface. Such carbon-containing ceramic materials may be considered inorganic, although they may include carbon. In some embodiments, the dielectric material at the bonding surface does not comprise polymeric materials such as epoxy resins (e.g., epoxy adhesives, cured epoxy resins, or epoxy composites such as FR-4), resins, or molding materials.

[0058] In other embodiments, the bonding layer may include a conductive material, such as a deposited conductive oxide material, for example, indium tin oxide (ITO), as disclosed in U.S. Provisional Patent Application No. 63 / 524,564, filed June 30, 2023, the entire contents of which are incorporated herein by reference in their entirety as an example of providing a conductive bonding layer without a short-circuit contact through the interface.

[0059] In direct bonding, the first and second elements can be directly bonded to each other without an adhesive, which differs from the deposition process and thus creates an interface structurally different from that produced by deposition. In one application, the width of the first element in the bonded structure is similar to the width of the second element. In some other embodiments, the width of the first element in the bonded structure differs from the width of the second element. The width or area of ​​the larger element in the bonded structure can be at least 10% larger than the width or area of ​​the smaller element. Furthermore, the interface between the direct bonded structures, unlike the interface beneath the deposited layer, can include defect regions in which nanoscale voids (nanopores) exist. Nanopores may form due to activation of one or both of the bonded surfaces (e.g., exposure to plasma, as explained below).

[0060] The bonding interface between non-conductive bonding surfaces may include a higher concentration of material from activation and / or final chemical treatment processes compared to the bulk of the bonding layer. For example, in embodiments utilizing nitrogen plasma for activation, a nitrogen concentration peak may be formed at the bonding interface. In some embodiments, the nitrogen concentration peak may be detected using secondary ion mass spectrometry (SIMS). In various embodiments, for example, nitrogen termination treatment (e.g., exposing the bonding interface to nitrogen-containing plasma) may replace the OH group of the hydrolyzed (OH-terminated) surface with NH2 molecules to produce a nitrogen-terminated surface. In embodiments utilizing oxygen plasma for activation, an oxygen concentration peak may be formed at the bonding interface between non-conductive bonding surfaces. In some embodiments, the bonding surface may include silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. Direct bonding may include covalent bonds stronger than van der Waals bonds. The bonding layer may also include a polished surface planarized to a high degree of smoothness.

[0061] In direct bonding processes, such as uniform direct bonding and hybrid bonding, two components are joined together without an intermediate adhesive. In indirect bonding processes utilizing adhesives, an intermediate material is typically applied to one or both components to achieve a physical bond between them. For example, in some adhesive-based processes, a flowing adhesive (e.g., an organic adhesive such as epoxy resin) that may include a conductive filler material can be applied to one or both components and cured to form a physical (rather than chemical or covalent) bond between the components. Typical organic adhesives lack strong chemical or covalent bonds with either component. In such processes, the bond between components is weak and / or easily reversed, such as by reheating or desoldering.

[0062] Conversely, direct bonding processes combine two elements by forming strong chemical bonds (e.g., covalent bonds) between opposing nonconductive materials. For example, in a direct bonding process between nonconductive materials, one or both nonconductive surfaces of the two elements are planarized and chemically prepared (e.g., activated and / or terminated) such that strong chemical bonds (e.g., covalent bonds) are formed when the elements come into contact, which are stronger than van der Waals or hydrogen bonds. In some embodiments (e.g., between opposing dielectric surfaces, such as opposing silicon oxide surfaces), the chemical bonds can occur spontaneously at room temperature upon contact. In some embodiments, the chemical bonds between opposing nonconductive materials can be strengthened after annealing the elements.

[0063] As noted above, hybrid bonding is a type of direct bonding in which non-conductive features are directly bonded to each other, and conductive features are directly bonded to conductive features of the elements being bonded. The non-conductive bonding materials and interfaces can be as described above, while the conductive bonding can be formed, for example, as a direct metal-to-metal connection. In conventional metal bonding processes, a fusible metal alloy (e.g., solder) can be provided between the conductors of two elements, heated to melt the alloy, and cooled to form a connection between the two elements. The resulting bond typically represents a sharp interface with conductors from both elements and is reversed by reheating. In contrast, direct metal bonding, as employed in hybrid bonding, does not require melting or intermediate fusible metal alloys and can thus generate strong mechanical and electrical connections, typically demonstrating the interdiffusion of conductive features in the bond, where grains grow between the elements at the bonding interface, even at much higher temperatures and pressures than thermocompression bonding.

[0064] Figure 6A and Figure 6B The illustration schematically shows cross-sectional side views of a first element 602 and a second element 604, respectively, before and after the process for forming a direct-joint structure, and more specifically a hybrid-joint structure, according to some embodiments. Figure 6BIn the illustrated hybrid bonding structure 600, a first element 602 and a second element 604 are directly bonded to each other at a bonding interface 618 without an intermediate adhesive. A conductive feature 606a of the first element 602 can be electrically connected to a corresponding conductive feature 606b of the second element 604. In the illustrated hybrid bonding structure 600, conductive features 606a are directly bonded to corresponding conductive features 606b without intercalation solder or conductive adhesive.

[0065] In the illustrated embodiment, conductive features 606a and 606b are embedded in a first bonding layer 608a of the first element 602 and a second bonding layer 608b of the second element 604, respectively, and can be considered as part of the first bonding layer 608a of the first element 602 and the second bonding layer 608b of the second element 604. Field regions of bonding layers 608a and 608b extend between and partially or completely surround the conductive features 606a and 606b. Bonding layers 608a and 608b may comprise layers of non-conductive material suitable for direct bonding, as described above, and the field regions are directly bonded to each other without adhesive. Non-conductive bonding layers 608a and 608b may be disposed on corresponding front surfaces 614a and 614b of the substrate portions 610a and 610b.

[0066] First element 602 and second element 604 may include microelectronic elements, such as semiconductor elements, including, for example, integrated device dies, wafers, passive devices, discrete active devices such as power switches, MEMS, etc. In some embodiments, the substrate portion may include device portions, such as bulk semiconductor (e.g., silicon) portions of elements 602, 604 and back-end line (BEOL) interconnect layers above such semiconductor portions. Bonding layers 608a, 608b may be provided during device manufacturing as part of such BEOL layers, as part of redistribution layers (ROLs), or as specific bonding layers added to existing devices, wherein bonding pads extend from contacts of the underlying layer. Active devices and / or circuit arrangements may be patterned and / or additionally disposed in or on substrate portions 610a, 610b, and may be electrically connected to at least some of the conductive features 606a, 606b. Active devices and / or circuitry may be disposed on or near the front surfaces 614a, 614b of the substrate portions 610a, 610b, and / or on or near the opposite back surfaces 616a, 616b of the substrate portions 610a, 610b. In other embodiments, the substrate portions 610a, 610b may not include active circuitry, but may alternatively include dummy substrates, passive interpolation layers, passive optical elements (e.g., glass substrates, gratings, lenses), etc. Bonding layers 608a, 608b are shown as being provided on the front surface of the element, but similar bonding layers may be additionally or optionally provided on the back surface of the element.

[0067] In some embodiments, substrate portions 610a and 610b may have significantly different coefficients of thermal expansion (CTE), and bonding elements including such different substrate portions may form heterojunction structures. The CTE difference between substrate portions 610a and 610b, particularly the CTE difference between the bulk semiconductor (typically single-crystal) portions of substrate portions 610a and 610b, may be greater than 5 ppm / °C or greater than 10 ppm / °C. For example, the CTE difference between substrate portions 610a and 610b may be in the range of 5 ppm / °C to 100 ppm / °C, 5 ppm / °C to 40 ppm / °C, 10 ppm / °C to 100 ppm / °C, or 10 ppm / °C to 40 ppm / °C.

[0068] In some embodiments, one portion of the substrate portions 610a and 610b may include a photoelectric single-crystal material, including perovskite materials, for optical piezoelectric or thermoelectric applications, and the other portion of the substrate portions 610a and 610b may include a more conventional substrate material. For example, one portion of the substrate portions 610a and 610b may include lithium tantalate (LiTaO3) or lithium niobate (LiNbO3), and the other portion of the substrate portions 610a and 610b may include silicon (Si), quartz, fused silica glass, sapphire, or glass. In other embodiments, one portion of the substrate portions 610a and 610b may include a group III-V single semiconductor material, such as gallium arsenide (GaAs) or gallium nitride (GaN), and the other portion of the substrate portions 610a and 610b may include a non-group III-V semiconductor material, such as silicon (Si), or may include other materials with similar CTEs, such as quartz, fused silica glass, sapphire, or glass. In other embodiments, one of the substrate portions 610a and 610b includes a semiconductor material, and the other of the substrate portions 610a and 610b includes an encapsulation material, such as a glass, organic, or ceramic substrate.

[0069] In some arrangements, the first element 602 may include a monolithic element, such as a monolithic integrated device die. In other arrangements, the first element includes a carrier or substrate (e.g., a semiconductor wafer) comprising multiple (e.g., tens, hundreds, or more) device regions that, when monolithically formed, create multiple integrated device dies; however, in other embodiments, such a carrier may be a packaging substrate or a passive or active interpolation layer. Similarly, the second element 604 may include a monolithic element, such as a monolithic integrated device die. In other arrangements, the second element 604 may include a carrier or substrate (e.g., a semiconductor wafer). The embodiments disclosed herein can therefore be applied to wafer-to-wafer (W2W), die-to-die (D2D), or die-to-wafer (D2W) bonding processes. In a W2W process, two or more wafers may be directly bonded to each other (e.g., direct hybrid bonding) and monolithically formed using a suitable monolithic process. After monolithization, the side edges of the monolithic structure (e.g., the side edges of the two joining elements) can be substantially flush (substantially aligned xy dimensions), and / or the edges for the joining interface of both the joining and monolithic elements can extend together and may include a mark indicating the common monolithic process of the joining structure (e.g., a saw mark if a sawing monolithic process is used).

[0070] Although only two elements 602 and 604 are shown, any suitable number of elements can be stacked in the bonding structure 600. For example, a third element (not shown) can be stacked on top of the second element 604, etc. In this embodiment, substrate vias can be formed to provide vertical electrical connections between and / or among vertically stacked elements. Additionally or alternatively, one or more additional elements (not shown) can be stacked laterally adjacent to each other along the first element 602. In some embodiments, the laterally stacked additional elements may be smaller than the second element. In some embodiments, the bonding structure can be encapsulated with an insulating material such as an inorganic dielectric (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.). One or more insulating layers can be provided on the bonding structure. For example, in some embodiments, a first insulating layer can be conformally deposited on the bonding structure, and a second insulating layer (which may include the same material or a different material as the first insulating layer) can be provided on top of the first insulating layer.

[0071] To achieve direct bonding between bonding layers 608a and 608b, bonding layers 608a and 608b can be prepared for direct bonding. Non-conductive bonding surfaces 612a and 612b on the upper or outer surfaces of bonding layers 608a and 608b can be prepared for direct bonding by polishing, for example, by chemical mechanical polishing (CMP). The roughness of the polished bonding surfaces 612a and 612b can be less than 30 Å rms. For example, the roughness of the polished bonding surfaces 612a and 612b can be in the range of approximately 0.1 Å rms to 15 Å rms, 0.5 Å rms to 10 Å rms, or 1 Å rms to 5 Å rms. Polishing can also be adjusted to make conductive features 606a and 606b recessed relative to the field regions of bonding layers 608a and 608b.

[0072] Preparation for direct bonding may further include cleaning one or both of the bonding surfaces 612a, 612b, and exposing one or both of the bonding surfaces 612a, 612b to plasma and / or an etchant to activate at least one of the surfaces 612a, 612b. In some embodiments, one or both of the surfaces 612a, 612b may be terminated with a substance after activation or during activation (e.g., during a plasma and / or etchant process). Without being theoretically limited, in some embodiments, the activation process may be performed to break the chemical bonds at the bonding surfaces(s) 612a, 612b, and the termination process may provide additional chemicals at the bonding surfaces(s) 612a, 612b that alter the chemical bonds and / or improve the bonding energy during direct bonding. In some embodiments, activation and termination are provided in the same steps, for example, plasma to activate and terminate the surfaces(s) 612a, 612b. In other embodiments, one or both of the bonding surfaces 612a, 612b may be terminated in a separate treatment to provide additional substances for direct bonding. In various embodiments, the terminating material may include nitrogen. For example, in some embodiments, the bonding surfaces(s) 612a, 612b may be exposed to nitrogen-containing plasma. Other terminating materials may be suitable to improve the bonding energy, depending on the material of the bonding surfaces 612a, 612b. Furthermore, in some embodiments, the bonding surfaces(s) 612a, 612b may be exposed to fluorine. For example, one or more fluorine concentration peaks may be present at or near the bonding interface 618 between the first element 602 and the second element 604. Typically, fluorine concentration peaks appear at the interfaces between material layers. Additional examples of activation and / or termination treatments can be found in U.S. Patent No. 9,391,143, column 5, line 55 through column 7, line 3; column 8, line 52 through column 9, line 45; column 10, lines 24-36; column 11, lines 24-32, 42-47, 52-55, and 60-64; column 12, lines 3-14, 31-33, and 55-67; ​​column 14, lines 38-40 and 44-50; and U.S. Patent No. 10,434,749, column 4, lines 41-50; column 5, lines 7-22, 39, and 55-61; column 8, lines 25-31, 35-40, and 49-56; and column 12, lines 46-61, whose activation and termination teachings are incorporated herein by reference.

[0073] Therefore, in the direct bonding structure 600, the bonding interface 618 between the two non-conductive materials (e.g., bonding layers 608a, 608b) may include a very smooth interface with high nitrogen (or other terminating material) content and / or fluorine concentration peaks at the bonding interface 618. In some embodiments, the nitrogen and / or fluorine concentration peaks can be detected using various types of detection techniques such as SIMS technology. After the activation process, the polished bonding surfaces 612a and 612b may be slightly rough (e.g., approximately 1 Å rms to 30 Å rms, 3 Å rms to 20 Å rms, or possibly rougher). In some embodiments, activation and / or termination may result in a slightly smoother surface before bonding, such as plasma treatment preferably eroding the high points on the bonding surface.

[0074] Non-conductive bonding layers 608a, 608b can be directly bonded to each other without an adhesive. In some embodiments, elements 602, 604 are aggregated together at room temperature without the need for voltage application and without the need for external pressure or force exceeding the application required to initiate contact between the two elements 602, 604. Contact can alone cause direct bonding (e.g., covalent dielectric bonding) between the non-conductive surfaces of bonding layers 608a, 608b. Subsequent annealing of the bonding structure 600 can cause the conductive features 606a, 606b to bond directly.

[0075] In some embodiments, prior to direct bonding, conductive features 606a and 606b are recessed relative to the surrounding field region such that the total gap between the opposing contacts after dielectric bonding and before annealing is less than 15 nm, or less than 10 nm. Because the recess depth of conductive features 606a and 606b can vary on each element due to process variations, the noted gap may represent the maximum or average gap between the corresponding conductive features 606a and 606b of the two bonded elements (before annealing). During annealing, conductive features 606a and 606b may expand and contact each other to form a metal-to-metal direct bond.

[0076] During annealing, the conductive features 606a, 606b (e.g., metallic materials) can expand, while the direct bonding between the non-conductive materials surrounding the bonding layers 608a, 608b resists the separation of the elements, causing thermal expansion to increase the internal contact pressure between the opposing conductive features. Annealing can also cause the growth of metallic grains at the bonding interface, allowing grains from one element to migrate at least partially to the other element, and vice versa. Therefore, in some hybrid bonding embodiments, opposing conductive materials are bonded without heating above the melting temperature of the conductive materials, allowing bonding to be formed at a lower annealing temperature compared to welding or thermocompression bonding.

[0077] In various embodiments, conductive features 606a, 606b may include discrete pads, contacts, electrodes, or traces at least partially embedded in non-conductive field regions of bonding layers 608a, 608b. In some embodiments, conductive features 606a, 606b may include exposed contact surfaces of TSVs (e.g., through-silicon vias).

[0078] As noted above, in some embodiments, prior to direct engagement... Figure 6A In elements 602 and 604, portions of the corresponding conductive features 606a and 606b may be recessed below the non-conductive bonding surfaces 612a and 612b, for example, with a recess of less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, for example, a recess in the range of 2 nm to 20 nm, or in the range of 4 nm to 10 nm. Due to process variations, both the dielectric thickness and the conductor recess depth can vary on the element. Therefore, the above recess depth range can be applied to individual conductive features 606a and 606b or to the average depth of the recess relative to a local non-conductive field region. Even for individual conductive features 606a and 606b, the vertical recess can vary on the feature and can therefore be measured at or near the lateral midpoint or center of the cavity forming a given conductive feature 606a or 606b, or on the side of the cavity.

[0079] Advantageously, hybrid bonding technologies (such as direct bonding interconnects, or DBI) ® The use of technology acquired from Adeia of San Joes, CA enables high-density connections (e.g., for small or fine pitches in regular arrays) between conductive features 606a, 606b on the direct bonding interface 618.

[0080] In some embodiments, the pitch p of conductive features 606a and 606b, such as conductive traces embedded in the bonding surface of an element in a bonding element, may be less than 40 μm, less than 20 μm, less than 10 μm, less than 5 μm, less than 2 μm, or even less than 1 μm. For some applications, the ratio of the pitch of conductive features 606a and 606b to one of the lateral dimensions (e.g., diameter) of the bonding pad is less than 20, or less than 10, or less than 5, or less than 3, and sometimes desirably less than 2. In various embodiments, conductive features 606a and 606b and / or traces may comprise copper or a copper alloy, although other materials may be suitable, such as nickel, aluminum, or alloys thereof. The conductive features disclosed herein, such as conductive features 606a and 606b, may comprise fine-grained metals (e.g., fine-grained copper). In addition, the main lateral dimensions (such as pad diameter) can also be small, for example, in the range of approximately 0.25 μm to 30 μm, in the range of approximately 0.25 μm to 5 μm, or in the range of approximately 0.5 μm to 5 μm.

[0081] For hybrid bonding elements 602 and 604, as shown, the orientation of one or more conductive features 606a, 606b from opposing elements may be opposite to each other. As is known in the art, conductive features can generally be formed with near-vertical sidewalls, particularly where directional reactive ion etching (RIE) defines the conductor sidewalls directly by etching the conductive material or indirectly by etching the surrounding insulator in a damascene process. However, some slight taper of the conductor sidewalls may be present, where the conductor becomes narrower further away from the surface initially exposed to the etch. The taper can be even more pronounced when the conductive sidewalls are defined directly or indirectly by isotropic wet or dry etching. In the illustrated embodiment, at least one conductive feature 606b (and / or at least one internal conductive feature, such as a BEOL feature) in the bonding layer 608b of the upper element 604 may taper or narrow upward away from the bonding surface 612b. In contrast, at least one conductive feature 606a (and / or at least one internal conductive feature, such as a BEOL feature) in the bonding layer 608a of the lower element 602 may taper or narrow downward away from the bonding surface 612a. Similarly, any bonding layer (not shown) on the back surfaces 616a, 616b of elements 602, 604 may taper or narrow away from the back surface, having an opposite taper orientation to the front conductive features 606a, 606b of the same element.

[0082] As described above, during the annealing stage of the hybrid bonding process, conductive features 606a and 606b can expand and contact each other to form a direct metal-to-metal bond. In some embodiments, the materials of conductive features 606a and 606b of opposite elements 602 and 604 can diffuse into each other during the annealing process. In some embodiments, metal grains grow into each other at the bonding interface 618. In some embodiments, the metal is or includes copper, which may have grains oriented along the 111 crystal plane to improve copper diffusion at the bonding interface 618. In some embodiments, conductive features 606a and 606b may include a nanotwinned copper grain structure, which may facilitate the merging of conductive features during annealing. At or near the bonding conductive features 606a and 606b, there is substantially no gap between the non-conductive bonding layers 608a and 608b. In some embodiments, a barrier layer (e.g., which may include copper) may be provided below and / or laterally around the conductive features 606a and 606b. In other embodiments, however, there may be no barrier layer beneath the conductive features 606a and 606b.

[0083] In the foregoing specification, the system and process have been described with reference to specific embodiments thereof. However, it will be apparent that various modifications and changes can be made to it without departing from the broader spirit and scope of the embodiments disclosed herein. Therefore, the specification and drawings are to be considered illustrative rather than restrictive.

[0084] In fact, although systems and processes have been disclosed in the context of certain embodiments and examples, those skilled in the art should understand that various embodiments of the systems and processes extend beyond the specifically disclosed embodiments to other alternative embodiments and / or uses of the systems and processes, as well as their obvious modifications and equivalents. Furthermore, although several variations of embodiments of the systems and processes have been shown and described in detail, other modifications within the scope of this disclosure will be apparent to those skilled in the art based on this disclosure. It is also contemplated that specific features of the embodiments and various combinations or sub-combinations of the embodiments can be implemented and still fall within the scope of this disclosure. It should be understood that various features and embodiments of the disclosed embodiments can be combined or substituted with each other to form variations of embodiments of the disclosed systems and processes. No method disclosed herein needs to be performed in the stated order. Therefore, the scope of the systems and processes disclosed herein should not be limited to the specific embodiments described above.

[0085] It should be understood that the systems and methods of this disclosure each have several novel embodiments, wherein no single embodiment is solely responsible for or required to achieve the desired properties disclosed herein. The various features and processes described above may be used independently of each other or may be combined in various ways. All possible combinations and sub-combinations are intended to fall within the scope of this disclosure.

[0086] In the context of individual embodiments, some features described herein may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as acting in certain combinations and even initially claimed in this way, one or more features from a claimed combination may be removed from that combination in some cases, and the claimed combination may involve sub-combinations or variations thereof. No single feature or group of features is required or indispensable for every embodiment.

[0087] It should also be understood that the conditional language used herein, such as “can,” “could,” “might,” “may,” “for example,” etc., unless otherwise specifically stated or understood in the context in which they are used, is generally intended to convey that certain embodiments include certain features, elements, and / or steps that are not included in other embodiments. Therefore, such conditional language is not generally intended to imply that features, elements, and / or steps are required in any way for one or more embodiments, or that one or more embodiments must include logic for determining, with or without author input or prompting, whether such features, elements, and / or steps are included in any particular embodiment or to be performed in any particular embodiment. The terms “comprising,” “including,” “having,” etc., are synonymous and used inclusively in an open-ended manner, and do not exclude additional elements, features, actions, operations, etc. Furthermore, the term “or” is used in its inclusive sense (rather than in its exclusionary sense) such that when used, for example, to connect a list of elements, the term “or” means one, some, or all of the elements in the list. Furthermore, the articles “a,” “an,” and “the” used in this application and the appended claims are to be interpreted as meaning “one or more” or “at least one,” unless otherwise stated. Similarly, although operations may be depicted in the drawings in a specific order, it should be understood that such operations need not be performed in the specific order shown or in a sequential order, or that all illustrated operations are performed to achieve the desired result. Furthermore, the drawings may schematically depict one or more example processes in the form of flowcharts. However, other operations not depicted may be incorporated into the schematically illustrated example methods and processes. For example, one or more additional operations may be performed before, after, simultaneously with, or between any of the illustrated operations. Furthermore, in other embodiments, operations may be rearranged or reordered. Additionally, other embodiments are within the scope of the following claims. In some cases, the actions described in the claims may be performed in a different order and still achieve the desired result.

[0088] Furthermore, while the methods and apparatus described herein are readily subject to various modifications and substitutions, specific examples have been shown in the accompanying drawings and described in detail herein. However, it should be understood that embodiments are not limited to the specific forms or methods disclosed, but rather, embodiments will cover all modifications, equivalents, and substitutions falling within the spirit and scope of the various implementations described and the appended claims. Furthermore, any particular feature, aspect, method, characteristic, feature, quality, property, element, etc., disclosed herein in conjunction with an implementation or embodiment may be used in all other implementations or embodiments set forth herein. No method disclosed herein needs to be performed in the order described. Methods disclosed herein may include certain actions taken by a practitioner; however, methods may also explicitly or implicitly include any third-party instructions regarding those actions. The scope of this disclosure also covers any and all its overlaps, subscopes, and combinations. Languages ​​such as “at most,” “at least,” “greater than,” “less than,” “between,” etc., include the stated numbers. Numbers preceded by terms such as “about” or “approximately” include the stated numbers and should be interpreted on a case-by-case basis (e.g., as accurately as reasonably possible in the case, such as ±5%, ±10%, ±15%, etc.). For example, "approximately 3.5 mm" includes "3.5 mm". Phrases preceded by terms such as "substantially" include the stated phrase and should be interpreted on a case-by-case basis (e.g., interpreted as reasonably possible under the circumstances). For example, "substantially constant" includes "constant". Unless otherwise stated, all measurements are taken under standard conditions including temperature and pressure.

[0089] As used herein, the phrase “at least one of…” in a list of items refers to any combination of those items, including a single item. For example, “at least one of A, B, or C” is intended to cover: A, B, and C; A and B; A and C; B and C; and A, B, and C. Unless otherwise expressly stated, combined language such as the phrase “at least one of X, Y, and Z” is also understood in context to generally convey that an item, term, etc., may be at least one of X, Y, or Z. Therefore, such combined language is not generally intended to imply that some embodiments require at least one of X, at least one of Y, and at least one of Z to be present individually. The headings provided herein, if any, are for convenience only and do not necessarily affect the scope or meaning of the devices and methods disclosed herein.

[0090] Therefore, the claims are not intended to limit the embodiments shown herein, but should be accorded the widest scope consistent with the disclosure, principles and novel features disclosed herein.

Claims

1. A joining structure, comprising: carrier; A first memory cell is disposed on the carrier, the first memory cell including a first memory channel, the first memory cell including a first plurality of memory dies directly coupled to each other; The second memory cell includes a second memory channel that is different from the first memory channel. The second memory cell includes a second plurality of memory dies that are directly coupled to each other. The second memory cell is stacked on top of the first memory cell. as well as A serializer-deserializer is disposed in or on the carrier and electrically connected to the first memory channel of the first memory cell and the second memory channel of the second memory cell. The serializer-deserializer has an external channel configured to electrically connect the bonding structure to the processor.

2. The bonding structure according to claim 1, wherein the carrier comprises a logic die.

3. The bonding structure according to claim 1 further includes a logic die. The carrier includes an intercalation layer, and The logic die is disposed between the first memory cell and the interpolation layer.

4. The joining structure according to claim 1, further comprising: Encapsulation body; as well as Logic chip The carrier includes a redistribution layer; The logic die is disposed between the first memory cell and the redistribution layer; The first memory cell, the second memory cell, the logic die, and the serializer-deserializer are partially enclosed within the encapsulation.

5. The bonding structure according to claim 1 further includes a logic die. The carrier includes a printed circuit board. The logic die is disposed between the first memory cell and the printed circuit board.

6. The bonding structure according to any one of claims 1 to 5, wherein the first memory cell is directly coupled to the second memory cell.

7. The bonding structure according to any one of claims 1 to 5, wherein the first memory cell is directly bonded to the carrier.

8. The bonding structure according to any one of claims 1 to 5, wherein the serializer-deserializer is directly coupled to the carrier.

9. A structure comprising: A first memory cell has a top surface and a bottom surface, the first memory cell comprising a first plurality of memory dies directly coupled to each other; The second memory cell has a top surface and a bottom surface, and the second memory cell includes a second plurality of memory dies that are directly coupled together with each other; Logic die, having a top surface and a bottom surface; as well as Serializer-deserializer, with a top surface and a bottom surface. The bottom surface of the second memory cell is disposed on the top surface of the first memory cell. The bottom surface of the first memory cell is disposed on the top surface of the logic die. The bottom surface of the serializer-deserializer is disposed on the top surface of the logic die. The structure described therein has a first number of internal channels electrically connecting the serializer-deserializer, the logic die, the first memory cell, and the second memory cell. The structure described herein has a second number of external channels configured to electrically connect the structure to the processor. The first number is greater than the second number.

10. The structure according to claim 9, wherein the first number of internal channels is two, and wherein the second number of external channels is one.

11. The structure according to claim 9, wherein the first number of internal channels is four, and wherein the second number of external channels is one.

12. The structure according to any one of claims 9 to 11, wherein the second memory cell is directly coupled to the first memory cell.

13. The structure according to any one of claims 9 to 12, wherein the first memory cell is directly coupled to the logic die.

14. The structure according to any one of claims 9 to 13, wherein the serializer-deserializer is directly coupled to the logic die.

15. The structure according to any one of claims 9 to 14, wherein the first internal channel is electrically connected to the active circuitry of the first memory cell, wherein the second internal channel is electrically connected to the active circuitry of the second memory cell, wherein the second internal channel is not electrically connected to the active circuitry of the first memory cell.

16. A structure comprising: A first memory cell has a top surface and a bottom surface, the first memory cell comprising a first plurality of memory dies directly coupled to each other; The second memory cell has a top surface and a bottom surface, and the second memory cell includes a second plurality of memory dies that are directly coupled together with each other; Logic die, having a top surface and a bottom surface; An intercalation layer having a top surface and a bottom surface; as well as Serializer-deserializer, with a top surface and a bottom surface; The bottom surface of the second memory cell is disposed on the top surface of the first memory cell; The bottom surface of the first memory cell is disposed on the top surface of the logic die; The bottom surface of the logic die is disposed on the top surface of the interpolation layer; The bottom surface of the serializer-deserializer is disposed on the top surface of the interpolation layer; The structure described therein has a first number of internal channels that electrically connect the serializer-deserializer, the logic die, the first memory cell, and the second memory cell; The structure described above has a second number of external channels configured to electrically connect the structure to a processor; and The first number is greater than the second number.

17. The structure of claim 16, wherein the first number of internal channels is two, and wherein the second number of external channels is one.

18. The structure of claim 16, wherein the first number of internal channels is four, and wherein the second number of external channels is one.

19. The structure according to any one of claims 16 to 18, wherein the second memory cell is directly coupled to the first memory cell.

20. The structure according to any one of claims 16 to 19, wherein the first memory cell is directly coupled to the logic die.

21. The structure according to any one of claims 16 to 20, wherein the serializer-deserializer is directly coupled to the interpolation layer.

22. The structure according to any one of claims 16 to 21, wherein the logic die is directly mixed-bonded to the interpolation layer.

23. The structure according to any one of claims 16 to 22, wherein the first internal channel is electrically connected to the active circuitry of the first memory cell, wherein the second internal channel is electrically connected to the active circuitry of the second memory cell, wherein the second internal channel is not electrically connected to the active circuitry of the first memory cell.

24. A structure comprising: A first memory cell has a top surface and a bottom surface, the first memory cell comprising a first plurality of memory dies directly coupled to each other; The second memory cell has a top surface and a bottom surface, and the second memory cell includes a second plurality of memory dies that are directly coupled together with each other; Logic die, having a top surface and a bottom surface; Redistribution layer; Serializer-deserializer, with a top surface and a bottom surface; and Encapsulation body; The bottom surface of the second memory cell is disposed on the top surface of the first memory cell; The bottom surface of the first memory cell is disposed on the top surface of the logic die; The first memory cell, the second memory cell, the logic die, and the serializer-deserializer are at least partially enclosed within the encapsulation. The top surface of the logic die and the top surface of the serializer-deserializer are exposed; The redistribution layer is formed on the top surface of the serializer-deserializer and the top surface of the logic die; The redistribution layer is electrically connected to the serializer-deserializer and the logic die; The redistribution layer is configured to electrically connect the serializer-deserializer to the processor; The structure described above has a first number of internal channels electrically connecting the serializer-deserializer, the logic die, the first memory cell, and the second memory cell; and The structure has a second number of external channels configured to electrically connect the structure to a processor; The first number is greater than the second number.

25. The structure according to claim 24, wherein the first number of internal channels is two, and wherein the second number of external channels is one.

26. The structure of claim 24, wherein the first number of internal channels is four, and wherein the second number of external channels is one.

27. The structure according to any one of claims 24 to 26, wherein the second memory cell is directly coupled to the first memory cell.

28. The structure according to any one of claims 24 to 27, wherein the first memory cell is directly coupled to the logic die.

29. The structure according to any one of claims 24 to 28, wherein the redistribution layer is deposited.

30. The structure according to any one of claims 24 to 29, wherein the redistribution layer is directly coupled to the logic die and the serializer-deserializer.

31. The structure according to any one of claims 24 to 30, wherein the first internal channel is electrically connected to the active circuitry of the first memory cell, wherein the second internal channel is electrically connected to the active circuitry of the second memory cell, wherein the second internal channel is not electrically connected to the active circuitry of the first memory cell.

32. A structure comprising: A first memory cell has a top surface and a bottom surface, the first memory cell comprising a first plurality of memory dies directly coupled to each other; The second memory cell has a top surface and a bottom surface, and the second memory cell includes a second plurality of memory dies that are directly coupled together with each other; Logic die, having a top surface and a bottom surface; Substrate; as well as Serializer-deserializer, with a top surface and a bottom surface. The bottom surface of the second memory cell is disposed on the top surface of the first memory cell. The bottom surface of the first memory cell is disposed on the top surface of the logic die. The top surface of the logic die is disposed on the bottom surface of the substrate. The serializer-deserializer is embedded in the substrate. The serializer-deserializer is electrically connected to the logic die. The structure described therein has a first number of internal channels electrically connecting the serializer-deserializer, the logic die, the first memory cell, and the second memory cell. The structure described therein has a second number of external channels configured to electrically connect the serializer-deserializer to the processor. The first number is greater than the second number.

33. The structure according to claim 32, wherein the first number of internal channels is two, and wherein the second number of external channels is one.

34. The structure according to claim 32, wherein the first number of internal channels is four, and wherein the second number of external channels is one.

35. The structure according to any one of claims 32 to 34, wherein the second memory cell is directly coupled to the first memory cell.

36. The structure according to any one of claims 32 to 35, wherein the first memory cell is directly coupled to the logic die.

37. The structure according to any one of claims 32 to 36, wherein the first internal channel is electrically connected to the active circuitry of the first memory cell, wherein the second internal channel is electrically connected to the active circuitry of the second memory cell, wherein the second internal channel is not electrically connected to the active circuitry of the first memory cell.

38. The structure according to any one of claims 32 to 37, wherein the substrate comprises a printed circuit board.

39. A joining structure, comprising: carrier; A first memory cell is disposed on the carrier, the first memory cell including a first memory channel and a first plurality of memory dies that are directly coupled to each other; The second memory cell includes a second memory channel that is different from the first memory channel and a second plurality of memory dies that are directly mixed and bonded to each other, and the second memory cell is stacked on top of the first memory cell; as well as A serializer-deserializer is directly coupled to the carrier and electrically connected to the first memory channel of the first memory cell and the second memory channel of the second memory cell, the serializer-deserializer having an external channel configured to electrically connect the coupling structure to the processor.

40. The bonding structure of claim 39, wherein the bonding structure has a first number of internal channels electrically connecting the serializer-deserializer, the carrier, the first memory cell and the second memory cell, wherein a second number of external channels are configured to electrically connect the structure to a processor, and wherein the first number is different from the second number.

41. The bonding structure according to any one of claims 39 to 40, wherein the carrier comprises a logic die.

42. The joining structure according to any one of claims 39 to 40, further comprising: Logic chip; The carrier includes an intercalation layer; as well as The logic die is disposed between the first memory cell and the interpolation layer.

43. The joining structure according to any one of claims 39 to 40, further comprising: Encapsulation body; as well as Logic chip; The carrier includes a redistribution layer; The logic die is disposed between the first memory cell and the redistribution layer; as well as The first memory cell, the second memory cell, the logic die, and the serializer-deserializer are partially enclosed within the encapsulation.

44. The joining structure according to any one of claims 39 to 40, further comprising: Logic chip; The carrier mentioned above includes a printed circuit board; as well as The logic die is disposed between the first memory cell and the printed circuit board.

45. The bonding structure according to any one of claims 39 to 44, wherein the first memory cell is directly coupled to the second memory cell.

46. ​​The bonding structure according to any one of claims 39 to 45, wherein the first memory cell is directly co-bonded to the carrier.

47. A joining structure, comprising: carrier; A first memory unit and a second memory unit, the first memory unit including a first memory channel, the second memory unit including a second memory channel different from the first memory channel, wherein the second memory unit is stacked on top of the first memory unit, wherein the first memory unit and the second memory unit are disposed on the carrier, wherein the first memory unit includes a first plurality of memory dies directly coupled to each other, and wherein the second memory unit includes a second plurality of memory dies directly coupled to each other. as well as A serializer-deserializer is disposed on or at least partially embedded in the carrier and electrically connected to the first memory channel of the first memory cell and the second memory channel of the second memory cell, the serializer-deserializer having an external channel configured to electrically connect the bonding structure to the processor.

48. The bonding structure of claim 47, wherein the bonding structure has a first number of internal channels electrically connecting the serializer-deserializer, the carrier, the first memory cell and the second memory cell, wherein a second number of external channels are configured to electrically connect the structure to a processor, and wherein the first number is different from the second number.

49. The bonding structure according to any one of claims 47 to 48, wherein the serializer-deserializer is directly coupled to the carrier.

50. The bonding structure according to any one of claims 47 to 49, wherein the carrier comprises a logic die.

51. The joining structure according to any one of claims 47 to 49, further comprising: Logic chip; The carrier includes an intercalation layer, and The logic die is disposed between the first memory cell and the interpolation layer.

52. The joining structure according to any one of claims 47 to 49, further comprising: Encapsulation body; as well as Logic chip; The carrier includes a redistribution layer; The logic die is disposed between the first memory cell and the redistribution layer; as well as The first memory cell, the second memory cell, the logic die, and the serializer-deserializer are partially enclosed in an encapsulation.

53. The joining structure according to any one of claims 47 to 49, further comprising: Logic chip; The carrier mentioned above includes a printed circuit board; as well as The logic die is disposed between the first memory cell and the printed circuit board.

54. The bonding structure according to any one of claims 47 to 53, wherein the first memory cell is directly coupled to the second memory cell.

55. The bonding structure according to any one of claims 47 to 54, wherein the first memory cell is directly co-bonded to the carrier.

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