Imaging device

Abstract

An imaging device is provided with a plurality of pixels 24. Each of the plurality of pixels 24 has a lower electrode 2, an upper electrode 5 disposed facing the lower electrode 2, a photoelectric conversion layer 4 that is located between the lower electrode 2 and the upper electrode 5, contains a donor semiconductor material and an acceptor semiconductor material, and generates signal charges, and a charge blocking layer 3 located between the photoelectric conversion layer 4 and the lower electrode 2. And a charge accumulation region that is electrically connected to the lower electrode 2 and accumulates signal charges. When the thickness of the charge blocking layer (3) is D and the area of the lower electrode (2) in planar view is S, D / [square root of] S > = 0.07 is satisfied.

Description

Technical Field

[0001] This disclosure relates to a filming device. Background Technology

[0002] As a MOS (Metal Oxide Semiconductor) type imaging device, a stacked imaging device has been proposed. In the stacked imaging device, a photoelectric conversion element including a photoelectric conversion layer is stacked on top of a semiconductor substrate, and electrodes are used to capture and store the charge generated by photoelectric conversion within the photoelectric conversion layer in a charge storage region. For example, Patent Document 1 discloses a stacked imaging device that uses a CCD (Charge Coupled Device) circuit or a CMOS (Complementary Metal Oxide Semiconductor) circuit within a semiconductor substrate to read out the charge stored in the charge storage region.

[0003] The photoelectric conversion element used in imaging devices sometimes has a structure consisting of multiple functional layers stacked together, such as a photoelectric conversion layer that absorbs light to generate signal charge and a charge blocking layer that suppresses charge injection from electrodes. For example, Patent Document 2 discloses an imaging device employing a photoelectric conversion element having a structure consisting of a photoelectric conversion layer and a charge blocking layer stacked together.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2007-311647

[0007] Patent Document 2: Japanese Patent Application Publication No. 2012-94660 Summary of the Invention

[0008] Imaging devices are used in various environments. For example, imaging devices used in surveillance or vehicle-mounted applications, where brightness varies significantly, require high-quality imaging regardless of the environment. That is, a wide dynamic range is important in terms of imaging device performance. Dynamic range is determined by the saturation signal and noise of the imaging device and can be achieved by increasing the saturation signal and / or reducing noise. Furthermore, reducing noise is also important for improving the quality of the captured images.

[0009] Therefore, this disclosure provides a shooting device with reduced noise.

[0010] One aspect of the imaging device disclosed herein includes a plurality of pixels, each of which comprises: a first electrode; a second electrode disposed opposite to the first electrode; a photoelectric conversion layer located between the first electrode and the second electrode, comprising a donor semiconductor material and an acceptor semiconductor material, for generating signal charge; an intermediate layer located between the photoelectric conversion layer and the first electrode; and a charge storage region electrically connected to the first electrode for storing the signal charge; wherein, given that the thickness of the intermediate layer is D and the area of ​​the first electrode in planar observation is S, D / √S ≥ 0.07 is satisfied.

[0011] Additionally, one aspect of the imaging device disclosed herein includes a plurality of pixels, each of which comprises: a first electrode; a second electrode disposed opposite to the first electrode; a photoelectric conversion layer located between the first electrode and the second electrode, comprising a donor semiconductor material and an acceptor semiconductor material to generate signal charge; an intermediate layer located between the photoelectric conversion layer and the first electrode; and a charge storage region electrically connected to the first electrode to store the signal charge; wherein the planar viewing shape of the first electrode is square, and given that the thickness of the intermediate layer is D and the length of one side of the square planar viewing shape of the first electrode is L, D / L≥0.07 is satisfied.

[0012] According to this disclosure, it is possible to provide a shooting device with reduced noise. Attached Figure Description

[0013] Figure 1 This is a schematic cross-sectional view showing the structure of the photoelectric conversion element in the embodiment.

[0014] Figure 2 This is an exemplary energy band diagram of the photoelectric conversion element of the embodiment.

[0015] Figure 3 This is a schematic cross-sectional view showing the structure of another photoelectric conversion element in the embodiment.

[0016] Figure 4 This is a diagram illustrating an example of the circuit structure of the imaging device according to an embodiment.

[0017] Figure 5 This is a schematic cross-sectional view showing the device structure of pixels in the imaging apparatus of the embodiment.

[0018] Figure 6 This is a plan view showing an exemplary electrode layout of the imaging device.

[0019] Figure 7 It is used to illustrate that in having Figure 2 The diagram shows the situation where an intermediate energy level is generated in the photoelectric conversion element with the shown band structure.

[0020] Figure 8 It is a diagram that illustratively represents the distribution of the amount of charge accumulated at charge accumulation nodes.

[0021] Figure 9 This is a graph showing the relationship between D / √S and random noise for the imaging apparatus of the embodiments and comparative examples.

[0022] Figure 10 This is a graph showing the relationship between D / L and random noise for the imaging apparatus of the embodiments and comparative examples. Detailed Implementation

[0023] (This is one way to make this public.)

[0024] In order to provide a shooting device with reduced noise, the inventors discovered the following problem.

[0025] When using a photoelectric conversion element in an imaging device with multiple stacked functional layers, the energy level design of the materials contained in each layer needs to be optimized. For example, the energy level of the material in the photoelectric conversion layer, which absorbs light to generate signal charge, significantly affects the sensitivity of the imaging device. Furthermore, the energy level of the material in intermediate layers, such as charge blocking layers, located between the photoelectric conversion layer and the electrodes, significantly affects the signal charge extraction efficiency. Additionally, in photoelectric conversion elements, intermediate energy levels are easily generated near the interfaces of adjacent layers due to film formation conditions and material polarization. In particular, since the intermediate layers and the photoelectric conversion layer, located between the photoelectric conversion layer and the electrodes, play different roles in the photoelectric conversion element, it is difficult to predict the generation of intermediate energy levels when designing the material energy levels. Due to the presence of intermediate energy levels, electrons are easily excited in these levels, and unlike signal charges generated by light, charges are easily generated by thermal excitation even in the dark. In imaging devices with multiple pixels, charges are generated in the region near the interfaces of adjacent layers in each pixel and are extracted into the electrodes of specific pixels with a certain probability, which can become a major cause of noise.

[0026] This disclosure is based on the insight that provides a photographic apparatus for reducing noise by minimizing the effects of charge generated by thermal excitation.

[0027] (Summary of this disclosure)

[0028] As a summary of one aspect of this disclosure, examples of the imaging apparatus of this disclosure are shown below.

[0029] The imaging device of the first aspect of this disclosure includes a plurality of pixels, each of which has: a first electrode; a second electrode disposed opposite to the first electrode; a photoelectric conversion layer located between the first electrode and the second electrode, comprising a donor semiconductor material and an acceptor semiconductor material to generate signal charge; an intermediate layer located between the photoelectric conversion layer and the first electrode; and a charge storage region electrically connected to the first electrode to store the signal charge; wherein, given that the thickness of the intermediate layer is D and the area of ​​the first electrode in planar observation is S, D / √S≥0.07 is satisfied.

[0030] Based on the structure of this method, a shooting device with reduced noise can be realized.

[0031] Specifically, the charge generated by thermal excitation near the interface between the photoelectric conversion layer and the intermediate layer depends on the size of the interface. That is, the larger the area of ​​the first electrode, which is related to the size of the substantial interface when viewed in a planar manner, the greater the amount of charge generated by thermal excitation. Since noise is proportional to the square root of the amount of charge accumulated in the charge accumulation region, noise increases as the charge generated by thermal excitation increases. On the other hand, if the thickness of the intermediate layer is large, it is difficult for the charge generated by thermal excitation to be taken into the first electrode. Typically, the charge generated in the photoelectric conversion layer is hopped between the materials contained in each layer and taken into the first electrode, where it is accumulated in the charge accumulation region. In this case, the charge generated by thermal excitation is hopped at least by the thickness of the intermediate layer, but if the hopping distance is long, the probability of deactivation increases, and the contribution of the charge generated by thermal excitation to noise decreases. Therefore, by adjusting the relationship between the thickness of the intermediate layer and the area of ​​the first electrode, noise can be reduced. With the thickness of the intermediate layer set as D and the area of ​​the first electrode set as S, sufficient noise reduction can be achieved if D / √S ≥ 0.07.

[0032] Furthermore, for example, in the second imaging apparatus of this disclosure, the thickness of the intermediate layer is 10 nm or more in the first imaging apparatus.

[0033] Thus, for example, even if a large potential difference is generated between the first electrode and the second electrode, leakage current from the first electrode to the photoelectric conversion layer can be suppressed.

[0034] Furthermore, for example, in the third-party imaging device disclosed herein, in the first or second type of imaging device, the signal charge is a hole, the intermediate layer contains a first semiconductor material, and the difference between the ionization potential of the first semiconductor material contained in the intermediate layer and the ionization potential of the donor semiconductor material contained in the photoelectric conversion layer is less than 1 eV.

[0035] Furthermore, for example, in the fourth imaging device of this disclosure, in the first or second imaging device, the signal charge is an electron, the intermediate layer contains a first semiconductor material, and the difference between the electron affinity of the first semiconductor material contained in the intermediate layer and the electron affinity of the acceptor semiconductor material contained in the photoelectric conversion layer is less than 1 eV.

[0036] Therefore, the signal charge generated in the photoelectric conversion layer when irradiated by light can be easily transported from the photoelectric conversion layer to the first electrode through the intermediate layer, thereby improving the efficiency of signal charge extraction.

[0037] Furthermore, for example, in any of the first to fourth methods of the imaging apparatus disclosed in the fifth method, the plurality of pixels further have a charge blocking layer located between the second electrode and the photoelectric conversion layer.

[0038] This allows for the suppression of leakage current from the second electrode to the photoelectric conversion layer.

[0039] Furthermore, for example, in the sixth imaging apparatus of this disclosure, the thickness of the charge blocking layer is 5 nm or more in the fifth imaging apparatus.

[0040] Thus, for example, even if a large potential difference is generated between the first electrode and the second electrode, leakage current from the second electrode to the photoelectric conversion layer can be suppressed.

[0041] Furthermore, for example, in the seventh imaging device of this disclosure, in the fifth or sixth imaging device, the signal charge is a hole, the charge blocking layer contains a second semiconductor material, and the difference between the electron affinity of the second semiconductor material contained in the charge blocking layer and the electron affinity of the acceptor semiconductor material contained in the photoelectric conversion layer is less than 1 eV.

[0042] Furthermore, for example, in the eighth imaging device of this disclosure, in the fifth or sixth imaging device, the signal charge is an electron, the charge blocking layer contains a second semiconductor material, and the difference between the ionization potential of the second semiconductor material contained in the charge blocking layer and the ionization potential of the donor semiconductor material contained in the photoelectric conversion layer is less than 1 eV.

[0043] Therefore, charges with opposite polarity to the signal charges generated in the photoelectric conversion layer during light irradiation are easily transported from the photoelectric conversion layer to the second electrode via the charge blocking layer. Charges with opposite polarity to the signal charges generated in the photoelectric conversion layer are difficult to recombine with the signal charges, thus suppressing the decrease in sensitivity.

[0044] Furthermore, for example, the shooting device of the ninth aspect of this disclosure satisfies D / √S≥0.14 in any of the shooting devices of the first to eighth aspects.

[0045] This enables the development of a shooting device with further reduced noise.

[0046] Furthermore, for example, the shooting device of the tenth aspect of this disclosure satisfies D / √S≥0.21 in any of the shooting devices of the first to ninth aspects.

[0047] This enables the development of a shooting device with further reduced noise.

[0048] Furthermore, for example, the imaging device of the eleventh aspect of this disclosure includes a plurality of pixels, each of which has: a first electrode; a second electrode disposed opposite to the first electrode; a photoelectric conversion layer located between the first electrode and the second electrode, comprising a donor semiconductor material and an acceptor semiconductor material to generate signal charge; an intermediate layer located between the photoelectric conversion layer and the first electrode; and a charge storage region electrically connected to the first electrode to store the signal charge; wherein the planar viewing shape of the first electrode is square, and the thickness of the intermediate layer is D, and the length of one side of the square of the planar viewing shape of the first electrode is L, satisfying D / L≥0.07.

[0049] Based on the structure of this method, a shooting device with reduced noise can be achieved, similar to the shooting device of the first method.

[0050] The embodiments will now be described with reference to the accompanying drawings.

[0051] Furthermore, the embodiments described below are either general or specific examples. The numerical values, shapes, constituent elements, arrangement positions of constituent elements, connection methods, steps, and order of steps shown in the following embodiments are examples and are not intended to limit this disclosure. In addition, constituent elements in the following embodiments that are not described in the independent claims are described as optional constituent elements.

[0052] In addition, the figures may not be strictly representational. In the figures, the same reference numerals are used to label the same actual structures, and sometimes repeated descriptions are omitted or simplified.

[0053] Furthermore, in this specification, terms such as vertical to indicate the relationship between elements, terms such as rectangle to indicate the shape of elements, and numerical ranges are not merely expressions of a strict meaning, but rather expressions that also include substantially equivalent ranges.

[0054] Furthermore, in this specification, the terms "above" and "below" do not refer to "above" (vertically above) and "below" (vertically below) in absolute spatial recognition, but are used as terms defined by relative positional relationships based on the stacking order in a layered structure. Additionally, the terms "above" and "below" are merely used to specify the mutual arrangement between components and are not intended to limit the posture of the imaging device during use. Furthermore, the terms "above" and "below" apply not only to cases where two constituent elements are arranged apart from each other and other constituent elements exist between them, but also to cases where two constituent elements are arranged closely together and connected.

[0055] Furthermore, unless otherwise specified, "planar view" in this specification refers to view from a direction perpendicular to the main surface of the photoelectric conversion layer. Additionally, in this specification, the main surface is a surface perpendicular to the thickness direction, and the direction perpendicular to the main surface of the photoelectric conversion layer coincides with the thickness direction of each layer or electrode in the photoelectric conversion element.

[0056] In addition, for convenience, electromagnetic waves including visible light, infrared light and ultraviolet light are collectively referred to as "light" in this specification.

[0057] (Implementation Method)

[0058] The following describes this embodiment.

[0059] [Photoelectric conversion element]

[0060] First, use Figure 1 The photoelectric conversion element included in the imaging device of this embodiment will be described. The photoelectric conversion element of this embodiment is a charge readout type photoelectric conversion element. Figure 1 This is a schematic cross-sectional view showing the structure of the photoelectric conversion element 10 in this embodiment.

[0061] like Figure 1 As shown, the photoelectric conversion element 10 is supported by a support substrate 1 and includes an upper electrode 5 and a lower electrode 2 as a pair of electrodes, a photoelectric conversion layer 4 located between the upper electrode 5 and the lower electrode 2, and a charge blocking layer 3 located between the lower electrode 2 and the photoelectric conversion layer 4. In this embodiment, the lower electrode 2 is an example of a first electrode, and the upper electrode 5 is an example of a second electrode. Furthermore, the charge blocking layer 3 is an example of an intermediate layer.

[0062] The photoelectric conversion element 10 is used, for example, in a configuration in which light transmitted through the upper electrode 5 is incident on the photoelectric conversion layer 4.

[0063] Hereinafter, the constituent elements of the photoelectric conversion element 10 of this embodiment will be described.

[0064] The support substrate 1 can be any substrate used to support a typical photoelectric conversion element, such as a glass substrate, quartz substrate, semiconductor substrate, or plastic substrate.

[0065] The lower electrode 2 and the upper electrode 5 are film-shaped electrodes arranged opposite each other.

[0066] The lower electrode 2 captures the signal charge generated in the photoelectric conversion layer 4. The lower electrode 2 is formed of a metal, a metal nitride, a metal oxide, or polycrystalline silicon that has been given conductivity. Examples of metals include aluminum, copper, titanium, and tungsten. Examples of methods for giving polycrystalline silicon conductivity include adding impurities.

[0067] The upper electrode 5 is disposed opposite to the lower electrode 2, separated by the photoelectric conversion layer 4. The upper electrode 5 is, for example, a transparent electrode formed of a transparent conductive material. Examples of materials for the upper electrode 5 include transparent conductive oxide (TCO), indium tin oxide (ITO), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), flotation oxide (FTO), SnO2, and TiO2. Alternatively, the upper electrode 5 may be fabricated using TCO and various metallic materials such as aluminum (Al) and gold (Au), either individually or in combination, depending on the desired transmittance.

[0068] Furthermore, the materials used for the lower electrode 2 and the upper electrode 5 are not limited to the conductive materials described above, and other materials may also be used. For example, the lower electrode 2 may also be a transparent electrode.

[0069] In the fabrication of the lower electrode 2 and the upper electrode 5, various methods are used depending on the materials used. For example, when using ITO, methods such as electron beam deposition, sputtering, resistance heating vapor deposition, chemical reaction methods such as sol-gel deposition, and coating of indium tin oxide dispersions can be used. In this case, after forming the ITO film, the lower electrode 2 and the upper electrode 5 can be further treated with UV-ozone or plasma treatment.

[0070] The photoelectric conversion layer 4 generates electrons and holes by absorbing light. One of the electrons and holes is used as a signal charge. That is, the photoelectric conversion layer 4 converts light into signal charge.

[0071] The photoelectric conversion layer 4 may include, for example, a donor semiconductor material and an acceptor semiconductor material. The photoelectric conversion layer 4 may be fabricated using, for example, an organic semiconductor material. The fabrication method for the photoelectric conversion layer 4 may include, for example, a wet method such as spin coating, or a dry method such as vacuum evaporation. Vacuum evaporation is a method that vaporizes the material of the layer by heating it under vacuum and deposits it onto a substrate. Furthermore, the charge blocking layer 3 may also be fabricated using the same method as the photoelectric conversion layer 4.

[0072] Furthermore, the photoelectric conversion layer 4 is, for example, a hybrid film comprising a donor semiconductor material such as a donor organic semiconductor material and an acceptor semiconductor material such as an acceptor organic semiconductor material. Alternatively, the photoelectric conversion layer 4 may have a stacked structure consisting of layers of donor semiconductor material and layers of acceptor semiconductor material.

[0073] The photoelectric conversion layer 4 is readily formed as a thin film by comprising a donor organic semiconductor material and an acceptor organic semiconductor material. Hereinafter, specific examples of donor and acceptor organic semiconductor materials will be given.

[0074] Examples of donor organic semiconductor materials include triarylamine compounds, benzidine compounds, pyrazoline compounds, styreneamine compounds, hydrazone compounds, triphenylmethane compounds, carbazole compounds, polysilane compounds, thiophene compounds, phthalocyanine compounds, naphthalenephthalocyanine compounds, phthalocyanine compounds, anthocyanin compounds, oxonol compounds, polyamine compounds, indole compounds, pyrrole compounds, pyrazole compounds, biphenyl compounds, terphenyl compounds, polyaryl compounds, fused aromatic carbocyclic compounds, and metal complexes with nitrogen-containing heterocyclic compounds as ligands.

[0075] Fused aromatic carbocyclic compounds include, for example, naphthalene derivatives, anthracene derivatives, phenanthrene derivatives, tetraphenyl derivatives, pyrene derivatives, perylene derivatives, and fluoranthene derivatives.

[0076] Examples of acceptor organic semiconductor materials include fullerenes, fullerene derivatives, fused aromatic carbocyclic compounds, 5- to 7-membered heterocyclic compounds containing nitrogen, oxygen, and sulfur atoms, polyarylene compounds, fluorene compounds, cyclopentadiene compounds, silyl compounds, and metal complexes with nitrogen-containing heterocyclic compounds as ligands.

[0077] Fullerenes include, for example, C60 fullerenes and C70 fullerenes.

[0078] Fullerene derivatives include, for example, PCBM (methyl phenyl C61 butyrate) and ICBA (indene C60 diadduct).

[0079] Five- to seven-membered heterocyclic compounds containing nitrogen, oxygen, and sulfur atoms include pyridine, pyrazine, pyrimidine, pyridazine, triazine, quinoline, quinoxaline, quinazoline, phthalazine, cinnamic acid, isoquinoline, pteridine, acridine, phenazine, phenanthrene, tetrazolium, pyrazole, imidazole, thiazole, oxazole, indazole, benzimidazole, benzoindole, benzoxazole, benzothiazole, carbazole, purine, triazolopyridazine, triazolopyrimidine, tetrazalind, oxadiazole, imidazolepyridine, pyrrolidine, pyrrolopyridine, thiadiazopyridine, dibenzoacoxane, and tribenzoacoxane, etc.

[0080] Furthermore, the donor organic semiconductor materials and acceptor organic semiconductor materials are not limited to the examples mentioned above. As long as the organic compound can be formed as a photoelectric conversion layer by either dry or wet methods, low-molecular-weight compounds and high-molecular-weight compounds can be used as the donor organic semiconductor materials and acceptor organic semiconductor materials constituting the photoelectric conversion layer 4.

[0081] In addition, the photoelectric conversion layer 4 may also contain semiconductor materials other than organic semiconductor materials as donor and acceptor semiconductor materials. As semiconductor materials, the photoelectric conversion layer 4 may contain silicon semiconductors, compound semiconductors, quantum dots, perovskite materials, carbon nanotubes, etc., or any two or more of them.

[0082] As described above, the photoelectric conversion element 10 of this embodiment includes a charge blocking layer 3 disposed between the lower electrode 2 and the photoelectric conversion layer 4. The charge blocking layer 3 is, for example, connected to the lower electrode 2 and the photoelectric conversion layer 4.

[0083] The charge-blocking layer 3 may contain, for example, a first semiconductor material. The first semiconductor material may be, for example, an organic semiconductor material. The organic semiconductor material may be, for example, the donor organic semiconductor material or the acceptor organic semiconductor material described above. The first semiconductor material forming the charge-blocking layer 3 is not limited to organic semiconductor materials; it may also be an oxide semiconductor or a nitride semiconductor, or a composite material thereof. The material forming the charge-blocking layer 3 may also be, for example, a metal oxide such as aluminum oxide.

[0084] Alternatively, the charge blocking layer 3 can also have a structure consisting of multiple stacked layers. In this case, the materials constituting the multiple layers can be the same or different from each other.

[0085] The thickness of the charge blocking layer 3 is set according to the size of the lower electrode 2, as described later, and is, for example, 10 nm or more. From the viewpoint of effectively suppressing dark current and noise, the thickness of the charge blocking layer 3 can be 100 nm or more, 150 nm or more, or 200 nm or more. Furthermore, from the viewpoint of suppressing sensitivity reduction, the thickness of the charge blocking layer 3 can be 1000 nm or less, or 600 nm or less.

[0086] Figure 2 yes Figure 1 The example performance band diagram of the photoelectric conversion element is shown. Figure 2 In the diagram, rectangles represent the energy bands of each layer. Additionally, in... Figure 2 In the diagram, black circles represent electrons and white circles represent holes, schematically illustrating a part of the movement of electrons and holes.

[0087] The photoelectric conversion layer 4 generates excitons internally upon receiving light irradiation. These excitons diffuse within the photoelectric conversion layer 4 and are separated into electrons and holes at the interface between the acceptor and donor semiconductor materials. The separated electrons and holes move towards the lower electrode 2 or the upper electrode 5, respectively, depending on the electric field applied to the photoelectric conversion layer 4. When a voltage is applied between the upper electrode 5 and the lower electrode 2, such that the potential of the upper electrode 5 is higher than that of the lower electrode 2, electrons move towards the upper electrode 5, and holes move towards the lower electrode 2. When the photoelectric conversion element 10 is used in an imaging device, for example, holes are captured by the lower electrode 2 and stored as signal charges at a charge accumulation node electrically connected to the lower electrode 2. A charge accumulation node is an example of a charge accumulation region that stores the signal charges captured by the lower electrode 2. Thus, the photoelectric conversion layer 4 converts light into signal charges, and the lower electrode 2 captures the signal charges generated by the photoelectric conversion layer 4. Additionally, the upper electrode 5 captures charges with the opposite polarity to the signal charges. The following describes the case where holes move towards the lower electrode 2 and are used as signal charges. Alternatively, electrons can also be used as signal charges. In this case, a voltage is applied between the upper electrode 5 and the lower electrode 2 so that the potential of the upper electrode 5 is lower than the potential of the lower electrode 2. Holes move towards the upper electrode 5, and electrons move towards the lower electrode 2.

[0088] Here, the material that supplies electrons from the electron-hole pairs generated by absorbing light to the other material is called the donor material, and the material that accepts electrons is called the acceptor material. In this embodiment, the donor semiconductor material is the donor material, and the acceptor semiconductor material is the acceptor material. When using two different organic semiconductor materials, which one becomes the donor material and which one becomes the acceptor material is usually determined by the relative positions of the HOMO (Highest Occupied-Molecular-Orbital) and LUMO (Lowest Unoccupied-Molecular-Orbital) energy levels of the two organic semiconductor materials at the contact interface. Figure 2 Within the rectangle representing energy bands, the upper end represents the LUMO level, and the lower end represents the HOMO level. The energy difference between the vacuum level and the LUMO level is called the electron affinity. The energy difference between the vacuum level and the HOMO level is called the ionization potential. Figure 2 In the middle, the lower the position, the greater the electron affinity and ionization potential.

[0089] like Figure 2 As shown, among the two semiconductor materials included in the photoelectric conversion layer 4, the one with a shallower LUMO energy level, i.e., a lower electron affinity, becomes the donor material, i.e., the donor semiconductor material 4A. Conversely, among the two semiconductor materials included in the photoelectric conversion layer 4, the one with a deeper LUMO energy level, i.e., a higher electron affinity, becomes the acceptor material, i.e., the acceptor semiconductor material 4B. Furthermore, in... Figure 2 In the diagram, the energy bands of the donor semiconductor material 4A and the acceptor semiconductor material 4B are staggered laterally. However, this is for ease of observation and does not imply that the donor semiconductor material 4A and the acceptor semiconductor material 4B are separately distributed in the thickness direction of the photoelectric conversion layer 4. Furthermore, the energy band of the acceptor semiconductor material 4B is represented by a dashed rectangle, but this is also for ease of observation and is not intended to distinguish it from the solid rectangle.

[0090] The ionization potential of donor semiconductor material 4A is, for example, less than that of acceptor semiconductor material 4B.

[0091] The charge blocking layer 3 is configured to transport signal charges and block charges with opposite polarity to the signal charges. In the case where holes are used as signal charges, such as... Figure 2As shown, the electron affinity of the charge blocking layer 3 is, for example, lower than the electron affinity of the acceptor semiconductor material 4B of the photoelectric conversion layer 4. Furthermore, the electron affinity of the charge blocking layer 3 is lower than the work function of the lower electrode 2. Therefore, the charge blocking layer 3 suppresses the injection of charges (specifically electrons) from the lower electrode 2 into the photoelectric conversion layer 4 whose polarity is opposite to the signal charge. As a result, noise signals caused by dark current, which adversely affect the signal-to-noise ratio (SNR), can be reduced. Additionally, when the charge blocking layer 3 has a structure with multiple layers stacked, the electron affinity of at least one layer is lower than the electron affinity of the acceptor semiconductor material 4B of the photoelectric conversion layer 4, and further lower than the work function of the lower electrode 2.

[0092] Furthermore, for example, the difference between the ionization potential of the charge blocking layer 3 and the ionization potential of the donor semiconductor material 4A is less than 1 eV. This improves the extraction efficiency of the signal charge (specifically, holes) from the lower electrode 2. Additionally, when the charge blocking layer 3 has a structure with multiple layers stacked, for example, the difference between the ionization potential of each layer and the ionization potential of the donor semiconductor material 4A is less than 1 eV.

[0093] exist Figure 2 In this context, the electron affinity and ionization potential of the charge barrier layer 3 are, for example, the electron affinity and ionization potential of the first semiconductor material contained in the charge barrier layer 3.

[0094] Furthermore, when electrons are used as signal charges, in order to suppress the injection of holes from the lower electrode 2 into the photoelectric conversion layer 4, the ionization potential of the charge blocking layer 3 is, for example, greater than the ionization potential of the donor semiconductor material 4A of the photoelectric conversion layer 4. Additionally, when electrons are used as signal charges, the ionization potential of the charge blocking layer 3 is greater than the work function of the lower electrode 2.

[0095] Furthermore, when electrons are used as signal charges, the difference between the electron affinity of the charge blocking layer 3 and the electron affinity of the acceptor semiconductor material 4B is less than 1 eV. As a result, the extraction efficiency of the signal charge (specifically electrons) of the lower electrode 2 is improved.

[0096] [Another example of a photoelectric conversion element]

[0097] In addition, the photoelectric conversion element of this embodiment may also have a charge blocking layer between the upper electrode 5 and the photoelectric conversion layer 4. Figure 3 This is a schematic cross-sectional view showing the structure of another photoelectric conversion element 11 in this embodiment. (Example) Figure 3 As shown, in addition to the structure of the photoelectric conversion element 10, the photoelectric conversion element 11 also has a charge blocking layer 6 between the upper electrode 5 and the photoelectric conversion layer 4. The charge blocking layer 6 is, for example, connected to the upper electrode 5 and the photoelectric conversion layer 4.

[0098] The charge-blocking layer 6 may contain a second semiconductor material, for example. This second semiconductor material may be composed of an organic semiconductor material, such as the donor or acceptor organic semiconductor material described above. The second semiconductor material forming the charge-blocking layer 6 is not limited to organic semiconductor materials; it may also be an oxide semiconductor, a nitride semiconductor, or a composite material thereof. The material forming the charge-blocking layer 6 may also be a metal oxide such as aluminum oxide. The charge-blocking layer 6 may contain the same material as the charge-blocking layer 3.

[0099] Furthermore, the charge blocking layer 6 can have a structure consisting of multiple stacked layers. In this case, the materials constituting the multiple layers can be the same or different from each other.

[0100] The thickness of the charge blocking layer 6 is, for example, 5 nm or more. From the viewpoint of effectively suppressing dark current and noise, the thickness of the charge blocking layer 6 can be 10 nm or more, 20 nm or more, or 30 nm or more. Furthermore, from the viewpoint of suppressing sensitivity reduction, the thickness of the charge blocking layer 6 can be 500 nm or less, or 300 nm or less.

[0101] The charge blocking layer 6 is configured to transport a charge opposite to the signal charge and block the signal charge. When holes are used as the signal charge, the ionization potential of the charge blocking layer 6 is, for example, greater than or equal to the ionization potential of the donor semiconductor material 4A of the photoelectric conversion layer 4. Furthermore, the ionization potential of the charge blocking layer 6 is greater than the work function of the upper electrode 5. Therefore, the charge blocking layer 6 suppresses the injection of signal charge (specifically, holes) from the upper electrode 5 into the photoelectric conversion layer 4. As a result, noise signals caused by dark current, which adversely affect the signal-to-signal ratio, can be reduced. Additionally, when the charge blocking layer 6 has a structure with multiple layers stacked, the ionization potential of at least one layer is greater than or equal to the ionization potential of the donor semiconductor material 4A of the photoelectric conversion layer 4 and is also greater than the work function of the upper electrode 5.

[0102] Furthermore, for example, the difference between the electron affinity of the charge-blocking layer 6 and the electron affinity of the acceptor semiconductor material 4B is less than 1 eV. This improves the efficiency of transporting charges (specifically electrons) to the upper electrode 5 with polarity opposite to the signal charge. Additionally, when the charge-blocking layer 6 has a structure with multiple layers stacked, for example, the difference between the electron affinity of each layer and the electron affinity of the acceptor semiconductor material 4B is less than 1 eV.

[0103] The electron affinity and ionization potential of the charge blocking layer 6 are, for example, the electron affinity and ionization potential of the second semiconductor material contained in the charge blocking layer 6. The second semiconductor material contained in the charge blocking layer 6 may be the same as the donor semiconductor material 4A contained in the photoelectric conversion layer 4.

[0104] Furthermore, when electrons are used as signal charges, in order to suppress the injection of electrons from the upper electrode 5 into the photoelectric conversion layer 4, the electron affinity of the charge blocking layer 6 is, for example, lower than the electron affinity of the acceptor semiconductor material 4B of the photoelectric conversion layer 4. Moreover, when electrons are used as signal charges, the electron affinity of the charge blocking layer 6 is less than the work function of the upper electrode 5.

[0105] Furthermore, when electrons are used as signal charges, the difference between the ionization potential of the charge blocking layer 6 and the ionization potential of the donor semiconductor material 4A is less than 1 eV. This improves the efficiency of the upward movement of charges (specifically holes) with polarity opposite to the signal charges to the upper electrode 5. Moreover, when electrons are used as signal charges, the second semiconductor material included in the charge blocking layer 6 can be the same material as the acceptor semiconductor material 4B included in the photoelectric conversion layer 4.

[0106] [Filming device]

[0107] Next, use Figure 4 and Figure 5 The imaging device of this embodiment will be described. Figure 4 This indicates that the installation has adopted... Figure 1 This diagram shows an example of the circuit structure of the imaging device 100 with the photoelectric conversion unit 10A of the photoelectric conversion element 10. Additionally, Figure 5 This is a schematic cross-sectional view showing an example of the device structure of pixel 24 in the imaging device 100 of this embodiment. Additionally, in Figure 4 In the middle, the following was omitted. Figure 5 The diagram shows the auxiliary electrode 7.

[0108] like Figure 4 and Figure 5 As shown, the imaging apparatus 100 of this embodiment includes a semiconductor substrate 40 and a plurality of pixels 24. Each of the plurality of pixels 24 has a charge detection circuit 35 disposed on the semiconductor substrate 40, a photoelectric conversion unit 10A disposed on the semiconductor substrate 40, and a charge accumulation node 34 electrically connected to the charge detection circuit 35 and the photoelectric conversion unit 10A. The photoelectric conversion unit 10A of the plurality of pixels 24 is constituted by the aforementioned photoelectric conversion element 10. That is, each of the plurality of pixels 24 has a lower electrode 2, an upper electrode 5, a photoelectric conversion layer 4, and a charge blocking layer 3. In this embodiment, the charge accumulation node 34 is an example of a charge accumulation region. Alternatively, the photoelectric conversion unit 10A may also be constituted by a photoelectric conversion element 11. That is, in addition to the above-described structure, each of the plurality of pixels 24 may also have a charge blocking layer 6.

[0109] In the photoelectric conversion unit 10A, an upper electrode 5, a photoelectric conversion layer 4, a charge blocking layer 3, and a lower electrode 2 are sequentially arranged from the side from which light is incident on the imaging device 100. In this embodiment, light that has passed through the upper electrode 5 is incident on the photoelectric conversion layer 4. Furthermore, in this embodiment, the side from which light is incident on the imaging device 100 is the side of the photoelectric conversion unit 10A opposite to the semiconductor substrate 40 side. Additionally, in this embodiment, the light incident side is designated as the upper side.

[0110] The charge accumulation node 34 accumulates the signal charge generated by the photoelectric conversion unit 10A, and the charge detection circuit 35 detects the signal charge accumulated in the charge accumulation node 34. In addition, the charge detection circuit 35 disposed on the semiconductor substrate 40 may also be disposed on the semiconductor substrate 40 or directly disposed in the semiconductor substrate 40.

[0111] like Figure 4 As shown, the imaging device 100 includes a plurality of pixels 24 and peripheral circuitry. The imaging device 100 is, for example, an image sensor implemented by a single-chip integrated circuit, having a pixel array PA comprising a plurality of pixels 24 arranged in two dimensions.

[0112] Multiple pixels 24 are arranged two-dimensionally on the semiconductor substrate 40, that is, along both row and column directions, forming a photosensitive area that serves as a pixel region. Figure 4 The image shows an example of pixels 24 arranged in a two-row, two-column matrix. The arrangement of pixels 24 is not limited to two rows and two columns; there is no particular limitation on the number of rows and columns. Furthermore, in... Figure 4 For ease of illustration, the diagram of the circuitry (e.g., pixel electrode control circuitry) used to individually set the sensitivity of pixel 24 is omitted. Furthermore, the imaging device 100 can also be a line sensor. In this case, the multiple pixels 24 can also be arranged in one dimension. Moreover, in this specification, row direction and column direction refer to the directions in which rows and columns extend, respectively. That is, in Figure 4 In the text, the vertical axis represents the column direction, and the horizontal axis represents the row direction.

[0113] like Figure 4 and Figure 5 As shown, each pixel 24 has a photoelectric conversion unit 10A, a charge detection circuit 35, and a charge accumulation node 34 electrically connected to the photoelectric conversion unit 10A and the charge detection circuit 35. The charge detection circuit 35 includes an amplification transistor 21, a reset transistor 22, and an address transistor 23.

[0114] The photoelectric conversion unit 10A includes a lower electrode 2, which serves as a pixel electrode, and an upper electrode 5, which serves as a counter electrode, opposite to the lower electrode 2. The photoelectric conversion unit 10A does not need to be a separate component for each pixel 24; a portion of the photoelectric conversion unit 10A can span multiple pixels 24. A voltage for applying a predetermined bias voltage is supplied to the upper electrode 5 via the counter electrode signal line 26.

[0115] The lower electrode 2 is connected to the gate electrode 21G of the amplifying transistor 21. The signal charge collected by the lower electrode 2 is stored in the charge storage node 34 located between the lower electrode 2 and the gate electrode 21G of the amplifying transistor 21. For example, when the signal charge is a hole, the charge storage node 34 is electrically connected to the lower electrode 2 and stores the holes in the excitons generated by the photoelectric conversion layer 4.

[0116] A voltage corresponding to the amount of signal charge accumulated at charge accumulation node 34 is applied to the gate electrode 21G of amplifying transistor 21. Amplifying transistor 21 amplifies this voltage, which is then selectively read out as a signal voltage via address transistor 23. The source / drain electrodes of reset transistor 22 are connected to the lower electrode 2 via charge accumulation node 34, resetting the signal charge accumulated at charge accumulation node 34. In other words, reset transistor 22 resets the potentials of the gate electrode 21G and the lower electrode 2 of amplifying transistor 21.

[0117] To selectively perform the aforementioned operations on multiple pixels 24, the imaging device 100 includes a power supply line 31, a vertical signal line 27, an address signal line 36, and a reset signal line 37, which are connected to each pixel 24 respectively. Specifically, the power supply line 31 is connected to the source / drain electrodes of the amplifying transistor 21, and the vertical signal line 27 is connected to the source / drain electrodes of the address transistor 23. The address signal line 36 is connected to the gate electrode 23G of the address transistor 23. Furthermore, the reset signal line 37 is connected to the gate electrode 22G of the reset transistor 22.

[0118] The peripheral circuitry includes a voltage supply circuit 19, a vertical scanning circuit 25, a horizontal signal readout circuit 20, multiple column signal processing circuits 29, multiple load circuits 28, and multiple differential amplifiers 32.

[0119] The voltage supply circuit 19 is electrically connected to the upper electrode 5 via the counter electrode signal line 26. The voltage supply circuit 19 applies a voltage between the upper electrode 5 and the lower electrode 2 by supplying a voltage to the upper electrode 5, i.e., applying a voltage between the upper electrode 5 and the lower electrode 2. When the lower electrode 2 captures holes as signal charges, the voltage supply circuit 19 supplies a voltage to the upper electrode 5 such that the potential of the upper electrode 5 is higher than the potential of the lower electrode 2. When the lower electrode 2 captures electrons as signal charges, the voltage supply circuit 19 supplies a voltage to the upper electrode 5 such that the potential of the upper electrode 5 is lower than the potential of the lower electrode 2.

[0120] The voltage supplied from the voltage supply circuit 19 to the upper electrode 5 switches between several different voltages, thereby controlling the sensitivity of the photoelectric conversion unit 10A. The voltage supply circuit 19 is not limited to a specific power supply circuit; it can be a circuit that generates a predetermined voltage, or a circuit that converts a voltage supplied from another power source into a predetermined voltage. Alternatively, the imaging device 100 may not include the voltage supply circuit 19. For example, the voltage may be supplied to the upper electrode 5 from an external power source.

[0121] The vertical scanning circuit 25 is connected to the address signal line 36 and the reset signal line 37, selecting multiple pixels 24 arranged in each row on a row-by-row basis to read out signal voltages and reset the potential of the lower electrode 2. The power supply wiring 31, serving as the source follower power supply, supplies a predetermined power voltage to each pixel 24. The horizontal signal readout circuit 20 is electrically connected to multiple column signal processing circuits 29. The column signal processing circuits 29 are electrically connected to the pixels 24 arranged in each column via vertical signal lines 27 corresponding to each column. The load circuit 28 is electrically connected to each vertical signal line 27. The load circuit 28 and the amplifying transistor 21 form a source follower circuit.

[0122] Multiple differential amplifiers 32 are arranged corresponding to each column. The inverting input terminal of the differential amplifier 32 is connected to the corresponding vertical signal line 27. In addition, the output terminal of the differential amplifier 32 is connected to the pixel 24 via the feedback line 33 corresponding to each column.

[0123] The vertical scan circuit 25 applies a row selection signal, which controls the on / off state of the address transistor 23, to the gate electrode 23G of the address transistor 23 via the address signal line 36. This scans and selects the row to be read. A signal voltage is read from the pixel 24 of the selected row to the vertical signal line 27. Furthermore, the vertical scan circuit 25 applies a reset signal, which controls the on / off state of the reset transistor 22, to the gate electrode 22G of the reset transistor 22 via the reset signal line 37. This selects the row containing the pixel 24 to be reset. The vertical signal line 27 transmits the signal voltage read from the pixel 24 selected by the vertical scan circuit 25 to the column signal processing circuit 29.

[0124] The signal processing circuit 29 performs noise suppression signal processing, represented by correlated double sampling, as well as analog-to-digital conversion (AD conversion).

[0125] The horizontal signal readout circuit 20 reads signals sequentially from multiple column signal processing circuits 29 to the horizontal common signal line.

[0126] The differential amplifier 32 is connected to the drain electrode of the reset transistor 22 via the feedback line 33. Therefore, the differential amplifier 32 receives the output value of the address transistor 23 at its inverting input terminal. The differential amplifier 32 performs a feedback operation to make the gate potential of the amplifying transistor 21 a predetermined feedback voltage. At this time, the output voltage value of the differential amplifier 32 is, for example, 0V or a positive voltage near 0V. The feedback voltage refers to the output voltage of the differential amplifier 32.

[0127] like Figure 5 As shown, pixel 24 has a semiconductor substrate 40, a charge detection circuit 35, a photoelectric conversion unit 10A, an auxiliary electrode 7, and a charge accumulation node 34 (see reference). Figure 4 ).

[0128] The semiconductor substrate 40 can be an insulating substrate, such as a p-type silicon substrate, on the surface of which a semiconductor layer is provided on the side where the photosensitive area is formed. The semiconductor substrate 40 has impurity regions 21D, 21S, 22D, 22S, and 23S, and a component separation region 41 for electrical separation between pixels 24. The impurity regions 21D, 21S, 22D, 22S, and 23S are, for example, n-type regions. Here, the component separation region 41 is provided between impurity regions 21D and 22D. This suppresses leakage of signal charge accumulated at the charge accumulation node 34. Furthermore, the component separation region 41 is formed, for example, by acceptor ion implantation under specified implantation conditions.

[0129] Impurity regions 21D, 21S, 22D, 22S, and 23S are, for example, diffusion regions formed within the semiconductor substrate 40. Figure 5As shown, the amplifying transistor 21 includes an impurity region 21S, an impurity region 21D, and a gate electrode 21G. The impurity regions 21S and 21D function as, for example, the source and drain regions of the amplifying transistor 21, respectively. A channel region of the amplifying transistor 21 is formed between the impurity regions 21S and 21D.

[0130] Similarly, address transistor 23 includes impurity regions 23S and 21S, and a gate electrode 23G connected to address signal line 36. In this example, amplification transistor 21 and address transistor 23 are electrically connected to each other through a shared impurity region 21S. Impurity region 23S functions as, for example, the source region of address transistor 23. Impurity region 23S and Figure 4 The vertical signal line 27 shown is connected.

[0131] An interlayer insulating layer 50 is stacked on the semiconductor substrate 40 in such a way that it covers the amplification transistor 21, the address transistor 23, and the reset transistor 22. Furthermore, Figure 5 In the diagram, for ease of observation, the shading indicating cross-section is omitted in the interlayer insulation layer 50.

[0132] Furthermore, a wiring layer (not shown) can be disposed in the interlayer insulating layer 50. The wiring layer is formed of a metal such as copper, and a portion thereof can contain wiring such as the vertical signal line 27 described above. The number of insulating layers in the interlayer insulating layer 50 and the number of layers contained in the wiring layer disposed in the interlayer insulating layer 50 can be arbitrarily set.

[0133] In the interlayer insulating layer 50, a contact plug 53 connected to the gate electrode 21G of the amplifying transistor 21, a contact plug 54 connected to the impurity region 22D of the reset transistor 22, a contact plug 51 connected to the lower electrode 2, and wiring 52 connecting the contact plugs 51, 54, and 53 are disposed. Thus, the impurity region 22D of the reset transistor 22 is electrically connected to the gate electrode 21G of the amplifying transistor 21. Figure 5 In the illustrated structure, contact plugs 51, 53 and 54, wiring 52, gate electrode 21G of amplifying transistor 21, and impurity region 22D of reset transistor 22 constitute at least a portion of charge accumulation node 34.

[0134] The charge detection circuit 35 detects the signal charge captured by the lower electrode 2 and outputs a signal voltage. The charge detection circuit 35 includes an amplifying transistor 21, a reset transistor 22, and an address transistor 23, and is formed on the semiconductor substrate 40.

[0135] The amplifying transistor 21 includes an impurity region 21D and an impurity region 21S formed in the semiconductor substrate 40 and functioning as a drain electrode and a source electrode, respectively, a gate insulating layer 21X formed on the semiconductor substrate 40, and a gate electrode 21G formed on the gate insulating layer 21X.

[0136] The reset transistor 22 includes impurity regions 22D and 22S formed in the semiconductor substrate 40 and functioning as drain and source electrodes, respectively, a gate insulating layer 22X formed on the semiconductor substrate 40, and a gate electrode 22G formed on the gate insulating layer 22X.

[0137] Address transistor 23 includes impurity regions 21S and 23S formed in semiconductor substrate 40 and functioning as drain and source electrodes, respectively, a gate insulating layer 23X formed on semiconductor substrate 40, and a gate electrode 23G formed on gate insulating layer 23X. Impurity region 21S is connected in series with amplification transistor 21 and address transistor 23.

[0138] The photoelectric conversion section 10A described above is disposed on the interlayer insulating layer 50. In other words, in this embodiment, a plurality of pixels 24 constituting the pixel array PA are formed on the semiconductor substrate 40. Furthermore, the plurality of pixels 24 disposed two-dimensionally on the semiconductor substrate 40 form photosensitive areas. The charge blocking layer 3, the photoelectric conversion layer 4, and the upper electrode 5 are formed, for example, across the plurality of pixels 24. On the other hand, the lower electrode 2 is provided for each pixel 24 and is spatially separated from the lower electrodes 2 of adjacent other pixels 24, thereby being electrically isolated from the lower electrodes 2 of other pixels 24. As described above, the upper electrode 5 is connected to the counter electrode signal line 26 connected to the voltage supply circuit 19. Therefore, a voltage of a desired magnitude can be applied simultaneously between the plurality of pixels 24 from the voltage supply circuit 19 via the counter electrode signal line 26. Furthermore, as long as a voltage of a desired magnitude can be applied from the voltage supply circuit 19, the upper electrode 5 can also be provided separately for each pixel 24. Similarly, the photoelectric conversion layer 4 and the charge blocking layer 3 can also be provided separately for each pixel 24.

[0139] The length L of one side of the lower electrode 2 in the photoelectric conversion unit 10A, the size of the lower electrode 2, and the thickness D of the charge blocking layer 3 will be described later. Figure 5 As shown, the thickness D of the charge blocking layer 3 is also the shortest distance between the lower electrode 2 and the photoelectric conversion layer 4.

[0140] Here, the layout of the multiple pixel electrodes, namely the lower electrode 2, of the imaging device 100 will be explained. Figure 6 This is a plan view showing an exemplary electrode layout of the imaging device 100. Figure 6This is a plan view showing the components above the lower electrode 2 and auxiliary electrode 7. Additionally, in Figure 6 In order to facilitate observation, additional electrodes were added to the lower electrode 2 and the auxiliary electrode 7. Figure 5 The cross-sectional view shows the lower electrode 2 and the auxiliary electrode 7 in the same shade.

[0141] Figure 6 The pixel electrode region 24A shown is the region corresponding to one pixel 24 when viewed in a planar manner. Figure 6 In the example shown, a lower electrode 2 and an auxiliary electrode 7 are provided in the pixel electrode region 24A.

[0142] like Figure 6 As shown, the lower electrodes 2 are arranged in an array, for example. The auxiliary electrodes 7 are positioned between adjacent lower electrodes 2 when viewed in a planar manner. In the illustrated example, the auxiliary electrodes 7 surround the lower electrodes 2 when viewed in a planar manner. Specifically, the auxiliary electrodes 7 are arranged in a grid pattern when viewed in a planar manner, with a lower electrode 2 disposed within each grid. The auxiliary electrodes 7 are formed together across multiple pixels 24, achieving the same potential in all pixels 24. Furthermore, the auxiliary electrodes 7 can also be separately arranged for each pixel 24, or separately arranged for each pixel block consisting of two or more pixels 24, which are a subset of the multiple pixels 24.

[0143] exist Figure 6 In the example shown, the planar shape of the lower electrode 2 is square, but the planar shape of the lower electrode 2 is not particularly limited. The planar shape of the lower electrode 2 can also be a rectangle, hexagon, octagon, or other polygons.

[0144] The auxiliary electrode 7 is connected to, for example, a voltage supply circuit (omitted) or ground, and is maintained at a predetermined potential. The auxiliary electrode 7 is electrically disconnected from the lower electrode 2. The potential of the auxiliary electrode 7 is, for example, a fixed potential, but it can also be varied.

[0145] The auxiliary electrode 7 is provided to suppress electrochromic mixing. Between pixels with significantly different amounts of signal charge accumulated at the charge accumulation node 34, the potential difference of the charge accumulation node 34 increases, causing mutual interference and degrading resolution. The auxiliary electrode 7 reduces the mutual interference between adjacent pixels.

[0146] Furthermore, when the signal charge is a hole, the potential of the auxiliary electrode 7 can be set to be higher than the potential of the charge accumulation node 34 when the signal charge is reset. This suppresses the movement of signal charge to adjacent pixels, efficiently extracts signal charge generated near the auxiliary electrode 7, and improves sensitivity. Alternatively, the potential of the auxiliary electrode 7 can also be set to be lower than the potential of the charge accumulation node 34 when the signal charge is reset. This allows the signal charge to be captured by the auxiliary electrode 7, also suppressing the movement of signal charge to adjacent pixels.

[0147] The auxiliary electrode 7 is formed of a metal, a metal nitride, a metal oxide, or polycrystalline silicon that has been given conductivity. Examples of metals include aluminum, copper, titanium, and tungsten. Examples of methods for giving polycrystalline silicon conductivity include doping with impurities. The auxiliary electrode 7 may also be made of the same material as the lower electrode 2.

[0148] Refer again Figure 5 A color filter 60 is formed above the photoelectric conversion unit 10A, and a microlens 61 is formed above it. The color filter 60 is formed, for example, as an on-chip color filter by patterning, and uses a photosensitive resin in which dyes or pigments are dispersed. The microlens 61 is formed, for example, as an on-chip microlens, and uses an ultraviolet photosensitive material.

[0149] In the manufacture of the imaging device 100, conventional semiconductor manufacturing processes can be used. In particular, when a silicon substrate is used as the semiconductor substrate 40, it can be manufactured using various silicon semiconductor processes.

[0150] The imaging device 100 can operate, for example, using a rolling shutter mode that sequentially exposes and reads signals from multiple pixels 24 per pixel row, or using a global shutter mode that unifies the exposure period of the multiple pixels 24. When operating using the rolling shutter mode, the voltage supply circuit 19, for example, maintains a voltage that enables the photoelectric conversion unit 10A to generate sensitivity during imaging, and sequentially reads signal charge per pixel row. Furthermore, when operating using the global shutter mode, the voltage supply circuit 19, for example, supplies a voltage to the upper electrode 5 during exposure for imaging with the desired sensitivity, and supplies a voltage to the upper electrode 5 that does not enable the photoelectric conversion unit 10A to generate sensitivity during non-exposure periods. Therefore, the photoelectric conversion efficiency of the multiple pixels 24 during exposure is different from that during non-exposure periods; specifically, it is higher than the photoelectric conversion efficiency of the multiple pixels 24 during non-exposure periods. This exposure period is used to accumulate signal charge at the charge accumulation node 34. Furthermore, during the non-exposure period, the signal charge accumulated at the charge accumulation node 34 during the exposure period is read out sequentially for each pixel row. However, the readout operation of the imaging device 100 is not limited to this operation; known imaging device readout operations can be used.

[0151] [Thickness of the charge blocking layer and size of the lower electrode]

[0152] According to the imaging device 100 of this embodiment, the thickness of the charge blocking layer 3 and the size of the lower electrode 2 have a predetermined relationship, thereby reducing noise.

[0153] First, the main causes of noise generation in the imaging device 100 will be explained.

[0154] Figure 7 It is used to illustrate that in having Figure 2 The diagram illustrates the generation of intermediate energy levels in the photoelectric conversion element 10 with its band structure. Near the interface between the charge blocking layer 3 and the photoelectric conversion layer 4, intermediate energy levels are easily generated due to the influence of film formation conditions and intermaterial polarization. For example... Figure 7 As shown, intermediate energy levels are generated, for example, in the acceptor semiconductor material 4B contained in the photoelectric conversion layer 4.

[0155] Compared to the energy difference between the HOMO energy level of the donor semiconductor material 4A and the LUMO energy level of the acceptor semiconductor material 4B contained in the photoelectric conversion layer 4, the energy difference between the HOMO energy level of the donor semiconductor material 4A and the intermediate energy level is small. Therefore, due to the presence of the intermediate energy level, even the energy generated by heat, which is usually small compared to light, can easily generate electrons and holes in the photoelectric conversion layer 4 via the intermediate energy level.

[0156] When the signal charge is a hole, electrons generated by thermal energy are extracted to the upper electrode 5 via the acceptor semiconductor material 4B. Furthermore, holes generated by thermal energy are extracted to the lower electrode 2 via the donor semiconductor material 4A and the charge blocking layer 3. The holes extracted to the lower electrode 2 accumulate at the charge accumulation node 34, and the deviation increases according to the average value of the charge accumulated at the charge accumulation node 34, becoming a major cause of noise. This noise is a type of shot noise, which is random noise proportional to the square root of the average charge value. Hereinafter, there is a case where charges generated via intermediate energy levels, such as holes as described above, that have the same polarity as the signal charge are referred to as noise charges.

[0157] Figure 8 This is a diagram illustrating the distribution of charge accumulated at charge accumulation node 34. Figure 8 In the diagram, the horizontal axis represents the amount of charge accumulated at charge accumulation node 34. Additionally, in... Figure 8 In the figure, the vertical axis represents the number of charge accumulation nodes 34 that have accumulated the amount of charge shown on the horizontal axis when multiple charge accumulation nodes 34 have accumulated charge under the same conditions, or the number of times the amount of charge shown on the horizontal axis has accumulated at the charge accumulation nodes 34 under the same conditions at certain intervals.

[0158] In addition, Figure 8 In the diagram, the solid line curve illustrates the distribution of charge when the amount of charge accumulated at charge accumulation node 34 is large. Additionally, in... Figure 8 In the diagram, the dashed curve illustrates the distribution when the amount of charge accumulated at charge accumulation node 34 is small. Here, as mentioned above, the deviation in charge is proportional to the square root of the average charge value; therefore, when the average value on the horizontal axis decreases, the distribution narrows. Consequently, noise is reduced.

[0159] Intermediate energy levels tend to form near the interface between the charge blocking layer 3 and the photoelectric conversion layer 4. Therefore, the amount of noise charge generated via the intermediate energy level depends on the size of the interface between the charge blocking layer 3 and the photoelectric conversion layer 4. Thus, in each pixel 24, the amount of noise charge generated via the intermediate energy level depends on the size of the effective photoelectric conversion layer 4 and charge blocking layer 3 area from which the charge can be extracted via the lower electrode 2. In each pixel 24, the photoelectric conversion layer 4 and charge blocking layer 3 are stacked on the entire surface of the lower electrode 2. Therefore, the size of the effective photoelectric conversion layer 4 and charge blocking layer 3 area is determined by the size of the lower electrode 2 when viewed from a planar perspective. For example, in each pixel 24, the larger the area of ​​the lower electrode 2 when viewed from a planar perspective, the easier it is for the amount of noise charge accumulated at the charge accumulation node 34 to increase. This deviation is represented by a physical quantity calculated based on the square root of the amount of noise charge.

[0160] Furthermore, some of the noise charges generated via the intermediate energy level recombine with charges of opposite polarity to the noise charges and become inactive. At this point, the longer the distance until the noise charges are extracted at the lower electrode 2, i.e., the thicker the charge blocking layer 3, the easier it is for the noise charges to recombine with charges of opposite polarity to the noise charges. As a result, the amount of noise charges accumulated at the charge accumulation node 34 decreases.

[0161] Thus, the deviation in the amount of noise charge generated and stored at the charge accumulation node 34 via the intermediate energy level depends on the area of ​​the lower electrode 2 and the thickness of the charge blocking layer 3 during planar observation. Therefore, by ensuring that the ratio between the area of ​​the lower electrode 2 and the thickness of the charge blocking layer 3 during planar observation satisfies a predetermined condition, a noise-reduced imaging device 100 can be achieved. Specifically, in the imaging device 100, when the thickness of the charge blocking layer 3 is set to D and the area of ​​the lower electrode 2 during planar observation is set to S, a noise-reduced imaging device 100 can be achieved by satisfying D / √S ≥ 0.07. That is, in the imaging device 100, the thickness D of the charge blocking layer 3 is 7% or more of the square root of the area S of the lower electrode 2. From the viewpoint of further reducing noise, in the imaging device 100, D / √S ≥ 0.14 or D / √S ≥ 0.21 can also be satisfied. Figure 6 In the example shown, the planar observation shape of the lower electrode 2 is square. Therefore, when the length of one side of the square of the planar observation shape of the lower electrode 2 is set to L, the image capturing device 100 satisfies D / L≥0.07. From the viewpoint of further reducing noise, the image capturing device 100 can also satisfy D / L≥0.14 or D / L≥0.21.

[0162] Furthermore, from the viewpoint of suppressing the decrease in the electric field strength acting on the photoelectric conversion unit 10A and maintaining the sensitivity of the photoelectric conversion unit 10A, the upper limits of D / √S and D / L can be either 0.50 or 0.25. That is, D / √S ≤ 0.50 and D / L ≤ 0.50 can be satisfied, and D / √S ≤ 0.25 and D / L ≤ 0.25 can also be satisfied.

[0163] Furthermore, the auxiliary electrode 7 has a minimal impact on noise. As described above, when the signal charge is a hole, for example, the potential of the auxiliary electrode 7 is set to be greater than the potential of the charge accumulation node 34 after the signal charge is reset. That is, most of the charge generated in the photoelectric conversion unit 10A is taken down to the lower electrode 2 regardless of the presence or absence of the auxiliary electrode 7. Therefore, the same applies to the noise charge generated via the intermediate energy level; the auxiliary electrode 7 has a minimal impact on noise.

[0164] Next, refer to Figure 4This section explains the saturation signal quantity of the imaging device 100 and the ratio of the saturation signal quantity to noise, i.e., the dynamic range. Here, the case where holes are used as signal charges is explained.

[0165] exist Figure 4 As described above, holes generated in the photoelectric conversion unit 10A are stored in the charge storage node 34. If holes are stored, the potential of the charge storage node 34 rises. That is, in this case, the maximum potential corresponding to the amount of charge that the charge storage node 34 can retain becomes the saturation signal quantity of the imaging device 100. Typically, a voltage amplitude of about 3V is allowed in the charge storage node 34, which is equivalent to the gate voltage of the amplifying transistor 21. In this case, for example, with a conversion gain of 50μV / e... - In the filming device, 6e occurred - Even in noisy conditions, a dynamic range of 80 dB corresponding to the human eye can be ensured. In the imaging device 100 of this embodiment, as described above, noise charge generated via the intermediate energy level is difficult to accumulate at the charge accumulation node 34, thus reducing noise and achieving a wide dynamic range.

[0166] Example

[0167] The following examples illustrate the imaging device of this disclosure, but this disclosure is not limited to the following examples. In detail, the imaging device of this disclosure and the imaging device for characteristic comparison were manufactured, and noise was measured.

[0168] (The construction of the filming equipment)

[0169] The imaging apparatus for the embodiments and comparative examples was fabricated.

[0170] [Comparative Example 1]

[0171] First of all, with Figure 5 and Figure 6 The device structure of pixel 24 and the layout of the lower electrode 2 are shown. On a semiconductor substrate 40 with a stacked interlayer insulating layer 50 on which the charge detection circuit 35 is formed, a lower electrode 2 is formed from TiN and connected to the charge detection circuit 35 via a charge accumulation node 34. Furthermore, the length L of one side of the square shape of the lower electrode 2 in planar view is set to 2.1 μm. Therefore, the area S of the lower electrode 2 in planar view is 4.41 μm. 2 .

[0172] Next, 9,9'-[1,1'-Biphenyl]-4,4'-diylbis[3,6-bis(1,1-dimethylethyl)]-9H-carbazole was deposited on the lower electrode 2 by vacuum evaporation, thereby forming a charge barrier layer 3. The thickness D of the charge barrier layer was set to 50 nm.

[0173] Next, on the charge blocking layer 3, the photoelectric conversion layer 4 is formed by vacuum evaporation using subphthalocyanine as the donor semiconductor and fullerene C60 as the acceptor semiconductor. Furthermore, the subphthalocyanine used is one with boron (B) as the central metal and chloride ions as ligands coordinated at B.

[0174] Next, an ITO film was formed on the photoelectric conversion layer 4 as the upper electrode 5 by sputtering, and an Al2O3 film was formed on the upper electrode 5 as a sealing film by atomic layer deposition, thereby obtaining the imaging device of Comparative Example 1. In the imaging device of Comparative Example 1, D / L=D / √S=0.024.

[0175] [Example 1]

[0176] Except for setting the thickness D of the charge blocking layer 3 to 150 nm, the same process as in Comparative Example 1 was performed to obtain the imaging device of Example 1. In the imaging device of Example 1, D / L = D / √S = 0.071.

[0177] [Example 2]

[0178] Except for setting the thickness D of the charge blocking layer 3 to 300 nm, the same process as in Comparative Example 1 was performed to obtain the imaging device of Example 2. In the imaging device of Example 2, D / L = D / √S = 0.14.

[0179] [Example 3]

[0180] Except for setting the thickness D of the charge blocking layer 3 to 450 nm, the same process as in Comparative Example 1 was performed to obtain the imaging device of Example 3. In the imaging device of Example 3, D / L = D / √S = 0.21.

[0181] (Measurement of random noise)

[0182] For the imaging apparatus of the embodiments and comparative examples, in order to evaluate noise, the output detected by the charge detection circuit 35 of each pixel 24 was obtained. Specifically, in a state where no light is incident on the imaging apparatus, the output detected by the charge detection circuit 35 based on the amount of charge accumulated in the charge accumulation node 34 is obtained after a predetermined period has elapsed since the potential of the charge accumulation node 34 of each pixel 24 was reset. In addition, at this time, a voltage of -1V is applied between the lower electrode 2 and the upper electrode 5, with the potential of the lower electrode 2 as a reference. That is, a voltage is applied between the lower electrode 2 and the upper electrode 5 such that the potential of the upper electrode 5 is lower than the potential of the lower electrode 2. Furthermore, as random noise, the standard deviation of the output from each pixel 24 is calculated.

[0183] Figure 9 This is a graph showing the relationship between D / √S and random noise for the imaging apparatus of the embodiments and comparative examples. Figure 10 This is a graph showing the relationship between D / L and random noise of the imaging apparatus in the embodiments and comparative examples. Figure 9 and Figure 10 In the diagram, the vertical axis represents random noise. The value of the random noise on the vertical axis is a value that has been normalized to 1, based on the saturated signal of the imaging device in the embodiments and comparative examples, under the condition that the dynamic range corresponding to 80 dB of the human eye is achieved. Furthermore, the dynamic range at this time is 20log 10 (Saturated semaphore / random noise). Additionally, in Figure 9 In the diagram, the horizontal axis represents D / √S. Figure 10 In the diagram, the horizontal axis represents D / L.

[0184] like Figure 9 and Figure 10 As shown, in the imaging devices of Examples 1 to 3, the random noise of the imaging device is reduced to less than 1 when D / √S≥0.07 and D / L≥0.07, thus achieving a wide dynamic range of more than 80dB corresponding to the human eye.

[0185] As described above, in the imaging apparatus of this disclosure, such as the imaging apparatuses in Embodiments 1 to 3, a noise-reducing imaging apparatus can be achieved by satisfying D / √S≥0.07 and D / L≥0.07. This is believed to be because, as described above, even if noise charges are generated via intermediate energy levels, the noise charges are difficult to accumulate at the charge accumulation node 34.

[0186] The imaging device of this disclosure has been described above based on the implementation methods and embodiments, but this disclosure is not limited to these implementation methods and embodiments. Various modifications to the implementation methods and embodiments that can be conceived by those skilled in the art, as well as other ways of constructing by combining some of the constituent elements of the implementation methods and embodiments, are also included within the scope of this disclosure, as long as they do not depart from the spirit of this disclosure.

[0187] Industrial applicability

[0188] The imaging device disclosed herein can be applied to various camera systems and sensor systems, such as medical cameras, surveillance cameras, vehicle-mounted cameras, rangefinder cameras, microscope cameras, drone cameras, and robot cameras.

[0189] Explanation of reference numerals in the attached figures

[0190] 1 Support substrate; 2 Lower electrode; 3, 6 Charge blocking layers; 4 Photoelectric conversion layer; 4A Donor semiconductor material; 4B Acceptor semiconductor material; 5 Upper electrode; 7 Auxiliary electrode; 10, 11 Photoelectric conversion element; 10A Photoelectric conversion section; 19 Voltage supply circuit; 20 Horizontal signal readout circuit; 21 Amplifying transistor; 22 Reset transistor; 23 Address transistor; 21D, 21S, 22D, 22S, 23S Impurity regions; 21G, 22G, 23G Gate electrodes; 21X, 22X, 23X Gate electrodes Insulating layer; 24 pixels; 24A pixel electrode area; 25 vertical scanning circuit; 26 counter electrode signal line; 27 vertical signal line; 28 load circuit; 29 column signal processing circuit; 31 power supply wiring; 32 differential amplifier; 33 feedback line; 34 charge accumulation node; 35 charge detection circuit; 36 address signal line; 37 reset signal line; 40 semiconductor substrate; 41 component separation area; 50 interlayer insulating layer; 51, 53, 54 contact plugs; 52 wiring; 60 color filter; 61 microlens; 100 imaging device.

Claims

1. A shooting device, characterized in that, It has multiple pixels, The plurality of pixels each have: First electrode; The second electrode is disposed opposite to the first electrode; A photoelectric conversion layer, located between the first electrode and the second electrode, comprises donor semiconductor material and acceptor semiconductor material, and generates signal charge; The intermediate layer is located between the photoelectric conversion layer and the first electrode; as well as The charge accumulation region is electrically connected to the first electrode and accumulates the signal charge. Let the thickness of the intermediate layer be D, and the area of ​​the first electrode when viewed from a plane be S, then the following conditions are met: D / √S≥0.

07.

2. The shooting device according to claim 1, characterized in that, The thickness of the intermediate layer is 10 nm or more.

3. The shooting device according to claim 1 or 2, characterized in that, The signal charge is a hole. The intermediate layer contains a first semiconductor material. The difference between the ionization potential of the first semiconductor material contained in the intermediate layer and the ionization potential of the donor semiconductor material contained in the photoelectric conversion layer is less than 1 eV.

4. The shooting device according to claim 1 or 2, characterized in that, The signal charge is an electron. The intermediate layer contains a first semiconductor material. The difference between the electron affinity of the first semiconductor material contained in the intermediate layer and the electron affinity of the acceptor semiconductor material contained in the photoelectric conversion layer is less than 1 eV.

5. The shooting device according to claim 1, characterized in that, Each of the plurality of pixels also has a charge blocking layer located between the second electrode and the photoelectric conversion layer.

6. The shooting device according to claim 5, characterized in that, The thickness of the charge blocking layer is 5 nm or more.

7. The shooting device according to claim 5 or 6, characterized in that, The signal charge is a hole. The charge barrier layer contains a second semiconductor material. The difference between the electron affinity of the second semiconductor material contained in the charge blocking layer and the electron affinity of the acceptor semiconductor material contained in the photoelectric conversion layer is less than 1 eV.

8. The shooting device according to claim 5 or 6, characterized in that, The signal charge is an electron. The charge barrier layer contains a second semiconductor material. The difference between the ionization potential of the second semiconductor material contained in the charge blocking layer and the ionization potential of the donor semiconductor material contained in the photoelectric conversion layer is less than 1 eV.

9. The imaging apparatus according to any one of claims 1, 2, 5, and 6, characterized in that, The condition D / √S ≥ 0.14 is satisfied.

10. The imaging apparatus according to any one of claims 1, 2, 5, and 6, characterized in that, The condition D / √S ≥ 0.21 is satisfied.

11. A shooting device, characterized in that, It has multiple pixels, The plurality of pixels each have: First electrode; The second electrode is disposed opposite to the first electrode; A photoelectric conversion layer, located between the first electrode and the second electrode, comprises donor semiconductor material and acceptor semiconductor material, and generates signal charge; The intermediate layer is located between the photoelectric conversion layer and the first electrode; as well as The charge accumulation region is electrically connected to the first electrode and accumulates the signal charge. The first electrode has a square shape when viewed from a planar perspective. Let the thickness of the intermediate layer be D, and let the length of one side of the square shape of the first electrode (observed from a planar perspective) be L. satisfy D / L≥0.07.

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