Analog sampling and protection circuit for solving multiple intersections

Abstract

The present application relates to current sampling, protection field, specifically to a kind of analog sampling and protection circuit of multiple intersection solution.Mainly by current voltage signal conversion network, first proportional amplification network, sampling signal filter network, current ripple processing network, second proportional amplification network, signal processing control and isolation network is constituted.By analog sampling circuit processing current ripple in switching power supply, solve the problem that the output jitter caused by multiple intersection of existing digital control due to ripple current, and peak current protection can be realized.

Description

Technical Field

[0001] This invention relates to the field of current sampling and protection, and specifically to an analog sampling and protection circuit that solves the problem of multiple intersections. Background Technology

[0002] In the field of switching power supplies, digital control loops are widely used due to their significant advantages. They can implement a variety of complex control strategies, improve control loop performance, and compared with analog control loops, have higher computational accuracy, are less affected by device aging, environmental changes, and parameter fluctuations, thus reducing system instability caused by calculation errors. Furthermore, control parameters and algorithms can be adjusted through software programming without modifying the hardware circuitry.

[0003] However, introducing inductor or capacitor current into the digital control loop can easily lead to multiple digital cutoffs, resulting in output voltage waveform jitter. Existing technologies mostly address this issue by processing the sampled inductor or capacitor current in software. However, this software processing method has significant drawbacks: firstly, it causes control loop delay, affecting the phase margin of the loop control and causing system instability; secondly, sacrificing loop gain to improve phase margin will adversely affect output performance indicators.

[0004] Therefore, it is necessary to develop an analog sampling circuit that can effectively solve the problem of multiple intersections in digital control, integrate peak current protection function, and balance current sampling accuracy and system protection reliability. Summary of the Invention

[0005] The purpose of this invention is to provide an analog sampling and protection circuit that solves the problem of multiple intersections. It not only solves the problem of output jitter caused by multiple intersections due to ripple current in existing digital control, but also enables peak current protection.

[0006] To achieve the above objectives, the present invention employs the following technical solutions.

[0007] An analog sampling and protection circuit for resolving multiple intersections includes a Hall current sensor, resistors R1~R22, capacitors C1~C7, diodes D1~D4, operational amplifiers OP1~OP6, comparator COMP, inverter NOT, digital processing chip DSP, and buffer.

[0008] The analog sampling circuit includes a current-voltage signal conversion network, a first-stage proportional amplifier network, a sampling signal filtering network, a current ripple processing network, a second-stage proportional amplifier network, and a signal processing control and isolation network, used to acquire and process current signals;

[0009] The protection circuit is a peak current protection circuit, including a precision rectifier network, a voltage comparison network, and the aforementioned signal processing control and isolation network, used to achieve peak current protection;

[0010] The signal processing control and isolation network includes a digital processing chip (DSP) and a buffer. The DSP receives and processes the sampled signal and generates a PWM control signal, while the buffer transmits the control signal. The DSP also controls the working state of the buffer through input and output ports.

[0011] Furthermore, the current-voltage signal conversion network includes a Hall current sensor, a resistor R1, and a capacitor C1. The first end of the resistor R1 is connected to the Hall output current, and the second end is grounded. The capacitor C1 is connected in parallel with the resistor R1.

[0012] Furthermore, the first-stage proportional amplifier network includes resistors R2, R3, R4, C2, and operational amplifier OP1; the first end of resistor R2 is connected to the Hall output current, the second end of resistor R2 is connected to the negative input terminal of operational amplifier OP1 and is also connected to the first end of resistor R4 and capacitor C2; the second ends of resistor R4 and capacitor C2 are both connected to the output terminal of operational amplifier OP1, and resistor R4 and capacitor C2 are connected in parallel; the first end of resistor R3 is connected to the positive input terminal of operational amplifier OP1, and the second end of resistor R3 is grounded.

[0013] Furthermore, the sampling signal filtering network includes a resistor R5 and a capacitor C3; the first end of the resistor R5 is connected to the output of the first-stage proportional amplifier network, the second end of the resistor R5 is connected to the capacitor C3, and the second end of the capacitor C3 is grounded.

[0014] Furthermore, the current ripple processing network includes a voltage follower composed of operational amplifier OP2, a band-stop filter composed of a T-type low-pass filter and a T-type high-pass filter connected in parallel, and a voltage follower composed of operational amplifier OP3 connected in sequence.

[0015] Furthermore, the current ripple processing network includes operational amplifiers OP2-OP3, resistors R6-R9, and capacitors C4-C7; the positive input terminal of operational amplifier OP2 is connected to the output terminal of the sampling signal filtering network, and the negative input terminal of operational amplifier OP2 is connected to its own output terminal; the first terminal of resistor R6 is connected to the output terminal of operational amplifier OP2, the second terminal of resistor R6 is connected to the first terminals of capacitors C4 and C5 and the first terminal of resistor R7, the second terminals of capacitors C4 and C5 are grounded, and capacitors C4 and C5 are connected in parallel; the second terminal of resistor R7 is connected to the positive input terminal of operational amplifier OP3, and resistors R6-R9 and... Capacitors C4 and C5 form a T-type low-pass filter; the first terminal of capacitor C6 is connected to the output terminal of operational amplifier OP2, and the second terminal of capacitor C6 is connected to the first terminals of resistors R8 and R9. The second terminals of resistors R8 and R9 are grounded and connected in parallel. The first terminal of capacitor C7 is connected to the second terminal of capacitor C6, and the second terminal of capacitor C7 is connected to the positive input terminal of operational amplifier OP3. Capacitors C6 and C7 and resistors R8 and R9 form a T-type high-pass filter; the negative input terminal of operational amplifier OP3 is connected to its own output terminal; resistors R6 = R7 and R8 = R9, and capacitors C4 = C5 and C6 = C7.

[0016] Furthermore, the second-stage proportional amplifier network includes resistors R10~R12, operational amplifier OP4, and diode D1; the first end of resistor R10 is connected to the output of the current ripple processing network, the second end of resistor R10 is connected to the negative input of operational amplifier OP4 and the first end of resistor R12, and the second end of resistor R12 is connected to the output of operational amplifier OP4; the first end of resistor R11 is connected to the positive input of operational amplifier OP4, and the second end of resistor R11 is grounded; the output of operational amplifier OP4 is connected to the signal input pin of the digital processing chip DSP; the cathode of diode D1 is connected to the output of operational amplifier OP4, and the anode of diode D1 is connected to 3.3V.

[0017] Furthermore, the precision rectifier network includes resistors R13~R19, diodes D2~D3, and operational amplifiers OP5~OP6. The first terminal of resistor R13 is connected to the output of the sampling signal filtering network; the second terminal of resistor R13 is simultaneously connected to the negative input of operational amplifier OP5, the first terminal of resistor R14, and the cathode of diode D2; the anode of diode D2 is simultaneously connected to the output of operational amplifier OP5 and the cathode of diode D3; the second terminal of resistor R14 is simultaneously connected to the anode of diode D3 and the first terminal of resistor R17; the first terminal of resistor R15 is connected to the positive input of operational amplifier OP5, and the second terminal of resistor R15 is grounded; the first terminal of resistor R16 is connected to the first terminal of resistor R13; the second terminal of resistor R16 is connected to the negative input of operational amplifier OP6, the second terminal of resistor R17, and the first terminal of resistor R18; the second terminal of resistor R18 is connected to the output of operational amplifier OP6; the first terminal of resistor R19 is connected to the positive input of operational amplifier OP6, and the second terminal of resistor R19 is grounded.

[0018] Furthermore, the voltage comparison network includes resistors R20~R22, comparator COMP, inverter NOT, and diode D4; the first end of resistor R20 is connected to the reference signal, and the second end of resistor R20 is connected to both the positive input of comparator COMP and the first end of resistor R21; the second end of resistor R21 is connected to the output of comparator COMP; the negative input of comparator COMP is connected to the output of the precision rectification network; the first end of resistor R22 is connected to both the output of comparator COMP and the input of inverter NOT, and the second end of resistor R22 is connected to VCC; the output of inverter NOT is connected to the cathode of diode D4, and the anode of diode D4 is grounded; the output of inverter NOT is also connected to the input / output port of the digital processing chip DSP and the enable pin of the buffer.

[0019] Furthermore, the buffer is a bidirectional bus buffer. The digital processing chip DSP outputs four PWM signals to the buffer, which is used to transmit PWM signals. When the digital processing chip DSP receives a trigger signal from the protection circuit, it controls the buffer to stop working to cut off the PWM signal output.

[0020] The advantages of this invention are as follows: the current Hall sensor collects the current signal, which is then converted into a voltage signal by a current-to-voltage signal conversion network; the voltage signal is amplified by a first-stage proportional amplifier network and filtered by a sampling signal filtering network before entering a current ripple processing network; the band-stop filter in the current ripple processing network removes ripple components, and the second-stage proportional amplifier network adjusts the signal amplitude to the appropriate range before transmitting it to the DSP; the DSP calculates the signal and generates a PWM signal, which is output through a 74LVC245 to achieve precise control; the entire process processes ripple through analog circuits, eliminating signal delay and solving the problem of multiple intersections in digital control.

[0021] The sampled signal is shunted by resistor R5 and then enters a precision rectifier network, where it is converted into a positive level signal without attenuation. This positive level signal is input to a voltage comparison network and compared with a reference signal. When the signal is higher than the reference signal, the comparator COMP outputs a low level, which is converted to a high level by the inverter NOT. This locks the PWM conversion of the 74LVC245, stopping the output, and sends an alarm signal to the DSP. When the signal is lower than the reference signal, the comparator COMP outputs a high level, which is converted to a low level by the inverter NOT. The DSP confirms that there is no alarm, and the 74LVC245 is working normally, achieving real-time protection against peak current. Attached Figure Description

[0022] Figure 1 This is the circuit diagram for analog sampling and protection in Embodiment 1 of the present invention to solve the problem of multiple intersections;

[0023] Figure 2 This is the equivalent diagram of the sampling voltage being greater than zero in Embodiment 1 of the present invention;

[0024] Figure 3 This is the equivalent diagram of the sampling voltage being less than zero in Embodiment 1 of the present invention. Detailed Implementation

[0025] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0026] In this embodiment, the following is constructed: Figure 1 The analog sampling and protection circuit diagram shown includes a Hall current sensor, resistors R1~R22, capacitors C1~C7, diodes D1~D4, operational amplifiers OP1~OP6, comparator COMP, inverter NOT, digital processing chip DSP, and a buffer. The buffer is a bidirectional bus buffer 74LVC245.

[0027] The signal processing control and isolation network is a common network for analog sampling circuits and protection circuits. It consists of a DSP and a 74LVC245. The DSP is mainly used for sampling signal calculation and generates PWM for system control. The DSP output generates four PWM signals and outputs them to the 74LVC245. At the same time, it controls the 74LVC245's enable pin OE through I / O to control whether the 74LVC245 is working.

[0028] The analog sampling circuit includes a current-voltage signal conversion network, a first-stage proportional amplifier network, a sampling signal filtering network, a current ripple processing network, a second-stage proportional amplifier network, and a signal processing control and isolation network.

[0029] The current-voltage signal conversion network includes a Hall current sensor, a resistor R1, and a capacitor C1. The first end of the resistor R1 is connected to the Hall output current, and the second end is grounded. The capacitor C1 is connected in parallel with the resistor R1.

[0030] The first-stage proportional amplifier network includes resistors R2, R3, R4, C2, and operational amplifier OP1. The first terminal of resistor R2 is connected to the Hall output current, and the second terminal of resistor R2 is connected to the negative input terminal of operational amplifier OP1 and also to the first terminals of resistor R4 and capacitor C2. The second terminals of resistor R4 and capacitor C2 are both connected to the output terminal of operational amplifier OP1, and resistor R4 and capacitor C2 are connected in parallel. The first terminal of resistor R3 is connected to the positive input terminal of operational amplifier OP1, and the second terminal of resistor R3 is grounded.

[0031] The sampling signal filtering network includes resistor R5 and capacitor C3. The first terminal of resistor R5 is connected to the output of the first-stage proportional amplifier network, and the second terminal of resistor R5 is connected to capacitor C3, with the second terminal of capacitor C3 grounded. R3 and C3 form the filtering network, and its filter cutoff frequency is:

[0032] .

[0033] The current ripple processing network includes operational amplifiers OP2-OP3, resistors R6-R9, and capacitors C4-C7. The positive input of operational amplifier OP2 is connected to the output of the sampling signal filtering network, and the negative input of operational amplifier OP2 is connected to its own output to form a voltage follower. The first end of resistor R6 is connected to the output of operational amplifier OP2, and the second end of resistor R6 is connected to the first ends of capacitors C4 and C5 and the first end of resistor R7. The second ends of capacitors C4 and C5 are grounded and connected in parallel. The second end of resistor R7 is connected to the positive input of operational amplifier OP3. Resistors R6-R7 and capacitors C4-C5 form a T-type low-pass filter. The circuit consists of: capacitor C6 connected to the output of operational amplifier OP2; capacitor C6 connected to the first terminals of resistors R8 and R9; resistors R8 and R9 grounded; resistors R8 and R9 connected in parallel; capacitor C7 connected to the second terminal of capacitor C6; capacitor C7 connected to the positive input of operational amplifier OP3; capacitors C6-C7 and resistors R8-R9 form a T-type high-pass filter; a T-type low-pass filter and a T-type high-pass filter connected in parallel form a band-stop filter; the negative input of operational amplifier OP3 connected to its own output forms a voltage follower; resistors R6=R7, R8=R9; capacitors C4=C5, C6=C7. Its cutoff frequency is:

[0034] .

[0035] Since the high-pass filter and low-pass filter have the same cutoff frequency, which is the ripple current frequency, the current can pass through both frequencies higher and lower than the current ripple frequency. This achieves the filtering out of the sampling current ripple without causing a delay in the sampling signal. It solves the problem of multiple intersections caused by the introduction of current ripple into digital control and avoids affecting the output waveform jitter.

[0036] The second-stage proportional amplifier network includes resistors R10-R12, operational amplifier OP4, and clamping diode D1. The first terminal of resistor R10 is connected to the output of the current ripple processing network, and the second terminal of resistor R10 is connected to the negative input terminal of operational amplifier OP4 and the first terminal of resistor R12. The second terminal of resistor R12 is connected to the output of operational amplifier OP4. The first terminal of resistor R11 is connected to the positive input terminal of operational amplifier OP4, and the second terminal of resistor R11 is grounded. The output of operational amplifier OP4 is connected to the signal input pin of the digital processing chip (DSP). The cathode of diode D1 is connected to the output of operational amplifier OP4, and the anode of diode D1 is connected to 3.3V. Its main function is to limit the sampled current signal to 3.3V when the current signal is abnormal, preventing damage to the DSP due to overvoltage.

[0037] The protection circuit is a peak current protection circuit, including a precision rectifier network, a voltage comparison network, and the aforementioned signal processing control and isolation network.

[0038] The precision rectifier network includes resistors R13-R19, diodes D2-D3, and operational amplifiers OP5-OP6. The first terminal of resistor R13 is connected to the output of the sampling signal filtering network. The second terminal of resistor R13 is simultaneously connected to the negative input of operational amplifier OP5, the first terminal of resistor R14, and the cathode of diode D2. The anode of diode D2 is simultaneously connected to the output of operational amplifier OP5 and the cathode of diode D3. The second terminal of resistor R14 is simultaneously connected to the anode of diode D3 and the first terminal of resistor R17. The first terminal of resistor R15 is connected to the positive input of operational amplifier OP5, and the second terminal of resistor R15 is grounded. The first terminal of resistor R16 is connected to the first terminal of resistor R13. The second terminal of resistor R16 is connected to the negative input of operational amplifier OP6, the second terminal of resistor R17, and the first terminal of resistor R18. The second terminal of resistor R18 is connected to the output of operational amplifier OP6. The first terminal of resistor R19 is connected to the positive input of operational amplifier OP6, and the second terminal of resistor R19 is grounded.

[0039] The working principle of a precision rectifier circuit is as follows: when the input voltage is greater than zero, diode D2 is turned off and D3 is turned on. Its equivalent circuit is as follows: Figure 2 As shown, OP5 is an inverting proportional operational amplifier, and OP6 is an inverting adder. One input signal is Vin, and the other input signal is the output of op-amp OP5. Therefore, their input-output relationship is as follows:

[0040]

[0041] Where R13=R14, R18=R16=2R17, the input-output relationship is:

[0042] .

[0043] When the input voltage is less than zero, diode D2 conducts and D3 is turned off. Its equivalent circuit is as follows: Figure 3 As shown, the output of op-amp OP5 is off, the input pin to the left of resistor R17 is zero, and the input pin of resistor R16 is Vin. The input-output relationship is as follows:

[0044]

[0045] After the sampled signal passes through a precision rectifier circuit, the input signal is converted from a negative level to a positive level of the same amplitude. The amplitude of the positive level signal remains unchanged, thus achieving signal rectification without attenuation.

[0046] The voltage comparison network includes resistors R20-R22, comparator COMP, inverter NOT, and diode D4. The first terminal of resistor R20 is connected to the reference signal, and the second terminal of resistor R20 is connected to both the positive input of comparator COMP and the first terminal of resistor R21. The second terminal of resistor R21 is connected to the output of comparator COMP. The negative input of comparator COMP is connected to the output of the precision rectifier network. The first terminal of resistor R22 is connected to both the output of comparator COMP and the input of inverter NOT, and the second terminal of resistor R22 is connected to VCC. The output of inverter NOT is connected to the cathode of diode D4, and the anode of diode D4 is grounded. The output of inverter NOT is also connected to the input / output port (I / O port) of the digital processing chip (DSP) and the enable pin (OE) of the buffer.

[0047] The peak current protection principle is as follows: After the precision rectifier network converts the signal into a lossless positive level, it is compared with a reference signal. When the signal is higher than the reference signal, the comparator COMP outputs a low level, which is then converted to a high level by the inverter NOT, locking the PWM conversion of the buffer 74LVC245 and stopping the output. At the same time, an alarm high level is sent to the DSP. When the signal is lower than the reference signal, the comparator COMP outputs a high level, which is converted to a low level by the inverter NOT. The DSP receives the low level to confirm that there is no alarm, the enable signal OE of the buffer 74LVC245 is normal, and the 74LVC245 performs normal PWM conversion, resulting in normal output. Diode D4 is a clamping diode that limits the output of the inverter NOT to a safe range, preventing high-level glitches from damaging the DSP and the buffer 74LVC245.

[0048] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An analog sampling and protection circuit that addresses multiple-interception, characterized in that, It includes Hall current sensors, resistors R1~R22, capacitors C1~C7, diodes D1~D4, operational amplifiers OP1~OP6, comparator COMP, inverter NOT, digital processing chip DSP and buffer; The analog sampling circuit includes a current-voltage signal conversion network, a first-stage proportional amplifier network, a sampling signal filtering network, a current ripple processing network, a second-stage proportional amplifier network, and a signal processing control and isolation network, used to acquire and process current signals; The protection circuit is a peak current protection circuit, including a precision rectifier network, a voltage comparison network, and the aforementioned signal processing control and isolation network, used to achieve peak current protection; The signal processing control and isolation network includes a digital processing chip (DSP) and a buffer. The DSP is used to receive and process the sampled signal and generate a PWM control signal. The buffer is used to transmit the control signal. The DSP also controls the working state of the buffer through input and output ports. The current ripple processing network includes operational amplifiers OP2-OP3, resistors R6-R9, and capacitors C4-C7. The positive input terminal of operational amplifier OP2 is connected to the output terminal of the sampling signal filtering network, and the negative input terminal of operational amplifier OP2 is connected to its own output terminal to form a voltage follower. The first terminal of resistor R6 is connected to the output terminal of operational amplifier OP2, and the second terminal of resistor R6 is connected to the first terminals of capacitors C4 and C5 and the first terminal of resistor R7. The second terminals of capacitors C4 and C5 are grounded and connected in parallel. The second terminal of resistor R7 is connected to the positive input terminal of operational amplifier OP3. Resistors R6-R7 and capacitors C4-C5 form a T-type low-pass filter. A high-pass filter is formed by connecting the first terminal of capacitor C6 to the output terminal of operational amplifier OP2, and the second terminal of capacitor C6 to the first terminals of resistors R8 and R9. The second terminals of resistors R8 and R9 are grounded. Resistors R8 and R9 are connected in parallel. The first terminal of capacitor C7 is connected to the second terminal of capacitor C6, and the second terminal of capacitor C7 is connected to the positive input terminal of operational amplifier OP3. Capacitors C6-C7 and resistors R8-R9 form a T-type high-pass filter. A band-stop filter is formed by connecting a T-type low-pass filter and a T-type high-pass filter in parallel. The negative input terminal of operational amplifier OP3 is connected to its own output terminal to form a voltage follower. Resistors R6=R7, R8=R9, and capacitors C4=C5 and C6=C7. The high-pass filter and the low-pass filter have the same cutoff frequency, which is the ripple current frequency.

2. The analog sampling and protection circuit for multiple-interception according to claim 1, wherein, The current-voltage signal conversion network includes a Hall current sensor, a resistor R1, and a capacitor C1. The first end of the resistor R1 is connected to the Hall output current, and the second end is grounded. The capacitor C1 is connected in parallel with the resistor R1.

3. The analog sampling and protection circuit for multiple-interception according to claim 1, wherein, The first-stage proportional amplifier network includes resistors R2, R3, R4, C2, and operational amplifier OP1. The first end of resistor R2 is connected to the Hall output current, and the second end of resistor R2 is connected to the negative input terminal of operational amplifier OP1 and simultaneously connected to the first ends of resistor R4 and capacitor C2. The second ends of resistor R4 and capacitor C2 are both connected to the output terminal of operational amplifier OP1, and resistor R4 and capacitor C2 are connected in parallel. The first end of resistor R3 is connected to the positive input terminal of operational amplifier OP1, and the second end of resistor R3 is grounded.

4. The analog sampling and protection circuit for multiple-interception according to claim 1, wherein, The sampling signal filtering network includes a resistor R5 and a capacitor C3; the first end of the resistor R5 is connected to the output of the first-stage proportional amplifier network, the second end of the resistor R5 is connected to the capacitor C3, and the second end of the capacitor C3 is grounded.

5. The analog sampling and protection circuit of claim 1, wherein, The second-stage proportional amplifier network includes resistors R10~R12, operational amplifier OP4, and diode D1. The first end of resistor R10 is connected to the output of the current ripple processing network, the second end of resistor R10 is connected to the negative input of operational amplifier OP4 and the first end of resistor R12, and the second end of resistor R12 is connected to the output of operational amplifier OP4. The first end of resistor R11 is connected to the positive input of operational amplifier OP4, and the second end of resistor R11 is grounded. The output of operational amplifier OP4 is connected to the signal input pin of the digital processing chip DSP. The cathode of diode D1 is connected to the output of operational amplifier OP4, and the anode of diode D1 is connected to 3.3V.

6. The analog sampling and protection circuit for resolving multiple intersections according to claim 1, characterized in that, The precision rectifier network includes resistors R13-R19, diodes D2-D3, and operational amplifiers OP5-OP6. The first terminal of resistor R13 is connected to the output of the sampling signal filtering network; the second terminal of resistor R13 is simultaneously connected to the negative input of operational amplifier OP5, the first terminal of resistor R14, and the cathode of diode D2. The anode of diode D2 is simultaneously connected to the output of operational amplifier OP5 and the cathode of diode D3. The second terminal of resistor R14 is simultaneously connected to the anode of diode D3 and the first terminal of resistor R17. The first terminal of resistor R15 is connected to the positive input of operational amplifier OP5, and the second terminal of resistor R15 is grounded. The first terminal of resistor R16 is connected to the first terminal of resistor R13; the second terminal of resistor R16 is connected to the negative input of operational amplifier OP6, the second terminal of resistor R17, and the first terminal of resistor R18. The second terminal of resistor R18 is connected to the output of operational amplifier OP6. The first terminal of resistor R19 is connected to the positive input of operational amplifier OP6, and the second terminal of resistor R19 is grounded.

7. The analog sampling and protection circuit for resolving multiple intersections according to claim 1, characterized in that, The voltage comparison network includes resistors R20-R22, comparator COMP, inverter NOT, and diode D4. The first terminal of resistor R20 is connected to the reference signal, and the second terminal of resistor R20 is connected to both the positive input terminal of comparator COMP and the first terminal of resistor R21. The second terminal of resistor R21 is connected to the output terminal of comparator COMP. The negative input terminal of comparator COMP is connected to the output terminal of the precision rectifier network. The first terminal of resistor R22 is connected to both the output terminal of comparator COMP and the input terminal of inverter NOT, and the second terminal of resistor R22 is connected to VCC. The output terminal of inverter NOT is connected to the cathode of diode D4, and the anode of diode D4 is grounded. The output terminal of inverter NOT is also connected to the input / output port of the digital processing chip DSP and the enable pin of the buffer.

8. The analog sampling and protection circuit for resolving multiple intersections according to claim 1, characterized in that, The buffer is a bidirectional bus buffer. The digital processing chip (DSP) outputs four PWM signals to the buffer, which is used to transmit PWM signals. When the DSP receives a trigger signal from the protection circuit, it controls the buffer to stop working and cut off the PWM signal output.

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