An internal signal adjustable chip trimming test circuit

Abstract

The present application relates to the technical field of chip testing, and in particular to a chip trimming test circuit with adjustable internal signals. The chip trimming test circuit with adjustable internal signals provided by the present application is provided with a test module selection circuit and a logic signal generation circuit. After an input signal is received by the first end of the chip trimming test circuit, the selection signal and trimming signal can be output to control the corresponding test module to work. The test module generates internal signals to process the trimming fuses, thereby reducing the operation difficulty of the chip trimming test circuit and simplifying the operation process of the chip trimming test circuit.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and more specifically to a chip tuning and testing circuit with adjustable internal signals. Background Technology

[0002] Existing chip trimming test circuits typically require multiple input signals to be connected to a test module selection circuit and a trimming signal generation circuit, respectively. First, the test module selection circuit selects the appropriate test module based on the input signal. Then, the trimming signal generation circuit generates the trimming signal required by the corresponding test module based on the input signal. Finally, the corresponding test module performs a "fuse-burning" process on the corresponding trimming fuse in its internal trimming circuit based on the trimming signal, thereby completing the chip trimming test. However, the power levels of the trimming fuses inside chips of different power levels are also different, while the trimming signals generated by the existing trimming signal generation circuits are all fixed values. Therefore, when the power level of the trimming fuse is low, it will increase the energy consumption of the chip trimming test circuit. When the power level of the trimming fuse is high, it will prolong the time required to "burn" the trimming fuse, thus greatly increasing the trimming test time.

[0003] Therefore, the chip tuning and testing circuits in the prior art require multiple external input signals and multiple steps to complete the tuning and testing. At the same time, the internal signals of the chip tuning and testing circuits in the prior art cannot be adaptively adjusted according to the chip power level. As a result, the chip tuning and testing circuits in the prior art are time-consuming, labor-intensive and have poor adaptability, and urgently need to be improved. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a chip tuning and testing circuit with adjustable internal signals to solve the technical problem that the chip tuning and testing circuit in the prior art requires multiple external input signals, resulting in time-consuming and laborious operation.

[0005] The technical solutions provided by the embodiments of the present invention are as follows:

[0006] The first aspect of this invention provides a chip tuning and testing circuit with adjustable internal signals, comprising:

[0007] The test module selection circuit has a first terminal that receives an input signal, a second terminal that is connected to an external power supply, a third terminal that is grounded, and multiple fourth terminals that are connected to multiple test modules. It is used to output a high-level selection signal to the corresponding test module among the multiple test modules according to the input signal.

[0008] A logic signal generating circuit has a first terminal that receives the input signal, a second terminal that is connected to an external power supply, a third terminal that is grounded, and multiple fourth terminals that are connected to multiple test modules. It is used to output adjustment signals to the corresponding test modules among the multiple test modules according to the input signal.

[0009] Multiple test modules are used to generate internal signals to process the adjustment fuse when the corresponding test module receives the high-level selection signal and the adjustment signal.

[0010] In one alternative implementation, the input signal includes a first waveform signal and a second waveform signal connected in sequence, wherein the first waveform signal and the second waveform signal include a plurality of square wave signals with varying high-level durations.

[0011] In one optional implementation, the test module selection circuit includes: a first voltage generation circuit, a first trigger circuit, and a selection signal conversion circuit;

[0012] The first voltage generating circuit has a first terminal receiving an input signal, a second terminal grounded, a third terminal connected to an external power supply, a fourth terminal connected to the first terminal of the first trigger circuit, and a fifth terminal connected to the second terminal of the first trigger circuit. The first voltage generating circuit is used to charge and discharge its internal first capacitor according to the input signal to generate a first voltage signal including multiple square wave signals. The first time constant of the first capacitor is different from the high-level duration of the square wave signal in the input signal.

[0013] The first trigger circuit has its third terminal grounded and its multiple fourth terminals respectively connected to multiple input terminals of the selection signal conversion circuit. The first trigger circuit is used to generate a first trigger signal including a combination of high and low levels based on the input signal and the first voltage signal.

[0014] The selection signal conversion circuit has multiple output terminals connected to multiple test modules respectively. The selection signal conversion circuit is used to output selection signals to the corresponding test modules among the multiple test modules according to the first trigger signal.

[0015] In one optional embodiment, the first voltage generating circuit includes a first switching transistor, a second switching transistor, a first inverter, a first capacitor, and a first resistor; the first triggering circuit includes a third switching transistor, a plurality of cascaded D flip-flops, and a latched D flip-flop.

[0016] The input terminal of the first inverter receives the input signal, the output terminal of the first inverter is connected to the first terminal of the first switch and the first terminal of the second switch, the second terminal of the first switch is connected to an external power supply, the third terminal of the first switch is connected to one end of a first resistor, the other end of the first resistor is connected to the second terminal of the second switch, one end of the first capacitor and the input terminal of the first D flip-flop in a plurality of cascaded D flip-flops, and the third terminal of the second switch is connected to the other end of the first capacitor and grounded.

[0017] In a series of cascaded D flip-flops, the input of each subsequent D flip-flop is connected to the non-inverting output of the preceding D flip-flop. The non-inverting output of each cascaded D flip-flop is connected to a selection signal conversion circuit. The clock terminals of the cascaded D flip-flops are connected to the clock terminal of the latched D flip-flop, the output of the first inverter, and the first terminal of the third switch. The input of the latched D flip-flop is connected to the non-inverting output of the last D flip-flop in the series of cascaded D flip-flops. The output of the latched D flip-flop is connected to the second terminal of the third switch, and the third terminal of the third switch is grounded.

[0018] In one optional implementation, each test module includes multiple fuse circuits, and the logic signal generation circuit includes a second voltage generation circuit, a third voltage generation circuit, and a second trigger circuit.

[0019] The second voltage generating circuit has a first terminal that receives an input signal, a second terminal that is connected to an external power supply, a third terminal that is grounded, a fourth terminal that is connected to the first terminal of the third voltage generating circuit, and a fifth terminal that is connected to the first terminal of the second trigger circuit. The second voltage generating circuit is used to charge and discharge its internal second capacitor according to the input signal to generate a second voltage signal including multiple square wave signals.

[0020] The third voltage generating circuit has its second terminal connected to an external power supply, its third terminal grounded, and its fourth terminal connected to the second terminal of the second trigger circuit. The third voltage generating circuit is used to charge and discharge its internal third capacitor according to the input signal to generate a third voltage signal including multiple square wave signals. The second time constant of the second capacitor, the third time constant of the third capacitor, and the high-level duration of the square wave signal in the input signal are all different.

[0021] The second trigger circuit has multiple third terminals connected to the corresponding fuse circuit in each test module. The second trigger circuit is used to output multiple adjustment signals according to the second voltage signal and the third voltage signal. Each adjustment signal is input to the corresponding fuse circuit in each test module.

[0022] In one optional embodiment, the second voltage generating circuit includes a fourth switch, a fifth switch, a fourth inverter, a second resistor, and a second capacitor; the third voltage generating circuit includes a sixth switch, a seventh switch, a third resistor, and a third capacitor; and the second trigger circuit includes a seventh inverter and multiple cascaded D flip-flops.

[0023] The input terminal of the fourth inverter receives the input signal, and the output terminal of the fourth inverter is connected to the first terminal of the fourth switch, the first terminal of the fifth switch, the first terminal of the sixth switch, and the first terminal of the seventh switch. The second terminal of the fourth switch is connected to an external power supply, and the third terminal of the fourth switch is connected to one end of the second resistor. The other end of the second resistor is connected to the second terminal of the fifth switch, one end of the second capacitor, and the input terminal of the first D flip-flop in a plurality of cascaded D flip-flops. The third terminal of the fifth switch is connected to the other end of the second capacitor and grounded.

[0024] The second terminal of the sixth switch is connected to an external power supply, the third terminal of the sixth switch is connected to one end of the third resistor, the other end of the third resistor is connected to the second terminal of the seventh switch, the first terminal of the third capacitor and the input terminal of the seventh inverter, and the third terminal of the seventh switch is connected to the other end of the third capacitor and grounded.

[0025] The output of the seventh inverter is connected to the clock terminal of each of the multiple cascaded D flip-flops. The input of the next D flip-flop in the multiple cascaded D flip-flops is connected to the non-inverting output of the previous D flip-flop. The non-inverting output of each D flip-flop in the multiple cascaded D flip-flops is connected to the corresponding fuse-burning circuit in each test module.

[0026] In one optional implementation, the chip tuning and testing circuit further includes:

[0027] A time signal adjustment circuit has a first terminal receiving an input signal, a second terminal connected to the fourth terminal of the second voltage generation circuit, a third terminal grounded, a fourth terminal connected to an external power supply, and a fifth terminal connected to the fifth terminal of the second voltage generation circuit. The time signal adjustment circuit is used to generate a time signal that is continuously high-level based on the input signal and the second voltage signal. The time signal is matched with the chip power level.

[0028] Each test module also includes an AND gate connected to each fuse-burning circuit. When the AND gate receives the high-level selection signal, the adjustment signal, and the time signal, it outputs an internal signal to the corresponding fuse-burning circuit so that the fuse-burning circuit processes the adjustment fuse.

[0029] In one optional embodiment, the time signal conditioning circuit includes a first switch, a second switch, a third switch, a fourth switch, an eighth inverter, a ninth inverter, a tenth inverter, an eleventh inverter, a first NOR gate, and a second NOR gate.

[0030] The positive control terminal of the first switch, the negative control terminal of the second switch, the negative control terminal of the third switch, and the positive control terminal of the fourth switch receive the input signal. The negative control terminals of the first switch and the fourth switch are grounded. The positive control terminals of the second switch and the third switch are connected to an external power supply. The first terminal of the first switch is connected to the fifth terminal of the second voltage generating circuit. The second terminal of the first switch is connected to the input terminal of the eighth inverter and the first terminal of the third switch.

[0031] The second terminal of the third switch is connected to the output terminal of the second NOR gate. The output terminal of the eighth inverter is connected to the first terminal of the second switch and the first input terminal of the second NOR gate. The second terminal of the second switch is connected to the first input terminal of the first NOR gate, the input terminal of the ninth inverter, and the first terminal of the fourth switch. The second terminal of the fourth switch is connected to the output terminal of the eleventh inverter. The input terminal of the eleventh inverter is connected to the output terminal of the first NOR gate. The input terminal of the tenth inverter is connected to the fourth terminal of the second voltage generating circuit. The output terminal of the tenth inverter is connected to the second input terminal of the first NOR gate and the second input terminal of the second NOR gate. The output terminal of the ninth inverter is connected to each AND gate in each test module.

[0032] In one optional embodiment, the first waveform signal includes a first preset number of square wave signals, the number of cascaded D flip-flops in the first trigger circuit is set according to the number of test modules, the first preset number is the same as the number of D flip-flops in the first trigger circuit, and the high-level duration of the first square wave signal in the first waveform signal is greater than the first time constant.

[0033] In one optional implementation, the selection signal conversion circuit adjusts the level of the selection signal output to each test module according to the high-low level combination in the first trigger signal, and each high-low level combination can only make the selection signal of one test module high, while the others are low.

[0034] The combination of high and low levels is adjusted according to the duration of the high level of the square wave signal starting from the second square wave signal in the first waveform signal. When the duration of the high level of the second square wave signal is greater than the first time constant, the output of the last D flip-flop in the cascaded D flip-flops in the first trigger circuit is adjusted to a high level; when the duration of the high level of the second square wave signal is less than the first time constant, it is adjusted to a low level. Similarly, when the duration of the high level of the last square wave signal in the first waveform signal is greater than the first time constant, the output of the first D flip-flop in the cascaded D flip-flops in the first trigger circuit is adjusted to a high level; when the duration of the high level of the last square wave signal in the first waveform signal is less than the first time constant, it is adjusted to a low level.

[0035] In one optional embodiment, the second waveform signal includes a second preset number of square wave signals, the high-level duration of the second preset number of square wave signals is greater than the third time constant, and the second preset number, the number of multiple cascaded D flip-flops in the second trigger circuit, and the number of fuse circuits in each test module are the same.

[0036] In one optional embodiment, the high or low level of the output level of the multiple cascaded D flip-flops in the second trigger circuit is determined based on the fuse circuit to be operated, and the high or low level of the output level of the multiple cascaded D flip-flops in the second trigger circuit is adjusted by the time when the second preset number of square wave signals are at a high level.

[0037] When the time for which the first square wave signal in the second waveform signal is at a high level is greater than the second time constant, the last D flip-flop in the multiple cascaded D flip-flops outputs a high level; when the time for which the first square wave signal in the second waveform signal is at a high level is greater than the third time constant and less than the second time constant, the last D flip-flop outputs a low level.

[0038] When the last square wave signal in the second waveform signal is at a high level for a period of time greater than the second time constant, the first D flip-flop in the multiple cascaded D flip-flops outputs a high level. When the first square wave signal in the second waveform signal is at a high level for a period of time greater than the third time constant and less than the second time constant, the first D flip-flop outputs a low level.

[0039] In one optional embodiment, the second waveform signal further includes a third preset number of first-type square wave signals, wherein the first-type square wave signals are square wave signals with a high-level duration less than the third time constant, and the second preset number of square wave signals includes a fourth preset number of second-type square wave signals, wherein the second-type square wave signals are square wave signals with a high-level duration greater than the second time constant, and the third preset number and the fourth preset number are equal; each second-type square wave signal is sequentially connected to one first-type square wave signal;

[0040] The time during which the time signal output by the time signal conditioning circuit is at a high level is determined by the time between the falling edge of the second type square wave signal and the rising edge of the first type square wave signal that is sequentially connected to it.

[0041] The technical solution of this invention has the following advantages:

[0042] The chip trimming test circuit with adjustable internal signals provided in this embodiment of the invention includes a test module selection circuit and a logic signal generation circuit. After receiving an input signal through its first terminal, it can output a selection signal and a trimming signal to control the operation of the corresponding test module. The test module generates internal signals to process the trimming fuse, thereby reducing the operational difficulty of the chip trimming test circuit and simplifying the operation process of the chip trimming test circuit.

[0043] The chip tuning and testing circuit with adjustable internal signals provided in this embodiment of the invention can obtain an internal signal matching the chip's power level by connecting a suitable input signal through an input terminal. The tuning fuse is then processed based on this matching internal signal, enabling the selection of test modules and circuit tuning. This significantly improves the adaptability of the chip tuning and testing circuit, balances energy consumption and tuning test time, reduces operational difficulty, and simplifies the operation process. Attached Figure Description

[0044] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0045] Figure 1 This is a structural block diagram of the chip tuning and testing circuit with adjustable internal signals in an embodiment of the present invention;

[0046] Figure 2This is a structural block diagram of a chip tuning and testing circuit with adjustable internal signals in another embodiment of the present invention;

[0047] Figure 3 This is a structural block diagram of a chip tuning and testing circuit with adjustable internal signals in another embodiment of the present invention;

[0048] Figure 4 This is a schematic diagram of the internal signal adjustable chip tuning and testing circuit in an embodiment of the present invention.

[0049] Figure 5 This is a schematic diagram of the first waveform signal of the input signal in an embodiment of the present invention;

[0050] Figure 6 This is a schematic diagram of the voltage waveforms of the first voltage and the second voltage in an embodiment of the present invention;

[0051] Figure 7 This is a schematic diagram of the output voltage waveforms of the first D flip-flop, the second D flip-flop, and the third D flip-flop in an embodiment of the present invention;

[0052] Figure 8 This is a schematic diagram illustrating that the input signal in an embodiment of the present invention includes a first waveform signal and a second waveform signal;

[0053] Figure 9 This is a schematic diagram of the voltage waveforms of the second and third voltages in an embodiment of the present invention;

[0054] Figure 10 This is a schematic diagram of the output voltage waveforms of the fourth and fifth D flip-flops in an embodiment of the present invention;

[0055] Figure 11 This is a structural block diagram of a chip tuning and testing circuit with adjustable internal signals in another embodiment of the present invention;

[0056] Figure 12 This is a schematic diagram of the input waveforms of the time signal conditioning circuit in an embodiment of the present invention;

[0057] Figure 13 This is a schematic diagram of the waveform of the time signal in an embodiment of the present invention;

[0058] Figure 14 This is a schematic diagram comparing the waveforms of time signals under different time conditions in an embodiment of the present invention;

[0059] Figure 15 The present invention provides a structural block diagram of a chip tuning and testing circuit with adjustable internal signals in another embodiment. Detailed Implementation

[0060] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0061] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0062] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can also refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0063] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0064] This invention provides a chip tuning and testing circuit with adjustable internal signals, such as... Figure 1 As shown, the system includes: a test module selection circuit 10, whose first terminal receives the input signal IN, its second terminal is connected to an external power supply VDD, its third terminal is grounded, and its multiple fourth terminals are connected to multiple test modules 30. This circuit is used to output a high-level selection signal to the corresponding test module among the multiple test modules 30 according to the input signal; a logic signal generation circuit 20, whose first terminal receives the input signal IN, its second terminal is connected to an external power supply VDD, its third terminal is grounded, and its multiple fourth terminals are connected to the multiple test modules 30. This circuit is used to output a trimming signal (fuse burn signal) to the corresponding test module among the multiple test modules 30 according to the input signal; and multiple test modules 30, which generate internal signals to process the trimming fuse when the corresponding test module receives the high-level selection signal and the trimming signal. Figure 1 Only one test module is shown in the image.

[0065] Specifically, a test module selection circuit and a logic signal generation circuit are configured to control the operation of one of the multiple test modules. The test module selection circuit outputs a selection signal to determine which test module should operate next. For example, if five test modules are configured, the test module selection circuit outputs five selection signals (four low-level selection signals and one high-level selection signal). The high-level selection signal is input to the test module that needs to operate, while the other test modules that do not need to operate receive the low-level selection signal. It should be noted that the number of fourth terminals on the test module selection circuit is the same as the number of test modules, with each fourth terminal connected to one test module. When the input signal received by the test module selection circuit changes, it can output a high-level selection signal to different test modules.

[0066] After the test module selection circuit outputs a high-level selection signal to "select" a test module, that test module also needs to receive a trimming signal output by the logic signal generation circuit to enter the working state and generate internal signals. In other words, for each test module, it can only generate internal signals when it receives both a high-level selection signal and a trimming signal simultaneously; it will not work if it only receives either a high-level selection signal or a trimming signal.

[0067] In this invention, a test module selection circuit and a logic signal generation circuit are set up. After receiving the same input signal through their first terminals, they can output selection signals and adjustment signals respectively to control the operation of the corresponding test modules and generate internal signals to process the adjustment fuses, thereby reducing the operational difficulty of the chip adjustment test circuit and simplifying the operation process of the chip adjustment test circuit.

[0068] In one optional implementation, the input signal includes a first waveform signal and a second waveform signal connected in sequence, wherein the first waveform signal and the second waveform signal include a plurality of square wave signals with varying high-level durations.

[0069] like Figure 2 As shown, the test module selection circuit includes: a first voltage generation circuit, a first trigger circuit, and a selection signal conversion circuit.

[0070] The first voltage generating circuit 11 has a first terminal receiving an input signal IN, a second terminal grounded, a third terminal connected to an external power supply VDD, a fourth terminal connected to the first terminal of the first trigger circuit 12, and a fifth terminal connected to the second terminal of the first trigger circuit 12. The first voltage generating circuit 11 is used to charge and discharge its internal first capacitor according to the input signal to generate a first voltage signal including multiple square wave signals. The first time constant of the first capacitor is different from the high-level duration of the square wave signal in the input signal.

[0071] The first trigger circuit 12 has its third terminal grounded and its multiple fourth terminals respectively connected to multiple input terminals of the selection signal conversion circuit 13. The first trigger circuit 12 is used to generate a first trigger signal including a combination of high and low levels according to the input signal and the first voltage signal.

[0072] The selection signal conversion circuit 13 has multiple output terminals connected to multiple test modules respectively. The selection signal conversion circuit 13 is used to output selection signals to the corresponding test modules among the multiple test modules according to the first trigger signal.

[0073] The time constant of a capacitor characterizes the speed at which it charges or discharges; a larger time constant results in a faster charging and discharging speed. In the first voltage generation circuit, the first capacitor generates a charging and discharging process based on the high and low voltage changes caused by the square wave signal in the input signal. Specifically, when the high-level duration of the square wave signal in the input signal is greater than the first time constant, the first capacitor can complete the charging process within that high-level duration, resulting in the first voltage signal output by the first voltage generation circuit reaching a high level. Conversely, if the high-level duration is less than the first time constant, the first capacitor cannot complete the charging process, i.e., it is undercharged, and a low-level signal is output. Therefore, by setting the relationship between the high-level duration of each square wave signal in the input signal and the first time constant, the first voltage generation circuit can output the required first voltage signal.

[0074] In the first trigger circuit, multiple D flip-flops can be configured. When they receive an input signal and a first voltage signal, they can generate multiple high and low level signals. As the high and low levels of the input signal and the first voltage signal change, the combination of high and low levels generated by the first trigger circuit also changes. Specifically, the first trigger signal, including the high and low level combination, is input to a selection signal conversion circuit. This selection signal conversion circuit can adjust the output selection signal to each test module according to the input high and low level combination. Each high and low level combination can only make the selection signal of one test module high, while the others are low, thus enabling the selection of different test modules. Specifically, the selection signal conversion circuit can be implemented using logic gate circuits commonly used in the prior art, which will not be elaborated upon here.

[0075] In one alternative implementation, such as Figure 3 As shown, each test module includes multiple fuse circuits, and the logic signal generation circuit includes a second voltage generation circuit 21, a third voltage generation circuit 22, and a second trigger circuit 23.

[0076] The second voltage generating circuit 21 has a first terminal that receives the input signal IN, a second terminal that is connected to an external power supply VDD, a third terminal that is grounded, a fourth terminal that is connected to the first terminal of the third voltage generating circuit 22, and a fifth terminal that is connected to the first terminal of the second trigger circuit 23. The second voltage generating circuit 21 is used to charge and discharge its internal second capacitor according to the input signal to generate a second voltage signal including multiple square wave signals.

[0077] The third voltage generating circuit 22 has its second terminal connected to an external power supply VDD, its third terminal grounded, and its fourth terminal connected to the second terminal of the second trigger circuit 23. The third voltage generating circuit 22 is used to charge and discharge its internal third capacitor according to the input signal to generate a third voltage signal including multiple square wave signals. The second time constant of the second capacitor, the third time constant of the third capacitor, and the high-level duration of the square wave signal in the input signal are all different.

[0078] The second trigger circuit 23 has multiple third terminals connected to the corresponding fuse circuits in each test module. The second trigger circuit 23 is used to output multiple adjustment signals according to the second voltage signal and the third voltage signal. Each adjustment signal is input to the corresponding fuse circuit of each test module.

[0079] Specifically, similar to the first voltage generation circuit, the capacitors in the second and third voltage generation circuits are also fully charged or undercharged based on the time constant and the duration of the high-level signal in the input signal, thereby adjusting the square wave signal in the input signal to obtain the desired second and third voltage signals. Simultaneously, this embodiment includes multiple fuse-burning circuits in the test module, and multiple adjustment signals output by the second trigger circuit enable independent control of these multiple fuse-burning circuits. The multiple fuse-burning circuits in a single test module can process the adjustment fuses corresponding to the parameters requiring adjustment in the same functional module of the chip.

[0080] To achieve independent control of multiple fuse circuits in each test module, this embodiment uses multiple D flip-flops in the second trigger circuit. The output of each D flip-flop is connected to one fuse circuit in each of the multiple test modules. For example, if each test module includes a first fuse circuit, a second fuse circuit, a third fuse circuit, and so on up to the Nth fuse circuit, then the first D flip-flop is connected to the first fuse circuit in each test module, the second D flip-flop is connected to the second fuse circuit, and so on, with the Nth D flip-flop connected to the Nth fuse circuit. When there are M test modules, one D flip-flop is connected to M fuse circuits. For the test module selection circuit, the multiple outputs of its selection signal conversion circuit are connected to the multiple test modules respectively; that is, one output of the selection signal conversion circuit is connected to multiple fuse circuits in one test module.

[0081] Based on the aforementioned connection relationships and the settings of the input signals, the logic signal generation circuit can output one or more high-level signals as adjustment signals to the corresponding fuse circuits of multiple test modules. Thus, the logic signal generation circuit can send adjustment signals to multiple test modules, but the selection signal conversion circuit only sends a high-level selection signal to one test module. Therefore, only the fuse circuit that receives both the adjustment signal and the high-level selection signal will operate. Therefore, based on a single input signal, this embodiment only controls the operation of one or more fuse circuits within a single test module.

[0082] In one alternative implementation, such as Figure 4 As shown, the first voltage generating circuit includes a first switching transistor M1, a second switching transistor M2, a first inverter A1, a first capacitor C1, and a first resistor R1; the first triggering circuit includes a third switching transistor M3, multiple cascaded D flip-flops, and a latched D flip-flop.

[0083] The input terminal of the first inverter A1 receives the input signal IN. The output terminal of the first inverter A1 is connected to the first terminal of the first switch M1 and the first terminal of the second switch M2. The second terminal of the first switch M1 is connected to an external power supply. The third terminal of the first switch M1 is connected to one end of the first resistor R1. The other end of the first resistor R1 is connected to the second terminal of the second switch M2, one end of the first capacitor C1, and the input terminal of the first D flip-flop in a plurality of cascaded D flip-flops. The third terminal of the second switch M2 is connected to the other end of the first capacitor C1 and grounded.

[0084] In a series of cascaded D flip-flops, the input of the next D flip-flop is connected to the non-inverting output of the previous D flip-flop. The non-inverting output of each D flip-flop in the series of cascaded D flip-flops is connected to a selection signal conversion circuit. The clock terminals of the series of cascaded D flip-flops are connected to the clock terminal of the latched D flip-flop, the output of the first inverter A1, and the first terminal of the third switch M3. The input of the latched D flip-flop is connected to the non-inverting output of the last D flip-flop in the series of cascaded D flip-flops. The output of the latched D flip-flop is connected to the second terminal of the third switch M3. The third terminal of the third switch M3 is grounded.

[0085] Among them, Figure 4 In this circuit, multiple cascaded D flip-flops include a first D flip-flop D1 and a second D flip-flop D2, while a latched D flip-flop includes a third D flip-flop D3. The first voltage generation circuit also includes two inverters connected in series: a second inverter A2 and a third inverter A3. These two inverters are connected in series between one end of the first capacitor C1 and the input terminal of the first D flip-flop D1. Using two inverters connected in series enhances the signal driving capability.

[0086] The first waveform signal includes a first preset number of square wave signals. The number of cascaded D flip-flops in the first trigger circuit is set according to the number of test modules. The first preset number is the same as the number of D flip-flops in the first trigger circuit. The high-level duration of the first square wave signal in the first waveform signal is greater than the first time constant.

[0087] The combination of high and low levels in the first trigger signal is adjusted according to the duration of the high level of the square wave signal starting from the second square wave signal in the first waveform signal. When the duration of the high level of the second square wave signal is greater than the first time constant, the output of the last D flip-flop in the cascaded D flip-flops in the first trigger circuit is adjusted to a high level; when the duration of the high level of the second square wave signal is less than the first time constant, it is adjusted to a low level. Similarly, when the duration of the high level of the last square wave signal in the first waveform signal is greater than the first time constant, the output of the first D flip-flop in the cascaded D flip-flops in the first trigger circuit is adjusted to a high level; when the duration of the high level of the last square wave signal in the first waveform signal is less than the first time constant, it is adjusted to a low level.

[0088] like Figure 4 As shown, the second voltage generating circuit includes a fourth switch M4, a fifth switch M5, a fourth inverter A4, a second resistor R2, and a second capacitor C2; the third voltage generating circuit includes a sixth switch M6, a seventh switch M7, a third resistor R3, and a third capacitor C3; and the second trigger circuit includes a seventh inverter A7 and multiple cascaded D flip-flops.

[0089] The input terminal of the fourth inverter A4 receives the input signal IN. The output terminal of the fourth inverter A4 is connected to the first terminal of the fourth switch M4, the first terminal of the fifth switch M5, the first terminal of the sixth switch M6, and the first terminal of the seventh switch M7. The second terminal of the fourth switch M4 is connected to an external power supply. The third terminal of the fourth switch M4 is connected to one end of the second resistor R2. The other end of the second resistor R2 is connected to the second terminal of the fifth switch M5, one end of the second capacitor C2, and the input terminal of the first D flip-flop in the plurality of cascaded D flip-flops. The third terminal of the fifth switch M5 is connected to the other end of the second capacitor C2 and grounded.

[0090] The second terminal of the sixth switch M6 is connected to an external power supply, the third terminal of the sixth switch M6 is connected to one end of the third resistor R3, the other end of the third resistor R3 is connected to the second terminal of the seventh switch M7, the first terminal of the third capacitor C3 and the input terminal of the seventh inverter A7, and the third terminal of the seventh switch M7 is connected to the other end of the third capacitor C3 and grounded.

[0091] The output of the seventh inverter A7 is connected to the clock terminal of each of the multiple cascaded D flip-flops. The input of the next D flip-flop in the multiple cascaded D flip-flops is connected to the non-inverting output of the previous D flip-flop. The non-inverting output of each D flip-flop in the multiple cascaded D flip-flops is connected to the corresponding fuse-burning circuit in each test module.

[0092] Among them, Figure 4 In the second trigger circuit, multiple cascaded D flip-flops include a fourth D flip-flop D4 and a fifth D flip-flop D5. Simultaneously, the second voltage generation circuit also includes two series-connected inverters: a fifth inverter A5 and a sixth inverter A6. The two inverters are connected in series between one end of the second capacitor C2 and the input terminal of the fourth D flip-flop D4. Using two series-connected inverters enhances the signal driving capability.

[0093] The second waveform signal includes a second preset number of square wave signals, the high-level duration of the second preset number of square wave signals is greater than the third time constant, and the second preset number, the number of multiple cascaded D flip-flops in the second trigger circuit, and the number of fuse circuits in each test module are the same.

[0094] The output level of the multiple cascaded D flip-flops in the second trigger circuit is determined based on the fuse circuit to be operated. The output level of the multiple cascaded D flip-flops in the second trigger circuit is adjusted by the time when the second preset number of square wave signals are at a high level.

[0095] When the time for which the first square wave signal in the second waveform signal is at a high level is greater than the second time constant, the last D flip-flop in the multiple cascaded D flip-flops outputs a high level; when the time for which the first square wave signal in the second waveform signal is at a high level is greater than the third time constant and less than the second time constant, the last D flip-flop outputs a low level.

[0096] When the last square wave signal in the second waveform signal is at a high level for a period of time greater than the second time constant, the first D flip-flop in the multiple cascaded D flip-flops outputs a high level. When the first square wave signal in the second waveform signal is at a high level for a period of time greater than the third time constant and less than the second time constant, the first D flip-flop outputs a low level.

[0097] Based on the structure of the test module selection circuit and logic signal generation circuit described above, the first time constant t1, the second time constant t2, and the third time constant t3 of the first capacitor, the second capacitor, and the third capacitor are expressed by the following formulas:

[0098]

[0099]

[0100]

[0101] In the formula, R1, R2 and R3 represent the resistance values ​​of the first resistor, the second resistor and the third resistor, respectively, and C1, C2 and C3 represent the capacitance values ​​of the first capacitor, the second capacitor and the third capacitor, respectively.

[0102] The following describes a chip tuning and testing circuit that includes two test modules. The first trigger circuit includes two cascaded D flip-flops (first D flip-flop D1 and second D flip-flop D2) and a latch-up flip-flop (third D flip-flop D3). The first waveform signal is as follows: Figure 5 The working principle of the chip adjustment and testing circuit is explained using the example shown below:

[0103] The first waveform signal includes three square wave signals, and the high-level time of the first and third square wave signals is T1 ( The high-level time of the second square wave signal is less than the first time constant t1. When the first waveform signal is input as the input signal IN into the chip adjustment and testing circuit, when the first waveform signal is high, signals INB1 and INB2 are both low. At this time, the first switch M1 and the fourth switch M4 are turned on, the second switch M2 and the fifth switch M5 are turned off, and the first capacitor C1 and the second capacitor C2 are both in a charging state. After time T1, the first waveform signal switches to a low level, and signals INB1 and INB2 switch to a high level. The first switch M1 and the fourth switch M4 are turned off, the second switch M2 and the fifth switch M5 are turned on, and the first capacitor C1 and the second capacitor C2 are both in a discharging state.

[0104] Due to the first time constant Therefore, when the first square wave signal is input, after time t1, the voltage across the first capacitor C1 switches to a high level. Then, when the first waveform signal switches to a low level, the voltage across the first capacitor C1 switches back to a low level after a brief discharge. Simultaneously, due to the second time constant... Therefore, the voltage across the second capacitor C2 remains low (insufficiently charged); while after the second square wave signal is input, the voltages across both the first capacitor C1 and the second capacitor C2 remain low; after the third square wave signal is input, the voltage across the second capacitor C2 remains low, while the voltage across the first capacitor C1 switches to a high level, and then briefly discharges before switching back to a low level when the first waveform signal enters a low level. Thus, the voltage waveforms of the first voltage signal V1 and the second voltage signal V2 can be obtained, as follows: Figure 6 As shown.

[0105] Specifically, based on the first waveform signal IN and the first voltage signal V1, the working process of each D flip-flop in the first trigger circuit can be analyzed. When both the input signal and the first voltage are low, although the signal at the clock terminal of the first D flip-flop is high, the output is low because the input is low. When the input signal is high, the clock terminal is low, and it does not trigger. When the input signal reaches the falling edge of the first square wave signal, the clock terminal is high, the input terminal is high, and the first D flip-flop outputs a high level. Due to the delay in this output, the input of the second D flip-flop is the state of the first D flip-flop from the previous moment, i.e., it outputs a low level, and the third D flip-flop also outputs a low level. At the falling edge of the second square wave signal, the input of the first D flip-flop is low, so the output is low. The input of the second D flip-flop is the state of the first D flip-flop from the previous moment, so the second D flip-flop outputs a high level, and the third D flip-flop outputs a low level. At the falling edge of the third square wave signal, the input of the first D flip-flop is high, so the output is high, the second D flip-flop outputs a low level, and the third D flip-flop outputs a high level. Therefore, the output voltage waveforms of the three D flip-flops in the first trigger circuit are as follows: Figure 7 As shown.

[0106] It can be seen that when the third square wave signal switches from high level to low level, the outputs of the first D flip-flop, the second D flip-flop, and the third D flip-flop are high level, low level, and high level, respectively. At this time, the third D flip-flop outputs a high level to the third switch M3, and the third switch M3 is turned on, thereby pulling down the signal INB1. This keeps the CK signal terminal (clock terminal) of the first D flip-flop, the second D flip-flop, and the third D flip-flop at a low level. Therefore, when the third square wave signal switches from high level to low level, the outputs of the first D flip-flop, the second D flip-flop, and the third D flip-flop remain at a high level, a low level, and a high level, respectively.

[0107] At this time, combined Figure 4 As can be seen from the circuit structure, the high-level signal output by the first D flip-flop and the low-level signal output by the second D flip-flop are input into the signal conversion circuit. The signal conversion circuit selects the corresponding test module based on the combination of high and low levels of the first and second D flip-flops.

[0108] Based on the above analysis of the waveform signals, it can be seen that in order to ensure that the third switch M3 turns on and pulls down the signal INB1 after all the square wave signals in the first waveform signal are input into the adjustment and testing circuit, the high-level time of the first square wave signal in the first waveform signal must be set to be greater than the first time constant t1, preferably time T1. In this way, the first square wave signal causes the first voltage generating circuit to output a high-level signal, which triggers the first D flip-flop to output a high-level signal. The high-level signal output by the first D flip-flop is transmitted to the third D flip-flop through two square wave signals, causing the third D flip-flop to output a high-level signal. This high-level signal must be maintained at all times, thereby locking the third switch M3 in the on state.

[0109] Therefore, when the number of D flip-flops in the first trigger circuit changes, the number of square wave signals in the first waveform signal must also be adjusted accordingly. Furthermore, the number of square wave signals in the first waveform signal must be the same as the number of D flip-flops in the first trigger circuit. The number of D flip-flops in the first trigger circuit needs to be adjusted according to the number of test modules. Since each combination of high and low levels can only cause the selection signal conversion circuit to output one high-level signal, and the rest are low-level signals, then a combination of two high and low levels can achieve the output of four (2...) 2 That is, a two-signal input selection signal conversion circuit, each signal has two possible states) test module selection, the combination of three high and low levels can achieve eight (2 3 This refers to the selection of test modules for three signal input selection signal conversion circuits, with each signal having two possible outcomes. Based on this, we can first determine the number of test modules, then determine the number of cascaded D flip-flops (connected to the selection signal conversion circuit) in the first trigger circuit, and finally determine the number of square wave signals in the first waveform signal.

[0110] Furthermore, as can be seen from the waveforms above, the output voltage of the D flip-flop in the first trigger circuit changes as the high-level duration of each square wave signal changes. Therefore, by adjusting the high-level duration of the square wave signal starting from the second square wave signal in the first waveform signal, the output of the cascaded D flip-flops can be adjusted, thereby enabling the selection of the required test module.

[0111] Specifically, when it is necessary to adjust the output of the last D flip-flop in the cascaded D flip-flops to a high level, the time for the second square wave signal to be at a high level can be designed to be greater than the first time constant t1, preferably time T1. Conversely, the time for the second square wave signal to be at a high level can be designed to be less than the first time constant t1. When it is necessary to adjust the output of the first D flip-flop in the cascaded D flip-flops to a high level, the time for the last square wave signal to be at a high level can be designed to be greater than the first time constant t1, preferably time T1. Conversely, the time for the last square wave signal to be at a high level can be designed to be less than the first time constant t1. In this way, different combinations of high and low levels can be achieved for the outputs of the first to the last D flip-flops in the cascaded D flip-flops.

[0112] The above analysis shows that the selection of the corresponding test module was achieved by designing the first waveform signal in the input signal. Meanwhile, because the high-level duration of the square wave signal in the first waveform signal is less than the second time constant, the output of the second voltage generation circuit remains at a low level. That is, the D flip-flop in the second trigger circuit is never triggered. Therefore, to trigger the D flip-flop in the second trigger circuit, the input signal also includes a second waveform signal.

[0113] The following describes a chip tuning test circuit comprising two test modules. Each test module includes two fuse-burning circuits. The first trigger circuit includes two cascaded D flip-flops (first D flip-flop D1 and second D flip-flop D2) and a latch-up flip-flop (third D flip-flop D3). The second trigger circuit includes two D flip-flops (fourth D flip-flop D4 and fifth D flip-flop D5). The waveform of the input signal is as follows: Figure 8 The working principle of the chip adjustment and testing circuit is explained using the example shown below:

[0114] As analyzed above, after the three square wave signals in the first waveform signal are input into the chip adjustment and testing circuit, the third D flip-flop outputs a high-level signal, and the third switch M3 is turned on. This keeps the signal INB1 at a low level. Therefore, regardless of the input signal, the clock input of the D flip-flop in the first trigger circuit will always be low, preventing it from being triggered. The outputs of the first, second, and third D flip-flops will always remain high, low, and high, respectively. Simultaneously, after the first waveform signal is input into the chip adjustment and testing circuit, the second voltage signal V2 remains at a low level.

[0115] when Figure 8After the fourth square wave signal is input into the adjustment and testing circuit, signal INB2 is at a low level. At this time, the fourth switch M4 and the sixth switch M6 are turned on, the fifth switch M5 and the seventh switch M7 are turned off, and the second capacitor C2 and the third capacitor C3 are both in a charging state. After time T2, the second waveform signal switches to a low level, signal INB2 switches to a high level, the fourth switch M4 and the sixth switch M6 are turned off, the fifth switch M5 and the seventh switch M7 are turned on, and the second capacitor C2 and the third capacitor C3 are both in a discharging state. During this process, because... Therefore, when the second waveform signal is high, after time t3, the terminal voltage of the third capacitor C3 switches to high, and after time t2, the terminal voltage of the second capacitor C2 switches to high. Then, when the second waveform signal switches to low, the terminal voltages of the second capacitor C2 and the third capacitor C3 switch back to low after a brief discharge.

[0116] When the fifth square wave signal is input into the adjustment and testing circuit, since the time during which the square wave signal remains at a high level is less than the third time constant t3, the terminal voltages of the second capacitor C2 and the third capacitor C3 are always at a low level.

[0117] When the sixth square wave signal is input into the adjustment and testing circuit, since the time during which the square wave signal remains at a high level is greater than the third time constant t3 and less than the second time constant t2, the voltage at the end of the second capacitor C2 remains at a low level. After time t3, the voltage at the end of the third capacitor C3 is charged to a high level. Then, when the second waveform signal switches to a low level, the voltage at the end of the third capacitor C3 switches back to a low level after a brief discharge.

[0118] From the above analysis, the voltage waveforms of the second voltage signal V2 and the third voltage signal V3 can be obtained, as follows: Figure 9 As shown, it should be noted that after the first three square wave signals are input into the adjustment and testing circuit, the second voltage signal V2 remains at a low level. Therefore, regardless of how the waveforms of the third voltage signal V3 and signal INB2 change, the logic signal generation circuit outputs a low-level signal. Figure 9 The voltage waveform of the third voltage signal V3 is not shown when the first three square wave signals are emitted. Regardless of the relationship between the third time constant t3 and the first time constant t1, the third voltage signal V3 is always at a low level after the third square wave signal is emitted.

[0119] Depend on Figure 4From the circuit structure, we know that the second voltage signal V2 is input to the input terminal of the fourth D flip-flop, and the third voltage signal V3, after passing through the seventh inverter A7, is input to the CK terminals of the fourth D flip-flop D4 and the fifth D flip-flop D5. Therefore, based on the second voltage signal V2 and the third voltage signal V3, the operation of the D flip-flops in the second trigger circuit can be analyzed. Thus, at this time, the output voltage waveforms of the fourth and fifth D flip-flops can be obtained from the voltage waveforms of the second voltage signal V2 and the third voltage signal V3, as shown below. Figure 10 As shown.

[0120] Depend on Figure 10 It can be seen that after the sixth square wave signal briefly switches from high to low, the outputs of the fourth D flip-flop D4 and the fifth D flip-flop D5 are low and high, respectively. Afterward, the CK terminals of the fourth D flip-flop D4 and the fifth D flip-flop D5 remain at a high level. Therefore, the outputs of the fourth D flip-flop D4 and the fifth D flip-flop D5 remain at low and high levels, respectively. At this time, combined with... Figure 4 As can be seen from the circuit structure, the "fuse burnout" signals output by the fourth D flip-flop D4 and the fifth D flip-flop D5 are input into the test module, and the test module processes each adjustment fuse according to each "fuse burnout" signal.

[0121] Based on the above analysis of the second waveform signal, it can be seen that each square wave signal with a high level duration greater than the third time constant can realize the signal transmission of a D flip-flop in the second trigger circuit. When the second trigger circuit includes N cascaded flip-flops (the same number as the number of fuse circuits in each test module), the second waveform signal includes N square wave signals with a high level duration greater than the third time constant (i.e., the second preset number is N).

[0122] Furthermore, when an adjustment signal is required to be input to the corresponding fuse circuit in the test module, the corresponding connected D flip-flops are controlled to output a high-level signal as the adjustment signal. Thus, the output of the D flip-flops can be adjusted according to the fuse circuit to be operated. The output of the D flip-flops can be adjusted by the duration of a second preset number of square wave signals at a high level. Firstly, to ensure that all D flip-flops in the second trigger circuit have a high-level input at their CK terminals, thus triggering each D flip-flop in the second trigger circuit, the duration of the fourth square wave signal in the input signal at a high level must be greater than the third time constant.

[0123] Secondly, when it is necessary to adjust the output of the first D flip-flop to a high level, the time when the fourth square wave signal is at a high level can be designed to be greater than the second time constant t2, preferably time T2. Conversely, the time when the fourth square wave signal is at a high level can be designed to be greater than the third time constant t3 and less than the second time constant t2. When it is necessary to adjust the output of the first D flip-flop to a high level, the time when the last square wave signal with a high level time greater than the third time constant t3 is at a high level can be designed to be greater than the second time constant t2, preferably time T2. Conversely, the time when the last square wave signal with a high level time greater than the third time constant t3 is at a high level can be designed to be less than the second time constant t2. In this way, the outputs of each D flip-flop in the logic signal generation circuit can be adjusted to obtain various high and low level combinations of adjustment signals.

[0124] It should be noted that, Figure 8 The high-level duration of the square wave signal in the second waveform is just an example. When it is necessary to change the output of the D flip-flop, it can be adjusted accordingly.

[0125] In one alternative implementation, such as Figure 11 As shown, the chip adjustment and testing circuit further includes: a time signal adjustment circuit 40, whose first terminal receives the input signal IN, its second terminal is connected to the fourth terminal of the second voltage generation circuit 21, its third terminal is grounded, its fourth terminal is connected to the external power supply VDD, and its fifth terminal is connected to the fifth terminal of the second voltage generation circuit 21. The time signal adjustment circuit 40 is used to generate a time signal that is continuously high-level for adjustment based on the input signal and the second voltage signal. The time signal is matched with the chip power level. Figure 4 As shown, each test module also includes an AND gate connected to each fuse-burning circuit. When the AND gate receives the high-level selection signal, the adjustment signal, and the time signal, it outputs an internal signal to the corresponding fuse-burning circuit so that the fuse-burning circuit processes the adjustment fuse.

[0126] Specifically, based on the working principles of the selection circuit and logic signal generation circuit in the aforementioned test module, the fuse-burning circuit in the test module can operate according to the selection signal and the adjustment signal. However, because the high-level duration of the adjustment signal cannot be controlled, it cannot be matched with the chip's power level. Therefore, a time signal adjustment circuit is further set up in the chip adjustment test circuit. This circuit can output a time signal to adjust the high-level duration of the adjustment signal. That is, by adjusting this time signal, the high-level duration of the adjustment signal can be matched with the chip's power level. In addition, in order to enable the fuse-burning circuit to operate according to the received selection signal, adjustment signal, and time signal, an AND gate connected to each fuse-burning circuit is set in the test module. That is, the fuse-burning circuit connected to the corresponding AND gate is only controlled to operate when all three signals received by the AND gate are high.

[0127] In one alternative implementation, such as Figure 4 As shown, the time signal adjustment circuit includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, an eighth inverter A8, a ninth inverter A9, a tenth inverter A10, an eleventh inverter A11, a first NOR gate F1, and a second NOR gate F2.

[0128] The positive control terminal of the first switch S1, the negative control terminal of the second switch S2, the negative control terminal of the third switch S3, and the positive control terminal of the fourth switch S4 receive the input signal. The negative control terminals of the first switch S1 and the fourth switch S4 are grounded. The positive control terminals of the second switch S2 and the third switch S3 are connected to an external power supply. The first terminal of the first switch S1 is connected to the fifth terminal of the second voltage generating circuit. The second terminal of the first switch S1 is connected to the input terminal of the eighth inverter A8 and the first terminal of the third switch S3.

[0129] The second terminal of the third switch S3 is connected to the output terminal of the second NOR gate F2. The output terminal of the eighth inverter A8 is connected to the first terminal of the second switch S2 and the first input terminal of the second NOR gate F2. The second terminal of the second switch S2 is connected to the first input terminal of the first NOR gate F1, the input terminal of the ninth inverter A9, and the first terminal of the fourth switch S4. The second terminal of the fourth switch S4 is connected to the output terminal of the eleventh inverter A11. The input terminal of the eleventh inverter A11 is connected to the output terminal of the first NOR gate F1. The input terminal of the tenth inverter A10 is connected to the fourth terminal of the second voltage generating circuit. The output terminal of the tenth inverter A10 is connected to the second input terminal of the first NOR gate F1 and the second input terminal of the second NOR gate F2. The output terminal of the ninth inverter A9 is connected to each AND gate in each test module.

[0130] Combination Figure 4 It can be seen that when the input signal IN is low, the first switch S1 and the fourth switch S4 are off, and the second switch S2 and the third switch S3 are on. When the input signal IN is high, the first switch S1 and the fourth switch S4 are on, and the second switch S2 and the third switch S3 are off. And when... Figure 8 The first and second waveform signals shown are input as input signals IN into the tuning and testing circuit, and then combined with... Figure 10 The waveforms of each signal in the input time signal conditioning circuit can be obtained, such as... Figure 12 As shown.

[0131] When the input signal IN is at the high level of the first square wave signal, the signal INB2 is at the low level. At this time, the first switch S1 and the fourth switch S4 are turned on, and the second switch S2 and the third switch S3 are turned off. Since the second voltage signal V2 is at the low level, the eighth inverter A8 outputs a high level. At the same time, since the signal INB2 is at the low level, the tenth inverter A10 outputs a high level, the first NOR gate F1 outputs a low level, the eleventh inverter A11 outputs a high level, and at this time, the ninth inverter A9 outputs a low level.

[0132] When the input signal IN is at a low level after the first square wave signal, the signal INB2 is at a high level. At this time, the first switch S1 and the fourth switch S4 are off, and the second switch S2 and the third switch S3 are on. As analyzed above, the eighth inverter A8 outputs a high level at this time. This high-level signal is input into the second NOR gate F2, and the second NOR gate F2 outputs a low level, thus continuing to pull the input terminal of the eighth inverter A8 low, so that the eighth inverter A8 continues to output a high level. The output terminal of the eighth inverter A8 is connected to the ninth inverter A9 through the on second switch S2. At this time, the ninth inverter A9 still outputs a low level. Similarly, when the input signal IN is at the second and third square wave signals, the ninth inverter A9 always outputs a low level.

[0133] Subsequently, when the input signal IN is at the high level of the fourth square wave signal, the signal INB2 is at a low level. At this time, the first switch S1 and the fourth switch S4 are turned on, and the second switch S2 and the third switch S3 are turned off. Since the second voltage signal V2 is first at a low level and then at a high level, the eighth inverter A8 first outputs a high level and then outputs a low level. At the same time, since the signal INB2 is at a low level, the tenth inverter A10 outputs a high level, the first NOR gate F1 outputs a low level, the eleventh inverter A11 outputs a high level, and at this time, the ninth inverter A9 outputs a low level.

[0134] When the input signal IN is at a low level after the fourth square wave signal, the signal INB2 is at a high level. At this time, the first switch S1 and the fourth switch S4 are turned off, and the second switch S2 and the third switch S3 are turned on. As analyzed above, the eighth inverter A8 outputs a low level at this time. This low-level signal is input into the second NOR gate F2. At the same time, since the signal INB2 is at a high level, the tenth inverter A10 outputs a low level. This low level is also input into the second NOR gate F2. Therefore, the second NOR gate F2 outputs a high level, thereby pulling the input terminal of the eighth inverter A8 high, so that the eighth inverter A8 continues to output a low level. The output terminal of the eighth inverter A8 is connected to the ninth inverter A9 through the turned-on second switch S2. At this time, the ninth inverter A9 outputs a high level.

[0135] When the input signal IN is at the high level of the fifth square wave signal, the signal INB2 is at the low level. At this time, the first switch S1 and the fourth switch S4 are turned on, and the second switch S2 and the third switch S3 are turned off. Since the second voltage signal V2 is at the low level, the eighth inverter A8 outputs a high level. At the same time, since the signal INB2 is at the low level, the tenth inverter A10 outputs a high level, the first NOR gate F1 outputs a low level, and the eleventh inverter A11 outputs a high level. At this time, the output of the ninth inverter A9 switches to a low level again.

[0136] As analyzed above, the output of the ninth inverter A9 remains low thereafter; at this point, the waveform of the time signal VT output by the ninth inverter A9 can be obtained, as shown below. Figure 13 As shown.

[0137] Combination Figure 13 It can be seen that the time when the time signal VT is at a high level is equal to the time T0 between the falling edge of the square wave signal that holds the high level for a time greater than the second time constant t2 and the rising edge of the square wave signal that holds the high level for a time less than the third time constant t3. Therefore, the time when the time signal VT is at a high level can be adjusted by adjusting the time T0. Figure 14 The waveform comparison of the time signal VT after adjusting the time T0 is shown;

[0138] Combination Figure 14 As can be seen from the above analysis, a square wave signal that maintains a high level for a time less than the third time constant t3 can adjust the time that the time signal VT is at a high level. Therefore, each square wave signal that maintains a high level for a time greater than the second time constant t2 must be followed by a square wave signal that maintains a high level for a time less than the third time constant t3, thereby controlling the time signal VT.

[0139] Meanwhile, in the second waveform signal, the square wave signal that remains high for a time less than the third time constant t3 is not used to adjust the logic signal generation circuit. Furthermore, the square wave signal that remains high for a time less than the third time constant t3 must appear immediately after the square wave signal that remains high for a time greater than the second time constant t2. Therefore, in the second waveform signal, the fourth square wave signal must be high for a time greater than the third time constant t3. At this point, the fourth square wave signal can be set to either a square wave signal that remains high for a time greater than the second time constant t2 or a square wave signal that remains high for a time greater than the third time constant t3 but less than the second time constant t2, according to the actual requirements of the chip.

[0140] Based on the above analysis, it can be concluded that Figure 8 The square wave signal with a high-level duration less than t3 is set in order to adjust the time signal. Therefore, if no time signal adjustment circuit is set, the square wave signal with a high-level duration less than t3 can be omitted in the second waveform signal of the input signal.

[0141] Therefore, a first type of square wave signal can be defined as a square wave signal with a high-level duration less than the third time constant, and a second type of square wave signal can be defined as a square wave signal with a high-level duration greater than the second time constant. The first type of square wave signal includes a third preset number, and the second type of square wave signal includes a fourth preset number. The third preset number and the fourth preset number are equal. Each second type of square wave signal is sequentially connected to one first type of square wave signal. The high-level duration of the time signal output by the time signal adjustment circuit is determined by the time between the falling edge of the second type of square wave signal and the rising edge of the first type of square wave signal sequentially connected to it.

[0142] like Figure 15 As shown, based on the working principles of the test module selection circuit, logic signal generation circuit, and time signal adjustment circuit described above, the working principle of this chip trimming test circuit is as follows: According to the chip power level, an input signal IN is input to the chip trimming test circuit. At this time, the input signal IN is input to the test module selection circuit, logic signal generation circuit, and time signal adjustment circuit. The test module selection circuit outputs a selection signal to the corresponding test module. The logic signal generation circuit generates the trimming signal required by the corresponding test module. The time signal adjustment circuit generates a time signal that remains high based on the input signal IN. At this time, the AND gate in the corresponding test module outputs an internal signal that matches the chip power level based on the selection signal, trimming signal, and time signal. The fuse-burning circuit in the test module performs a "fuse-burning" process on the trimming fuse based on the internal signal output by the corresponding AND gate.

[0143] Specifically, the adjustment test circuit can input corresponding input signals, including a first waveform signal and a second waveform signal, according to the chip's power level. The test module selection circuit adjusts the selection signal of the test module to be adjusted to a high level according to the input signal. At the same time, the logic signal generation circuit adjusts the output of the second trigger circuit according to the input signal to obtain the high-level adjustment signals of each test module to be adjusted. Furthermore, the time signal adjustment circuit adjusts the time when the time signal VT is at a high level according to the time T0 between the falling edge of the second type square wave signal and the rising edge of the first type square wave signal to obtain a time signal that matches the chip's power level.

[0144] Subsequently, the high-level selection signal, adjustment signal, and time signal are input into the AND gates of the corresponding test modules to obtain internal signals VO1, VO2, etc., that match the chip power level. The fuse-burning circuit in the test module performs "fuse-burning" processing on the adjustment fuse based on the internal signals that match the chip power level output by the corresponding AND gates, while taking into account the power consumption and adjustment test time of the chip adjustment test circuit. At the same time, the chip adjustment test circuit in this application can process the adjustment fuse by connecting an input signal through one input terminal, thereby reducing the operational difficulty of the chip adjustment test circuit and simplifying the operation process of the chip adjustment test circuit.

[0145] The chip tuning and testing circuit with adjustable internal signals provided by this invention allows for the acquisition of an internal signal matching the chip's power level by connecting a suitable input signal through an input terminal. This internal signal, matching the chip's power level, is then used to process the tuning fuse, enabling the selection of test modules and circuit tuning. This significantly improves the adaptability of the chip tuning and testing circuit, balances energy consumption and tuning / testing time, reduces operational difficulty, and simplifies the operational process.

[0146] While exemplary embodiments and their advantages have been described in detail, those skilled in the art can make various changes, substitutions, and modifications to these embodiments without departing from the spirit of the invention and the scope of protection defined by the appended claims. Such modifications and variations all fall within the scope defined by the appended claims. For other examples, those skilled in the art should readily understand that the order of process steps can be changed while remaining within the scope of the invention.

[0147] Furthermore, the scope of this invention is not limited to the processes, mechanisms, manufacturing methods, material compositions, means, methods, and steps of the specific embodiments described in the specification. From the disclosure of this invention, those skilled in the art will readily understand that any existing or future processes, mechanisms, manufacturing methods, material compositions, means, methods, or steps that perform substantially the same function or obtain substantially the same results as the corresponding embodiments described in this invention can be applied according to this invention. Therefore, the appended claims are intended to include these processes, mechanisms, manufacturing methods, material compositions, means, methods, or steps within their scope of protection.

Claims

1. A chip tuning and testing circuit with adjustable internal signals, characterized in that, include: The test module selection circuit has a first terminal that receives an input signal, a second terminal that is connected to an external power supply, a third terminal that is grounded, and multiple fourth terminals that are connected to multiple test modules. It is used to output a high-level selection signal to the corresponding test module among the multiple test modules according to the input signal. A logic signal generating circuit has a first terminal that receives the input signal, a second terminal that is connected to an external power supply, a third terminal that is grounded, and multiple fourth terminals that are connected to multiple test modules. It is used to output adjustment signals to the corresponding test modules among the multiple test modules according to the input signal. Multiple test modules are used to generate internal signals to process the adjustment fuse when the corresponding test module receives the high-level selection signal and the adjustment signal. Each test module includes multiple fuse circuits, and the logic signal generation circuit includes a second voltage generation circuit, which is used to generate a second voltage signal. A time signal adjustment circuit has a first terminal receiving an input signal, a second terminal connected to the fourth terminal of the second voltage generation circuit, a third terminal grounded, a fourth terminal connected to an external power supply, and a fifth terminal connected to the fifth terminal of the second voltage generation circuit. The time signal adjustment circuit is used to generate a time signal that is continuously high-level based on the input signal and the second voltage signal. The time signal is matched with the chip power level. Each test module also includes an AND gate connected to each fuse-burning circuit. When the AND gate receives the high-level selection signal, the adjustment signal, and the time signal, it outputs an internal signal to the corresponding fuse-burning circuit so that the fuse-burning circuit can process the adjustment fuse.

2. The chip tuning and testing circuit with adjustable internal signals according to claim 1, characterized in that, The input signal includes a first waveform signal and a second waveform signal connected in sequence, wherein the first waveform signal and the second waveform signal include a plurality of square wave signals with varying high-level durations.

3. The chip tuning and testing circuit with adjustable internal signals according to claim 2, characterized in that, The test module selection circuit includes: a first voltage generation circuit, a first trigger circuit, and a selection signal conversion circuit; The first voltage generating circuit has a first terminal receiving an input signal, a second terminal grounded, a third terminal connected to an external power supply, a fourth terminal connected to the first terminal of the first trigger circuit, and a fifth terminal connected to the second terminal of the first trigger circuit. The first voltage generating circuit is used to charge and discharge its internal first capacitor according to the input signal to generate a first voltage signal including multiple square wave signals. The first time constant of the first capacitor is different from the high-level duration of the square wave signal in the input signal. The first trigger circuit has its third terminal grounded and its multiple fourth terminals respectively connected to multiple input terminals of the selection signal conversion circuit. The first trigger circuit is used to generate a first trigger signal including a combination of high and low levels based on the input signal and the first voltage signal. The selection signal conversion circuit has multiple output terminals connected to multiple test modules respectively. The selection signal conversion circuit is used to output selection signals to the corresponding test modules among the multiple test modules according to the first trigger signal.

4. The chip tuning and testing circuit with adjustable internal signals according to claim 3, characterized in that, The first voltage generating circuit includes a first switching transistor, a second switching transistor, a first inverter, a first capacitor, and a first resistor; the first triggering circuit includes a third switching transistor, multiple cascaded D flip-flops, and a latched D flip-flop. The input terminal of the first inverter receives the input signal, the output terminal of the first inverter is connected to the first terminal of the first switch and the first terminal of the second switch, the second terminal of the first switch is connected to an external power supply, the third terminal of the first switch is connected to one end of a first resistor, the other end of the first resistor is connected to the second terminal of the second switch, one end of the first capacitor and the input terminal of the first D flip-flop in a plurality of cascaded D flip-flops, and the third terminal of the second switch is connected to the other end of the first capacitor and grounded. In a series of cascaded D flip-flops, the input of each subsequent D flip-flop is connected to the non-inverting output of the preceding D flip-flop. The non-inverting output of each cascaded D flip-flop is connected to a selection signal conversion circuit. The clock terminals of the cascaded D flip-flops are connected to the clock terminal of the latched D flip-flop, the output of the first inverter, and the first terminal of the third switch. The input of the latched D flip-flop is connected to the non-inverting output of the last cascaded D flip-flop. The non-inverting output of the latched D flip-flop is connected to the second terminal of the third switch, and the third terminal of the third switch is grounded.

5. The chip tuning and testing circuit with adjustable internal signals according to claim 2, characterized in that, The logic signal generation circuit also includes a third voltage generation circuit and a second trigger circuit. The second voltage generating circuit has a first terminal that receives an input signal, a second terminal that is connected to an external power supply, a third terminal that is grounded, a fourth terminal that is connected to the first terminal of the third voltage generating circuit, and a fifth terminal that is connected to the first terminal of the second trigger circuit. The second voltage generating circuit is used to charge and discharge its internal second capacitor according to the input signal to generate a second voltage signal including multiple square wave signals. The third voltage generating circuit has its second terminal connected to an external power supply, its third terminal grounded, and its fourth terminal connected to the second terminal of the second trigger circuit. The third voltage generating circuit is used to charge and discharge its internal third capacitor according to the input signal to generate a third voltage signal including multiple square wave signals. The second time constant of the second capacitor, the third time constant of the third capacitor, and the high-level duration of the square wave signal in the input signal are all different. The second trigger circuit has multiple third terminals connected to the corresponding fuse circuit in each test module. The second trigger circuit is used to output multiple adjustment signals according to the second voltage signal and the third voltage signal. Each adjustment signal is input to the corresponding fuse circuit in each test module.

6. The chip tuning and testing circuit with adjustable internal signals according to claim 5, characterized in that, The second voltage generating circuit includes a fourth switch, a fifth switch, a fourth inverter, a second resistor, and a second capacitor; the third voltage generating circuit includes a sixth switch, a seventh switch, a third resistor, and a third capacitor; and the second trigger circuit includes a seventh inverter and multiple cascaded D flip-flops. The input terminal of the fourth inverter receives the input signal, and the output terminal of the fourth inverter is connected to the first terminal of the fourth switch, the first terminal of the fifth switch, the first terminal of the sixth switch, and the first terminal of the seventh switch. The second terminal of the fourth switch is connected to an external power supply, and the third terminal of the fourth switch is connected to one end of the second resistor. The other end of the second resistor is connected to the second terminal of the fifth switch, one end of the second capacitor, and the input terminal of the first D flip-flop in a plurality of cascaded D flip-flops. The third terminal of the fifth switch is connected to the other end of the second capacitor and grounded. The second terminal of the sixth switch is connected to an external power supply, the third terminal of the sixth switch is connected to one end of the third resistor, the other end of the third resistor is connected to the second terminal of the seventh switch, the first terminal of the third capacitor and the input terminal of the seventh inverter, and the third terminal of the seventh switch is connected to the other end of the third capacitor and grounded. The output of the seventh inverter is connected to the clock terminal of each of the multiple cascaded D flip-flops. The input of the next D flip-flop in the multiple cascaded D flip-flops is connected to the non-inverting output of the previous D flip-flop. The non-inverting output of each D flip-flop in the multiple cascaded D flip-flops is connected to the corresponding fuse-burning circuit in each test module.

7. The chip tuning and testing circuit with adjustable internal signals according to claim 6, characterized in that, The time signal conditioning circuit includes a first switch, a second switch, a third switch, a fourth switch, an eighth inverter, a ninth inverter, a tenth inverter, an eleventh inverter, a first NOR gate, and a second NOR gate. The positive control terminal of the first switch, the negative control terminal of the second switch, the negative control terminal of the third switch, and the positive control terminal of the fourth switch receive the input signal. The negative control terminals of the first switch and the fourth switch are grounded. The positive control terminals of the second switch and the third switch are connected to an external power supply. The first terminal of the first switch is connected to the fifth terminal of the second voltage generating circuit. The second terminal of the first switch is connected to the input terminal of the eighth inverter and the first terminal of the third switch. The second terminal of the third switch is connected to the output terminal of the second NOR gate. The output terminal of the eighth inverter is connected to the first terminal of the second switch and the first input terminal of the second NOR gate. The second terminal of the second switch is connected to the first input terminal of the first NOR gate, the input terminal of the ninth inverter, and the first terminal of the fourth switch. The second terminal of the fourth switch is connected to the output terminal of the eleventh inverter. The input terminal of the eleventh inverter is connected to the output terminal of the first NOR gate. The input terminal of the tenth inverter is connected to the fourth terminal of the second voltage generating circuit. The output terminal of the tenth inverter is connected to the second input terminal of the first NOR gate and the second input terminal of the second NOR gate. The output terminal of the ninth inverter is connected to each AND gate in each test module.

8. The chip tuning and testing circuit with adjustable internal signals according to claim 4, characterized in that, The first waveform signal includes a first preset number of square wave signals. The number of cascaded D flip-flops in the first trigger circuit is set according to the number of test modules. The first preset number is the same as the number of all D flip-flops in the first trigger circuit. The high-level duration of the first square wave signal in the first waveform signal is greater than the first time constant. All D flip-flops include multiple cascaded D flip-flops and locked D flip-flops.

9. The chip tuning and testing circuit with adjustable internal signals according to claim 8, characterized in that, The selection signal conversion circuit adjusts the level of the selection signal output to each test module according to the high and low level combination in the first trigger signal, and each high and low level combination can only make the selection signal of one test module high, while the others are low. The combination of high and low levels is adjusted according to the duration of the high level of the square wave signal starting from the second square wave signal in the first waveform signal. When the duration of the high level of the second square wave signal is greater than the first time constant, the output of the last D flip-flop in the cascaded D flip-flops in the first trigger circuit is adjusted to a high level; when the duration of the high level of the second square wave signal is less than the first time constant, the output of the last D flip-flop in the cascaded D flip-flops in the first trigger circuit is adjusted to a low level. When the duration of the high level of the last square wave signal in the first waveform signal is greater than the first time constant, the output of the first D flip-flop in the cascaded D flip-flops in the first trigger circuit is adjusted to a high level; when the duration of the high level of the last square wave signal in the first waveform signal is less than the first time constant, the output of the first D flip-flop in the cascaded D flip-flops in the first trigger circuit is adjusted to a low level.

10. The chip tuning and testing circuit with adjustable internal signals according to claim 7, characterized in that, The second waveform signal includes a second preset number of square wave signals, the high-level duration of the second preset number of square wave signals is greater than the third time constant, and the second preset number, the number of multiple cascaded D flip-flops in the second trigger circuit, and the number of fuse circuits in each test module are the same.

11. The chip tuning and testing circuit with adjustable internal signals according to claim 10, characterized in that, The output level of the multiple cascaded D flip-flops in the second trigger circuit is determined based on the fuse circuit to be operated. The output level of the multiple cascaded D flip-flops in the second trigger circuit is adjusted by the time when the second preset number of square wave signals are at a high level. When the time when the first square wave signal in the second waveform signal is at a high level is greater than the second time constant, the last D flip-flop in the multiple cascaded D flip-flops outputs a high level; when the time when the first square wave signal in the second waveform signal is at a high level is greater than the third time constant and less than the second time constant, the last D flip-flop in the multiple cascaded D flip-flops outputs a low level. When the last square wave signal in the second waveform signal is at a high level for a period of time greater than the second time constant, the first D flip-flop in the multiple cascaded D flip-flops outputs a high level. When the last square wave signal in the second waveform signal is at a high level for a period of time greater than the third time constant and less than the second time constant, the first D flip-flop in the multiple cascaded D flip-flops outputs a low level.

12. The chip tuning and testing circuit with adjustable internal signals according to claim 11, characterized in that, The second waveform signal further includes a third preset number of first-type square wave signals, wherein the first-type square wave signals are square wave signals with a high-level duration less than the third time constant, and the second preset number of square wave signals includes a fourth preset number of second-type square wave signals, wherein the second-type square wave signals are square wave signals with a high-level duration greater than the second time constant, and the third preset number and the fourth preset number are equal; each second-type square wave signal is sequentially connected to one first-type square wave signal; The time during which the time signal output by the time signal conditioning circuit is at a high level is determined by the time between the falling edge of the second type square wave signal and the rising edge of the first type square wave signal that is sequentially connected to it.

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