Makeup block diagram arrangement method
By automatically identifying and adjusting the placement of marking patterns within the dicing zone, the problem of low efficiency in manual layout in existing technologies is solved, and precise and efficient placement of marking patterns in semiconductor manufacturing processes is achieved.
Patent Information
- Application Number
- CN202511127819.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-12
- Publication Date
- 2025-11-14
AI Technical Summary
In existing technologies, the layout of marking patterns in semiconductor manufacturing processes relies on manual placement and visual inspection, which cannot efficiently and accurately meet the complex requirements of multi-chip panelization.
By automatically identifying the target boundary map in the initial layout, merging the boundary marker map to generate the zoning map, placing the marker map in the zoning map area, adjusting the distance between the center of the map matrix and the center of the boundary map to be less than a preset threshold, merging the layout and outputting an inspection report.
It enables precise, efficient, and automatic placement of marked graphics, improving the efficiency and reliability of layout for mosaic frames.
Smart Images
Figure CN120949518A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, specifically to a method for arranging panel block diagrams. Background Technology
[0002] In semiconductor manufacturing processes, photolithography is an important pattern transfer process. To ensure its accuracy, various marker patterns need to be introduced into the panel layout. The number of marker patterns is large, and different types and levels of marker patterns need to be placed in specific positions on the panel layout.
[0003] In existing technologies, the position of each marker graphic is generally determined by manual comparison and measurement. That is, the layout of the marker graphics relies on manual placement and visual inspection. However, with the expansion of chip integration scale and the increase in the complexity of multi-chip panelization, this manual method can no longer efficiently and accurately meet the requirements for marker graphic placement. Summary of the Invention
[0004] In view of this, this application provides a method for arranging layout diagrams, which can automatically arrange various marked graphics with precision and efficiency, and check the layout structure, thereby greatly improving the layout efficiency and reliability.
[0005] In a first aspect, embodiments of this application disclose a method for arranging a mosaic block diagram, including:
[0006] Identify the target boundary map in several boundary marker maps corresponding to the initial map;
[0007] By fusing the boundary marker diagrams other than the target boundary diagram onto the target boundary diagram, a slicing pattern on the target boundary diagram is obtained;
[0008] Place a first marker pattern within the complete slicing area of the slicing pattern;
[0009] A graphic matrix is formed by several second marker graphics. After adjusting the distance between the center of the graphic matrix and the center of the target boundary map to be less than a preset distance threshold, several second marker graphics are placed in the target boundary map, and several second marker graphics are respectively located at the intersection of the slicing lane graphics to obtain the target map.
[0010] The target layout and the initial layout are merged to form an output file, and the output file is checked and a check result report is output.
[0011] In one possible example, the step of fusing the boundary marker diagrams other than the target boundary diagram onto the target boundary diagram to obtain the slicing pattern on the target boundary diagram includes:
[0012] Take one vertex of the target boundary map as the origin of the coordinate system and establish a first coordinate system;
[0013] Extend the boundary identification diagram, excluding the target boundary diagram, along the X-axis and / or Y-axis of the first coordinate system;
[0014] The extended boundary marker diagram is merged into the target boundary diagram, and the slab pattern is obtained on the target boundary diagram.
[0015] In one possible example, after the merged and extended boundary marker diagram is applied to the target boundary diagram, and the slicing pattern is obtained on the target boundary diagram, the method further includes:
[0016] Mark the coordinates of the first vertex at the intersection of the same scribe line and the X-axis within the first coordinate system, and the coordinates of the second vertex that are diagonally mapped to the coordinates of the first vertex;
[0017] Using the coordinates of the first vertex and the coordinates of the second vertex as diagonal vertices, all scribbling tracks within the first coordinate system are generated into rectangular patterns;
[0018] Perform an AND-OR operation between the rectangular pattern and the target boundary map to obtain the complete slicing area of the slicing pattern on the target boundary map.
[0019] In one possible example, after obtaining the complete lane area of the lane pattern on the target boundary map, the first marker pattern is placed within the complete lane of the complete lane area, and the complete lane with the first marker pattern is removed from the complete lane area.
[0020] In one possible example, the complete lane area with the first marked pattern is located on both sides of the lane pattern.
[0021] In one possible example, adjusting the distance between the center of the graphic matrix and the center of the target bounding box map to be less than a preset distance threshold includes:
[0022] A second coordinate system is established using one vertex of the target boundary map as the origin.
[0023] The second marked graphic located at the starting point in the graphic matrix is designated as the starting marked graphic, and the starting coordinates of the starting marked graphic in the second coordinate system are generated;
[0024] Adjust the starting coordinates until the distance between the center of the graphic matrix and the center of the target boundary map is less than a preset distance threshold.
[0025] In one possible example, adjusting the starting coordinates until the distance between the center of the graphic matrix and the center of the target bounding box is less than a preset distance threshold includes:
[0026] Obtain the boundary dimensions of the graphic matrix, and move the starting coordinates within the second coordinate system until the boundary of the graphic matrix has the minimum absolute difference between the boundary of the target boundary map and the X-axis and Y-axis of the second coordinate system.
[0027] In one possible example, obtaining the boundary dimensions of the graphical matrix includes:
[0028] Identify the target chip among the several design chips corresponding to the target boundary block diagram. The boundary size of the target chip is smaller than that of the other design chips. In the X-axis and Y-axis directions of the second coordinate system, there is a target spacing between any second mark pattern and its adjacent second mark pattern. Set the target spacing to be greater than N times the boundary size of the target chip to obtain the boundary size of the pattern matrix, where N is an integer ≥ 1.
[0029] In one possible example, prior to merging the target layout and the initial layout to form the output file, the following is included:
[0030] Place the marker frame diagram, excluding the first and second marker graphics, into the slicing pattern.
[0031] In one possible example, before identifying the target boundary map in several boundary marker maps corresponding to the initial layout, the following is included:
[0032] Based on the block diagram design rules, the marker block diagrams, which include at least the first marker graphic and the second marker graphic, are named and collected into the layout library for use when arranging the layout block diagrams.
[0033] In summary, compared with the prior art, this application discloses a method for arranging layout diagrams, including identifying a target boundary diagram from several boundary marker diagrams corresponding to the initial layout; fusing boundary marker diagrams other than the target boundary diagram onto the target boundary diagram to obtain a slicing pattern on the target boundary diagram; placing a first marker pattern within a complete slicing pattern area in the slicing pattern; forming a pattern matrix with several second marker patterns; adjusting the distance between the center of the pattern matrix and the center of the target boundary diagram to be less than a preset distance threshold; placing several second marker patterns in the target boundary diagram, with the several second marker patterns respectively located at the intersection points of the slicing patterns within the target boundary diagram to obtain the target layout; merging the target layout and the initial layout to form an output file; checking the output file and outputting a check result report. That is, through the above settings, multiple marker patterns can be automatically arranged accurately and efficiently, and the arrangement structure can be checked, thereby significantly improving the arrangement efficiency and reliability. Attached Figure Description
[0034] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0035] Figure 1 This is a flowchart of the method for arranging the frame diagram according to an embodiment of this application;
[0036] Figure 2 This is a schematic diagram of the first structural change in the block diagram of the embodiments of this application;
[0037] Figure 3 This is a schematic diagram of a second structural change in the block diagram of an embodiment of this application;
[0038] Figure 4 This is a schematic diagram of the third structural change in the block diagram of the embodiments of this application;
[0039] Figure 5 This is a comparison diagram of the inspection result report of the embodiment of this application. Detailed Implementation
[0040] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the claims.
[0041] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.
[0042] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.
[0043] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.
[0044] In the description of this application, it should be noted that the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0045] The technical solutions shown in this application will be described in detail below through specific embodiments. It should be noted that the order of description of the following embodiments is not intended to limit the priority of the embodiments.
[0046] As described in the background section, existing panel layouts introduce various marker graphics. The position of each marker graphic is usually determined by manual comparison and measurement. There are a large number of marker graphics, and different types and levels of marker graphics need to be placed in specific positions on the panel layout. With the expansion of chip integration scale and the increase in the complexity of multi-chip panel layout, manual methods can no longer efficiently and accurately meet the needs of marker graphic placement.
[0047] Understandably, the finished product's panel layout, as a layout unit used for photolithography exposure in semiconductor manufacturing processes, not only includes several chip areas, but also other components related to production processes and measurement monitoring, such as marking patterns, dicing areas, boundary marker diagrams, and test structure areas.
[0048] The scribe line is a dividing area located between chip areas. Each chip area can be considered as being surrounded by the scribe line, and the marking pattern needs to be placed within the scribe line.
[0049] The marking patterns include alignment marks with spacing limitations, overlay marks, critical dimension marks, and other test patterns. Alignment marks can be used to monitor and measure the consistency between the actual process layout and the standard design layout. Overlay marks can be used to monitor the overlay accuracy between different film layers. Critical dimension marks can be used to monitor the line width of the patterns within the layout. Other test patterns can also measure the thickness of the patterns within the layout.
[0050] To address the aforementioned problems, this application provides a method for arranging panel diagrams, referencing... Figure 2 Initial version Figure 1 The data to be processed includes several chip regions 1a of different sizes, and each chip region 1a can have a different layout type, such as a flat layout, a cell layout, or a cell array layout, and different types of layouts may be nested within each other. Therefore, this application identifies the initial version. Figure 1 According to the requirements of the block diagram design rules, place the marking graphic 2 in the upper marking lane 1b.
[0051] like Figure 1 As shown, in the specific implementation process, the layout methods of the panel diagram include:
[0052] S101, Identify the target boundary map in several boundary marker maps corresponding to the initial layout;
[0053] S102, merge the boundary marker diagrams other than the target boundary diagram onto the target boundary diagram to obtain the slicing pattern on the target boundary diagram;
[0054] S103, Place the first marker graphic within the complete zoning area in the zoning pattern;
[0055] S104, a graphic matrix is formed by several second marker graphics. After adjusting the distance between the center of the graphic matrix and the center of the target boundary map to be less than a preset distance threshold, several second marker graphics are placed in the target boundary map, and several second marker graphics are respectively located at the intersection of the slicing paths of the slicing path graphics to obtain the target map.
[0056] S105, merge the target layout and the initial layout to form an output file, and check the output file and output a report of the check results.
[0057] Therefore, it can automatically arrange various marked graphics with precision and efficiency, and check the arrangement structure, thereby greatly improving the efficiency and reliability of the layout of the puzzle frame.
[0058] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0059] Please refer to Figure 3 During the execution of S101, the initial version is identified. Figure 1 The corresponding boundary marker boxes above Figure 3 target bounding box Figure 3 a.
[0060] By identifying the initial version Figure 1 The corresponding boundary marker boxes above Figure 3 target bounding box Figure 3 a, to determine the initial version Figure 1 The complete outline area and defined boundaries facilitate the placement of subsequent marker graphics.
[0061] Among them, the target bounding box Figure 3 The boundary size of 'a' is larger than the initial version. Figure 1 Other corresponding boundary marker boxes Figure 3 .
[0062] In one possible implementation of this application, in identifying the initial version Figure 1 The corresponding boundary marker boxes above Figure 3 target bounding box Figure 3 Before a, it includes: a marker frame that includes at least the first marker graphic 21 and the second marker graphic 22. Figure 2 Based on the block diagram design rules, the marker box Figure 2 After naming, mark the box. Figure 2 Collect them into the layout library for use when arranging layout diagrams.
[0063] Among them, the marker box Figure 2This includes, but is not limited to, alignment mark graphics with different purposes and placement constraints, overlay accuracy graphics, critical dimension graphics, and other test graphics. To achieve automatic layout operations for subsequent panel layouts, the mark frames are designed based on the panel layout rules. Figure 2 Naming is performed, for example, including type information, hierarchy information, version information, size information, spacing information, and code information in the name, and then the named tag box is... Figure 2 Collect them into the layout library for automatic retrieval when arranging the layout diagram.
[0064] In one example, the initial version is retrieved from the layout library. Figure 1 The corresponding boundary marker boxes above Figure 3 And filter the boundary marker boxes. Figure 3 The largest boundary dimension is the target bounding box. Figure 3 a, i.e., target bounding box Figure 3 'a' indicates the initial version. Figure 1 The complete block diagram area and defined boundaries can be considered as covering all chip areas 1a and dicing tracks 1b.
[0065] In one example, identifying the initial version Figure 1 All cell layouts and cell array layouts, which may actually exist in the physical layout as nested, referenced, or repeated layouts, are then used to determine the target bounding box. Figure 3 To improve the accuracy of identification, the cell layout and cell array layout are broken down and expanded to the lowest graphic level, while the boundary marker boxes are... Figure 3 After raising it to the top-level processing priority, select the boundary marker box. Figure 3 The largest of the boundary dimensions is the target bounding box. Figure 3 a.
[0066] Continue to refer to Figure 3 During the execution of S102, in the target bounding box Figure 3 merging above the target bounding box Figure 3 The boundary marker outside of a Figure 3 Obtain the target bounding box Figure 3 The lane markings on a are shown in Figure 4.
[0067] Through the target bounding box Figure 3 The above-ground pattern 4 is obtained so that the corresponding marker box can be placed. Figure 2 The quasi-marking pattern, overlay accuracy pattern, key dimension pattern, and other test patterns are placed into the dicing pattern 4.
[0068] Among them, the marker box Figure 2 It can be retrieved from the plate library and placed into the corresponding dicing pattern 4.
[0069] In one possible implementation of this application, in the target bounding box Figure 3 merging above the target bounding box Figure 3 The boundary marker outside of a Figure 3 Obtain the target bounding box Figure 3 The scribing pattern 4 on a includes:
[0070] Get the target bounding box Figure 3 Establish the first coordinate system X1O1Y1 with one vertex of a as the origin O1;
[0071] Remove the target bounding box Figure 3 The boundary marker outside of a Figure 3 Extending along the X-axis and / or Y-axis of the first coordinate system X1O1Y1;
[0072] Merged and extended boundary marker box Figure 3 At the target bounding box Figure 3 a, to be in the target bounding box Figure 3 The lane marking pattern 4 is obtained from a.
[0073] That is, in the boundary marker box Figure 3 During the fusion process, the first coordinate system X1O1Y1 is used as the reference system for obtaining the dicing pattern 4. The first coordinate system X1O1Y1 is used to uniformly describe the position, orientation, and size relationship of the boundary diagram. Then, for the boundary marker box... Figure 3 The extension extends along the X-axis and / or Y-axis of the first coordinate system X1O1Y1, and is based on the target bounding box. Figure 3 The boundary size of 'a' is larger than the initial version. Figure 1 Other corresponding boundary marker boxes Figure 3 The setting of the boundary marker box Figure 3 The extensions are all within the target bounding box. Figure 3 Within the boundary of 'a' in the X-axis or Y-axis direction, and then within the extended boundary marker box. Figure 3 Merge into target bounding box Figure 3 After a, the target bounding box is obtained. Figure 3 The lane markings on a are shown in Figure 4.
[0074] Thus, through geometric extension and merging operations, an initial version is systematically generated. Figure 1 The marking path 1b avoids the inaccuracies of manual coordinate calculation or drawing, and uses the first coordinate system X1O1Y1 as the basis for subsequent marking boxes. Figure 2 Placement provides a standardized benchmark.
[0075] The dicing pattern 4 includes multiple dicing tracks 1b arranged along the X-axis and Y-axis directions, thus forming a gap area between chips for cutting and placing marks.
[0076] In one example, the merged extended boundary marker boxes Figure 3 At the target bounding box Figure 3 a, within the target bounding box Figure 3 After obtaining the scribing pattern 4 on a, it also includes:
[0077] Mark the coordinates of the first vertex x' at the intersection of the same scribe line 1b and the X-axis within the first coordinate system X1O1Y1, and the coordinates of the second vertex y' which are diagonally mapped to the coordinates of the first vertex x';
[0078] Using the first vertex coordinate x' and the second vertex coordinate y' as diagonal vertices, all scribe lines 1b within the first coordinate system X1O1Y are used to generate rectangular patterns 4a;
[0079] Compare the rectangular pattern 4a with the target bounding box. Figure 3 Perform an AND-OR operation on 'a' to obtain the target bounding box. Figure 3 The complete lane markings on a are 4b.
[0080] Specifically, for lane 1b in lane pattern 4, in the first coordinate system X1O1Y1, the intersection point coordinates are extracted to identify the coordinates of the first vertex x' at its intersection with the X-axis and the coordinates of the second vertex y' which is diagonally mapped to the first vertex x'. This yields the position coordinates of lane 1b in the first coordinate system X1O1Y1, which describe the boundary range of a rectangular lane area. Therefore, by simultaneously identifying the position coordinates of each lane 1b, the target bounding box can be defined. Figure 3 A set of rectangular patterns 4a are produced in batches on a, clearly displaying all the dicing patterns 1b included in the dicing pattern 4.
[0081] Furthermore, based on the acquisition of rectangular pattern 4a, rectangular pattern 4a is compared with the target bounding box. Figure 3 A performs an AND-OR operation to define the target bounding box. Figure 3 a) The complete lane division is obtained from 4b.
[0082] Therefore, by using coordinate extraction and diagonal positioning, the target bounding box is... Figure 3 A traceable dicing pattern is constructed on a to facilitate the accuracy of AND / OR operations.
[0083] Continue to refer to Figure 3 During the execution of S103, a first marker pattern 21 is placed within the complete slicing area 4b in the slicing pattern 4.
[0084] The first marking graphic 21 includes, but is not limited to, overprinting accuracy graphics and key dimension graphics. It is understood that the overprinting accuracy graphics and key dimension graphics have a relatively long physical size in the vertical (i.e., Y-axis) direction. Due to design and functional constraints, they are not suitable for splitting or placement at breakpoints. Therefore, the first marking graphic 21 is designed to be placed within the complete dicing channel area 4b in the dicing channel graphic 4 during the layout process, thereby ensuring that it has its own dedicated space in the layout of the panel frame.
[0085] Preferably, the complete dicing area 4b on which the first marking pattern 21 is placed is located on both sides of the dicing pattern 4. That is, the two sides of the dicing pattern 4 are usually not in the chip core arrangement area and have continuous patterning space, which is suitable for laying out such overlay precision patterns and key size patterns.
[0086] In one example, the target bounding box is obtained. Figure 3 After the complete slicing lane area 4b of the slicing lane pattern 4 is completed, the first marker pattern 21 is placed in the complete slicing lane of the complete slicing lane area 4b, and the complete slicing lane with the first marker pattern 21 is removed from the complete slicing lane area 4b.
[0087] That is, within the target bounding box Figure 3 After generating the slicing pattern 4 on a and further identifying the complete slicing area 4b therein, preferably the first marking pattern 21 is arranged in the corresponding complete slicing area 4b, and after the first marking pattern 21 is arranged, the complete slicing area is removed from the complete slicing area 4b.
[0088] The removal operation may include marking the complete lane with the first marker graphic 21 as occupied or disabled to prevent other marker graphics placed subsequently from occupying the already arranged area, thereby avoiding problems such as layout overlap, inconsistent spacing, and functional failure.
[0089] Alternatively, the removal operation may include logically removing the complete lane with the first marker graphic 21 from the set of available areas of the complete lane area 4b to ensure that the lane is not called or attempted to be reused in subsequent layout processes.
[0090] Therefore, each type of marker graphic can have a clear and non-interfering layout space, that is, the layout area of the panel layout is dynamically adjusted according to the actual use, so as to facilitate more complex multi-stage layout logic and improve layout efficiency and reliability.
[0091] refer to Figure 4 During the execution of S104, several second marker graphics 22 form a graphic matrix 5, and the center of the graphic matrix 5 is adjusted to align with the target bounding box. Figure 3 After the distance to the center of a is less than the preset distance threshold, several second marker graphics 22 are placed in the target bounding box. Figure 3 In step a, several second marker graphics 22 are located at the intersection of the slicing paths of the slicing path graphics 4, so as to obtain the target layout 10.
[0092] Among them, the center of the graphic matrix 5 and the target bounding box are adjusted. Figure 3 If the distance to the center of a is less than a preset distance threshold, it can be considered that the graphic matrix 5 is adjusted to the target bounding box. Figure 3 At the center of a, or near its center.
[0093] Preferably, the second marking pattern 22 includes, but is not limited to, alignment marking patterns for alignment and positioning during the photolithography process.
[0094] Then adjust the center of graphic matrix 5 and the target bounding box. Figure 3 The distance between the center of 'a' and the center is less than a preset distance threshold, which helps maintain the average consistency of alignment accuracy across the entire panel layout. This is especially suitable for large-size panel layouts or high-precision process nodes. Furthermore, the adjusted graphic matrix 5 makes its left-right and top-bottom layout structure more symmetrical, which is beneficial for marking the frame. Figure 2 The distribution is balanced, and the center of the graphic matrix 5 is aligned with the target bounding box. Figure 3 When the distance to the center of a is less than the preset distance threshold, it can effectively avoid occupied lanes or boundary constraint areas, reduce the risk of overlapping with other graphics, and thus form a regular layout strategy to improve the overall layout efficiency and space utilization.
[0095] In the specific implementation process, continue to refer to Figure 4 The graphic matrix 5, composed of several second marker graphics 22, is a two-dimensional matrix structure. Each second marker graphic 22 is a graphic matrix unit, and the number of rows and columns of the graphic matrix 5 can be dynamically set according to the chip size, dicing distribution and design rules. For example, the graphic matrix 5 can be constructed in a 2×2, 3×3 or larger row and column form.
[0096] In one example, to achieve a symmetrical, centralized, and reusable automatic placement strategy for the second marker graphic 22 in the tiled frame, the center of the graphic matrix 5 and the target bounding box are adjusted. Figure 3 The distance to the center of a is less than a preset distance threshold, including:
[0097] With target bounding box Figure 3 Establish a second coordinate system X2O2Y2 with one vertex of a as the origin O2;
[0098] The second marker 22 located at the starting point in the marker matrix 5 is the starting marker 22a, and the starting coordinates z' of the generated starting marker 22a in the second coordinate system X2O2Y2 are also specified.
[0099] Adjust the starting coordinate z' until the center of the graphics matrix 5 aligns with the target bounding box. Figure 3 The distance to the center of a is less than the preset distance threshold.
[0100] Specifically, a second coordinate system X2O2Y2 is established to describe and control the layout of the graphic matrix 5 and the second marker graphic 22 it comprises, and the starting coordinates z' of the starting marker graphic 22a in the graphic matrix 5 are adjusted so that the center of the graphic matrix 5 is aligned with the target bounding box. Figure 3 The distance from the center of a is less than a preset distance threshold, thus placing several second marker graphics 22 within the target bounding box. Figure 3 At the intersection of the dicing lines in pattern 4 in section a, the target pattern 10 is obtained.
[0101] In one example, after generating the initial coordinates z' of the initial marker graphic 22a in the second coordinate system X2O2Y2, the initial coordinates p' of the center of the graphic matrix 5, as well as the target bounding box, can also be generated. Figure 3 The coordinates of the center of point a are q'. Then, the Euclidean distance D = |p'-q'| between these two center points is calculated, and it is determined whether D meets the distance threshold condition. If D > the preset distance threshold, the graphic matrix 5 is adjusted in the target bounding box. Figure 3 The position in a is tracked until D is less than the preset distance threshold.
[0102] The first coordinate system X1O1Y1 and the second coordinate system X2O2Y2 can be selected as the same two-dimensional rectangular coordinate system.
[0103] In one example, the starting coordinate z' is adjusted until the center of the graphics matrix 5 aligns with the target bounding box. Figure 3 The distance to the center of a is less than a preset distance threshold, including:
[0104] Obtain the boundary dimensions of graphic matrix 5, and move the starting coordinate z' within the second coordinate system X2O2Y2 until the boundary of graphic matrix 5 aligns with the target bounding box in the X-axis and Y-axis directions of the second coordinate system X2O2Y2. Figure 3 The boundaries of 'a' all have a minimum absolute difference in distance.
[0105] After obtaining the absolute difference of this minimum distance, all second marker graphics 22 within the graphic matrix 5, except for the initial marker graphic 22a, are placed within the target bounding box. Figure 3 within a.
[0106] Preferably, the initial coordinate z' can be adjusted along the X-axis of the second coordinate system X2O2Y2 until the boundary of the graphic matrix 5 extending along the Y-axis coincides with the target bounding box. Figure 3After the boundary extending along the Y-axis has the minimum absolute difference, that is, after the absolute difference between K1 and K2 is minimized, adjust the starting coordinate z' along the Y-axis direction of the second coordinate system X2O2Y2 until the boundary of the graphic matrix 5 extending along the X-axis is close to the target bounding box. Figure 3 If the boundary extending along the X-axis has the minimum absolute difference in distance, that is, the minimum absolute difference between L1 and L2, then it can be considered as the boundary box between the center of the graphic matrix 5 and the target. Figure 3 If the distance to the center of a is less than a preset distance threshold, then all second marker graphics 22 within the graphic matrix 5, except for the initial marker graphic 22a, will be placed within the target bounding box. Figure 3 Within 'a', it is placed at the intersection of the lane markings in lane marking diagram 4.
[0107] Alternatively, the starting coordinate z' can be adjusted along the Y-axis of the second coordinate system X2O2Y2 until the boundary of the graphic matrix 5 extending along the X-axis coincides with the target bounding box. Figure 3 After the boundary extending along the X-axis has the minimum absolute difference, that is, after the absolute difference between L1 and L2 is minimized, adjust the starting coordinate z' along the X-axis direction of the second coordinate system X2O2Y2 until the boundary extending along the Y-axis of the graphic matrix 5 is close to the target bounding box. Figure 3 If the boundary extending along the Y-axis has the minimum absolute difference in distance, that is, the minimum absolute difference between K1 and K2, then it can be considered as the boundary box between the center of the graphic matrix 5 and the target. Figure 3 If the distance to the center of a is less than a preset distance threshold, then all second marker graphics 22 within the graphic matrix 5, except for the initial marker graphic 22a, will be placed within the target bounding box. Figure 3 within a.
[0108] It is understandable that this is done after confirming the center of graphic matrix 5 and the target bounding box. Figure 3 When the distance to the center of a is less than the preset distance threshold, the initial coordinates z' of the initial marker graphic 22a are transformed into the center coordinates z in the second coordinate system X2O2Y2.
[0109] Specifically, to precisely control the graphic matrix 5 composed of the second marker graphic 22 within the target bounding box... Figure 3 The placement of the marker in 'a', and the precise placement of the second marker 22 (excluding the initial marker 22a), requires prior acquisition of the boundary dimensions of the graphic matrix 5. Specifically, acquiring the boundary dimensions of the graphic matrix 5 includes: identifying the target bounding box. Figure 3The target chip in the several design chips corresponding to a has a boundary size smaller than other design chips, that is, the boundary size of the target chip is the smallest in the design chips, so as to reflect the scale reference of the smallest available unit in the current panel block diagram; and, in the X-axis direction and Y-axis direction of the second coordinate system X2O2Y2, there is a target spacing between any second mark pattern 22 and its adjacent second mark pattern 22, and the target spacing is set to be greater than N times the boundary size of the target chip, so as to obtain the boundary size of the pattern matrix 5, where N is an integer ≥1.
[0110] Therefore, based on the center coordinate z”, the target spacing, and the boundary dimensions of the graphic matrix 5, all second marker graphics 22 within the graphic matrix 5, except for the initial marker graphic 22a, can be placed within the target bounding box. Figure 3 within a.
[0111] Optionally, a preset distance threshold is greater than or equal to the absolute distance (diagonal radius) between the center point of the target chip and any of its vertices.
[0112] During the execution of S105, the target version is merged. Figure 1 The initial layout 10 is used to form an output file, and the output file is checked and a check result report is output.
[0113] In one example, in merging the target version Figure 1 Before the initial layout 10 is used to form the output file, it also includes: according to the block diagram design rules, marking the marker boxes other than the first marker graphic 21 and the second marker graphic 22. Figure 2 Placed in the dicing pattern 4, i.e., on the target plate. Figure 1 After placing the first marker graphic 21 and the second marker graphic 22 in sequence, the marker frame is... Figure 2 The other included marker graphics are automatically arranged to obtain the target layout 10, which in turn generates the final output file.
[0114] Optionally, the marker box Figure 2 It also includes the third marker graphic 23.
[0115] The third marker graphic 23 includes, but is not limited to, boundary corner graphics, used for edge alignment or map boundary marking.
[0116] In the specific implementation process, the output file is from the target version. Figure 1 It is obtained by merging with the initial layout 10, that is, by overlaying the initial layout 10 onto the target layout. Figure 1 To obtain the output file.
[0117] To ensure the accuracy of the layout diagram and the quality of the marked graphics placement, the output file is checked and a check result report is generated as the target version. Figure 1 A secondary confirmation method.
[0118] refer to Figure 5 ,exist Figure 5 In the comparison diagram shown, 10a represents the correct result report for the inspection item, and 10b represents the incorrect result report for the inspection item. In the incorrect result report for the inspection item, the content at point A indicates that the spacing index of the first mark graphic 21 is incorrect. For example, the content at point A shows that the spacing between the overlay marks is insufficient. The content at point B indicates that the second mark graphic 22 has an error in the graphic matrix 5 because it is not aligned in the same row / column. For example, the content at point A shows that the alignment mark graphics are not aligned in the same row / column of the graphic matrix 5. The content at point C indicates that there is a mark graphic of a different mark type than the second mark graphic 22 in the row array of the graphic matrix 5. The content at point D indicates that there is an error in the sorting of the second mark graphic 22 in the row array of the graphic matrix 5.
[0119] Therefore, by checking the output file and outputting the check result report, it is possible to verify whether the output file contains all the expected marked diagrams, identify whether there are problems such as missing layers, overlapping graphics, graphic defects, and layer misalignment, and retain them for a long time as process traces, thus forming a closed-loop process of automatic layout and automatic inspection of the layout diagram, and improving the reliability of the layout diagram.
[0120] The present application has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only for the purpose of helping to understand the core ideas of the present application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present application. Therefore, the content of this specification should not be construed as a limitation of the present application.
Claims
1. A method for arranging a frame diagram, characterized in that, include: Identify the target boundary map in several boundary marker maps corresponding to the initial map; By fusing the boundary marker diagrams other than the target boundary diagram onto the target boundary diagram, a slicing pattern on the target boundary diagram is obtained; Place a first marker pattern within the complete slicing area of the slicing pattern; A graphic matrix is formed by several second marker graphics. After adjusting the distance between the center of the graphic matrix and the center of the target boundary map to be less than a preset distance threshold, several second marker graphics are placed in the target boundary map, and several second marker graphics are respectively located at the intersection of the slicing lane graphics to obtain the target map. The target layout and the initial layout are merged to form an output file, and the output file is checked and a check result report is output.
2. The method for arranging the frame diagram as described in claim 1, characterized in that, The process of fusing the boundary marker diagrams other than the target boundary diagram onto the target boundary diagram to obtain the slicing pattern on the target boundary diagram includes: Take one vertex of the target boundary map as the origin of the coordinate system and establish a first coordinate system; Extend the boundary identification diagram, excluding the target boundary diagram, along the X-axis and / or Y-axis of the first coordinate system; The extended boundary marker diagram is merged into the target boundary diagram, and the slab pattern is obtained on the target boundary diagram.
3. The method for arranging the frame diagram as described in claim 2, characterized in that, After the merged and extended boundary marker diagram is applied to the target boundary diagram, and the slicing pattern is obtained on the target boundary diagram, the method further includes: Mark the coordinates of the first vertex at the intersection of the same scribe line and the X-axis within the first coordinate system, and the coordinates of the second vertex that are diagonally mapped to the coordinates of the first vertex; Using the coordinates of the first vertex and the coordinates of the second vertex as diagonal vertices, all scribbling tracks within the first coordinate system are generated into rectangular patterns; Perform an AND-OR operation between the rectangular pattern and the target boundary map to obtain the complete slicing area of the slicing pattern on the target boundary map.
4. The method for arranging the frame diagram as described in claim 3, characterized in that, After obtaining the complete slicing area of the slicing pattern on the target boundary map, the first marker pattern is placed in the complete slicing area of the complete slicing area, and the complete slicing area with the first marker pattern is removed from the complete slicing area.
5. The method for arranging the frame diagram as described in claim 3, characterized in that, The complete slit lane area with the first marked pattern is located on both sides of the slit lane pattern.
6. The method for arranging the frame diagram as described in claim 1, characterized in that, Adjusting the distance between the center of the graphic matrix and the center of the target boundary map to be less than a preset distance threshold includes: A second coordinate system is established using one vertex of the target boundary map as the origin. The second marked graphic located at the starting point in the graphic matrix is designated as the starting marked graphic, and the starting coordinates of the starting marked graphic in the second coordinate system are generated; Adjust the starting coordinates until the distance between the center of the graphic matrix and the center of the target boundary map is less than a preset distance threshold.
7. The method for arranging the frame diagram as described in claim 6, characterized in that, The step of adjusting the starting coordinates until the distance between the center of the graphic matrix and the center of the target boundary map is less than a preset distance threshold includes: Obtain the boundary dimensions of the graphic matrix, and move the starting coordinates within the second coordinate system until the boundary of the graphic matrix has the minimum absolute difference between the boundary of the target boundary map and the X-axis and Y-axis of the second coordinate system.
8. The method for arranging the frame diagram as described in claim 7, characterized in that, Obtaining the boundary dimensions of the graphic matrix includes: Identify the target chip among the several design chips corresponding to the target boundary block diagram. The boundary size of the target chip is smaller than that of the other design chips. In the X-axis and Y-axis directions of the second coordinate system, there is a target spacing between any second mark pattern and its adjacent second mark pattern. Set the target spacing to be greater than N times the boundary size of the target chip to obtain the boundary size of the pattern matrix, where N is an integer ≥ 1.
9. The method for arranging the frame diagram as described in claim 1, characterized in that, Before merging the target layout and the initial layout to form the output file, the process includes: Place the marker frame diagram, excluding the first and second marker graphics, into the slicing pattern.
10. The method for arranging layout diagrams as described in any one of claims 1 to 9, characterized in that, Before the target boundary map in the several boundary marker maps corresponding to the initial layout, the following is included: Based on the block diagram design rules, the marker block diagrams, which include at least the first marker graphic and the second marker graphic, are named and collected into the layout library for use when arranging the layout block diagrams.