Write management mechanism for performance and lifetime enhancement of four-level storage unit flash memory

Abstract

The invention relates to a write management mechanism for cross-energy and lifetime enhancement of a four-level storage unit flash memory. The invention provides a method for controlling a flash memory, which comprises the following steps of: in response to one or more host write commands, writing host data associated with the one or more host write commands into a target block in a region of the flash memory in a one-time programming manner and in a specific write mode; performing a block reliability check on the target block to generate a block reliability indication; selecting one of a direct conversion mode and a conversion mode based on garbage collection operation according to the block reliability indication; and performing storage unit level reconfiguration on the target block according to the selected conversion mode.

Description

Technical Field

[0001] This invention relates to flash memory, and more particularly to a control method for improving the performance and durability of quad-level cell (QLC) flash memory, as well as related memory controllers and data storage devices. Background Technology

[0002] Quadruple-Level Cell (QLC) flash memory is an advanced storage technology whose main advantage lies in its significantly increased storage density. Each QLC memory cell can store 4 bytes of information, meaning that compared to Single-Level Cell (SLC), Multi-Level Cell (MLC), and Triple-Level Cell (TLC) technologies, QLC technology can store more information in the same physical space. This higher storage density makes QLC flash memory a highly cost-effective storage solution, particularly suitable for large-scale data storage applications and enterprise-level applications. However, because each QLC memory cell has 16 possible charge states (corresponding to 4 bits), the difficulty of identification is inherently increased, leading to an increased error rate during write and read operations. Compared to other technologies, QLC flash memory has slower read and write speeds and a relatively higher read / write error rate. Clearly, QLC flash memory requires more advanced write management mechanisms to overcome its inherent shortcomings. Summary of the Invention

[0003] Based on the above background, the purpose of this invention is to provide a block management and configuration mechanism for QLC flash memory. In embodiments of this invention, a method for controlling flash memory is provided. This method performs cell-level reconfiguration on TLC blocks of the flash memory and selectively performs direct conversion based on the block reliability check results of the TLC blocks, thereby reconfiguring and writing the TLC blocks to convert them into QLC blocks. This method maintains the write performance of the QLC flash memory while ensuring storage reliability. In embodiments of this invention, a method for determining the control strategy of QLC flash memory is also provided. This method selects either a performance-oriented strategy or a lifetime-oriented strategy based on the wear and tear status of the QLC flash memory, maintaining the write performance of the QLC flash memory while considering device lifetime.

[0004] Embodiments of the present invention provide a method for controlling a flash memory, the method comprising: in response to one or more host write commands, writing host data associated with the one or more host write commands to a target block within a region of the flash memory in a one-time programming manner and in a specific write mode; performing a block reliability check on the target block to generate a block reliability indication; selecting, based on the block reliability indication, one of a direct conversion mode and a garbage collection-based conversion mode; and performing a storage cell hierarchy reconfiguration on the target block according to the selected conversion mode.

[0005] Embodiments of the present invention provide a memory controller for use in a flash memory. The memory controller includes a storage unit and a processing unit. The storage unit stores program code. The processing unit executes the program code to perform the following operations on the flash memory: in response to one or more host write commands, in a one-time programming manner, write host data associated with the one or more host write commands into a target block within a region of the flash memory in a specific write mode; perform a block reliability check on the target block to generate a block reliability indication; select, based on the block reliability indication, one of a direct conversion mode and a garbage collection-based conversion mode; and perform a storage unit hierarchy reconfiguration on the target block according to the selected conversion mode.

[0006] Embodiments of the present invention provide a method for controlling a flash memory. The method includes: selecting a first strategy to configure the flash memory and controlling the flash memory according to the first strategy; determining whether a wear-out status indicator value related to the flash memory exceeds a predetermined threshold; and if the wear-out status indicator value exceeds the predetermined threshold, selecting a second strategy to configure the flash memory and controlling the flash memory according to the second strategy. Further, in the first strategy, a garbage collection operation is not immediately performed once the number of available blocks in a specific region of the flash memory falls below a lower limit. In the second strategy, a garbage collection operation is immediately performed once the number of available blocks in the specific region of the flash memory falls below the lower limit.

[0007] Embodiments of the present invention provide a memory controller for use in a flash memory. The memory controller includes a storage unit and a processing unit. The storage unit stores program code. The processing unit executes the program code to perform the following operations on the flash memory: selecting a first strategy to configure the flash memory and controlling the flash memory according to the first strategy; determining whether a wear-out status indicator value related to the flash memory exceeds a predetermined threshold; and if the wear-out status indicator value exceeds the predetermined threshold, selecting a second strategy to configure the flash memory and controlling the flash memory according to the second strategy. In the first strategy, a garbage collection operation is not immediately performed once the number of available blocks in a specific region of the flash memory falls below a lower limit. In the second strategy, a garbage collection operation is immediately performed once the number of available blocks in the specific region of the flash memory falls below the lower limit. Attached Figure Description

[0008] Figure 1 A schematic diagram illustrating the architecture of a data storage device according to an embodiment of the present invention is shown.

[0009] Figure 2 A flowchart illustrating how an embodiment of the present invention performs a block reliability check on a target block is shown.

[0010] Figure 3 The illustrations depict how embodiments of the present invention perform a direct conversion mode and a conversion mode based on garbage collection operations.

[0011] Figure 4 A flowchart illustrating a method for controlling a flash memory according to an embodiment of the present invention is shown.

[0012] Figure 5 This illustration depicts how embodiments of the present invention configure and control flash memory according to performance-oriented and lifetime-oriented strategies.

[0013] Figure 6 A flowchart illustrating a method for controlling a flash memory according to an embodiment of the present invention is shown.

[0014] [Symbol Explanation]

[0015] 50 Main Units

[0016] 52 processor

[0017] 54 RAM

[0018] 100 Data storage devices

[0019] 110 Memory Controller

[0020] 112 Processing Units

[0021] 112C program code

[0022] 112M ROM

[0023] 113 Internal Memory

[0024] 114 Control Logic Circuit

[0025] 118 Transmission Interface Circuit

[0026] 120 NV memory

[0027] 121-page cache

[0028] 122_1~122_N NV memory elements

[0029] 123 Control Circuit

[0030] 130 ECC processing circuit Detailed Implementation

[0031] Numerous specific details are described below to provide the reader with a thorough understanding of embodiments of the invention. However, those skilled in the art will appreciate how the invention can be implemented in the absence of one or more specific details, or by utilizing other methods, elements, or materials. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the core concepts of the invention. Furthermore, unless otherwise stated, similar reference numerals in the drawings and written description will be used to denote similar elements and will not be described repeatedly. And, for clarity, the dimensions of specific elements and their relative proportions in the drawings do not necessarily conform to their physical dimensions or relative proportions.

[0032] The use of the terms "an embodiment" or "one embodiment" in this specification essentially means that a particular feature, structure, or characteristic associated with the described embodiment or example is included in at least one embodiment. Therefore, the use of "an embodiment" or "one embodiment" in different locations within this specification does not necessarily refer to the same embodiment. Furthermore, the aforementioned specific features, structures, or characteristics may be combined in any suitable form in one or more embodiments.

[0033] Figure 1This is an architectural diagram of an electronic device and a data storage device according to an embodiment of the present invention. The electronic device 10 includes a host device 50 and a data storage device 100. The host device 50 may include: at least one processor 52 for controlling the host device 50, and a random access memory (RAM) 54 for storing data and information required by the processor 52. Examples of the host device 50 include, but are not limited to: smartphones, tablets, wearable devices, personal computers (e.g., desktop computers and laptop computers), imaging devices (e.g., digital cameras or camcorders), game consoles, car navigation systems, printers, scanners, or server systems. Examples of the data storage device 100 include, but are not limited to: portable storage devices (e.g., memory cards conforming to SD / MMC, CF, MS, XD, or UFS specifications), solid-state drives (SSDs), and various embedded storage devices (e.g., embedded storage devices conforming to UFS or eMMC specifications).

[0034] In various embodiments of the present invention, the data storage device 100 may include a controller (e.g., a memory controller 110) and may also include a non-volatile (NV) memory 120. The NV memory 120 is used to store information. The NV memory 120 may contain one or more NV memory elements, for example, a plurality of NV memory elements 122_1 to 122_N. The NV memory 120 may be a flash memory, and the NV memory elements 122_1 to 122_N may be a plurality of flash memory chips or a plurality of flash memory dies, but the present invention is not limited thereto. Furthermore, the NV memory 120 may include memory cells with a two-dimensional structure or memory cells with a three-dimensional structure.

[0035] like Figure 1As shown, the memory controller 110 may include a processing unit 112, a read-only memory (ROM) 112M, an internal memory 113, a control logic circuit 114, a transmission interface circuit 118, and an error correction coding (ECC) processing circuit 130. At least some of these circuit elements can be coupled and communicate with each other via a bus. The internal memory 113 may be implemented by one or more memory devices. For example, the internal memory 113 may be static RAM (SRAM) and / or dynamic RAM (DRAM). The internal memory 113 can be used to provide internal storage space for the memory controller 110, for example, temporarily storing information such as variables / parameters, data, commands, addresses, and / or address mapping tables. In some embodiments, the memory controller 110 may not have an internal memory 113 and relies on host memory buffer (HMB) technology. By using HMB technology, the memory controller 110 can utilize the host device 50's RAM 54 (e.g., DRAM) as part of or an extension of the internal memory 113, or use RAM 54 as an alternative to the internal memory 113, thereby improving the read and write performance of the data storage device 100.

[0036] Furthermore, program code 112C in ROM 112M (or, program code 112C may be stored in a non-volatile memory (not shown) of memory controller 110) can be read and executed by microprocessor 112, thereby realizing access control of NV memory 120. Program code 112C may include one or more program modules, such as boot loader program code. When data storage device 100 receives power from host device 50, processing unit 112 may start an initialization program of data storage device 100 by executing program code 112C. In the initialization program, microprocessor 112 may load a set of in-system programming (ISP) program code (not shown) from NV memory 120. Figure 1The microprocessor 112 can execute this set of in-system programming code, enabling the data storage device 100 to perform various functions. In one embodiment of the invention, the set of in-system programming code may include, but is not limited to: one or more program modules related to memory access (e.g., read, write, and erase) (e.g., a read operation module), a lookup table module, a wearleveling module, a read refresh module, a read reclaim module, a garbage collection module, and a Sudden Power Off Recovery (SPOR) module, respectively provided to perform corresponding read, lookup table, wearleveling, read refresh, read reclaim, garbage collection, and unexpected power off recovery operations.

[0037] The memory controller 110 controls the reading, writing, and erasing of the NV memory 120 via control logic circuitry 114. Furthermore, the memory controller 110 can simultaneously perform: user data writing based on host commands from the host device 50, and writing of valid data read from the NV memory 120 based on garbage collection operations and / or wear leveling operations. The transmission interface circuit 118 may conform to specific communication specifications (e.g., Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed-I (UHS-I) interface standard, Ultra High Speed-II (UHS-II) interface standard, CompactFlash (CF) interface standard, Multimedia Card (MMC) interface standard, eMMC interface standard, Universal Flash Storage (UFS) interface standard, Advanced Technology Attachment (ATA) standard, Serial ATA (SATA) standard, Peripheral Component Interconnect Express (PCI-E) standard, Parallel Advanced Technology Attachment (PATA) standard, etc.), and can communicate with the host device 50 according to specific communication specifications.

[0038] Typically, the host device 50 may indirectly access the NV memory 120 by transmitting host commands and corresponding logical addresses to the memory controller 110. Upon receiving the host commands and logical addresses, the memory controller 110 translates the logical addresses into physical addresses and the host commands into memory operation commands. It then controls the NV memory 120 via these memory operation commands to perform read, program, or erase operations on memory cells or data pages with physical addresses. The NV memory 120 includes one or more page buffers 121 (which may be implemented using SRAM) and one or more control circuits 123. Data that the memory controller 110 intends to write to the NV memory 120 is first written to the page buffers 121 and then to the memory cells of the NV memory 120. The one or more control circuits 123 read, program, or erase data according to the memory operation commands sent by the memory controller 110. When the memory controller 110 performs an erase operation on any one of the plurality of NV memory elements 122_k (from 122_1 to 122_N), at least one block in the NV memory element 122_k can be used as the target of the erase operation. Furthermore, each block of the NV memory element 122_k can contain multiple pages, and one or more pages can be used as the target of read or write operations.

[0039] In one embodiment, each of the NV memory elements 122_1 to 122_N may be an NV memory die or chip. Each NV memory die 122_1 to 122_N has control circuitry for executing memory operation commands issued by the memory controller 110. Furthermore, each NV memory die 122_1 to 122_N may contain multiple planes. Each plane has multiple blocks composed of memory cells, and associated column and row control circuitry. The memory cells in each plane may be arranged in a 2D or 3D memory structure. Moreover, through multi-plane operation commands, various processing operations can be performed simultaneously on different planes; for example, multiple memory operations can be performed in parallel (simultaneously) on memory blocks in different planes to perform multi-plane (e.g., read, write, erase) operations. Additionally, in one embodiment, the memory controller 110 can combine the blocks of the NV memory 120 into multiple super blocks. In one embodiment, the superblock may span across NV memory chips 122_1 to 122_N. Furthermore, the superblock may serve as one or more storage blocks for each NV memory chip 122_1 to 122_N.

[0040] In one embodiment of the invention, an L2P address mapping table, consisting of a plurality of logical-to-physical (L2P) address mapping entries, may be divided into multiple mapping groups. Each mapping group includes a portion of the address mapping entries from the L2P address mapping table to perform logical-to-physical address translation. These mapping groups are permanently stored in blocks of NV memory 120 and loaded into internal memory 113 when needed. Similarly, a P2L address mapping table, consisting of a plurality of physical-to-logical (P2L) address mapping entries, may be divided into multiple mapping groups. Each mapping group includes a portion of the address mapping entries from the P2L address mapping table to perform physical-to-logical address translation. These mapping groups are permanently stored in blocks of NV memory 120 and loaded into internal memory 113 when needed.

[0041] In this embodiment of the invention, the memory controller 110 supports multiple write modes. In the single-level cell (SLC) write mode supported by the memory controller 110, 1 bit of data can be written to each memory cell. In the multi-level cell (MLC) write mode supported by the memory controller 110, 2 bits of data can be written to each memory cell. In the triple-level cell (TLC) write mode supported by the memory controller 110, 3 bits of data can be written to each memory cell. In the quadruple-level cell (QLC) write mode supported by the memory controller 110, 4 bits of data can be written to each memory cell. Accordingly, the memory controller 110 will select one of its supported write modes to perform a write operation on the NV memory 120.

[0042] Each NV memory element 122_1 to 122_N can be a flash memory where each memory cell stores one or more bits of metadata. For example, an SLC flash memory where each memory cell stores 1 bit of metadata, an MLC flash memory where each memory cell stores 2 bits of metadata, a TLC flash memory where each memory cell stores 3 bits of metadata, and a QLC flash memory where each memory cell stores 4 bits of metadata. Each page within each NV memory element 122_1 to 122_N contains memory cells connected to a word line as the unit for data write / read operations. Alternatively, a word line can also serve as the unit for data write / read operations.

[0043] In one embodiment, the NV memory 120 can be configured as an MLC flash memory, with each memory cell storing 2 bits. In typical applications, two pages of data (i.e., lower page data and upper page data) are written to memory cells connected to a single word line, allowing each memory cell to store 2 bits. However, any region (e.g., one or more blocks) within the MLC flash memory 120 can be selectively designated as a specific region, which can be configured to store only 1 bit per memory cell to improve performance. This flexibility allows the creation of SLC regions (i.e., SLC caches) within the MLC flash memory 120. In this way, the memory controller 110 can perform write operations in SLC write mode, programming data to the SLC region so that a single page of data is written to the memory cell connected to a single word line. In short, within the SLC regions within the MLC flash memory 120, each block is used as an SLC block; blocks outside of these regions are used as MLC blocks.

[0044] In one embodiment, the NV memory 120 can be configured as a TLC flash memory, allowing each memory cell to store 3 bits. In typical applications, three pages of data (i.e., lower page data, middle page data, and upper page data) are written to memory cells connected to a single word line, thus enabling each memory cell to store 3 bits. However, any region (e.g., one or more blocks) of the TLC flash memory 120 can be selectively configured as an SLC region (storing 1 bit per memory cell) and / or an MLC region (storing 2 bits per memory cell) to improve performance. This flexibility allows for the creation of SLC regions (i.e., SLC cache) and / or MLC regions within the TLC flash memory 120. In this way, the memory controller 110 can perform write operations in SLC write mode, programming data to the SLC region such that a single page of data is written to a memory cell connected to a single word line. Alternatively, the memory controller 110 can perform a write operation in MLC write mode, programming data into the MLC region so that two pages of data are written to the memory cell connected to a single word line. Therefore, within the SLC region of the TLC flash memory 120, each block is used as an SLC block, while within its MLC region, each block is used as an MLC block; blocks outside of this region are used as TLC blocks.

[0045] In one embodiment, the non-volatile memory 120 can be configured as a QLC flash memory, allowing each memory cell to store 4 bits. In typical applications, four pages of data (i.e., lower page data, middle page data, upper page data, and top page data) are written to memory cells connected to a single word line, thus enabling each memory cell to store 4 bits. However, any region (e.g., one or more blocks) of the QLC flash memory 120 can be selectively configured as an SLC region (1 bit per memory cell), an MLC region (2 bits per memory cell), and / or a TLC region (3 bits per memory cell) to improve performance. This flexibility allows for the creation of SLC regions (i.e., SLC cache), MLC regions, and / or TLC regions within the QLC flash memory 120. In this way, the memory controller 110 can perform write operations in SLC write mode, programming data to the SLC region such that a single page of data is written to a memory cell connected to a single word line. Alternatively, the memory controller 110 can perform a write operation in MLC write mode, programming data into the MLC region so that two pages of data are written to the memory cell connected to a single word line. It can also perform a write operation in TLC write mode, programming data into the TLC region so that three pages of data are written to the memory cell connected to a single word line. Therefore, within the QLC flash memory 120, each block is used as an SLC block within the SLC region, as an MLC block within the MLC region, and as a TLC block within the TLC region; blocks outside these regions are used as QLC blocks.

[0046] In one embodiment, if a target block of the NV memory 120 is filled with data (e.g., host data associated with a host write command), the memory controller 110 may perform a cell-level reconfiguration on that target block. The target block may be a TLC block within the TLC region of the QLC flash memory 120. Furthermore, data is written to the TLC block in a one-shot programming manner within a program cycle. Before performing cell-level reconfiguration on the target block, a block reliability check is performed to determine how to perform the cell-level reconfiguration.

[0047] Please see Figure 2The figure illustrates a flowchart of performing a block reliability check on a target block in an embodiment of the present invention. In step S101, it is determined whether a write temperature when data is written to the target block is within a predetermined temperature range. If so, the process proceeds to step S102. Otherwise, the process ends, and a block reliability indication indicating that the target block has weak reliability is generated. In one embodiment, the predetermined temperature range is approximately 20°C to 60°C. That is, if the write temperature when data is written to the target block is below 20°C or above 60°C, the target block is considered to have weak reliability.

[0048] In step S102, it is determined whether the number of reads of data within the target block exceeds a predetermined read count threshold TH1. If not, the process proceeds to step S103. If yes, the process ends, and a block reliability indication indicating that the target block has weak reliability is generated. In one embodiment, the predetermined read count threshold TH1 may be lower than a typical read count threshold that the block of the NV memory 120 can accept (withstand). Generally, when the number of reads of a block of the NV memory 120 exceeds the typical read count threshold, the memory controller 110 performs a refresh operation on the block by moving the data of the block to a new or blank block (which can be achieved through garbage collection), thereby avoiding the potential risk of read disturbance to the data within the block. However, the predetermined read count threshold TH1 used for block reliability checking in this invention will be lower than the typical read count threshold to achieve higher reliability requirements. In one embodiment, the predetermined read count threshold TH1 may be half of the typical read count threshold.

[0049] In step S103, it is determined whether the time elapsed since the target block was erased or written with data (i.e., the block lifetime) exceeds a predetermined block lifetime threshold TH2. If not, the process proceeds to step S104; if yes, the process ends, and a block reliability indication indicating that the target block has weak reliability is generated. In one embodiment, the predetermined block lifetime threshold TH2 may be lower than a typical block lifetime threshold that the NV memory 120 can accept (withstand). Generally, if the lifetime of a block in the NV memory 120 from when data is written to until it is erased exceeds the typical block lifetime threshold, the memory controller 110 updates the block by moving the data of the block to a new / blank block (which can be achieved through garbage collection), thereby improving data retention. However, the predetermined block lifetime threshold TH2 used for block reliability checking in this invention is lower than the typical block lifetime threshold to achieve higher reliability requirements. In one embodiment, the predetermined block lifetime threshold TH2 can be half of the usual block lifetime threshold.

[0050] In step S104, it is determined whether the ECC processing circuit 130 initiated soft decoding when reading data within the target block. If not, the process proceeds to step S105; if yes, the process ends, and a block reliability indicator indicating that the target block has weak reliability is generated. Furthermore, if the ECC processing circuit 130 initiated soft decoding when reading data within the target block, this means that the target block has a potential risk of data corruption.

[0051] In step S105, it is determined whether the number of read retry operations performed when reading data in the target block exceeds a predetermined read retry threshold TH3. If not, the process proceeds to step S106; if yes, the process ends, and a block reliability indication indicating that the target block has weak reliability is generated. In one embodiment, the predetermined read retry threshold TH3 may be lower than a typical read retry threshold that the block of the NV memory 120 can accept (withstand). Generally, when the number of read retries for a block of the NV memory 120 exceeds the typical read retry threshold, the memory controller 110 performs an update / move operation on the block by moving the data of the block to a new / blank block (which can be achieved through garbage collection), thereby ensuring the data integrity of the block. However, the predetermined read retry threshold TH3 used for block reliability checking in this invention is lower than the typical read retry threshold to achieve higher reliability requirements. In one embodiment, the predetermined read retry threshold TH3 can be half of the normal read retry threshold. In step S106, a block reliability indicator is generated, indicating that the target block has relatively high reliability. It should be noted that although the block reliability is determined through steps S101 to S105 in the above process, in some embodiments of the present invention, some steps can be omitted, and it is not necessary to fully execute all steps to determine the block reliability.

[0052] Once according to Figure 2 The illustrated process generates a block reliability indicator. The memory controller 110 will select either a direct conversion mode or a garbage-collection-based conversion mode to perform a storage unit hierarchy reconfiguration on the target block. If the block reliability indicator indicates that the target block has poor reliability, the memory controller 110 will select the garbage-collection-based conversion mode to perform the storage unit hierarchy reconfiguration. Conversely, if the block reliability indicator indicates that the target block has high reliability, the memory controller 110 will select the direct conversion mode to perform the storage unit hierarchy reconfiguration.

[0053] Please see Figure 3 To gain a deeper understanding. Figure 3A target block storing page data D_1 to D_12 is drawn; this target block is a TLC block. The page data D_1 to D_12 can be written to this target block using one-shot programming in TLC write mode. In subsequent memory cell level reconfiguration, if a garbage collection-based conversion mode is selected, the memory controller 110 will initiate a garbage collection operation, reading page data D_1, D_2, and D_3 (i.e., low page data (LP), middle page data (MP), and high page data (UP) – potentially corresponding to the same word line) – from the target block, and reading valid page data D_N from a source block in the NV memory 120 that is different from the target block. Then, the memory controller 110 will program the page data D_1, D_2, D_3, and D_N to a destination block in the NV memory 120 that is different from the target block (i.e., the destination of the garbage collection operation) using two-pass programming. That is, page data D_1, D_2, D_3, and D_N are programmed into the destination block in two programming passes. Finally, the destination block will be configured as a QLC block to store page data D_1, D_2, D_3, and D_N (i.e., low page data (LP), middle page data (MP), high page data (UP), and top page data (TP)). The above process is also known as TLC to QLC conversion based on garbage collection operations.

[0054] On the other hand, if the direct conversion mode is selected, the memory controller 110 reads page data D_1, D_2, and D_3 (i.e., low page data (LP), middle page data (MP), and high page data (UP) (possibly corresponding to the same word line)) from the target block (i.e., the TLC block) and reads valid page data D_N from a source block in the NV memory 120 that is different from the target block. Accordingly, the memory controller 110 writes the page data D_1, D_2, D_3, and D_N back to the target block through one-pass programming. This operation is possible because a first programming pass was performed on the target block when it was configured as a TLC block. In other words, the target block is written with page data D_1, D_2, and D_3 through a first programming pass, and page data D_N is written through a second programming pass. Afterward, the target block is converted from a TLC block to a QLC block storing page data D_1, D_2, D_3, and D_N (i.e., low page data (LP), middle page data (MP), high page data (UP), and top page data (TP) (these may correspond to the same word line)). This process is also known as a direct TLC to QLC conversion.

[0055] Based on the above embodiments, the present invention provides a method for controlling flash memory. Please refer to... Figure 4 The diagram shows a simplified flowchart of controlling a flash memory, including the following steps:

[0056] Step S201: In response to one or more host write commands, host data associated with the one or more host write commands is written to a target block within a region of the flash memory in a one-shot programming manner, in a specific write mode;

[0057] Step S202: Perform a block reliability check on the target block to generate a block reliability indication;

[0058] Step S203: Based on the block reliability indication, select one of a direct conversion mode and a garbage collection-based conversion mode; and

[0059] Step S204: Perform storage unit level reconfiguration on the target block according to the selected conversion mode.

[0060] Since the principles and specific details of the above steps have been described in detail in the previous embodiments, they will not be repeated here. It is worth mentioning that the above process can be improved by adding other additional steps or by making appropriate modifications and adjustments to specific steps to enhance the performance, durability, and reliability of the QLC flash memory. Such modifications should also be considered within the scope of this invention.

[0061] In one embodiment, the memory controller 110 may select either a lifetime-oriented strategy or a performance-oriented strategy. The memory controller 110 then configures the NV memory 120 according to the selected strategy and performs specific forms of write operations (or other control operations) on the NV memory 120 based on host write commands.

[0062] Please see Figure 5 To further understand. For example... Figure 5 As shown, in the lifetime-oriented strategy, the NV memory 120 is configured to have a static SLC region 210 containing multiple SLC blocks and a QLC region 220 containing multiple QLC blocks. Furthermore, in the lifetime-oriented strategy, the memory controller 110 is configured to prioritize writing host data to the SLC blocks of the SLC region 210. Once the number of available (remaining) SLC blocks in the SLC region 210 falls below a lower limit, the memory controller 110 performs a garbage collection operation, collecting valid data from the SLC blocks of the SLC region 210 and correspondingly writing the collected valid data to the QLC blocks of the QLC region 220 (i.e., an SLC-to-QLC (S2Q) GC operation). Furthermore, the memory controller 110 can also collect valid data from the QLC blocks of the QLC region 220 and write the collected valid data to the empty QLC blocks in the QLC region 220 accordingly (i.e., QLC-to-QLC (Q2Q) GC operation). In other words, in the lifetime-oriented strategy, the memory controller 110 will perform a garbage collection operation whenever the number of SLC blocks in the SLC region 210 is insufficient.

[0063] In the performance-oriented strategy, the NV memory 120 is configured to have: a static SLC region 310 and / or a dynamic SLC region 320 (each containing multiple SLC blocks), a TLC region 330 (containing multiple TLC blocks), and a QLC region 340 (containing multiple QLC blocks). In this performance-oriented strategy, the memory controller 110 prioritizes writing host data to the SLC blocks of the static SLC region 310 and / or the dynamic SLC region 320. Once the number of available (remaining) SLC blocks in the static SLC region 310 and / or the dynamic SLC region 320 falls below a lower limit, the memory controller 110 will write the host data to the TLC blocks of the TLC region 330 in a one-time programming manner (i.e., TLC direct write). At this time, the memory controller 110 will not perform SLC-to-QLC garbage collection. Furthermore, when the number of available TLC blocks within TLC region 330 is low, memory controller 110 may further perform the aforementioned storage cell hierarchy reconfiguration (i.e., perform a direct TLC to QLC conversion) to reconfigure TLC blocks as QLC blocks to store more data. If the number of available TLC blocks within TLC region 330, and / or the number of available SLC blocks within static SLC region 310 and / or dynamic SLC region 320, is still below this lower limit, memory controller 110 will perform a garbage collection operation, collecting valid data from SLC blocks within static SLC region 310 and / or dynamic SLC region 320, and correspondingly writing the collected valid data to QLC blocks within QLC region 340 (i.e., performing an S2Q garbage collection operation), and / or collecting valid data from TLC blocks within TLC region 330, and correspondingly writing the collected valid data to QLC blocks within QLC region 340 (i.e., performing a T2Q garbage collection operation). In other words, in a performance-oriented strategy, the memory controller 110 will not immediately perform garbage collection once the number of available SLC blocks in the static SLC region 310 and / or the dynamic SLC region 320 falls below the lower limit, because garbage collection is time-consuming. Therefore, the memory controller 110 will prioritize other operations (e.g., prioritizing TLC direct writes or TLC-to-QLC direct conversions) to delay write performance degradation as much as possible before performing garbage collection.

[0064] In one embodiment, the memory controller 110 selects between a lifetime-oriented strategy and a performance-oriented strategy based on a wear condition indication value that reflects the wearing condition of the NV memory 120. In one embodiment, the memory controller 110 first selects the performance-oriented strategy to control the writing of the NV memory 120. If the wear condition indication value exceeds a predetermined threshold (meaning that the wear condition of the NV memory 120 is significant), the memory controller 110 selects the lifetime-oriented strategy. In the performance-oriented strategy, the memory controller 110 determines the wear condition indication value based on the maximum number of program / erase cycles (P / E cycles) of blocks in the dynamic SLC region 320, the maximum number of P / E cycles of blocks in the TLC region 330, and the maximum number of P / E cycles of blocks in the QLC region 340. Further, one P / E cycle for a particular block includes one erase operation (i.e., erasing data stored in all memory cells in the block) and writing data to each page in the block. In another embodiment, the memory controller 110 may further determine the wear status indication value based on the average P / E cycle count of blocks in the dynamic SLC region 320, the average P / E cycle count of blocks in the TLC region 330, and the average P / E cycle count of blocks in the QLC region 340. In one embodiment, the wear status indication value may be determined by the following formula: (DSLC_P / E)*f1+(TLC_P / E)*f2+(QLC_P / E). Wherein, "DSLC_P / E" can be the maximum (or average) P / E cycle count of blocks in the dynamic SLC region 320, "TLC_P / E" can be the maximum (or average) P / E cycle count of blocks in the TLC region 330, and "QLC_P / E" can be the maximum (or average) P / E cycle count of blocks in the QLC region 340. Furthermore, the weighting factors f1 and f2 can be any values ​​less than "1". This approach can ensure write performance (i.e., by selecting a performance-oriented strategy) while taking into account the wear and tear of the NV memory 120 (i.e., by selecting a lifetime-oriented strategy), thereby avoiding a decrease in the lifetime of the NV memory 120 due to excessive pursuit of performance.

[0065] Based on the above embodiments, the present invention provides a method for controlling a flash memory. Please refer to Figure 64, which shows a simplified flowchart of controlling a flash memory, including the following steps:

[0066] Step S301: Select a first strategy to configure the flash memory, and control the flash memory according to the first strategy; wherein, in the first strategy, a garbage collection operation will not be performed immediately once the number of available blocks in a specific region of the flash memory falls below a lower limit;

[0067] Step S302: Determine whether a wear status indicator value related to the flash memory exceeds a predetermined threshold; and

[0068] Step S303: If the wear status indication value exceeds the predetermined threshold, a second strategy is selected to configure the flash memory, and the flash memory is controlled according to the second strategy; wherein, in the second strategy, once the number of available blocks in the specific area of ​​the flash memory is lower than the lower limit, the garbage collection operation will be performed immediately.

[0069] Since the principles and specific details of the above steps have been described in detail in the previous embodiments, they will not be repeated here. It is worth mentioning that the above process can be improved by adding other additional steps or by making appropriate modifications and adjustments to specific steps to enhance the performance, durability, and reliability of the QLC flash memory. Such modifications should also be considered within the scope of this invention.

[0070] Embodiments of the present invention can be embodied as apparatus, method, or computer program product. Accordingly, embodiments of the present invention can take the form of an entity entirely implemented in hardware, an entity entirely implemented in software (including firmware, resident software, microcode, etc.), or an entity combining software and hardware aspects, which can be collectively referred to as a "module" or "system". Furthermore, embodiments of the present invention can take the form of a computer program product embodied in any tangible medium having computer-usable program code. In terms of hardware, the present invention can be implemented by applying any of the following technologies or related combinations: individual operational logic of logic gates capable of executing logic functions according to data signals, and application-specific integrated circuits (ASICs), programmable gate arrays (PGAs), or field-programmable gate arrays (FPGAs) having appropriate combinational logic.

[0071] Flowcharts and block diagrams illustrate the architecture, functionality, and operation of systems, methods, and computer program products that represent different possible implementations of embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of program code, including one or more executable instructions to implement a specific logical function. It should also be noted that each block in a block diagram and / or flowchart, as well as combinations of blocks in block diagrams and / or flowcharts, can be implemented by a special-purpose hardware infrastructure system, or a combination of special hardware and computer program instructions. These computer program instructions may be stored in readable computer media to command a computer or other programmable data processing device to operate in a specific manner so that the instructions stored in the readable computer media produce the functions / operations specified in the blocks or combinations of blocks in the flowcharts and / or block diagrams.

[0072] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

Claims

1. A method for controlling a flash memory, comprising: In response to one or more host write commands, host data associated with the one or more host write commands is written to a target block within a region of the flash memory in a one-shot programming manner, in a specific write mode; Perform a block reliability check on the target block to generate a block reliability indication; Based on the reliability indication of the block, select one of a direct conversion mode and a conversion mode based on garbage collection operations; as well as The target block is reconfigured based on the selected conversion mode.

2. The method as described in claim 1, characterized in that, The steps for performing storage unit hierarchy reconfiguration on the target block based on the selected conversion mode include: Read the lower page, middle page, and upper page data from the target block; Read a valid page of data from a source block that is different from the target block in the flash memory; as well as If the direct conversion mode is selected, then in quad-level cell (QLC) write mode, the next page data, middle page data, and previous page data in the target block, as well as the valid page data in the source block, are programmed into the target block in one programming pass.

3. The method as described in claim 1, characterized in that, The steps for performing storage unit hierarchy reconfiguration on the target block based on the selected conversion mode include: Read the next page data, the middle page data, and the previous page data from the target block; Read a valid page of data from a source block that is different from the target block in the flash memory; as well as If the garbage collection-based conversion mode is selected, then in QLC write mode, the next page data, middle page data, and previous page data in the target block, as well as the valid page data in the source block, are programmed into a target block of the flash memory that is different from the target block through two programming passes.

4. The method as described in claim 1, characterized in that, The steps for performing a reliability check on the target block include: A block reliability indication is generated based on whether the write temperature when writing data into the target block falls within a predetermined temperature range. A reliability indicator for the target block is generated based on whether the number of times the data within the target block has been read exceeds a predetermined threshold. A block reliability indicator is generated based on whether the block's lifetime since data was written to it has exceeded a predetermined block lifetime threshold. A reliability indicator for the block is generated based on whether a soft decoding operation was initiated during the reading of data within the target block. and / or A block reliability indicator is generated based on whether the number of read retries that occur while reading data within the target block exceeds a predetermined read retrieval threshold.

5. The method as described in claim 1, characterized in that, The steps for selecting either the direct conversion mode or the garbage collection-based conversion mode based on the block reliability indicator include: If the block reliability indicator suggests that the target block exhibits strong reliability, then the direct conversion mode is selected; and If the block reliability indicator suggests that the target block exhibits weak reliability, then the conversion mode based on garbage collection operations is selected.

6. The method as described in claim 1, characterized in that, The flash memory is a QLC flash memory, and the target block is a TLC block within a triple-level cell (TLC) region of the QLC flash memory; and within this TLC region, each cell is written with 3 bits of metadata.

7. A memory controller for use in a flash memory, comprising: A storage unit for storing a program code; A processing unit is configured to execute the program code to perform the following operations on the flash memory: In response to one or more host write commands, host data associated with the one or more host write commands is written to a target block within a region of the flash memory in a one-shot programming manner, in a specific write mode; Perform a block reliability check on the target block to generate a block reliability indication; Based on the reliability indication of the block, select one of a direct conversion mode and a conversion mode based on garbage collection operations; as well as The target block is reconfigured based on the selected conversion mode.

8. A data storage device comprising a memory controller as described in claim 7 and a flash memory.

9. A method for controlling a flash memory, comprising: Select a first strategy to configure the flash memory, and control the flash memory according to the first strategy; Determine whether a wear status indicator value related to the flash memory exceeds a predetermined threshold; and If the wear status indication value exceeds the predetermined threshold, a second strategy is selected to configure the flash memory, and the flash memory is controlled according to the second strategy. in, In the first strategy, a garbage collection operation will not be performed immediately once the number of available blocks in a specific region of the flash memory falls below a lower limit; while in the second strategy, a garbage collection operation will be performed immediately once the number of available blocks in the specific region of the flash memory falls below the lower limit.

10. The method as described in claim 9, characterized in that, The first strategy is a performance-oriented strategy, while the second strategy is a lifetime-oriented strategy.

11. The method as described in claim 10, characterized in that, The steps for selecting the first strategy to configure the flash memory include: The flash memory is configured to include at least: a first region having a plurality of first type blocks, a second region having a plurality of first type blocks, a third region having a plurality of second type blocks, and a fourth region having a plurality of third type blocks; as well as If the number of available blocks of the first type is less than a lower limit, then data is written to the plurality of second type blocks in the third region in a one-time programming manner, without performing the garbage collection operation.

12. The method as described in claim 11, characterized in that, The wear status indicator value is determined by a weighted sum of the following values: the maximum number of program / erase cycles (P / E cycles) for the first type of block in the second region, the maximum number of P / E cycles for the second type of block in the third region, and the maximum number of P / E cycles for the third type of block in the fourth region.

13. The method as described in claim 12, characterized in that, The first type of block in the second region is an SLC block in a dynamic single-level cell (SLC) region, the second type of block in the third region is a TLC block in a TLC region, and the third type of block in the fourth region is a QLC block in a QLC region.

14. The method as described in claim 10, characterized in that, The steps for selecting the second strategy to configure the flash memory include: The flash memory is configured to include at least: a first region having a plurality of first-type blocks and a second region having a plurality of second-type blocks; and If the number of available blocks of the first type is less than a lower limit, the garbage collection operation is performed before writing data to the first type blocks in the first region, so as to move the valid data in the first type blocks in the first region to the second type blocks in the second region.

15. A memory controller for use in a flash memory, comprising: A storage unit for storing a program code; A processing unit is configured to execute the program code to perform the following operations on the flash memory: Select a first strategy to configure the flash memory, and control the flash memory according to the first strategy; Determine whether a wear status indicator value related to the flash memory exceeds a predetermined threshold; and If the wear status indication value exceeds the predetermined threshold, a second strategy is selected to configure the flash memory, and the flash memory is controlled according to the second strategy. in, In the first strategy, a garbage collection operation will not be performed immediately once the number of available blocks in a specific region of the flash memory falls below a lower limit; while in the second strategy, a garbage collection operation will be performed immediately once the number of available blocks in the specific region of the flash memory falls below the lower limit.

16. A data storage device comprising a memory controller as described in claim 16 and a flash memory.

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