Data path architecture with generalized parallel paradigms

Abstract

The invention relates to a data path architecture with generalized parallel paradigms. A method includes identifying a logical address of a logical address space; translating the logical address into a set of physical addresses of a physical address space by using a set of translation functions, the set of translation functions includes a location address translation function that translates the logical address to a location address in the set of physical addresses based on a cardinal number of a set of data cache segments and translates the logical address to a location address in the set of physical addresses based on the cardinal number of the set of data cache segments a segment address translation function of the segment address; and using the location address and the segment address to cause the set of data cache segments to process a set of media access operations in parallel, each media access operation of the set of media access operations corresponding to a respective data cache segment of the set of data cache segments.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to memory subsystems, and more specifically, to data path architectures with a generalized parallel paradigm. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] Embodiments of this disclosure provide a memory device comprising: a memory array; and processing logic operatively coupled to the memory array to perform operations including: identifying logical addresses in a logical address space; translating the logical addresses into a set of physical addresses in a physical address space using a set of translation functions, the set of translation functions including a location address translation function that translates the logical addresses into location addresses in the set of physical addresses based on a radix of a set of data cache segments, and a segment address translation function that translates the logical addresses into segment addresses in the set of physical addresses based on the radix of the set of data cache segments; and using the location addresses and the segment addresses to cause the set of data cache segments to process in parallel a set of media access operations, each media access operation in the set of media access operations corresponding to a corresponding data cache segment in the set of data cache segments.

[0004] Another embodiment of this disclosure provides a method comprising: identifying a logical address in a logical address space by a processing device; translating the logical address into a set of physical addresses in a physical address space by the processing device using a set of translation functions, the set of translation functions including a location address translation function that translates the logical address into a location address in the set of physical addresses based on a radix of a set of data cache segments and a segment address translation function that translates the logical address into a segment address in the set of physical addresses based on the radix of the set of data cache segments; and using the location address and the segment address to cause the set of data cache segments to process a set of media access operations in parallel, each media access operation in the set of media access operations corresponding to a corresponding data cache segment in the set of data cache segments.

[0005] Another embodiment of this disclosure provides a non-transitory computer-readable storage medium including instructions that, when executed by a processing device, cause the processing device to perform operations including: identifying logical addresses in a logical address space; translating the logical addresses into a set of physical addresses in a physical address space using a set of translation functions, the set of translation functions including a location address translation function that translates the logical addresses into location addresses in the set of physical addresses based on a radix of a set of data cache segments and a segment address translation function that translates the logical addresses into segment addresses in the set of physical addresses based on the radix of the set of data cache segments; and using the location addresses and the segment addresses to cause the set of data cache segments to process a set of media access operations in parallel, each media access operation in the set of media access operations corresponding to a corresponding data cache segment in the set of data cache segments. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are for explanation and understanding only.

[0007] Figures 1A to 2C This is a diagram of an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figures 3A to 3B This is a diagram illustrating an instance data path architecture with a generalized parallel paradigm according to some embodiments of the present disclosure.

[0009] Figure 4 This is a diagram illustrating instance mappings between physical address spaces and logical address spaces according to some embodiments of the present disclosure.

[0010] Figure 5 This is a flowchart of an example method for implementing a data path architecture with a generalized parallel paradigm, according to some embodiments of this disclosure.

[0011] Figure 6 This is a block diagram of an example computer system in which embodiments of this disclosure may be operated. Detailed Implementation

[0012] This disclosure relates to a data path architecture with a generalized parallel paradigm. The memory subsystem may be a storage device, a memory module, or a combination of a storage device and a memory module. The following is combined with… Figures 1A to 2CDescribe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0013] The memory subsystem may include a high-density non-volatile memory device in which data is expected to be retained when no power is supplied. One example of a non-volatile memory device is a NAND flash memory device. Other examples of non-volatile memory devices are described below. Figures 1A to 2C Describe it. A non-volatile memory device is a package of one or more dies. Each die may contain one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane contains a set of physical blocks. Each block contains a set of pages. Each page contains a set of memory cells. A memory cell is an electronic circuit that stores information. Depending on the type of memory cell, a memory cell may store one or more bits of binary information and has various logic states related to the number of bits stored. Logic states may be represented by binary values ​​such as "0" and "1" or combinations of such values.

[0014] The memory subsystem may include an interface between the memory subsystem controller and one or more memory devices, which can handle multiple different signals related to communication with the memory devices. The interface may utilize a set of command pins to implement an interface protocol.

[0015] Media access operation (e.g., read and / or write) performance can be improved by increasing the data transfer speed of the input / output (I / O) interface across memory devices (e.g., NAND flash devices). To improve data transfer speed, media access operations can be performed in parallel. For example, a data cache (which may contain page buffers and / or registers) can be divided into multiple segments that can be accessed (e.g., read and / or write) almost simultaneously in parallel. The size of a data cache segment can depend on the page size of the memory device. For example, if a page is a 16-kilobyte (KB) page, then each segment of the data cache can be 16 / N KB in size, where N is the number of segments. Each segment of the data cache can be assigned to the data (DQ) bus to handle the corresponding media access operation. Operation timing is defined as the product of the number of data cache segments (N) and the I / O interface data transfer speed (e.g., I / O interface data cycle). Operation timing can be directly related to the number of data cache segments.

[0016] The physical address space refers to the range of locations within a memory device that can be directly accessed by the memory device. A set of physical addresses in the physical address space defines the location of a data item. For example, a physical address set may contain segment addresses and location addresses. The segment address specifies the segment within which the data item is located, and the location address specifies the location of the data item within the segment.

[0017] The logical address space refers to the range of addresses used by components outside the memory device (such as the CPU, I / O controller, and peripheral devices) to communicate with the memory device. For example, when an external component requests access to the location of the memory device, it provides a logical address. The controller can then translate the logical address into a physical address.

[0018] Media access operations (such as reading, programming, or erasing) can be performed in response to commands. Commands can specify the type of operation and the command address. The command address can include the block address identifying the block in which the operation will be performed and the page address identifying the page within that block.

[0019] A page can be divided into positions called columns. For some media access operations, the command address may further include the column address of the position within the page in which the media access operation will begin. For example, a column address can be used to specify a position within the page to begin writing to or programming the page (e.g., partial page programming). As another example, a column address can be used to specify the position of a data item on the page to begin reading the page.

[0020] For an 8-bit interface, page data items are bytes, and each column address references the corresponding byte of the page. For example, for a 2 kilobyte (KB) page containing 2048 bytes using an 8-bit interface, there are 2048 possible column addresses, each referencing the corresponding byte of the page. It takes 11 bits to represent all possible column addresses within a 2KB page using an 8-bit interface (2^32 KB). 11 = 2048 bytes). As another example, for a 16KB page containing 16,384 bytes using an 8-bit interface, the page has 16,384 possible column addresses, where each column address references the corresponding byte of the page. 14 bits are needed to represent all possible column addresses within a 16KB page using an 8-bit interface (2^32 bytes). 14 =16,384 bytes).

[0021] For a 16-bit interface, a page's data item is a word defined by 2 bytes of data, and each column address references the corresponding word in the page. For example, for a 2KB page using a 16-bit interface, the page has 1024 possible column addresses, each referencing a corresponding word in the page. It takes 10 bits to represent all possible column addresses within a 2KB page using a 16-bit interface (2^25 bytes). 10= 1024 words). As another example, for a 16KB page using a 16-bit interface, the page has 8,192 possible column addresses, where each column address references a corresponding word in the page. 13 bits are needed to represent all possible column addresses within a 16KB page using a 16-bit interface (2^32 bits). 13 =8,192 bytes).

[0022] More specifically, the column address identifies the starting data item (e.g., byte or word) within the page from which a media access operation will begin. For example, for an 8-bit interface, column address 512 could indicate that the starting position of a media access operation performed on a page is the 512th bit of the page. As another example, for a 16-bit interface, column address 512 could indicate that the starting position of a media access operation performed on a page is the 512th word of the page.

[0023] For example, a column address can be a k-bit column address represented by CA[k-1:0], where CA represents the column address and [k-1:0] indicates the bit range. This means that the address bus used to hold the column address has k lines, labeled from k-1 to 0. More specifically, "k-1" refers to the most significant bit of the bit range and "0" represents the least significant bit of the bit range. A k-bit column address can support 2^k bits. k A possible unique column address. The type of memory interface (8-bit, 16-bit, etc.) can be used to determine how much data a single column address points to. In some implementations, the column address is a 15-bit column address represented by CA[14:0] (k=15). In these implementations, 32,768 possible unique column addresses are supported.

[0024] The segment address of a page's data item (e.g., a byte or word) can be represented by CA[m-1:0]. The location address of a page's data item can be represented by CA[k-1:m]. In these implementations, the number m is determined to be the base-2 logarithm of N (m = x).

[0025] Typically, the number of data cache segments (N) is a fixed number that is a power of 2 (e.g., N = 2). x (where x is a positive integer). That is, the number of data cache segments can be increased by doubling the previous number of data cache segments. Due to the exponential growth caused by doubling, implementing this power-of-2 parallel paradigm can lead to inefficient use of resources, which can make it difficult or impossible to implement the corresponding data path architecture to handle the number of data cache segments.

[0026] For example, suppose the data path architecture is designed to process 32 data cache segments in parallel (N=32). In the power-of-two parallel paradigm, the only way to increase the number of data cache segments that can be processed in parallel is by designing a data path architecture that processes 64 data cache segments in parallel. However, due to cost and / or on-chip footprint constraints, implementing this data path architecture may be impractical or impossible.

[0027] Additionally, engineers may want to design a data path architecture that achieves the minimum operational processing speed, achievable by parallelizing a number of data cache segments that are not powers of 2. For example, suppose an engineer wants to design a data path architecture that achieves a target operational processing speed, which can be achieved by parallelizing a number of data cache segments that are not powers of 2 (e.g., 40 data cache segments). Under the constraint of the power-of-2 parallel paradigm, the minimum data path architecture that can be used to achieve the target operational processing speed is one designed to parallelize 64 data cache segments (because the operational processing speed achievable by a data path architecture designed to parallelize 32 data cache segments would be less than the target). However, compared to a theoretical data path architecture designed to parallelize fewer than 64 data cache segments (e.g., 40 data cache segments) that could achieve the target operational processing speed, a data path architecture designed to parallelize 64 data cache segments would occupy a larger amount of chip surface area than required. Therefore, the power-of-2 parallel paradigm can cause memory device performance bottlenecks and / or inefficient data path architecture design.

[0028] This disclosure addresses the aforementioned and other drawbacks by implementing a data path architecture with a generalized parallel paradigm. The implementations described herein can be used to design data path architectures that extend parallelism to any positive integer N (e.g., not limited to powers of 2). That is, the data cache can be divided into N data cache segments, where N is not limited to a power of 2. The number N can be chosen to balance operation processing speed, depending on the size of the memory device architecture. For example, it can be determined that the data path architecture can be designed to process a number of data cache segments that are not powers of 2 in parallel to achieve the target operation processing speed. Assume that the number of data cache segments that are not powers of 2 is 40 (N = 40). Instead of using a data path architecture designed to process 64 data cache segments in parallel under a power-of-2 parallel paradigm as described above, a more efficient data path architecture that can process 40 data cache segments in parallel to achieve the target operation processing speed can be designed using the generalized parallel paradigm described herein.

[0029] As mentioned above, the segment address of a page's data item (e.g., a byte or word) can be represented by CA[m-1:0], and the location address of a page's data item can be represented by CA[k-1:m]. To implement a data path architecture with a generalized parallel paradigm, instead of defining m as the base-2 logarithm of N, m can be defined as the smallest integer greater than or equal to the base-2 logarithm of N. This can be achieved by... It indicates. Among them. This is the floor function. Although data items (such as bytes or words) can be addressed by determining m in this way, doing so introduces discontinuities ("holes") in the column address mapping of the physical address space when N is not a power of 2. Discontinuities reflect the absence of data items (such as bytes or words).

[0030] To address such discontinuities, the local media controller of the memory device can use a set of translation functions to translate logical addresses in the logical address space into a set of physical addresses in the physical address space for data items (e.g., bytes or words). For example, the translation function set might contain location address translation functions that translate logical addresses into location addresses within the physical address set. As another example, the translation function set might further contain segment address translation functions that translate logical addresses into segment addresses within the physical address space. Therefore, the translation function set is the set of translation functions that enables the power-of-two parallel paradigm to be extended to a generalized parallel paradigm. Further details regarding the implementation of a data path architecture with a generalized parallel paradigm will be referenced below. Figures 1A to 6 describe.

[0031] The advantages of this disclosure include, but are not limited to, improved memory device performance and resource efficiency. For example, the embodiments described herein can increase data path speed and input / output (I / O) data rate while maintaining a smaller device footprint.

[0032] Figure 1A This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0033] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0034] The computing system 100 may be, for example, a desktop computer, a laptop computer, a web server, a mobile device, a vehicle (e.g., an airplane, drone, train, car or other means of transport), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer contained in a vehicle, industrial equipment or networked commercial device), or a computing device containing memory and processing devices.

[0035] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to multiple memory subsystems 110 of different types. Figure 1A This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediary component), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0036] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include (but are not limited to) Serial Advanced Technology Attachment (SATA) interfaces, Compute Fast Link (CXL) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Double Data Rate (DDR) memory buses, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM slot interfaces supporting Double Data Rate (DDR)), etc. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus or a CXL bus), host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1A For example, memory subsystem 110 is described. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple individual communication connections, and / or a combination of communication connections.

[0037] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller, a CXL controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and to read data from the memory subsystem 110.

[0038] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (such as memory device 140) may be (but are not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0039] Some examples of non-volatile memory devices (such as memory device 130) include NAND flash memory and in-situ write memory, such as three-dimensional cross-point (“3D cross-point”) memory devices, which are cross-point arrays of non-volatile memory cells. Cross-point arrays of non-volatile memory cells can perform bit storage based on volume resistance variations combined with stackable cross-gate format data access arrays. Furthermore, compared to many flash-based memories, cross-point non-volatile memories can perform in-situ write operations, where non-volatile memory cells can be programmed without prior erasing of the non-volatile memory cells. NAND flash memories include, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0040] Memory device 130 may include one or more arrays of memory cells. For example, one type of memory cell, such as a single-level memory cell (SLC), may store one bit per memory cell. Other types of memory cells, such as multi-level memory cell (MLC), three-level memory cell (TLC), four-level memory cell (QLC), and five-level memory cell (PLC), may store multiple bits per memory cell. In some embodiments, each of memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include SLC portions and MLC portions, TLC portions, QLC portions, or PLC portions of memory cells. Memory cells of memory device 130 may be grouped into pages, which may refer to logical units of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0041] Although a non-volatile memory component such as NAND flash memory (e.g., 2D NAND, 3D NAND) has been described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0042] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-coded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0043] The memory subsystem controller 115 may include processing means configured to execute instructions stored in local memory 119, including one or more processors (e.g., processor 117). In the illustrative example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines for controlling the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0044] In some embodiments, local memory 119 may include memory registers for storing memory pointers, fetch data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although already... Figure 1A The instance memory subsystem 110 is described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0045] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, discard item collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0046] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive and decode addresses from the memory subsystem controller 115 to access the memory device 130.

[0047] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 includes a managed memory device comprising the original memory device 130 having on-die control logic (e.g., local media controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0048] Memory subsystem 110 includes a Data Path Architecture Parallel (DAP) component 137 for implementing a data path architecture with a generalized parallel paradigm. In some embodiments, local media controller 135 includes at least a portion of DAP component 137 and is configured to perform the functionality described herein. In some embodiments, memory subsystem controller 115 includes at least a portion of DAP component 137. In some embodiments, DAP component 137 is part of host system 120, an application, or an operating system. Further details regarding DAP component 137 and the implementation of a data path architecture with a generalized parallel paradigm will be referenced below. Figures 1B to 5 describe.

[0049] Figure 1B It is a present memory subsystem according to an embodiment (e.g.) Figure 1A A simplified block diagram of a first device in the form of a memory device 130 communicating with a second device in the form of a memory subsystem controller 115 (of memory subsystem 110). Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, game consoles, home appliances, vehicles, wireless devices, mobile phones, and the like. The memory subsystem controller 115 (e.g., a controller external to memory device 130) may be a memory controller or other external host device.

[0050] Memory device 130 includes a memory cell array 104 logically arranged in rows and columns. Memory cells in logical rows are connected to the same access line (e.g., a word line), while memory cells in logical columns are selectively connected to the same data line (e.g., a bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in memory cell array 104 ( Figure 1B (Not shown in the text) It can be programmed to one of at least two target data states.

[0051] Row decoding circuitry 108 and column decoding circuitry 112 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 130 also includes input / output (I / O) control circuitry 160 for managing commands, addresses, and data input to and from memory device 130 and data and status information output from memory device 130. Address register 114 communicates with I / O control circuitry 160, row decoding circuitry 108, and column decoding circuitry 112 to latch address signals before decoding. Command register 124 communicates with I / O control circuitry 160 and local media controller 135 to latch incoming commands.

[0052] A controller (e.g., a local media controller 135 within memory device 130) controls access to memory cell array 104 in response to commands and generates status information for external memory subsystem controller 115. Specifically, the local media controller 135 is configured to perform access operations (e.g., read operations, programming operations, and / or erase operations) on memory cell array 104. The local media controller 135 communicates with row decoding circuitry 108 and column decoding circuitry 112 to control them in response to addresses. In one embodiment, the local media controller 135 includes a DAP component 137 that can perform defect detection as described herein during an erase operation on memory device 130.

[0053] The local media controller 135 also communicates with cache register 118. Cache register 118, guided by the local media controller 135, latches incoming or outgoing data to temporarily store data while the memory cell array 104 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 118 to data register 170 for transfer to the memory cell array 104; subsequently, new data can be latched from I / O control circuitry 160 into cache register 118. During read operations, data can be transferred from cache register 118 to I / O control circuitry 160 for output to memory subsystem controller 115; subsequently, new data can be transferred from data register 170 to cache register 118. Cache register 118 and / or data register 170 may form a page buffer for memory device 130 (e.g., may form part of said page buffer). The page buffer may further include sensing means for sensing the data state of the memory cells, for example, by sensing the state of the data lines connected to the memory cell array 104. Figure 1B(Not shown in the image). Status register 122 can communicate with I / O control circuitry 160 and local media controller 135 to latch status information for output to memory subsystem controller 115.

[0054] The memory device 130 enables the local media controller 135 to receive control signals from the memory subsystem controller 115 via control link 132. For example, the control signals may include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protect signal WP#. Additional or alternative control signals (not shown) may be further received via control link 132 depending on the nature of the memory device 130. In one embodiment, the memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from the memory subsystem controller 115 via a multiplexed input / output (I / O) bus 136 and outputs data to the memory subsystem controller 115 via the I / O bus 136.

[0055] For example, a command can be received at I / O control circuitry 160 via I / O pins [7:0] of I / O bus 136 and then written to command register 124. An address can be received at I / O control circuitry 160 via I / O pins [7:0] of I / O bus 136 and then written to address register 114. Data can be received at I / O control circuitry 160 via I / O pins [7:0] of 8-bit device or I / O pins [15:0] of 16-bit device and then written to cache register 118. The data can then be written to data register 170 for programming memory cell array 104.

[0056] In this embodiment, cache register 118 may be omitted and data may be written directly to data register 170. Data may also be output via input / output (I / O) pins [7:0] of an 8-bit device or input / output (I / O) pins [15:0] of a 16-bit device. Although references may be made to I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that provide electrical connections to memory device 130 via external devices, such as memory subsystem controller 115.

[0057] Those skilled in the art should understand that additional circuitry and signals can be provided, and have been simplified. Figures 1A to 1B The memory device 130. It should be understood that, reference Figures 1A to 1BThe functionality of the various block components described is not necessarily separated into different components or component sections of an integrated circuit device. For example, a single component or component segment of an integrated circuit device can be adapted to perform... Figures 1A to 1B The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figures 1A to 1B The functionality of a single block component. Additionally, while specific I / O pins have been described according to popular conventions for receiving and outputting various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0058] Figure 2A This is a diagram of a system 200 according to some embodiments of the present disclosure. For example, system 200 may correspond to... Figure 1A The memory subsystem 110. As shown, system 200 includes... Figures 1A to 1B The memory subsystem controller 115 and a plurality of dies 210-1 to 210-N. The number of dies N should not be considered a limitation. In some embodiments, each of dies 210-1 to 210-N is contained in the same memory device (e.g., Figures 1A to 1B In some embodiments, at least one of dies 210-1 to 210-N is included in a first memory device and at least one of dies 210-1 to 210-N is included in a second memory device different from the first memory device.

[0059] Die 210-1 includes CA circuit system 212 and DQ circuit system 214. Although only die 210-1 is shown, each of the other dies 210-2 to 210-N may contain CA circuit systems and DQ circuit systems similar to CA circuit system 212 and DQ circuit system 214, respectively. Further details regarding CA circuit system 212 and DQ circuit system 214 will be referenced below. Figures 2B to 2C describe.

[0060] System 200 may further include at least one CE# pin 220 connected to dies 210-1 to 210-N via one or more conductive lines. At least one CE# pin 220 may be used to transmit a CE# signal from memory subsystem controller 115 to dies 210-1 to 210-N. For example, for each of dies 210-1 to 210-N, the CE# signal may be received by the corresponding CA circuitry system. That is, only the CA circuitry system of the die may be enabled by the CE# signal.

[0061] System 200 may further include a CA bus 230. The CA bus 230 can be used to transfer command transactions from the memory subsystem controller 115 to the corresponding CA circuitry systems (e.g., CA circuitry system 212 of die 210-1) of dies 210-1 to 210-N. The CA bus 230 is an m-bit bus, which can be represented by CA[m-1:0], where “m-1” represents the most significant bit of the range of m bits and “0” represents the least significant bit of the range of m bits. In some embodiments, the CA bus 230 is a 2-bit bus, which can be represented by CA[1:0].

[0062] System 200 may further include a DQ bus 240. The DQ bus 240 can be used to transfer data transactions from the memory subsystem controller 115 to the corresponding DQ circuitry systems (e.g., DQ circuitry system 214 of die 210-1) of dies 210-1 to 210-N. The DQ bus 240 is an n-bit bus, which can be represented by DQ[n-1:0], where “n-1” represents the most significant bit of a range of n bits and “0” represents the least significant bit of a range of n bits. In some embodiments, the DQ bus 240 is an 8-bit bus, which can be represented by DQ[7:0].

[0063] Figures 2B to 2C This is a diagram of bare die 210-1 according to some embodiments of this disclosure. (See diagram for example.) Figure 2B As shown, the CA circuit system 212 may include components including a CA pin 250 for receiving commands from the CA bus, a CE pin 252 for receiving CE signals, a receiver (Rx) analog circuit 254, an Rx digital circuit 256, a transmitter (Tx) analog circuit 258, a Tx digital circuit 260, and a command state machine and register 262. For example, the Rx analog circuit 254 may be implemented by an Rx 255 and one or more amplifiers, one or more voltage generators, and one or more analog-to-digital converters (not shown). The Rx digital circuit 256 may be implemented by one or more buffers, one or more latches, and combinational logic. The Tx analog circuit 258 may be implemented by a Tx 259 and one or more digital-to-analog converters, one or more voltage level shifters, and one or more voltage generators (not shown). The Tx digital circuit 260 may be implemented by one or more buffers, one or more latches, and combinational logic. The command state machine and register 262 can generate Rx control signal 264 for controlling Rx 255, Tx control signal 266 for controlling Tx 259 and / or DQ circuit system control signal 268 for controlling DQ circuit system 214 (e.g., controlling the state of DQ circuit system 214).

[0064] like Figure 2CAs shown, the DQ circuit system 214 may include components including a DQ pin 270 for receiving commands via the DQ bus, an Rx analog circuit 272, an Rx digital circuit 274, a Tx analog circuit 276, and a Tx digital circuit 278. For example, the Rx analog circuit 272 may be implemented using an Rx 273 and one or more amplifiers, one or more voltage generators, and one or more analog-to-digital converters (not shown). The Rx digital circuit 274 may be implemented using one or more buffers, one or more latches, and combinational logic. The Tx analog circuit 276 may be implemented using a Tx 277 and one or more digital-to-analog converters, one or more voltage level shifters, and one or more voltage generators (not shown). The Tx digital circuit 278 may be implemented using one or more buffers, one or more latches, and combinational logic. A DQ circuit system control signal 268 can be used to control the operation of one or more of the circuits 272 to 278 to control the state of the DQ circuit system 214. Rx digital circuit 274 and Tx digital circuit 278 can communicate with memory array 280 to cause data to be written to memory array 280 and / or cause data to be read from memory array 280.

[0065] Figures 3A to 3B This is a diagram illustrating an example data path architecture (“architecture”) 300 according to some embodiments of the present disclosure. Architecture 300 includes a data cache 310. In this example, architecture 300 is implementing N-degree of parallelism, where N is a positive integer. The data cache is divided into N segments 312-1 to 312-N. For example, an I / O control circuitry system (e.g., Figure 1B The I / O control circuitry system 160 can divide the data cache into N segments 312-1 to 312-N. The architecture may further include N secondary sense amplifiers (SSAs) 320, a DQ bus 330, a deserializer 340, and a column counter 350. Primary sense amplifiers (PSAs) (not shown) can be used to read data from the memory array, while the SSAs in the SSAs 320 can be used to read data from the PSAs. In some implementations, the SSAs include latches. For example, the latches may include a pair of cross-coupled inverters. The DQ 330 bus may have a width of 8N.

[0066] The location address of a data item (e.g., a byte or a word) within each of the N segments 312-1 to 312-N can be represented by CA[k-1:m], and the segment address where the data item is located can be represented by CA[m-1:0]. As described above, while data items (e.g., bytes or words) can be addressed by determining m in this way, doing so introduces discontinuities (“holes”) in the column address mapping of the physical address space when the number of segments (N) in the data cache is not a power of 2. Discontinuities reflect the absence of data items (e.g., bytes or words). The instance mapping between the physical and logical address spaces that introduces discontinuities will now be referenced below. Figure 4 describe.

[0067] Figure 4 Figure 400A illustrates an example column address mapping from addresses in physical address space 410 to columns in logical address space 420 according to some embodiments of this disclosure. As shown, a group of N addresses in physical address space 410 can be mapped to corresponding columns in logical address space 420. For example, N addresses 412 containing 0 to N-1 can be mapped to column 422, N addresses 414 containing N to 2N-1 can be mapped to column 424, and so on. If N is not a power of 2 (e.g., 2, 4, 8, 16, 32, ...), then discontinuities (e.g., gaps) can be introduced in the column address mapping.

[0068] Return to reference Figures 3A to 3B In order to solve such discontinuities (e.g.) Figure 4 The discontinuity shown in the figure), the local media controller of the memory device (e.g. Figures 1A to 1B The local media controller 135 can use a set of translation functions to remove discontinuities (by hiding them from the logical address space). More specifically, the set of translation functions is designed to translate addresses between the physical and logical address spaces in a manner that removes discontinuities in the physical address space when mapping to the corresponding address in the logical address space. Therefore, the logical address space is a contiguous address space.

[0069] For example, a translation function group may contain segment address translation functions, which define segment address translations between the logical address of a data item in the logical address space and the corresponding segment address of the data item in the physical address space. As another example, a translation function group may contain location address translation functions, which define location address translations between the logical address of a data item (e.g., a byte or word) in the logical address space and the location address of the data item in the physical address space. Address translations (e.g., segment address translations and location address translations) can be sent to the I / O control circuitry (e.g.,... Figure 1B (I / O control circuitry system 160). After using the translation function set, the column counter 350 can be initialized based on the translation to count the number of clock pulses or cycles.

[0070] For example, the segment address that identifies the location of a data item (e.g., a byte or word) within a page of the physical address space can be represented by CA[m-1:0], and the location address that identifies the position of a data item within that segment can be represented by CA[k-1:m]. As described above. In some implementations, k = 15. The logical address can be determined by Addr. log This indicates, for example, Addr log It can be the value of a data item (e.g., a byte or a word) in the referenced page (e.g., the value 132 refers to the 132nd data item in the referenced page).

[0071] The segment address translation function in the translation function group defines the segment address as the remainder of the quotient of the logical address divided by the number of segments (N) of the data cache. If the logical address is divisible by N (i.e., N is a factor of the logical address), then the location address translation function in the translation function group defines the location address as the quotient of the logical address divided by N; or if the logical address is not divisible by N (i.e., N is not a factor of the logical address), then the location address is defined as the non-fractional part of the quotient of the logical address divided by N. For example, the translation function group may contain:

[0072] CA[m-1:0] = Addr log mod(N)(1)

[0073] CA[k-1:m] = trunc(Addr log / N)(2)

[0074] Equation (1) is the segment address translation function, where mod(N) is the function that makes Addr... log The remainder when divided by N returns the modulo function. Equation (2) is the location address translation function, where trunc() removes Addr. log The decimal part of / N is truncated (e.g., rounding the input value down to the nearest smallest integer), and "=" is the assignment operator in equations (1) and (2) that translates the logical address into the corresponding segment and location address of the physical address space. As an illustrative example, assume N = 40, m = 6, k = 15 and Addr log =132. Using equation (1), CA[5:0] = 132 mod 40 = 12. Using equation (2), CA[14:5] = trunc(132 / 40) = trunc(3.3) = 3. That is, the segment address identifies the segment as segment 12, and the location address identifies the location within segment 13 as location 3.

[0075] Figure 5This is a flowchart of an example method 500 for implementing a data path architecture with a generalized parallel paradigm, according to some embodiments of the present disclosure. Method 500 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 500 is performed by… Figures 1A to 1B The local media controller 135 is executed.

[0076] At operation 510, the logical address is identified. For example, the processing logic can identify the logical address in the logical address space.

[0077] At operation 520, a logical address is translated into a set of physical addresses. For example, processing logic can translate a logical address into a set of physical addresses in the physical address space using a set of translation functions. The physical address set may correspond to a data item (e.g., a byte or a word). For example, the translation function set may contain location address translation functions that translate a logical address into a location address within the physical address set. As another example, the translation function set may further contain segment address translation functions that translate a logical address into a segment address within the physical address set. The location address may specify the location of a data item (e.g., a byte or a word) within a set of data cache segments in the data cache, and the segment address may specify the data cache segment. For example, the data cache may correspond to a page buffer region.

[0078] More specifically, the location address translation function can translate a logical address into a location address within a physical address set based on the radix of a set of data cache segments, and the segment address translation function can translate a logical address into a segment address within a physical address set based on the radix of a set of data cache segments. In some implementations, the location address is represented by CA[k-1:m], where k is the bit value. And N is the base of the data cache segment group. In some implementations, the segment address is represented by CA[m-1:0]. In some implementations, the location address translation function defines the location address as the remainder equal to the logical address divided by the base of the data cache segment group. In some implementations, the segment address translation function defines the segment address as the truncated value equal to the logical address divided by the base of the data cache segment group.

[0079] At operation 530, a group of media access operations is processed in parallel. For example, the processing logic can use location addresses and segment addresses to enable the data cache segment group to process the media access operation group in parallel (e.g., simultaneously or nearly simultaneously).

[0080] In some implementations, the cardinality of the data cache segment group is not a power of 2. That is, the data cache can be divided into a number of segments that define the data cache segment group as a non-power of 2. In these implementations, the translation between logical addresses and corresponding physical address groups (e.g., the translation performed at operation 520) can be used to efficiently remove any discontinuities that may exist in the resulting column address mapping between the physical address space and the logical address space. Thus, the translation enables the implementation of a data path architecture with a non-power of 2 degree of parallelism. Further details regarding operations 510 to 530 are referenced above. Figures 3A to 4 describe.

[0081] Figure 6 The computer system 600 describes an example machine within which a set of instructions can be executed to cause the machine to perform any or more of the methodologies discussed herein. In some embodiments, the computer system 600 may correspond to a host system (e.g., Figure 1A The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., a memory subsystem). Figure 1A The memory subsystem 110) or can be used to perform controller operations (e.g., to execute an operating system to perform operations corresponding to...). Figure 1A (Operation of DAP component 137). In alternative embodiments, the machine may connect (e.g., network) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0082] A machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by the machine. Furthermore, while a single machine is described, the term "machine" should also be considered as any collection of machines that individually or jointly execute a set (or more) of instructions to perform any or more of the methodologies discussed herein.

[0083] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM)) etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM) etc.) and a data storage system 618, which communicate with each other via a bus 630.

[0084] Processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, central processing unit, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or multiple processors implementing combinations of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 for communication via network 620.

[0085] Data storage system 618 may include machine-readable storage medium 624 (also referred to as computer-readable medium) thereon storing one or more sets of instructions 626 or software embodying any or more of the methodologies or functions described herein. Instructions 626 may also reside wholly or at least partially within main memory 604 and / or processing device 602 during execution by computer system 600, which also constitute machine-readable storage medium. Machine-readable storage medium 624, data storage system 618, and / or main memory 604 may correspond to... Figure 1A The memory subsystem 110.

[0086] In one embodiment, instruction 626 includes instructions for implementing a component corresponding to the DAP (e.g., Figure 1A The DAP component 137) contains functional instructions. Although the machine-readable storage medium 624 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered as a single medium or multiple media containing one or more sets of instructions. The term "machine-readable storage medium" should also be considered as any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any or more of the methodologies of this disclosure. Therefore, the term "machine-readable storage medium" should be considered as including (but not limited to) solid-state memory, optical media, and magnetic media.

[0087] Some parts of the foregoing detailed description have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Algorithms are generally conceived here as self-consistent sequences of operations that lead to desired results. Operations are operations that require the physical manipulation of physical quantities. Usually, but not always, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has proven convenient, sometimes primarily for common reasons, to refer to these signals as bits, values, elements, symbols, characters, items, numbers, or the like.

[0088] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels for application to those quantities. This disclosure may relate to the operation and processes of a computer system or similar electronic computing device that manipulate and transform data representing physical (electronic) quantities in the registers and memories of the computer system into other data similarly represented in the memory or registers of the computer system or other such information storage systems.

[0089] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0090] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used in conjunction with the teachings herein, or it can be demonstrated that it is convenient to construct more specialized devices to perform the methods. The structures of various such systems will be presented as set forth in the appended claims. Furthermore, this disclosure is not described with reference to any particular programming language. It should be understood that various programming languages ​​can be used to implement the teachings of this disclosure described herein.

[0091] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any means for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0092] In the foregoing description, embodiments of the present disclosure have been described with reference to specific examples. It should be understood that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the specification and drawings should be regarded as illustrative rather than limiting.

Claims

1. A memory device comprising: Memory array; and Processing logic, which is operatively coupled to the memory array to perform operations including: Identify logical addresses within the logical address space; A set of translation functions is used to translate the logical address into a set of physical addresses in the physical address space. The set of translation functions includes a location address translation function that translates the logical address into a location address within the set of physical addresses based on the radix of a set of data cache segments, and a segment address translation function that translates the logical address into a segment address within the set of physical addresses based on the radix of the set of data cache segments; and The location address and the segment address are used to enable the set of data cache segments to process a set of media access operations in parallel, wherein each media access operation in the set of media access operations corresponds to a corresponding data cache segment in the set of data cache segments.

2. The memory device of claim 1, wherein the location address specifies the location of a data item within a data cache segment of the set of data cache segments, and wherein the segment address specifies the data cache segment.

3. The memory device of claim 1, wherein the location address translation function defines the location address as equal to the remainder of the logical address divided by the base of the set of data cache segments.

4. The memory device of claim 1, wherein the segment address translation function defines the segment address as a truncated value equal to the logical address divided by the base of the set of data cache segments.

5. The memory device according to claim 1, wherein the location address is represented by CA[k-1:m], where k is a bit value, wherein And N is the cardinality of the set of data cache segments.

6. The memory device of claim 1, wherein the segment address is represented by CA[m-1:0], wherein And N is the cardinality of the set of data cache segments.

7. The memory device of claim 1, wherein the base of the set of data cache segments is not equal to a power of 2.

8. A method comprising: The logical address in the logical address space is identified by the processing device; The processing device translates the logical address into a set of physical addresses in the physical address space by using a set of translation functions. The set of translation functions includes a location address translation function that translates the logical address into a location address in the set of physical addresses based on the radix of a set of data cache segments, and a segment address translation function that translates the logical address into a segment address in the set of physical addresses based on the radix of the set of data cache segments. and The processing device uses the location address and the segment address to enable the set of data cache segments to process a set of media access operations in parallel, wherein each media access operation in the set of media access operations corresponds to a corresponding data cache segment in the set of data cache segments.

9. The method of claim 8, wherein the location address specifies the location of a data item within a data cache segment in the set of data cache segments, and wherein the segment address specifies the data cache segment.

10. The method of claim 8, wherein the location address translation function defines the location address as the remainder equal to the logical address divided by the base of the set of data cache segments.

11. The method of claim 8, wherein the segment address translation function defines the segment address as a truncated value equal to the logical address divided by the base of the set of data cache segments.

12. The method according to claim 8, wherein the location address is represented by CA[k-1:m], where k is a bit value, wherein And N is the cardinality of the set of data cache segments.

13. The method according to claim 8, wherein the segment address is represented by CA[m-1:0], wherein And N is the cardinality of the set of data cache segments.

14. The method of claim 8, wherein the base of the set of data cache segments is not equal to a power of 2.

15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing means, cause the processing means to perform operations including: Identify logical addresses within the logical address space; A set of translation functions is used to translate the logical address into a set of physical addresses in the physical address space. The set of translation functions includes a location address translation function that translates the logical address into a location address within the set of physical addresses based on the radix of a set of data cache segments, and a segment address translation function that translates the logical address into a segment address within the set of physical addresses based on the radix of the set of data cache segments; and The location address and the segment address are used to enable the set of data cache segments to process a set of media access operations in parallel, wherein each media access operation in the set of media access operations corresponds to a corresponding data cache segment in the set of data cache segments.

16. The non-transitory computer-readable storage medium of claim 15, wherein the location address specifies the location of a data item within a data cache segment of the set of data cache segments, and wherein the segment address specifies the data cache segment.

17. The non-transitory computer-readable storage medium of claim 15, wherein the location address translation function defines the location address as the remainder equal to the logical address divided by the base of the set of data cache segments.

18. The non-transitory computer-readable storage medium of claim 15, wherein the segment address translation function defines the segment address as a truncated value equal to the logical address divided by the base of the set of data cache segments.

19. The non-transitory computer-readable storage medium of claim 15, wherein the location address is a location address represented by CA[k-1:m], wherein the segment address is a segment address represented by CA[m-1:0], where k is a bit value, wherein And N is the cardinality of the set of data cache segments.

20. The non-transitory computer-readable storage medium of claim 15, wherein the set of data cache segments has a base that is not equal to a power of 2.

Images