DSP enhancement system based on RISC-V vector extension

Abstract

The invention relates to a DSP enhancement system based on RISC-V vector extension, which enhances RISC-V vector extension by using a customized DSP instruction, integrates data buffer layer automatic cycle addressing and hardware switching logic, replaces traditional DMA explicit handling or software address updating, reduces data handling delay reduction and bus bandwidth occupancy rate, realizes zero-overhead data flow management, and improves the reliability of the system. Finally, the complex signal processing cycle number performance and energy efficiency of the embedded system are remarkably improved, meanwhile, backward compatibility is kept, software reuse is fully achieved, the efficient signal processing capacity is achieved, the requirements of various end side AI inference signal processing workloads are met, and the application in complex signal processing is greatly improved.

Description

Technical Field

[0001] This invention belongs to the field of signal processing acceleration technology, and relates to a DSP enhancement system based on RISC-V vector extension. Background Technology

[0002] DSP (Digital Signal Processing) tasks place increasingly higher demands on processor energy efficiency and real-time performance. The open standard instruction set architecture RISC-V, with its open-source and modular characteristics, has become an important choice for low-power embedded devices and is already being used in DSP task processing. However, its native instruction set has the following bottlenecks in DSP-intensive tasks (such as Fourier Transform (FFT) and FIR filtering): Scalar instructions are inefficient; traditional scalar instructions require multiple loops to complete vector operations, resulting in limited computational throughput and difficulty in meeting real-time processing requirements. Coprocessor dependency: traditional DSP acceleration solutions often use independent coprocessors (such as dedicated DSP cores or GPUs), requiring data transfer via bus communication, introducing additional latency and power consumption. Mismatch between vector extension and DSP requirements: while RISC-V Vector Extension (RVV) supports SIMD (Single Instruction Multiple Data) parallel computation, it lacks dedicated instructions for DSP operations (such as complex multiplication and accumulation and circular addressing), resulting in high algorithm complexity and insufficient signal processing capabilities. Summary of the Invention

[0003] To address the problems existing in the aforementioned traditional technologies, this invention proposes a DSP enhancement system based on RISC-V vector extension, which can achieve efficient signal processing capabilities.

[0004] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: A DSP enhancement system based on RISC-V vector extension is provided, including a vector transmit queue, a scoring board, vector decoding and transmit logic, vector register file read / write control, an execution unit, a vector register group, a DSP extension enhancement unit, a vector load-store data first-in-first-out queue, an advanced consistency interface, and a data cache; The vector decoding and transmission logic are connected to the vector transmission queue, vector register file read / write control, and execution unit, respectively. The vector transmission queue is connected to the scoring board. The vector register group is connected to the vector register file read / write control, DSP extension and enhancement unit, and vector load-store data FIFO queue, respectively. The vector load-store data FIFO queue is connected to the advanced consistency interface and data cache, respectively. The execution unit is connected to the DSP extension and enhancement unit. The vector register group includes 32 vector registers with a bit width of 128 bits. The vector register group supports SIMD parallel computing. The DSP extension enhancement unit includes a DSP computing unit and a data buffer layer. The DSP computing unit is directly connected to the vector register group. The DSP computing unit is equipped with a complex multiply-accumulate instruction and is used to execute the decrypted vector complex multiply-accumulate instruction to complete the complex multiply-accumulate operation. The data buffer layer integrates a circular buffer address generator and zero-overhead switching logic. The circular buffer address generator is used to generate the circular access address and length according to the decrypted vector circular addressing instruction. The zero-overhead switching logic is used to seamlessly switch the buffer through a hardware counter. The vector complex multiply-accumulate instruction and the vector circular addressing instruction are DSP vector instructions based on RISC-V vector extension.

[0005] In one embodiment, the data buffer layer also adjusts the current vector length and element bit width through a dynamic bit width adaptation instruction to support 8 / 16 / 32-bit precision switching.

[0006] In one embodiment, the execution unit pipeline employs a five-stage pipeline including an instruction fetch stage, a decode stage, an execution stage, a memory access stage, and a write-back stage; wherein, the execution stage includes scalar instruction execution, vector instruction execution, and DSP vector instruction execution.

[0007] In one embodiment, the DSP computing unit is further provided with a bit inversion unit, which is used to implement bit inversion and bit extraction operations with a single instruction using a multi-stage barrel shifter hardware.

[0008] In one embodiment, complex data is stored in a vector register set in segments of real and imaginary parts.

[0009] One of the above technical solutions has the following advantages and beneficial effects: The aforementioned DSP enhancement system based on RISC-V vector extension enhances RISC-V vector extension by using custom DSP instructions, integrating automatic cyclic addressing and hardware switching logic in the data buffer layer to replace traditional DMA explicit data transfer or software address updates. This significantly reduces data transfer latency and bus bandwidth utilization, achieving zero-overhead data flow management. Ultimately, it significantly improves the cycle count performance and energy efficiency of complex signal processing in embedded systems, while maintaining backward compatibility and fully realizing software reuse. This enables highly efficient signal processing capabilities to meet the needs of various edge AI inference signal processing workloads, greatly enhancing its application in complex signal processing. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of the overall architecture of a DSP enhancement system based on RISC-V vector extension in one embodiment; Figure 2 This is a schematic diagram of a five-stage pipeline in one embodiment. Detailed Implementation

[0012] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention.

[0013] It should be noted that, in this document, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments. The term "and / or" as used in the specification and appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0014] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0015] In traditional technologies, dedicated hardware accelerators are external DSP accelerators attached to the processor core. These accelerators are triggered by extended instructions to execute specific tasks. For example, the FT-Matrix processor proposes integrating a dedicated FFT accelerator unit within the processor to achieve hardware acceleration of FFT operations. However, because this requires moving data from main memory to the accelerator's local cache via a bus, it introduces additional latency, poor scalability, large area overhead, and high bandwidth utilization. Therefore, it is difficult to adapt to DSP tasks with dynamically changing bit widths or precisions (such as switching between 8-bit audio processing and 32-bit image processing).

[0016] In the native support of RISC-V Vector Extensions (RVV), DSP algorithms are implemented using the RVV 1.0 standard instruction set (such as the vsetvl dynamic configuration instruction and vector multiply-accumulate instructions). SIMD parallel computing is implemented based on RVV, using vector register sets to complete batch data operations. SIMD stands for Single Instruction Multiple Data. However, this native support lacks DSP-specific instructions; complex number operations must be split into real and imaginary parts for step-by-step processing, increasing the number of instructions and power consumption. It is not optimized for DSP operations (such as complex number operations and bit flipping), leading to redundancy in the algorithm implementation. Furthermore, the lack of circular buffer support necessitates frequent updates of memory addresses via scalar instructions, reducing data reuse efficiency.

[0017] Traditional Haval architecture DSPs employ the Haval architecture, Very Long Instruction Word (VLIW) parallelism, dedicated instructions, and hardware acceleration components, such as the TI C66 series digital signal processors. Their dual-bus structure and VLIW support increase hardware implementation complexity; their independent software ecosystem is also problematic due to high programming complexity and a less-than-friendly environment. VLIW architectures require instruction programming to achieve high-performance signal processing capabilities.

[0018] In the context of accelerating complex signal processing in low-power, high-performance embedded systems, this invention enhances digital signal processing (DSP) capabilities by customizing the Vector Extension (RVV) of the RISC-V instruction set architecture. RISC-V, an open standard instruction set architecture (ISA), has led a new trend in processor design with its modular design and collaborative community. RISC-V RVV (RISC-V Vector Extension) is a vector processing extension of the RISC-V instruction set architecture.

[0019] In one embodiment, such as Figure 1As shown, a DSP enhancement system based on RISC-V vector extension is provided, including a vector issue queue, a scoring board, vector decoding and issue logic, vector register file read / write control, an execution unit, a vector register group, a DSP extension enhancement unit, a vector load-store data FIFO queue, an advanced consistency interface, and a data cache. The vector decoding and issue logic are connected to the vector issue queue, the vector register file read / write control, and the execution unit, respectively. The vector issue queue is connected to the scoring board. The vector register group is connected to the vector register file read / write control, the DSP extension enhancement unit, and the vector load-store data FIFO queue, respectively. The vector load-store data FIFO queue is connected to the advanced consistency interface and the data cache, respectively. The execution unit is connected to the DSP extension enhancement unit. The vector register group includes 32 vector registers with a bit width of 128 bits, and the vector register group supports SIMD parallel computing. The DSP extension enhancement unit includes a DSP computing unit and a data buffer layer. The DSP computing unit is directly connected to the vector register set. The DSP computing unit is additionally equipped with a complex multiply-accumulate function to execute decrypted vector complex multiply-accumulate instructions to complete the complex multiply-accumulate operation. The data buffer layer integrates a circular buffer address generator and zero-overhead switching logic. The circular buffer address generator is used to generate the circular access address and length based on the decrypted vector circular addressing instructions. The zero-overhead switching logic is used for seamless buffer switching via a hardware counter. The vector complex multiply-accumulate instruction and the vector circular addressing instruction are DSP vector instructions based on RISC-V vector extensions.

[0020] It can be understood that the processor architecture includes a Vector Issue Queue (VIQ), a Scoreboard, Vector Decode and Issue Logic, Vector Register Read / Write Control (VRF), an Execution Unit (EX), and a Vector Register Set (i.e., ... Figure 1 The VRF, DSP Extension Enhancement Unit (DSP EXT), Vector Load-Store Data First-In-First-Out Queue (Vector LS Data FIFO), Advanced Consistency Interface (ACE), and Data Cache (Dcache) are included.

[0021] The Scoreboard is a hardware mechanism for dynamically scheduling instruction execution. It tracks the execution status of instructions and monitors operand availability to determine when instructions can be sent to execution units, avoiding data and structural conflicts and improving the parallelism of instruction execution. The Vector Issue Queue (VIQ) temporarily stores vector instructions to be issued for execution. It caches vector instructions retrieved from the instruction cache and sends them to the Vector Decode and Issue Logic (VIDL) in a timely manner according to certain rules and conditions. The VIDL is responsible for decoding vector instructions, analyzing the operation type and operands, and determining when to issue the instruction to the appropriate execution unit based on status information from the Scoreboard and other components. EX0 to EX3 represent the execution units, and VRF0 to VRF3 represent the vector registers. Vector load-store data first-in-first-out queues, advanced consistency interfaces, and data caches are traditional components of the RISC-V processor architecture.

[0022] The DSP extension enhancement unit serves only as the execution unit for the RISC-V vector extension; other hardware components reuse the RISC-V vector extension. The DSP extension enhancement unit includes a DSP computation unit and a data buffer layer (DBL). The DSP computation unit is directly connected to the vector register set and adds a complex MAC (complex multiply-accumulate). The vector register set (RVV 1.0, which is a concrete implementation of the RISC-V vector extension and is itself part of the RISC-V vector extension; in this vector extension design, the DSP vector instruction extension supports vector operations, reusing this logic) supports SIMD parallel computing and includes 32 vector registers (VLEN = 128 bits). The data path can be as follows: scalar instructions and DSP vector instructions pass through the existing vector decoder (i.e., the decoder, also known as the decoder, corresponding to...). Figure 1 The CPU has vector decoding and transmission logic; the decoder is also layered in the CPU design. First, it determines whether it is a vector instruction. If it is a vector instruction, it is sent to the vector decoder for further decoding. Otherwise, it is transferred to other processing. After decoding, it is distributed to different execution units (EX), and finally executed by the DSP extension and enhancement unit.

[0023] The RISC-V-based DSP vector instruction extensions are as follows: the instruction format is based on RVV OP-V encoding, and two new DSP instruction categories, VFMAC (vector complex multiplication and accumulation) and VLCRD (vector circular addressing), are added. Example instructions are shown below: VFMAC (Vector Complex Multiplication and Accumulation) instruction: text; Copy Code; `vfmacc.vv ​​vd, vs1, vs2, v0.t` / / `vd = vd + (vs1 real part × vs2 real part - vs1 imaginary part × vs2 imaginary part) + j*(vs1 real part × vs2 imaginary part + vs1 imaginary part × vs2 real part)` Here, `vfmacc.vv` is a vector floating-point multiply-accumulate instruction, which performs multiply-accumulate operations on the elements in the vector register. `vd` represents the destination vector register; after the instruction is executed, the result of the multiply-accumulate operation will be stored in this destination vector register. `vs1` and `vs2` are the source vector registers; the instruction performs multiplication operations on the corresponding elements in these two registers.

[0024] VLCRD (Vector Circular Addressing) instruction: text; Copy Code; vlcrd a0, a1, vl / / Configures the base address a0 and length a1 of the circular buffer, where vl is the current vector length.

[0025] The newly added instructions support completing complex number operations and circular buffer configuration with a single instruction, eliminating the need to split the real and imaginary parts or manually update addresses. The circular buffer address generator generates the circular access address and length based on the VLCRD instruction configuration, enabling automatic data reuse (such as alternating input / output in FFT butterfly operations). Zero-overhead switching logic uses a hardware counter to achieve seamless buffer switching, avoiding latency and power consumption caused by explicit data movement, thus significantly reducing data handling overhead.

[0026] The aforementioned DSP enhancement system based on RISC-V vector extension enhances RISC-V vector extension by using custom DSP instructions. It integrates automatic cyclic addressing and hardware switching logic in the data buffer layer, replacing traditional DMA explicit data transfer or software address updates. This reduces data transfer latency and bus bandwidth utilization. Hardware-level complex number operations and address generation are implemented through dedicated instructions, reducing the number of instructions and bus interactions. Zero-overhead data flow management is achieved, ultimately significantly improving the cycle count performance and energy efficiency of complex signal processing in embedded systems. At the same time, it maintains backward compatibility and fully realizes software reuse, achieving efficient signal processing capabilities to meet the needs of various edge AI inference signal processing workloads, greatly enhancing its application in complex signal processing.

[0027] In one embodiment, the data buffer layer also adjusts the current vector length and element bit width through a dynamic bit width adaptation instruction to support 8 / 16 / 32-bit precision switching.

[0028] It is understood that this embodiment further employs a dynamic bit-width switching mechanism: that is, by dynamically configuring instructions to adjust the current vector length (vl) and element bit width (SEW) through dynamic bit-width adaptation instructions (vsetvl), it supports 8 / 16 / 32-bit precision switching, forming a dynamic bit-width switching and block-based computation mechanism to achieve the purpose of dynamic adaptation. The dynamic bit-width adaptation instruction (vsetvl) supports 8 / 16 / 32-bit precision switching, ensuring compatibility with different DSP task requirements. Hardware-level complex number operations and address generation are implemented through the aforementioned dedicated instructions, reducing the number of instructions and bus interactions, and reducing algorithm implementation complexity. By adopting a dynamic bit-width switching mechanism to replace the traditional splitting of real and imaginary parts or manual precision configuration, hardware-level complex number operations are accelerated, achieving efficient signal processing capabilities while being compatible with multiple precision requirements.

[0029] In one embodiment, the DSP computing unit is further provided with a bit inversion unit, which is used to implement bit inversion and bit extraction operations with a single instruction using a multi-stage barrel shifter hardware.

[0030] It is understandable that the bit reversal unit is implemented in hardware using a multi-stage barrel shifter, supporting single-instruction bit reversal (such as the vector bit reversal instruction vbitrev.v) and bit extraction (such as the vbitx.v instruction).

[0031] In one embodiment, the execution unit pipeline employs a five-stage pipeline including an instruction fetch stage, a decode stage, an execution stage, a memory access stage, and a write-back stage; wherein, the execution stage includes scalar instruction execution, vector instruction execution, and DSP vector instruction execution.

[0032] Understandable, such as Figure 2 As shown, the RISC-V processor core execution unit pipeline of the DSP enhancement system based on RISC-V vector extension adopts a five-stage pipeline: Fetch Stage (IF), Decode Stage (ID), Execute Stage (EX), Memory Access Stage (MEM), and Write-Back Stage (WB). The Fetch Stage (IF) is used to synchronously fetch scalar and vector instructions. The Decode Stage (ID) is used to identify DSP instructions and allocate them to dedicated execution units. The Execute Stage (EX) includes scalar instruction execution (i.e., scalar EX), vector instruction execution (i.e., vector EX), and DSP vector instruction execution (i.e., DSP EX). Scalar EX handles arithmetic logic instructions, vector EX executes standard RVV instructions (such as vadd.vv instructions), and DSP EX integrates a complex MAC and bit-flip unit to complete complex multiplication-accumulation and bit-flipping operations in a single cycle. The Memory Access Stage (MEM) manages data access through a data buffer layer and supports automatic addressing of circular buffers. The write-back stage (WB) is used to write the results back to the vector register set or memory.

[0033] In one embodiment, complex data is stored in a vector register set in segments of real and imaginary parts.

[0034] It can be understood that complex data is stored in the vector register in segments of real and imaginary parts (e.g., v0[0:31] is the real part and v0[32:63] is the imaginary part). The real and imaginary components are calculated in parallel internally by the VFMAC instruction to achieve automatic splitting and merging of complex number operations.

[0035] In some implementations, to more intuitively demonstrate the application of the DSP enhancement system based on RISC-V vector extension, one application flow example can be as follows: (1) Initialization configuration: asm; Copy Code; vsetivli t0, 4, e16 / / Sets the current vector length vl=4 (4 complex numbers), SEW=16 bits; vlcrd a0, 256, vl / / Configures the base address of the input buffer a0, with a length of 256 bytes.

[0036] (2) Data loading and preprocessing: asm; Copy Code; vle16.v v0, (a0) / / Load 4 complex numbers (alternating between real and imaginary parts); vbitrev.v v1, v0, 3 / / Hardware bit inversion (adapts to 128-point FFT input).

[0037] (3) Butterfly-shaped operation core: asm; Copy Code; vle16.v v2, (s0) / / Load the pre-computed twiddle factor; vfmacc.vv ​​v1, v1, v2 / / A single instruction performs the multiplication and summation of four complex numbers.

[0038] (4) Rearrangement of intermediate data: asm; Copy Code; vrgather.vv v3, v1, vindex / / Reorder data by index (to fit the next level of butterfly operation).

[0039] (5) Result storage and switching buffer: asm; Copy Code; vsse16.v v3, (a1), t0 / / Step to output buffer (step = VL × 2); vlcrd a0, 256, vl / / Automatically switch to the next data block (zero overhead).

[0040] (6) Iteration and normalization: asm; Copy Code; loop:... / / Repeat steps (3)-(5) (a total of log2(N) levels); vfdiv.vi v1, v1, 128 / / Normalize the result (divide by the number of FFT points).

[0041] Wherein, asm represents assembly, loop represents loop operation, vfdiv is vector floating-point division instruction, vsse16 is vector scalar storage byte extension instruction, (a0), (s0) and (a1) represent the memory addresses of various general-purpose registers, vrgather is vector collection instruction, vindex is index vector register, and vle16 is vector load half-word instruction.

[0042] The above design adds the VFMAC instruction (completion of complex multiplication and accumulation in a single instruction) and a dynamic bit-width switching mechanism (vsetvl instruction), replacing the traditional solution of splitting the real and imaginary parts or manually configuring precision. This achieves hardware-level acceleration of complex number operations while being compatible with various precision requirements. It integrates a DBL module (automatic circular addressing) and hardware switching logic, replacing traditional DMA explicit data transfer or software address updates, reducing data transfer latency and bus bandwidth utilization. It employs hardware-level dynamic bit-width adaptation (supporting 8 / 16 / 32-bit mixed computing), superior to fixed-bit-width coprocessor solutions, to adapt to different DSP task requirements through dynamic bit-width precision switching. Thus, through instruction set expansion (such as VFMAC, VLCRD), hardware module customization (such as DBL, NLU), and system-level optimization (heterogeneous core collaboration, dynamic precision), it comprehensively surpasses existing technologies in terms of computational efficiency, energy efficiency, and flexibility, adapting to complex digital information processing scenarios.

[0043] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0044] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of protection of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and all such modifications and improvements fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A DSP enhancement system based on RISC-V vector extension, characterized in that, This includes a vector transmission queue, a scoring board, vector decoding and transmission logic, vector register file read / write control, an execution unit, a vector register group, a DSP extension and enhancement unit, a vector load-store data first-in-first-out queue, an advanced consistency interface, and a data cache; The vector decoding and transmission logic are connected to the vector transmission queue, vector register file read / write control, and execution unit, respectively. The vector transmission queue is connected to the scoring board. The vector register group is connected to the vector register file read / write control, DSP extension and enhancement unit, and vector load-store data FIFO queue, respectively. The vector load-store data FIFO queue is connected to the advanced consistency interface and data cache, respectively. The execution unit is connected to the DSP extension and enhancement unit. The vector register group includes 32 vector registers with a bit width of 128 bits. The vector register group supports SIMD parallel computing. The DSP extension enhancement unit includes a DSP computing unit and a data buffer layer. The DSP computing unit is directly connected to the vector register group. The DSP computing unit is equipped with a complex multiply-accumulate instruction and is used to execute the decrypted vector complex multiply-accumulate instruction to complete the complex multiply-accumulate operation. The data buffer layer integrates a circular buffer address generator and zero-overhead switching logic. The circular buffer address generator is used to generate the circular access address and length according to the decrypted vector circular addressing instruction. The zero-overhead switching logic is used to seamlessly switch the buffer through a hardware counter. The vector complex multiply-accumulate instruction and the vector circular addressing instruction are DSP vector instructions based on RISC-V vector extension.

2. The DSP enhancement system based on RISC-V vector extension according to claim 1, characterized in that, The data buffer layer also adjusts the current vector length and element bit width through dynamic bit width adaptation instructions to support 8 / 16 / 32-bit precision switching.

3. The DSP enhancement system based on RISC-V vector extension according to claim 1 or 2, characterized in that, The execution unit pipeline employs a five-stage pipeline, including the instruction fetch stage, decode stage, execution stage, memory access stage, and write-back stage; among which, the execution stage includes scalar instruction execution, vector instruction execution, and DSP vector instruction execution.

4. The DSP enhancement system based on RISC-V vector extension according to claim 3, characterized in that, The DSP computing unit also includes a bit inversion unit, which uses a multi-stage barrel shifter to implement bit inversion and bit extraction operations with a single instruction.

5. The DSP enhancement system based on RISC-V vector extension according to claim 3, characterized in that, Complex data is stored in the vector register set in segments of real part and imaginary part.

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