A chip testing system based on local shared expected data comparators

Abstract

The application relates to the technical field of integrated circuit design, in particular to a chip test system based on a local shared expected data comparator, which divides the memory of a chip into multiple memory groups, and the memory in a single memory group shares a shared comparator; compared with configuring a corresponding comparator for each memory, the total number of comparators is effectively reduced, the area overhead of the chip is reduced, compared with all memories sharing the same comparator on the controller side, the shared comparator is arranged on the memory group side, the data path of the memory and the corresponding shared comparator is short, system timing convergence difficulties are avoided, the wiring density near the controller is reduced, and layout and wiring blockage is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip testing technical field, in particular to a chip testing system based on local shared expected data comparator. BACKGROUND

[0002] In the modern integrated circuit industry, the demand for on-chip memory is increasing, and the proportion of on-chip memory is increasing, especially in artificial intelligence chips, the proportion of on-chip memory is much higher than other logic, so the test of on-chip memory is indispensable. Generally, the functional test method is used to test the on-chip memory, which takes a long time and has low coverage, so the commonly used method in the prior art is to use the built-in self-test circuit to test the structure of the on-chip memory.

[0003] The built-in self-test circuit usually includes a controller module, an interface interaction module and an expected data comparator. In the conventional built-in self-test circuit, the controller can be shared, and the physical location of the controller is usually far away from the measured memory. The interface interaction logic needs to be matched with the measured memory, and the physical location of the interface interaction logic is close to the measured memory, and the number is large and cannot be shared.

[0004] The expected data comparator in the prior art usually has two arrangement methods, the first method is to place the interface interaction module together, and each memory independently sets the corresponding expected data comparator. This arrangement method is easy to converge in timing, and will not cause layout and wiring blockage, but the chip area overhead is large. The second method is to share all the expected data comparators of the memory, and the shared comparator is set in the controller, which has small chip area overhead, but the data path between the memory and the comparator is far away, and a large number of buffers need to be added, which will cause timing convergence difficulty, and the layout and wiring near the controller are easy to block.

[0005] The built-in test circuit expected data comparator has certain defects, so we propose a test circuit scheme that locally shares the expected data comparator and is as close as possible to the tested memory. It solves the problem of saving area and considering the physical location of the measured memory.

[0006] Therefore, how to save area and avoid wiring blockage, timing convergence difficulty and other problems has become a problem to be solved. SUMMARY

[0007] In view of the above technical problems, the technical scheme adopted by the present application is:

[0008] A chip test system based on local shared expected data comparator, the system comprises a chip, the chip comprises a controller, M memory banks, M memory banks corresponding shared comparators respectively and each memory corresponding interface interaction module, the memory bank comprises a plurality of memories of the same clock source.

[0009] The interface interaction module is used for sending test data to the corresponding memory.

[0010] The memory is used for memory test according to the received test data, and the actual test result corresponding to the test data is output to the corresponding interface interaction module.

[0011] The interface interaction module is also used for receiving the actual test result corresponding to the test data, and sending the actual test result corresponding to the test data and the expected test result corresponding to the test data to the shared comparator corresponding to the memory bank to which the corresponding memory belongs.

[0012] The shared comparator is used for determining a data comparison result according to the actual test result and the expected test result corresponding to the test data, and sending the data comparison result to the controller.

[0013] Compared with the prior art, the chip test system based on local shared expected data comparator provided by the application has obvious beneficial effects, and can achieve considerable technical progress and practicability, and has wide industrial utilization value, and at least has the following beneficial effects:

[0014] The memory of the chip is divided into a plurality of memory banks in the application, and the memories in a single memory bank share a shared comparator, which effectively reduces the total number of comparators, reduces the area overhead of the chip, and compared with all memories sharing the same comparator on the controller side, the shared comparator is arranged on the memory bank side, the data path of the memory and the corresponding shared comparator is shorter, the system timing convergence difficulty is avoided, and the wiring density near the controller is reduced, and layout and wiring blockage is avoided. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the application, the drawings needed to be used in the embodiment description will be briefly introduced, and obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0016] Figure 1 A structure schematic diagram of a chip test system based on local shared expected data comparator provided by the embodiment of the application. DETAILED DESCRIPTION

[0017] The technical solutions in the embodiments of the present application will be apparently and completely described in connection with the drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all the other embodiments obtained by a person skilled in the art without any creative work fall within the protection scope of the present application.

[0018] The embodiment provides a chip test system based on a local shared expected data comparator, the system comprises a chip, the chip comprises a controller, M memory banks, M memory banks respectively corresponding shared comparators and an interface interaction module corresponding to each memory, the memory bank comprises a plurality of memories with the same clock source;

[0019] The interface interaction module is used for sending test data to the corresponding memory;

[0020] The memory is used for storing the test data according to the received test data, and outputting actual test results corresponding to the test data to the corresponding interface interaction module;

[0021] The interface interaction module is also used for receiving the actual test results corresponding to the test data, and sending the actual test results corresponding to the test data and expected test results corresponding to the test data to the shared comparator corresponding to the memory bank to which the corresponding memory belongs;

[0022] The shared comparator is used for determining a data comparison result according to the actual test results corresponding to the test data and the expected test results, and sending the data comparison result to the controller.

[0023] In the prior art, the layout mode of the memory in the chip is usually two kinds, one is boundary arrangement, and one is center arrangement, and the embodiment is applied to the scenario that the memory is arranged in the chip in the boundary arrangement mode.

[0024] The controller is used for generating test data and coordinating the whole test process, the memory bank can be a set formed by a plurality of memories using the same clock source, and a plurality of memories in a single memory bank share a shared comparator, compared with the mode that each memory is independently configured with a comparator, the number of comparators is effectively reduced, and the chip area overhead is reduced.

[0025] The test data can adopt full 0, full 1, checkerboard, walking bit and the like.

[0026] Referring to Figure 1A structural schematic diagram of a chip test system based on a local shared expected data comparator is provided for an embodiment of the present application. The structural schematic diagram takes four memory groups as an example, each of which contains three memories. It should be understood by the implementer that the number of memory groups and the number of memories contained in each memory group can be flexibly adjusted according to actual conditions, and the number of memories contained in different memory groups can be different.

[0027] Specifically, the transmission and control logic between the plurality of memories in a single memory group and the shared comparator can reuse the transmission and control logic of all memories sharing the same comparator in the prior art, and the transmission and control logic between the plurality of shared comparators and the controller can reuse the transmission and control logic between each memory and the independent comparator and controller in the prior art, thereby effectively reducing the design complexity, directly reusing the mature interface logic, ensuring the design reliability and compatibility with the existing architecture, and facilitating the debugging and maintenance of the design.

[0028] In a specific embodiment, the memory includes a plurality of storage units, and the controller includes a data generator, an address generator, a memory control signal generator, and an algorithm controller. The algorithm controller is configured to determine a current test step. The address generator is configured to generate an access address of a storage unit in the memory corresponding to the current test step. The data generator is configured to generate test data corresponding to the current test step. The memory control signal generator is configured to generate an enable signal for the memory corresponding to the current test step, the enable signal including a write enable signal and a read enable signal. The controller is configured to send the test data corresponding to the current test step, the access address, and the enable signal to the interface interaction module.

[0029] Correspondingly, the sending of the test data to the corresponding memory includes:

[0030] sending the test data corresponding to the current test step, the access address, and the enable signal to the corresponding memory.

[0031] The memory test according to the received test data includes:

[0032] writing the test data into the storage unit corresponding to the access address according to the write enable signal;

[0033] reading out the data in the storage unit corresponding to the access address as the actual test result corresponding to the test data according to the read enable signal, and sending the data to the interface interaction module corresponding to the memory.

[0034] The algorithm controller is configured to manage the execution steps and state transitions of the test algorithm. The test algorithm can be a March algorithm or the like.

[0035] The generation of the access address can adopt an increment, decrement, jump, etc. generation mode, and the access address can be used to determine the corresponding storage unit in the memory.

[0036] Specifically, in the test flow, the read enable signal is usually generated after the write enable signal, so as to read out the test data written into the storage unit under the control of the write enable signal.

[0037] In a specific embodiment, the interface interaction module includes interface interaction sending logic and interface interaction receiving logic corresponding to the memory;

[0038] The interface interaction sending logic is configured to send test data to the corresponding memory;

[0039] The interface interaction receiving logic is configured to receive actual test results corresponding to the test data.

[0040] The interface interaction sending logic can also be configured to send access addresses and enable signals to the corresponding memory.

[0041] The interface interaction receiving logic can also be configured to pass the received actual test results corresponding to the test data to the shared comparator.

[0042] In a specific embodiment, the physical distance between each memory in a single memory group in the chip is less than a preset first distance threshold.

[0043] The first distance threshold is used to constrain the physical positions of the plurality of memories in the same memory group to be close to each other, so that when the same memory group uses the shared comparator, the data paths are all short, thereby reducing data transmission delay, improving timing convergence, and reducing wiring complexity.

[0044] Specifically, the implementer can divide the memory groups according to the respective physical positions of all the memories by using a density-based clustering algorithm, but needs to ensure that the plurality of memories in the divided memory group are of the same clock source. The density-based clustering algorithm can use a DBSCAN clustering algorithm.

[0045] In a specific embodiment, the physical distance between the corresponding center position of a single memory group in the chip and the corresponding physical position of the shared comparator corresponding to the memory group in the chip is less than a preset second distance threshold.

[0046] The second distance threshold is used to constrain the physical positions of the memory group and the shared comparator corresponding thereto to be close to each other, so as to shorten the data paths of the actual test results and the expected results to the shared comparator, reduce signal transmission delay from the memory to the shared comparator, and improve comparison speed.

[0047] In a specific embodiment, the chip corresponds to a plurality of test time periods, and only one memory exists in a single test time period.

[0048] In the above embodiment, each memory shares the comparator resource in a time division multiplexing manner to avoid conflict caused by simultaneous access of multiple memories to the shared comparator, thereby simplifying the control logic and reducing the peak power consumption.

[0049] In a specific embodiment, the shared comparator includes a gated switch.

[0050] The gated switch is configured to control the enable state of the shared comparator.

[0051] In the above embodiment, the gated switch is configured to close the corresponding shared comparator when the memory group is not tested, and open the corresponding shared comparator before the memory group is tested, thereby supporting dynamic power management of the shared comparator and facilitating improvement of the system energy efficiency.

[0052] In a specific embodiment, the controller is further configured to send a desired data mask to the shared comparator, and when the desired data mask is a first preset value, the gated switch of the shared comparator controls the enable state of the shared comparator to be enabled, and when the desired data mask is a second preset value, the gated switch of the shared comparator controls the enable state of the shared comparator to be disabled.

[0053] In the above embodiment, the first preset value can be 1, and the second preset value can be 0. The controller sends the desired data mask to the shared comparator to control the corresponding gated switch of the shared comparator, thereby controlling the enable state of the shared comparator.

[0054] In the above embodiment, the memories of the chip are divided into a plurality of memory groups, and the memories in a single memory group share a shared comparator. Compared with configuring a corresponding comparator for each memory, the total number of comparators is effectively reduced, and the area overhead of the chip is reduced. Compared with all memories sharing the same comparator on the controller side, the shared comparator is arranged on the memory group side. The data path between the memory and the corresponding shared comparator is short, which avoids difficulty in system timing convergence and reduces the wiring density near the controller, thereby avoiding layout and routing congestion.

[0055] Although some specific embodiments of the present application have been described in detail by way of examples, those skilled in the art should understand that the above examples are only for illustration, and are not intended to limit the scope of the present application. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the present application. The scope of the present application is defined by the appended claims.

Claims

1. A chip testing system based on a locally shared expected data comparator, characterized in that, The system includes a chip, which includes a controller, M memory groups, a shared comparator corresponding to each of the M memory groups, and an interface interaction module corresponding to each memory. The memory groups include several memories with the same clock source. The interface interaction module is used to send test data to the corresponding memory; The memory is used to perform memory testing based on the received test data and output the actual test results corresponding to the test data to the corresponding interface interaction module. The interface interaction module is also used to receive the actual test results corresponding to the test data, and send the actual test results corresponding to the test data and the expected test results corresponding to the test data to the shared comparator of the memory group to which the corresponding memory belongs. The shared comparator is used to determine the data comparison result based on the actual test result and the expected test result corresponding to the test data, and send the data comparison result to the controller.

2. The chip testing system based on a locally shared expected data comparator according to claim 1, characterized in that, The memory includes several storage units, and the controller includes a data generator, an address generator, a memory control signal generator, and an algorithm controller. The algorithm controller is used to determine the current test step, the address generator is used to generate the access address of the storage unit in the memory corresponding to the current test step, the data generator is used to generate the test data corresponding to the current test step, the memory control signal generator is used to generate an enable signal and send it to the memory corresponding to the current test step, the enable signal includes a write enable signal and a read enable signal, and the controller is used to send the test data, access address, and enable signal corresponding to the current test step to the interface interaction module. Accordingly, sending test data to the corresponding memory includes: Send the test data, access address, and enable signal corresponding to the current test step to the corresponding memory; The step of performing memory testing based on the received test data and outputting the actual test results corresponding to the test data to the corresponding interface interaction module includes: According to the write enable signal, the test data is written to the storage unit corresponding to the access address; Based on the read enable signal, the data in the storage unit corresponding to the access address is read out as the actual test result corresponding to the test data and sent to the interface interaction module corresponding to the memory.

3. The chip testing system based on a locally shared expected data comparator according to claim 1, characterized in that, The interface interaction module includes interface interaction sending logic and interface interaction receiving logic for the corresponding memory. The interface interaction sending logic is used to send test data to the corresponding memory; The interface interaction receiving logic is used to receive the actual test results corresponding to the test data.

4. The chip testing system based on a locally shared expected data comparator according to claim 1, characterized in that, The physical distance between each memory in a single memory group within the chip is less than a preset first distance threshold.

5. The chip testing system based on a locally shared expected data comparator according to claim 1, characterized in that, The physical distance between the center location of a single memory group in the chip and the physical location of the shared comparator corresponding to the memory group in the chip is less than a preset second distance threshold.

6. The chip testing system based on a locally shared expected data comparator according to claim 1, characterized in that, The chip corresponds to several test time periods, and only one memory is tested within a single test time period.

7. The chip testing system based on a locally shared expected data comparator according to claim 1, characterized in that, The shared comparator includes a gated switch; The gate switch is used to control the enable state of the shared comparator.

8. The chip testing system based on a locally shared expected data comparator according to claim 7, characterized in that, The controller is also configured to send a desired data mask to the shared comparator. When the desired data mask is a first preset value, the gating switch of the shared comparator controls the enabled state of the shared comparator to be enabled. When the desired data mask is a second preset value, the gating switch of the shared comparator controls the enabled state of the shared comparator to be disabled.

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