FPGA-based PCIe switch detection method and system

Abstract

The application discloses a PCIe Switch detection method and system based on FPGA, relates to the technical field of high-speed computer bus detection, and discloses the PCIe Switch detection method and system based on FPGA, which generates a comprehensive evaluation report by integrating link state data, error code rate statistical data and inter-channel delay difference data, and realizes standardized output by using an API interface layer, is low in cost, and can realize multi-dimensional link state comprehensive detection through simple operation.

Description

Technical Field

[0001] This application relates to the field of high-speed computer bus detection technology, and in particular to a PCIe Switch detection method and system based on FPGA. Background Technology

[0002] With the rapid development of information technology, PCIe (Peripheral Component Interconnect Express), as a high-speed serial computer expansion bus standard, has become a key technology for data transmission in modern computing systems. PCIe switches, as core components connecting multiple PCIe devices, play a crucial role in servers, storage systems, and high-performance computing environments. However, with the development of PCIe technology, especially its evolution from Gen3 to Gen4 and even Gen5, its speed and complexity have increased significantly, placing higher demands on link status monitoring and stability assessment.

[0003] Traditional PCIe testing methods primarily rely on hardware testing instruments such as protocol analyzers or bit error rate testers (BERTs). These tools are typically expensive and complex to operate, limiting their widespread use in practical applications. Furthermore, existing solutions often focus on single functions, such as providing only error correction or basic link status queries, lacking a comprehensive diagnostic tool that integrates multi-dimensional testing functions and provides a unified API interface. This forces users to learn multiple different tools and navigate fragmented testing processes, increasing learning costs and difficulty of use. Existing solutions are functionally fragmented, only addressing specific problems, such as only performing error correction or basic status queries, lacking comprehensive link health checks. Secondly, the operation methods of different tools vary significantly, requiring users to spend considerable time learning how to use each tool, increasing their workload. Moreover, for developers who want to integrate PCIe testing functionality into their products, existing solutions are difficult to utilize directly due to their closed and proprietary nature.

[0004] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The main purpose of this application is to provide a PCIe Switch detection method and system based on FPGA, which aims to achieve comprehensive detection of multi-dimensional link status through simple operation.

[0006] To achieve the above objectives, this application proposes an FPGA-based PCIe Switch detection method, the method comprising:

[0007] The link status data of the PCIe link is obtained through hardware layer operation of the FPGA; wherein, the link status data includes the current LTSSM status, historical status switching records, link rate and number of active lanes.

[0008] Based on the hardware layer operation of the FPGA, physical layer signal data is detected; wherein, the physical layer signal data includes bit error rate statistics and inter-channel delay difference data;

[0009] The link status data, bit error rate statistics, and inter-channel delay difference data are integrated and processed using a link stability analysis algorithm to generate a link stability assessment report.

[0010] In one embodiment, the step of obtaining the link status data of the PCIe link through the hardware layer operation of the FPGA includes:

[0011] Obtain the LTSSM status output signal from the PCIe IP core to obtain the original LTSSM status value;

[0012] The original LTSSM state value is latched using a shift register latching mechanism to record and store historical state switching data, thereby generating latched historical state data.

[0013] Based on the timestamp module recording the state switching time, and combined with the latched historical state data, complete link state data is generated.

[0014] In one embodiment, the step of obtaining the LTSSM status output signal from the PCIe IP core to obtain the original LTSSM status value includes:

[0015] The driver layer reads the LTSSM status output interface of the PCIe IP core to obtain the unprocessed LTSSM status signal;

[0016] The unprocessed LTSSM state signal is encoded to generate a 5-bit encoded original LTSSM state value.

[0017] In one embodiment, the step of detecting physical layer signal data based on the FPGA hardware layer operation includes:

[0018] The BERT detection module generates a PRBS pseudo-random sequence and performs bit error detection, generating bit error statistics.

[0019] Based on the bit error statistics and the total number of bits, the real-time bit error rate is calculated and bit error rate statistics are generated.

[0020] The edge time difference of each lane signal is measured by a multi-channel synchronous sampling circuit to generate the raw delay difference data;

[0021] The original delay difference data is averaged and calibrated to generate inter-channel delay difference data.

[0022] In one embodiment, the step of generating a PRBS pseudo-random sequence through the BERT detection module and performing bit error detection to generate bit error statistics results includes:

[0023] A PRBS sequence generator is implemented using FPGA logic resources to generate and transmit sequence data.

[0024] The transmitted sequence data and the received sequence data are compared, and bit errors are detected by bitwise XOR operation to generate bit error count data;

[0025] Based on the number of bit errors and the total number of bits, the number of bits required for the test is calculated using the confidence formula, and bit error statistics are generated.

[0026] In one embodiment, the step of measuring the edge time difference of each lane signal through a multi-channel synchronous sampling circuit to generate raw delay difference data includes:

[0027] The global clock network and phase-locked loop of the FPGA are used to realize the synchronous sampling of multi-channel signals and generate the sampled time signal;

[0028] The time difference between the rising or falling edge of the target Lane signal and other Lane signals is calculated based on the differential delay line module to generate time difference data.

[0029] The time difference data is processed by the threshold judgment module to generate the original delay difference data.

[0030] In one embodiment, the step of integrating the link status data, bit error rate statistics, and inter-channel delay difference data, processing them through a link stability analysis algorithm, and generating a link stability assessment report includes:

[0031] Integrate the LTSSM state switching frequency from the link status data, the bit error rate trend data from the bit error rate statistics data, and the delay difference fluctuation data from the inter-channel delay difference data to generate a link parameter dataset;

[0032] The link parameter dataset is processed based on a weighted scoring model to calculate stability score data; wherein, the weighted scoring model uses weight coefficients to weight the bit error rate, latency difference and state switching frequency.

[0033] Based on the stability score data and preset alarm thresholds, a link stability assessment report is generated.

[0034] In one embodiment, the step of processing the link parameter dataset based on a weighted scoring model to calculate stability score data includes:

[0035] The bit error rate trend data is subjected to sliding window statistical processing to generate a normalized bit error rate value;

[0036] The delay difference fluctuation data is scaled proportionally to generate a normalized delay difference value;

[0037] By combining the normalized bit error rate, normalized delay difference, and LTSSM state switching frequency data, stability score data is obtained through weighted calculation.

[0038] In one embodiment, the method further includes encapsulating the link stability assessment report into a standardized function output through an API interface layer for user invocation.

[0039] Furthermore, to achieve the above objectives, this application also proposes an FPGA-based PCIe Switch detection system, the system comprising: a memory, a processor, and an FPGA-based PCIe Switch detection program stored in the memory and executable on the processor, the FPGA-based PCIe Switch detection program being configured to implement the steps of the FPGA-based PCIe Switch detection method.

[0040] The FPGA-based PCIe Switch detection method and system proposed in this application generate a comprehensive evaluation report by integrating link status data, bit error rate statistics and inter-channel delay difference data, and achieves standardized output using the API interface layer. It has low cost and can achieve multi-dimensional comprehensive link status detection through simple operation. Attached Figure Description

[0041] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0042] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a flowchart illustrating an embodiment of the FPGA-based PCIe Switch detection method of this application.

[0044] Figure 2 For this application Figure 1A detailed flowchart of step S100;

[0045] Figure 3 For this application Figure 2 A detailed flowchart of step S110;

[0046] Figure 4 For this application Figure 1 A detailed flowchart of step S200;

[0047] Figure 5 For this application Figure 4 A detailed flowchart of step S210;

[0048] Figure 6 For this application Figure 4 A detailed flowchart of step S230;

[0049] Figure 7 For this application Figure 1 Detailed flowchart of step S300;

[0050] Figure 8 For this application Figure 7 A detailed flowchart of step S320;

[0051] Figure 9 This is a schematic diagram of a structural embodiment of the FPGA-based PCIe Switch detection system of this application.

[0052] Explanation of icon numbers:

[0053] 10. Memory; 20. Processor.

[0054] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0055] The technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of this application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0056] It should be understood that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0057] In existing technologies, the rapid development of PCIe technology has led to an increasing demand for link status monitoring. However, traditional detection methods rely on expensive hardware and have limited functionality. For example, protocol analyzers can only parse link-layer protocol status, and bit error rate testers can only perform physical layer signal detection. Users need to operate multiple devices simultaneously to complete a comprehensive diagnosis. In a data center operation and maintenance scenario, engineers need to monitor the link stability of PCIe switches in real time, but existing tools cannot simultaneously acquire link status and physical layer signal data, resulting in low efficiency in fault location.

[0058] To address these issues, the R&D team identified core shortcomings in traditional testing tools: functional fragmentation and integration difficulties. By analyzing the programmable characteristics of FPGAs, they proposed integrating multi-dimensional testing functions into a single hardware platform. The design approach includes: utilizing the parallel processing capabilities of FPGAs to achieve synchronous acquisition of link status and physical signals; developing a unified algorithm model for comprehensive analysis; and constructing standardized API interfaces to lower the barrier to entry.

[0059] Based on this, the embodiments of this application provide an FPGA-based PCIe Switch detection method, referring to... Figure 1 The FPGA-based PCIe Switch detection method includes steps S100 to S300, wherein:

[0060] Step S100: Obtain the link status data of the PCIe link through the hardware layer operation of the FPGA; wherein, the link status data includes the current LTSSM status, historical status switching records, link rate and number of active lanes.

[0061] Step S200: Based on the hardware layer operation of the FPGA, detect physical layer signal data; wherein, the physical layer signal data includes bit error rate statistics and inter-channel delay difference data;

[0062] Step S300: Integrate the link status data, bit error rate statistics data, and inter-channel delay difference data, process them using a link stability analysis algorithm, and generate a link stability assessment report.

[0063] In this embodiment, link status data refers to key parameters reflecting the operational status of the PCIe link. Specifically, it can be obtained by reading the status register of the PCIe IP core and is used to identify the real-time status of the link training state machine. Physical layer signal data refers to fundamental indicators characterizing signal transmission quality. Specifically, it can be measured using pseudo-random sequence testing and synchronous sampling circuits to evaluate signal integrity and timing consistency. Link stability analysis algorithms refer to multi-parameter fusion evaluation models. Specifically, a weighted scoring mechanism can be used to process the normalized dataset to quantify link health. The API interface layer refers to standardized function call interfaces, which can be implemented by encapsulating hardware operation instructions to simplify the user interaction process.

[0064] In this embodiment, the FPGA directly accesses the PCIe IP core through hardware logic to obtain LTSSM state machine information, while simultaneously utilizing a built-in test module for bit error rate detection. A multi-channel delay measurement circuit captures the time deviation of each lane signal, and all raw data is preprocessed before being input into the analysis algorithm. This algorithm comprehensively calculates the state switching frequency, bit error rate trend, and delay fluctuations, ultimately generating an evaluation report containing a stability score and alarm prompts. Users can obtain complete diagnostic information by calling standardized API functions without directly manipulating the underlying hardware.

[0065] In this embodiment, status monitoring, signal detection, and intelligent analysis are organically integrated on a single FPGA platform. Traditional methods rely on the closed architecture of dedicated equipment; this solution opens up detection functions through the API interface layer, supports user-defined extensions, reduces the implementation cost of PCIe link detection, and solves the efficiency bottleneck caused by multi-device collaborative operation. Hardware-level data acquisition ensures real-time detection, the comprehensive evaluation model improves fault diagnosis accuracy, and standardized API design simplifies system integration, providing a complete automated detection solution for PCIe device operation and maintenance.

[0066] In one feasible implementation, refer to Figure 2 Step S100 includes steps S110 to S130, wherein:

[0067] Step S110: Obtain the LTSSM status output signal from the PCIe IP core to obtain the original LTSSM status value;

[0068] Step S120: The original LTSSM state value is latched using a shift register latching mechanism to record and store historical state switching data, thereby generating latched historical state data.

[0069] Step S130: Based on the state switching time recorded by the timestamp module, and combined with the latched historical state data, generate complete link state data.

[0070] In this embodiment, the LTSSM state output signal refers to the real-time state signal output by the link training and state management state machine. Specifically, it can be obtained through the state register interface built into the PCIe IP core, reflecting the current negotiation phase or error state of the link. The shift register latching mechanism refers to the sequential storage of state changes using a multi-level register cascade structure. Specifically, it can be implemented using an FPGA internal trigger chain, used to capture the historical trajectory of state transitions. The timestamp module refers to the circuit that generates precise time stamps based on the system clock. Specifically, it can be implemented using an FPGA internal counter in conjunction with a global clock network, used to record the occurrence time of state transition events.

[0071] In this embodiment, during hardware layer operation, the LTSSM status signal is first read in real time through the PCIe IP core's status register interface. This signal directly reflects the status changes during link negotiation in binary encoding. Subsequently, the continuously read status values ​​are input into a shift register chain composed of multiple D flip-flops, with each register corresponding to a historical state storage unit. When a status change is detected, the current state sequence is automatically latched. Simultaneously, a separately running counter module generates a timestamp, recording the current count value at each state transition. Finally, the timestamp data is associated and combined with the latched state sequence to form a complete link state dataset containing the time dimension.

[0072] In this embodiment, state capture and storage are directly implemented through the internal hardware resources of the FPGA, eliminating dependence on external devices. Existing technologies typically only record the current state and cannot trace back historical switching processes. This solution uses a shift register chain to automatically store the state sequence, making historical state tracing possible. Furthermore, this solution achieves precise temporal correlation of state switching events through the coordinated operation of a hardware counter and a state latching mechanism. Thus, this application realizes end-to-end hardware acquisition and storage of link state data, capable of completely recording the time-series information of state switching, providing a high-precision temporal correlation data foundation for subsequent link stability analysis. This solution avoids the time accuracy loss caused by software polling in traditional methods, while ensuring complete capture of state switching events through a hardware latching mechanism.

[0073] In one feasible implementation, refer to Figure 3 Step S110 includes steps S111 to S112, wherein:

[0074] Step S111: Read the LTSSM status output interface of the PCIe IP core through the driver layer to obtain the unprocessed LTSSM status signal;

[0075] Step S112: Encode the unprocessed LTSSM state signal to generate a 5-bit encoded original LTSSM state value.

[0076] In this embodiment, driver layer reading refers to directly accessing the hardware interface of the PCIe IP core through the FPGA's underlying logic. Specifically, this can be implemented using a register access module implemented in a hardware description language to directly acquire the underlying state signals that have not been processed by the software protocol stack. The unprocessed LTSSM state signal refers to the raw level signal output by the IP core, which can be captured using a digital signal sampling circuit to reflect the actual transmission state of the physical layer. Encoding processing refers to converting multiple parallel signals into binary values. Specifically, a state mapping table can be implemented using combinational logic circuits to convert the physical level into a recognizable state code. The 5-bit encoded raw LTSSM state value refers to using a fixed bit width to represent the state type. This can be standardized through a predefined state code table to unify the state representation format across different IP core versions.

[0077] In this embodiment, within the FPGA driver layer, the hardware description language module directly accesses the PCIe IP core's status register via address mapping, capturing the raw level signals containing LTSSM status information in real time. This signal is transmitted to the encoding processing unit via a multiplexer, where lookup table logic maps each signal line combination into a 5-bit binary value. For example, when the IP core outputs three valid level signals, the encoding logic converts them into standardized codes containing states such as detection, configuration, and recovery. The resulting 5-bit status value is then transmitted to the upper-layer processing module via the bus, providing basic data for link status analysis.

[0078] Compared to existing technologies, traditional methods rely on protocol analyzers to indirectly obtain status information by parsing link-layer data packets through software, resulting in response delays and protocol dependencies. This solution directly reads the IP core status interface at the hardware layer, eliminating delays caused by protocol stack processing. Simultaneously, it employs a fixed-width encoding mechanism to standardize the status data format. For example, existing technologies suffer from compatibility issues due to differences in status signal output methods among IP cores from different vendors. This solution, however, unifies the data format through encoding, eliminating the need for upper-layer analysis modules to adapt to different hardware versions.

[0079] Through the above technical solution, this application achieves real-time and accurate capture of PCIe link status, solving the latency problem caused by software protocol parsing in traditional methods. Furthermore, standardized encoding enhances compatibility across different hardware platforms. This solution can be directly integrated into FPGA logic without relying on external testing equipment, reducing system complexity and development costs.

[0080] In one feasible implementation, refer to Figure 4Step S200 includes steps S210 to S240, wherein:

[0081] Step S210: Generate a PRBS pseudo-random sequence through the BERT detection module and perform bit error detection to generate bit error statistics results;

[0082] Step S220: Calculate the real-time bit error rate based on the bit error statistics and the total number of bits, and generate bit error rate statistics.

[0083] Step S230: Measure the edge time difference of each Lane signal through a multi-channel synchronous sampling circuit to generate raw delay difference data;

[0084] Step S240: The original delay difference data is averaged and calibrated to generate inter-channel delay difference data.

[0085] In this embodiment, the PRBS pseudo-random sequence refers to a periodic digital sequence with a specific polynomial structure, which can be implemented using a linear feedback shift register to simulate random data patterns in real transmission scenarios to detect bit errors. Bit error rate statistics refer to calculating the probability of bit errors by comparing the differences between the transmitted and received sequences, which can be implemented using bit-by-bit XOR operations and a counter module to quantify link transmission quality. The multi-channel synchronous sampling circuit refers to a circuit structure capable of simultaneously capturing signal changes from multiple physical channels, which can be implemented using a global clock network and a phase-locked loop to achieve phase alignment and eliminate the impact of sampling clock deviations on delay measurements. Averaging processing refers to performing an arithmetic average of multiple measurement results, which can be implemented using an accumulator and a shift register to suppress random noise interference. Calibration compensation refers to correcting the measurement data based on the known inherent system delay, which can be implemented using a lookup table or a linear regression model to eliminate errors introduced by non-ideal characteristics of the hardware circuit.

[0086] In this embodiment, during the bit error detection stage, the PRBS sequence generator, constructed using FPGA logic resources, generates a test data stream with a specific code pattern and injects it into the link under test. The receiving end compares the transmitted and received data bit by bit using XOR logic units, counts the number of bit errors, and calculates the bit error rate. During the delay difference measurement stage, the multi-channel synchronous sampling circuit utilizes a global clock network to ensure that the sampling clock phases of each channel are consistent, and accurately captures the time difference between the signal edges of adjacent channels using differential delay lines. After the raw measurement data undergoes a sliding window averaging algorithm to eliminate transient interference, offset compensation is performed based on pre-stored calibration parameters, ultimately outputting an accurate inter-channel delay difference value.

[0087] In this embodiment, integrated detection of bit error rate and delay difference is achieved through FPGA hardware logic. Data generation, signal acquisition, and algorithm processing are completed within a single chip, avoiding the time loss and interface compatibility issues caused by multi-device collaborative operation. This solution can simultaneously acquire link bit error rate and channel synchronization indicators, solving the problems of limited functionality and difficult data integration in traditional detection tools. The bit error rate detection module and delay measurement module share a clock source and data processing unit, reducing redundant hardware resource configuration and improving the efficiency of physical layer signal quality assessment. The calibration compensation mechanism effectively eliminates the impact of inherent hardware errors on measurement accuracy, ensuring that the detection results can be directly used for link stability analysis.

[0088] In one feasible implementation, refer to Figure 5 Step S210 includes steps S211 to S213, wherein:

[0089] Step S211: Implement the PRBS sequence generator using FPGA logic resources to generate the transmission sequence data;

[0090] Step S212: Compare the transmitted sequence data with the received sequence data, detect bit errors by bitwise XOR operation, and generate bit error count data;

[0091] Step S213: Based on the number of bit errors and the total number of bits, calculate the number of bits required for the test using the confidence formula, and generate the bit error statistics results.

[0092] In this embodiment, the PRBS sequence generator refers to the hardware module used to generate pseudo-random binary sequences. Specifically, it can be implemented using a linear feedback shift register structure, with a polynomial order of, for example, 31 or 63. The bitwise XOR operation refers to performing a logical XOR operation on corresponding bits at the transmitting and receiving ends. This can be implemented using the parallel logic unit built into the FPGA, processing multiple bits per clock cycle. The number of bit errors refers to the total number of bits whose XOR operation result is 1, which can be counted in real-time using an accumulator module. The confidence formula refers to the test sample size calculation model derived from statistical principles. Specifically, it can use a Poisson distribution or a normal distribution approximation method. For example, when setting the target bit error rate upper limit to 1e-12, it calculates the number of bits that need to be transmitted.

[0093] In this embodiment, the FPGA logic resources are configured to construct a PRBS generator, which continuously outputs a pseudo-random sequence based on a preset polynomial. After the transmitted sequence data is transmitted to the receiving end through the physical layer, it is synchronously compared with a locally generated reference sequence. During the bit error detection phase, each received bit is XORed with its corresponding transmitted bit; when the result is 1, the bit error counter is incremented. The total number of bits is determined by the product of the transmission time and the link rate; for example, at a rate of 5.0 GT / s, 5e9 bits can be transmitted in 1 second. The confidence formula is used to determine the minimum test sample size; when the actual number of transmitted bits reaches the calculated value, the bit error statistics result is considered valid.

[0094] In this embodiment, a complete bit error detection function is implemented using the FPGA's built-in logic resources. Furthermore, by dynamically calculating the number of bits required for testing, testing efficiency is optimized while ensuring statistical validity, thus achieving embedded bit error detection. This eliminates the need for external testing equipment to generate PRBS sequences and perform bit error statistics. Dynamically adjusting test parameters using a confidence formula solves the problems of insufficient statistical confidence or wasted testing time that may exist in traditional fixed-duration tests. The deep integration of the bit error detection process with the FPGA hardware allows the bit error statistics results to be directly output via an API interface, simplifying the testing process.

[0095] In one feasible implementation, refer to Figure 6 Step S230 includes steps S231 to S233, wherein:

[0096] Step S231: Use the FPGA's global clock network and phase-locked loop to achieve synchronous sampling of multi-channel signals and generate the sampled time signal;

[0097] Step S232: Calculate the rising or falling edge time difference between the target Lane signal and other Lane signals based on the differential delay line module, and generate time difference data;

[0098] Step S233: The time difference data is processed in conjunction with the threshold judgment module to generate the original delay difference data.

[0099] In this embodiment, the multi-channel synchronous sampling circuit refers to a hardware structure that uses a unified clock source to align and acquire signals from each channel. Specifically, a global clock network combined with a phase-locked loop can be used to achieve multi-channel clock synchronization, thereby eliminating measurement errors caused by sampling clock offset. The differential delay line module refers to a circuit that measures the difference in arrival time of signal edges through a programmable delay unit. Specifically, it can be implemented using the internal delay line resources of an FPGA, and the time difference between adjacent channel signals can be accurately captured by adjusting the delay step value. The threshold judgment module is a logic unit that filters the validity of the raw time difference data. Specifically, a comparator circuit combined with a preset threshold value can be used to filter noise interference and retain valid delay difference data.

[0100] In this embodiment, the global clock network distributes the master clock signal output from the phase-locked loop to each channel sampling unit, ensuring that all lane signals are synchronously acquired under the same reference. The differential delay line module detects the time difference between the edges of the target lane and the reference lane signals through progressively increasing delay units. When edge overlap is detected, the current delay step number is recorded and converted into time difference data. The threshold judgment module further compares the measured time difference with a preset range. For example, when the time difference exceeds the maximum allowable deviation of the channel, it is marked as invalid data, thereby eliminating abnormal values ​​caused by signal jitter or noise.

[0101] In this embodiment, parallel measurement and real-time filtering of multi-channel delay differences are achieved on a single FPGA platform through an integrated synchronous sampling circuit and digital processing module. This avoids timing errors caused by multi-device collaboration and effectively solves the problem of insufficient accuracy in synchronous measurement of multi-channel signals. Hardware-level clock synchronization ensures sampling consistency, and digital filtering improves the reliability of delay difference data. This solution achieves automated detection of delay characteristics between PCIe link channels without the need for external testing equipment, providing high-precision foundational data for subsequent link stability assessment.

[0102] In one feasible implementation, refer to Figure 7 Step S300 includes steps S310 to S330, wherein:

[0103] Step S310: Integrate the LTSSM state switching frequency in the link status data, the bit error rate trend data in the bit error rate statistics data, and the delay difference fluctuation data in the inter-channel delay difference data to generate a link parameter dataset.

[0104] Step S320: Process the link parameter dataset based on the weighted scoring model to calculate stability score data; wherein, the weighted scoring model uses weight coefficients to weight the bit error rate, latency difference and state switching frequency.

[0105] Step S330: Generate a link stability assessment report based on the stability score data and preset alarm thresholds.

[0106] In this embodiment, the link parameter dataset refers to a structured dataset formed by standardizing and integrating three types of heterogeneous data: link state switching frequency, bit error rate trend, and latency fluctuation. Specifically, this can be implemented using a data format conversion module and a normalization processing unit to eliminate calculation biases between data of different dimensions. The weighted scoring model is a mathematical model that assigns different weight coefficients to the three parameters—bit error rate, latency, and state switching frequency—for linear calculation. Specifically, it can be implemented using a dynamic weight adjustment algorithm to adjust the impact of each parameter on stability assessment according to the actual application scenario. The stability score data refers to the link health index value obtained through quantitative calculation. Specifically, it can be implemented using sliding window statistics and scaling algorithms to map multi-dimensional parameters to a single comparable evaluation result.

[0107] In this embodiment, during the link stability assessment process, the data acquisition module first acquires LTSSM state switching frequency, bit error rate trend data, and latency fluctuation data. This raw data undergoes format conversion before entering the normalization processing unit; for example, the bit error rate is converted to errors per megabit, the latency is converted to nanosecond-level absolute values, and the number of state switching events is converted to frequency values ​​per unit time. The processed standardized data constitutes a link parameter dataset, which is input into a weighted scoring model for calculation. This model can employ a dynamic weight allocation mechanism, for example, assigning higher weight to the bit error rate in high-speed transmission scenarios and higher weight to the latency in long-distance transmission scenarios. The final calculated stability score is compared with a preset threshold. When the score falls below the threshold, an alarm is automatically triggered, and an assessment report containing the score result, abnormal parameter items, and recommended measures is generated.

[0108] In this embodiment, a comprehensive quantitative assessment of link stability is achieved by constructing a multidimensional dataset and a dynamic weighted model. Furthermore, this solution significantly improves diagnostic efficiency and assessment accuracy through automated data processing and scoring calculation. Through the above technical solution, this application solves the technical problem that traditional detection methods cannot comprehensively assess link health status, realizing the collaborative analysis of bit error rate, transmission delay, and link status changes. The dynamic weighting mechanism adapts to the assessment needs of different application scenarios, accurately identifying key factors leading to link instability. The generated standardized assessment report can be directly used for system maintenance decisions, avoiding the workload of manually analyzing multiple independent detection data.

[0109] In one feasible implementation, refer to Figure 8 Step S320 includes steps S321 to S323, wherein:

[0110] Step S321: Perform sliding window statistical processing on the bit error rate trend data to generate a normalized bit error rate value;

[0111] Step S322: Perform proportional scaling on the delay difference fluctuation data to generate a normalized delay difference value;

[0112] Step S323: Combine the normalized bit error rate value, normalized delay difference value and LTSSM state switching frequency data to obtain stability score data through weighted calculation.

[0113] In this embodiment, sliding window statistical processing refers to periodically calculating the bit error rate trend data by setting a data window of fixed length. Specifically, a window with a length of 1000 sampling points can be used to perform moving average processing on the bit error rate data, thereby eliminating the impact of instantaneous fluctuations on the evaluation results. Scaling processing refers to mapping the delay difference fluctuation data to a preset numerical range. Specifically, a linear transformation can be used to convert the original delay difference value into a normalized value within the range of 0 to 1, allowing data of different dimensions to be weighted for calculation. Weighted calculation refers to assigning different weight coefficients to the normalized bit error rate, delay difference, and state switching frequency data. Specifically, a weighted sum can be performed with a bit error rate weight coefficient of 0.5, a delay difference weight coefficient of 0.3, and a state switching frequency weight coefficient of 0.2, ultimately generating stability score data.

[0114] In this embodiment, the bit error rate trend data, after undergoing sliding window statistical processing, reflects the stability change trend of the link over time, avoiding interference from single-point bit error anomalies on the evaluation results. Delay difference fluctuation data is converted into a uniform-dimensional value through scaling, facilitating weighted calculations with the bit error rate data. LTSSM state switching frequency data is directly used as the input parameter for weighted calculations, reflecting the state stability of the link protocol layer. During the weighted calculation process, the weight coefficients of each parameter can be dynamically adjusted according to the actual application scenario; for example, increasing the weight of the bit error rate in high-speed transmission scenarios and increasing the weight of the delay difference in low-latency scenarios.

[0115] In this embodiment, through normalization and weighted calculation, this application can effectively integrate multi-dimensional data such as bit error rate, latency difference and state switching frequency, and transform indicators of different dimensions into comparable and operable stability scoring data. This solves the problem of incomplete evaluation caused by functional dispersion in the prior art and improves the efficiency and reliability of PCIe link detection.

[0116] In one feasible implementation, the method further includes encapsulating the link stability assessment report into a standardized function output via an API interface layer for user invocation. In this embodiment, the API interface layer refers to an intermediate layer connecting software functional modules and external calling programs. Specifically, it can be implemented using a RESTful interface or a dynamic link library, and its function is to hide underlying implementation details and standardize data interaction formats. A standardized function refers to a callable program unit with predefined input parameters and return formats, which can be implemented by defining function prototypes and parameter type constraints. Its function is to reduce user call complexity and improve interface compatibility.

[0117] In this embodiment, after generating the link stability assessment report, the report data is converted into a JSON or XML structured format and encapsulated into a calling interface with a fixed function name and parameter list through the API interface layer. Users can directly obtain the assessment results by calling this standardized function without needing to understand the underlying data acquisition and analysis logic. For example, the function can be designed as `get_link_stability_report(device_id)`, where the `device_id` parameter specifies the target PCIeSwitch device identifier, and the function returns an analysis report containing link score, alarm status, and detailed parameters.

[0118] In some specific implementations, the API interface layer can integrate an authentication mechanism to ensure call security through key verification. Standardized functions support both synchronous and asynchronous calling modes; in asynchronous mode, processing results are returned via callback functions. In this embodiment, standardized function encapsulation decouples the detection function from the user program, and predefined interfaces enable automated data interaction, reducing manual intervention. This approach allows third-party developers to easily call the link evaluation function, and the standardized interface design lowers the user learning cost, enabling rapid integration of the detection function with upper-layer applications and improving system integration efficiency.

[0119] In the embodiments of this application, the FPGA-based PCIe Switch detection method proposed in this application generates a comprehensive evaluation report by integrating link status data, bit error rate statistics and inter-channel delay difference data, and uses the API interface layer to achieve standardized output. It has low cost and can achieve multi-dimensional comprehensive link status detection through simple operation.

[0120] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the FPGA-based PCIeSwitch detection method of this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0121] This application also provides an FPGA-based PCIe Switch detection system, referenced... Figure 9 The system includes: a memory, a processor, and an FPGA-based PCIe Switch detection program stored in the memory and executable on the processor. The FPGA-based PCIe Switch detection program is configured to implement the steps of the FPGA-based PCIe Switch detection method.

[0122] The FPGA-based PCIe Switch detection system provided in this application employs the FPGA-based PCIe Switch detection method described in the above embodiments, enabling simple operation and comprehensive multi-dimensional link status detection. Compared with the prior art, the beneficial effects of the FPGA-based PCIe Switch detection system provided in this application are the same as those of the FPGA-based PCIe Switch detection method provided in the above embodiments, and other technical features of the FPGA-based PCIe Switch detection system are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0123] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0124] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. All equivalent structural transformations made under the technical concept of this application using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the scope of patent protection of this application.

Claims

1. A method for detecting a PCIe switch based on FPGA, characterized in that, The method comprises: Obtaining link state data of a PCIe link through hardware layer operation of an FPGA; wherein the link state data comprises a current LTSSM state, a historical state switching record, a link rate and an active Lane number; Detecting physical layer signal data based on the hardware layer operation of the FPGA; wherein the physical layer signal data comprises error code rate statistical data and inter-channel delay difference data; Integrating the link state data, the error code rate statistical data and the inter-channel delay difference data, processing through a link stability analysis algorithm, and generating a link stability evaluation report; The step of obtaining the link state data of the PCIe link through the hardware layer operation of the FPGA comprises: Obtaining an LTSSM state output signal from a PCIe IP core to obtain an original LTSSM state value; Using a shift register latching mechanism to latch the original LTSSM state value to generate latched historical state data; Recording state switching time based on a timestamp module, and combining the latched historical state data to generate complete link state data; The step of obtaining the LTSSM state output signal from the PCIe IP core to obtain the original LTSSM state value comprises: Reading an LTSSM state output interface of the PCIe IP core through a driver layer to obtain an untreated LTSSM state signal; Encoding the untreated LTSSM state signal to generate a 5-bit encoded original LTSSM state value.

2. The method of claim 1, wherein the PCIe Switch detection method is based on FPGA, and The step of detecting the physical layer signal data based on the hardware layer operation of the FPGA comprises: Generating a PRBS pseudo-random sequence through a BERT detection module and performing error code detection to generate error code statistical results; Calculating a real-time error code rate based on the error code statistical results and a total number of bits to generate error code rate statistical data; Measuring edge time differences of Lane signals through a multi-channel synchronous sampling circuit to generate delay difference original data; Performing average processing and calibration compensation on the delay difference original data to generate inter-channel delay difference data.

3. The method of claim 2, wherein the PCIe Switch detection method is based on FPGA, and wherein the method further comprises: The step of generating the PRBS pseudo-random sequence through the BERT detection module and performing error code detection to generate the error code statistical results comprises: Implementing a PRBS sequence generator through FPGA logic resources to generate transmission sequence data; Comparing the transmission sequence data with reception sequence data, detecting error codes through bit-by-bit XOR operation, and generating error code number data; Calculating a number of required bits for testing based on the error code number data and the total number of bits, combining a confidence formula to generate error code statistical results.

4. The method of claim 2, wherein the PCIe Switch detection method is based on FPGA, and The step of measuring edge time differences of Lane signals through the multi-channel synchronous sampling circuit to generate delay difference original data comprises: Implementing multi-channel signal synchronous sampling through a global clock network and a phase-locked loop of an FPGA to generate sampled time signals; Calculating rising edge or falling edge time differences between a target Lane signal and other Lane signals based on a differential delay line module to generate time difference data; Processing the time difference data through a threshold judgment module to generate delay difference original data.

5. The method of claim 1, wherein the method further comprises: The step of integrating the link state data, the bit error rate statistical data and the inter-channel delay difference data, processing by a link stability analysis algorithm, and generating a link stability evaluation report comprises: Integrating the LTSSM state switching frequency in the link state data, the bit error rate trend data in the bit error rate statistical data, and the delay difference fluctuation data in the inter-channel delay difference data, and generating a link parameter data set; Processing the link parameter data set based on a weighted scoring model, and calculating stability score data; wherein the weighted scoring model uses a weight coefficient to weight and calculate the bit error rate, the delay difference and the state switching frequency; Generating a link stability evaluation report according to the stability score data and a preset alarm threshold.

6. The method of claim 5, wherein the PCIe Switch detection method is based on FPGA, and The step of processing the link parameter data set based on the weighted scoring model and calculating the stability score data comprises: Performing sliding window statistical processing on the bit error rate trend data to generate a normalized bit error rate value; Performing proportional scaling processing on the delay difference fluctuation data to generate a normalized delay difference value; Combining the normalized bit error rate value, the normalized delay difference value and the LTSSM state switching frequency data, and obtaining the stability score data through weighted calculation.

7. The method of claim 5, wherein the PCIe Switch detection method is based on FPGA, and wherein the method further comprises: determining whether the PCIe Switch is a PCIe Switch based on FPGA. The method further comprises encapsulating the link stability evaluation report as a standardized function output through an API interface layer for user calling.

8. A PCIe Switch detection system based on FPGA, characterized in that, The system comprises a memory, a processor, and a FPGA-based PCIe Switch detection program stored on the memory and executable on the processor, and the FPGA-based PCIe Switch detection program is configured to implement the steps of the FPGA-based PCIe Switch detection method according to any one of claims 1 to 7.

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