Universal serial bus host and device rate adaptation method and baseboard management controller

Abstract

The invention discloses a universal serial bus host and equipment rate adaptation method and a baseboard management controller, and relates to the technical field of baseboard management controller design. The circuit of the host physical layer and the circuit of the equipment physical layer both comprise a state machine and only comprise digital circuits, and do not comprise analog circuits, so that the structure of the physical layer is simplified, and the area of the substrate management controller occupied by the physical layer is reduced; secondly, the equipment state machine determines the current state of the equipment state machine according to the signal sent by the equipment controller, and determines data line signals (such as a data positive signal, a data negative signal and a chirp signal) based on the current state and a pre-established mapping relation between the state of the equipment state machine and the data line signals; therefore, the host controller determines the rate state of the equipment controller based on the data line signal output by the equipment physical layer, namely the identification of the equipment rate is realized; and thirdly, the rates of the host and the equipment are matched, so that the compatibility of communication between the USB host and the USB equipment is ensured.

Description

Technical Field

[0001] This invention relates to the field of board management controller design technology, and in particular to a universal serial bus host and device rate adaptation method and a board management controller. Background Technology

[0002] Universal Serial Bus (USB) is a high-speed universal serial bus used to connect computers and various external devices. USB supports multiple device modes, such as USB 2.0 supporting high speed (480 Mbps), backward compatible with USB 1.1 full speed (12 Mbps) and USB 1.0 low speed (1.5 Mbps). To ensure compatibility between USB hosts and USB devices, the host speed and device speed need to be matched. This matching process requires identifying the host speed and device speed.

[0003] When rate identification is performed, both the host's physical layer (PHY) and the device's PHY utilize digital and analog circuits to identify the host and device rates. Because digital and analog circuits require space, the PHY's baseboard management controller occupies a relatively large area and has a complex design.

[0004] Therefore, how to reduce the area occupied by the PHY on the board management controller and use the simplified PHY to identify the host speed and device speed in order to achieve speed matching between the host and the device is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a method for adapting the speed of a universal serial bus host and a baseboard management controller, to solve the problem that both the host and device physical layers use digital and analog circuits to identify the host and device speeds. Because digital and analog circuits require space, the baseboard management controller in the physical layer occupies a relatively large area and has a complex design.

[0006] To address the aforementioned technical problems, this invention provides a Universal Serial Bus (USB) host and device rate adaptation method, applied to a host controller in a baseboard management controller. The baseboard management controller includes a USB host and USB devices. Both the host physical layer and device physical layer circuits consist only of digital circuits, and both the host physical layer and device physical layer also include a state machine. The method includes:

[0007] In response to the data line signal output by the device physical layer, the current rate state of the device controller is determined based on the data line signal; wherein the data line signal includes at least a positive data signal, a negative data signal, and a chirp signal; the data line signal is determined by the device state machine based on the signal sent by the device controller to determine its current state, and based on the current state and a pre-established mapping relationship between the state of the device state machine and the data line signal;

[0008] The current rate state of the device controller and the current rate state of the host state machine are both determined according to the current rate state of the device controller.

[0009] Information used to characterize the state of the control device state machine as the current rate state is sent to the device state machine, so that the device state machine controls its own state to the current rate state according to the information.

[0010] The beneficial effects of this invention are as follows: First, in this method, the baseboard management controller includes a Universal Serial Bus (USB) host and a USB device. Both the host physical layer circuit and the device physical layer circuit include state machines and only digital circuits, excluding analog circuits. Since the state machine is mainly composed of digital logic, it can be implemented using simple flip-flops and combinational logic. Analog circuits, on the other hand, require complex transistors and components to process continuously changing signals. Therefore, the state machine typically occupies less area in the baseboard management controller than the analog circuit. This simplifies the structure of the host physical layer and the device physical layer, reducing the area occupied by the physical layers in the baseboard management controller. Second, since analog circuits are not used, in this method, the device state machine determines its current state based on the signals sent by the device controller, and based on the current state and... The pre-established mapping relationship between the device state machine state and the data line signals determines the data line signals (such as positive data signals, negative data signals, and chirp signals). This allows the host controller to determine the device controller's rate state based on the data line signals output by the device's physical layer, thus achieving device rate identification. Furthermore, after determining the device controller's current rate state based on the data line signals, the host controller adjusts itself and the host state machine to the same rate state as the device. Then, the device state machine adjusts itself to the same state based on the signals sent by the host controller. This ensures the consistency of the host controller rate, host state machine rate, device state machine rate, and device controller rate, achieving rate matching between the host and the device, thereby ensuring the compatibility of communication between the USB host and USB device.

[0011] Furthermore, before responding to the data line signal output by the device's physical layer and determining the current rate state of the device controller based on the data line signal, the host state machine changes from the initial state to the first state based on the detected host controller signal, and the device state machine changes from the initial state to the first sub-state or from the initial state to the second sub-state based on the detected device controller signal, thus achieving accurate adjustment of the host state machine state and the device state machine state before the host and device handshake; the host state machine changes from the first state to the second state based on the detected host controller signal, and the device state machine changes from the state to the first sub-state to the third sub-state based on the detected device controller signal, or the device state machine changes from the second sub-state to the third sub-state based on the detected device controller signal, thus achieving the handshake between the host and the device; the host state machine changes from the second state to the third state based on the detected host controller signal, and the device state machine changes from the third sub-state to the fourth sub-state based on the detected device controller signal, thus realizing that the control device is in the speed detection state.

[0012] When determining the current speed state of the device controller based on the data line signal, if the values ​​of the positive and negative data signals in the data line signal are both at a first preset value, the device is determined to be in a first speed state; if the values ​​of the positive and negative data signals are both at a second preset value, the device is determined to be in a second or third speed state. Since the first speed is less than the third speed, and the third speed is less than the second speed, the first speed state is called the low-speed state, the third speed state is called the high-speed state, and the second speed state is called the full-speed state. This achieves the judgment that the device controller is in a low-speed state, or preliminarily determines that the device controller is in a full-speed or high-speed state.

[0013] When the device is in the first speed state (i.e., low speed state), the host controller adjusts its own speed to low speed state through its speed adjustment module. The host state machine controls itself to jump from the third state to the low speed state according to the host controller's signal. The device state machine controls itself to jump from the first sub-state to the low speed state according to the host controller's signal. This achieves that the device controller, host controller, host state machine and device state machine are all in the low speed state, that is, the speed matching between the device and the host is achieved when the device is in the low speed state.

[0014] If the current rate state of the device controller is determined to be either the second or third rate state, before both the device controller's current rate state and the host state machine's rate state are in the current rate state, the host state machine controls itself to change from the third state to the fourth state based on a valid signal from the host controller's representation data, and outputs a chirp signal to the device controller, enabling the device controller to perform chirp state detection based on the chirp signal. If the host state machine receives an invalid signal from the host controller's representation data, it controls itself to change from the fourth state to the fifth state. This indicates that the host state machine has confirmed that the device controller is in the third rate state (i.e., the high-speed state), thus achieving the determination that the device controller is in the high-speed state.

[0015] After determining that the device controller is in the third rate state (i.e., high-speed state), the host controller adjusts its own rate to the high-speed state through its own rate adjustment module. The host state machine controls itself to jump from the fifth state to the high-speed state according to the host controller's signal. The device state machine controls itself to jump from the fifth sub-state to the high-speed state according to the host controller's signal. This achieves that the device controller, host controller, host state machine, and device state machine are all in the high-speed state, that is, the device and host rates are matched when the device is in the high-speed state.

[0016] After outputting a chirp signal to the device controller, if no signal representing the response to the chirp signal is received from the device state machine within a preset time period from the start of outputting the chirp signal to the device controller, the device is determined to be in the second speed state (i.e., full speed state), thus realizing the judgment that the device controller is in the full speed state.

[0017] After determining that the device controller is in the second speed state (i.e., full speed state), the host controller adjusts its own speed to the full speed state through its speed adjustment module. The host state machine controls itself to jump from the fourth state to the full speed state according to the host controller's signal. The device state machine controls itself to jump from the fourth sub-state to the full speed state according to the host controller's signal. This achieves that the device controller, host controller, host state machine, and device state machine are all in the full speed state, that is, the speed matching between the device and the host is achieved when the device is in the full speed state.

[0018] When both the host and the device are in high-speed mode, in the scenario where the host is suspended, the device controller, device state machine, and host state machine all change from high-speed mode to full-speed mode, thus achieving speed matching between the host and the device.

[0019] When both the host and the device are operating at high speed, in scenarios where bit stuffing and NRZI encoding are disabled on the host, the device controller transitions from high speed to the chirped state; the host state machine transitions from the high speed state to the state machine indicating that the device is in the speed detection state; and the device state machine transitions from the high speed state to the state machine indicating that the device controller has entered the chirped state, thus achieving speed matching between the host and the device.

[0020] When both the host and the device are at full speed, in the scenario of host wake-up, the device controller, device state machine and host state machine all change from full speed to high speed, thus achieving speed matching between the host and the device.

[0021] When both the host and the device are at full speed, in scenarios where bit stuffing and NRZI encoding are disabled on the host, the host controller transitions from the full-speed state to the chirped state; the host state machine transitions from the full-speed state to the state machine requiring the device to be in the speed detection state; the device state machine transitions from the full-speed state to the state machine requiring the device to be in the speed detection state, thus achieving speed matching between the host and the device.

[0022] In addition, the present invention also provides a baseboard management controller that has the same or corresponding technical features as the aforementioned Universal Serial Bus host and device rate adaptation method, and has the same effect. Attached Figure Description

[0023] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 A schematic diagram of the internal USB 2.0 module structure of a baseboard management controller provided in an embodiment of the present invention;

[0025] Figure 2 A schematic diagram of a baseboard management controller provided in an embodiment of the present invention;

[0026] Figure 3 A flowchart illustrating a method for rate adaptation between a universal serial bus host and a device, provided in an embodiment of the present invention;

[0027] Figure 4 A schematic diagram illustrating the state changes of the host state machine in a rate identification and matching process provided in an embodiment of the present invention;

[0028] Figure 5 A schematic diagram illustrating the state changes of a device state machine in a rate identification and matching process provided in an embodiment of the present invention;

[0029] Figure 6 This is a structural diagram of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0031] The core of this invention is to provide a method for adapting the speed of a universal serial bus host and a baseboard management controller, in order to solve the problem that both the physical layer of the host and the physical layer of the device use digital and analog circuits to identify the host speed and device speed. Because digital and analog circuits require space, the baseboard management controller occupied by the physical layer has a relatively large area and a complex design.

[0032] USB 2.0 is a high-speed universal serial bus that can be used to connect computers and various external devices. USB 2.0 supports high speed (480Mbps) and is backward compatible with USB 1.1 full speed (12Mbps) and USB 1.0 low speed (1.5Mbps). Figure 1 The diagram below illustrates the internal USB 2.0 module structure of a baseboard management controller according to an embodiment of the present invention. Figure 1As shown, it comprises a central processing unit (CPU) 1, a baseboard management controller internal interconnect bus 2 (i.e., a USB 2.0 controller), a high-speed universal serial bus controller 3 (i.e., a USB 2.0 PHY), and a high-speed universal serial bus physical layer 4. The high-speed universal serial bus controller internally includes registers and memory. The baseboard management controller internal interconnect bus is connected to the high-speed universal serial bus controller via a control bus and a data bus; the baseboard management controller internal interconnect bus is connected to the high-speed universal serial bus physical layer via a control bus. The USB 2.0 module inside the baseboard management controller typically consists of a USB 2.0 controller and a USB 2.0 PHY. The USB 2.0 controller primarily assembles and disassembles data according to the USB 2.0 protocol and interacts with the USB 2.0 PHY via the USB 2.0 Transceiver Macrocell Interface (UTMI). The USB 2.0 PHY is typically implemented using both digital and analog circuitry. Its main function is to convert the USB 2.0 protocol data stream from digital signals to analog signals for transmission over the USB cable; to convert parallel data sent from the USB 2.0 controller via the UTMI interface into serial data, which is then output to the external board management controller via USB 2.0 differential data lines (data transmission); and to receive serial data via the USB 2.0 differential data lines of the board management controller, converting the serial data into parallel data and sending it back to the USB 2.0 controller via the UTMI interface (data reception). The USB 2.0 PHY also has a rate identification function, capable of identifying USB 2.0 low-speed, full-speed, and high-speed devices.

[0033] In KVM (Keyboard Video Mouse) applications, a USB 2.0 device is needed to map a remote USB 2.0 device. If the entire KVM functionality is implemented using a single baseboard management controller, the USB 2.0 host controller, USB 2.0 PHY, USB 2.0 device controller, and USB 2.0 PHY all need to be integrated into this single controller. This requires integrating two USB 2.0 PHYs within the baseboard management controller. Since the interface between the USB 2.0 host controller and the USB 2.0 PHY is a UTMI interface, and the interface between the USB 2.0 device controller and the USB 2.0 PHY is also a UTMI interface, removing the two USB 2.0 PHYs and replacing them with two UTMI-interface USB 2.0 digital PHYs (in this embodiment, a PHY containing only digital circuitry is referred to as a digital PHY) can solve the problem of the USB 2.0 PHY occupying a large area of ​​the baseboard management controller and having a complex design. The 2.0 digital PHY is implemented solely with digital logic, eliminating the need for analog circuitry. It occupies a small area in the board management controller and is easy to design, making it an ideal solution for implementing KVM functionality with a single board management controller.

[0034] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Figure 2 This is a schematic diagram of a baseboard management controller provided in an embodiment of the present invention, as shown below. Figure 2 As shown, the system includes: a baseboard management controller comprising a Universal Serial Bus (USB) host and a USB device. Both the host physical layer and the device physical layer circuits consist only of digital circuits; the host physical layer is referred to as the host digital physical layer 6, and the device physical layer as the device digital physical layer 7. The USB host includes a host controller 5 and a host digital physical layer 6; the USB device includes a device controller 8 and a device digital physical layer 7. Both the host physical layer and the device physical layer also include state machines. To distinguish between the state machines in the host and the state machines in the device, in this embodiment, the state machine in the host is referred to as the host state machine, and the state machine in the device is referred to as the device state machine. The host controller is connected to the host digital physical layer via a transceiver macrocell interface. The host digital physical layer includes a host state machine (a state machine used for host rate identification) and digital circuits (digital circuits in...). Figure 2(Not shown in the image), the device controller connects to the device's digital physical layer via a transceiver macrocell interface. The device's digital physical layer includes a device state machine (a state machine used for device rate identification) and digital circuits (digital circuits in...). Figure 2 (Not shown in the diagram). Data positive (DP) signals, data negative (DM) signals, data (Data), and data valid (Txvalid) signals are transmitted between the host digital physical layer and the device digital physical layer. In the USB 2.0 speed identification system, the USB 2.0 host digital PHY is the primary controller, and the USB 2.0 device digital PHY is secondary. Furthermore, the signals they need to monitor and the specific processes they execute are different. Therefore, separate state machines need to be designed for the USB 2.0 host digital PHY and the USB 2.0 device digital PHY, and different processes need to be executed to perform USB 2.0 speed identification. Additionally, it is worth noting that the server where the baseboard management controller resides is usually located in a server room. The devices configured in the baseboard management controller are not actual remote devices, but rather devices with the same speed as the remote devices. Devices with the same speed as the remote devices are placed in the baseboard management controller. Furthermore, to distinguish between the states of the host state machine and the states of the device state machine, in this invention, the states of the host state machine are described as states, and the states of the device state machine are described as sub-states.

[0035] Figure 2 The example only demonstrates the interaction between one host and one device in the baseboard management controller. In practice, it can be expanded to allow the host to interact with multiple devices, achieving rate matching between the host and multiple devices. Based on Figure 2 The illustrated baseboard management controller, in which the Universal Serial Bus host and device rate adaptation method provided by this invention is applied to the host controller in the baseboard management controller. Figure 3 A flowchart illustrating a method for rate adaptation between a universal serial bus host and device, provided as an embodiment of the present invention. Figure 3 As shown, the method includes:

[0036] S10: Responds to the data line signal output by the device physical layer and determines the current rate state of the device controller based on the data line signal;

[0037] The data line signals include at least a positive data (DP) signal, a negative data (DM) signal, and a chirp K / J signal. The data line signals are determined by the device state machine based on the signals sent by the device controller to determine its current state, and based on the current state and the pre-established mapping relationship between the device state machine's state and the data line signals.

[0038] S11: Based on the current rate state of the device controller, both the rate state of the device itself and the rate state of the host state machine are the current rate state.

[0039] S12: Send the information used to characterize the state of the control device state machine as the current rate state to the device state machine, so that the device state machine can control its own state to the current rate state according to the information.

[0040] According to the UTMI interface protocol V1.0, Table 1 shows the USB 2.0 HOST speed correspondence table. Table 2 shows the USB 2.0 DEVICE speed correspondence table. Based on the correspondence of xcvrselect (transceiver selection), termselect (terminal selection), opmode (operation mode), and low speed, full speed, high speed, and chirp, the respective speed identification state machines of the USB 2.0 HOST digital PHY and USB 2.0 DEVICE digital PHY are designed.

[0041] Table 1 lists the modes as low-speed mode, full-speed mode, high-speed mode, and chirped mode. When xcvrselect is 10 and termselect is 1, the host is in low-speed mode; when xcvrselect is 01 / 11 and termselect is 1, the host is in full-speed mode; when xcvrselect is 00, termselect is 0, and opmode is 00 / 01 / 11, the host is in high-speed mode; and when xcvrselect is 00, termselect is 0, and opmode is 10, the host is in chirped mode.

[0042] Table 1

[0043]

[0044] Table 2 lists the modes as low-speed mode, full-speed mode, high-speed mode, and chirped mode. When xcvrselect is 10 and termselect is 1, the device is in low-speed mode; when xcvrselect is 01 / 11 and termselect is 1, the device is in full-speed mode; when xcvrselect is 00 and termselect is 0, the device is in high-speed mode; and when xcvrselect is 00 and termselect is 1, the device is in chirped mode.

[0045] Table 2

[0046]

[0047] Before performing device rate identification, that is, before responding to the data line signal output by the device physical layer and determining the current rate state of the device controller based on the data line signal, the following steps are also included:

[0048] In response to the detection signal sent by the host state machine when it is in the initial state;

[0049] A response signal, used to characterize the response detection signal, is sent to the host state machine so that when the host state machine detects that the response signal is a preset response signal, it controls its own state to jump from the initial state to the first state; wherein, the first state indicates that the host state machine confirms that the host controller is in the state corresponding to the preset response signal.

[0050] For the host side (host controller and host state machine), the initial state is usually the reset or power-on completed state. The initial state corresponds to the DP / DM output of the USB 2.0 HOST digital PHY being 0. When the host state machine is in the initial state, if the host's preset response signal is detected as: xcvrselect[0]=1'b1 && termselect=1'b1 && opmode=2' b00, the host state machine will jump from the initial state to the state machine confirming that the host is in the full-speed state (i.e., the first state).

[0051] Before responding to the data line signal output by the device physical layer and determining the current rate state of the device controller based on the data line signal, the method further includes:

[0052] The device controller responds to a detection signal sent by the device state machine when the device state machine is in its initial state; it sends a response signal characterizing the response to the detection signal to the device state machine, so that if the device state machine detects that the response signal is a first preset response signal, it controls its own state to jump from the initial state to a first sub-state; if it detects that the response signal is a second preset response signal, it controls its own state to jump from the initial state to a second sub-state; wherein, the first sub-state characterizes the device state machine's confirmation that the device controller is in the state corresponding to the first preset response signal; the second sub-state characterizes the device state machine's confirmation that the device controller is in the state corresponding to the second preset response signal.

[0053] For the device side (device controller and device state machine), the device state machine is in the initial state, which corresponds to the USB 2.0 DEVICE digital PHY not outputting signals via DP / DM.

[0054] When the device state machine is in the initial state, if the first preset response signal of the device controller is detected as dppulldown=0 &&dmpulldown=0 && xcvrselect[0]=1' b1 && termselect=1' b1, then the device state machine will jump from the initial state to the device state machine confirming that the device is in the full-speed state (i.e., the first sub-state). The first sub-state corresponds to the DP / DM of the USB 2.0 DEVICE digital PHY not outputting signals.

[0055] When the device state machine is in the initial state, if the second preset response signal of the device controller is detected as dppulldown=0 && dmpulldown=0 && xcvrselect=2' b10 && termselect=1' b1, the device state machine will jump from the initial state to the device state machine confirming that the device is in a low-speed state (i.e., the second sub-state). The second sub-state corresponds to the USB 2.0 DEVICE digital PHY not outputting signals on DP / DM.

[0056] In this method, the host state machine changes from an initial state to a first state based on the detected signal from the host controller, and the device state machine changes from an initial state to a first sub-state or from an initial state to a second sub-state based on the detected signal from the device controller, thus achieving accurate adjustment of the host state machine state and the device state machine state before the host and device handshake.

[0057] Before rate identification, the host needs to handshake with the device. Therefore, before responding to the data line signal output by the device's physical layer and determining the current rate state of the device controller based on the data line signal, the method further includes:

[0058] In response to the detection signal sent when the host state machine is in the first state;

[0059] The response signal, which characterizes the response detection signal, is sent to the host state machine so that when the host state machine detects that the response signal is a control signal of a preset pull-down resistor, it controls its own state to jump from the first state to the second state; wherein, the second state characterizes the state of the host state machine controlling the handshake between the host physical layer and the device physical layer.

[0060] The device controller responds to the detection signal sent by the device state machine in the first sub-state; it sends a response signal to the device state machine to characterize the response to the detection signal, so that when the device state machine detects that the response signal is a preset operation mode signal, it controls its own state to jump from the first sub-state to the third sub-state and outputs the first data line signal; wherein, the third sub-state characterizes the handshake state between the device state machine control host physical layer and the device physical layer.

[0061] The device controller responds to the detection signal sent when the device state machine is in the second sub-state; it sends a response signal, which characterizes the response to the detection signal, to the device state machine so that when the device state machine detects that the response signal is a preset operation mode signal, it controls its own state to jump from the second sub-state to the third sub-state and outputs the second data line signal.

[0062] Specifically, for the host side, when the host state machine is in the first state, it detects the control signal of the host controller's preset pull-down resistor as dppulldown=1'b1&& dmpulldown=1'b1, and then the host state machine jumps from the first state to the second state (i.e., the host state machine controls the handshake between the host physical layer and the device physical layer). For the device side, when the device state machine is in the first sub-state, it detects the device controller's preset operation mode signal as opmode =2'b00, and then the device state machine controls its own state to jump from the first sub-state to the third sub-state (i.e., the device state machine controls the handshake between the host physical layer and the device physical layer), and outputs the first data line signal. The DP output of the USB 2.0 DEVICE digital PHY is 1, and the DM output is 0. When the device state machine is in the second sub-state, if the device state machine detects that the preset operation mode signal of the device controller is opmode =2' b00, the device state machine controls its own state to jump from the second sub-state to the third sub-state (that is, the state of the device state machine controlling the host physical layer and the device physical layer to handshake), and outputs the second data line signal. The DP output of the USB 2.0 DEVICE digital PHY is 0 and the DM output is 1.

[0063] In this method, the host state machine changes from a first state to a second state based on the detected signal from the host controller, and the device state machine changes from a state to a first sub-state to a third sub-state based on the detected signal from the device controller, or the device state machine changes from a second sub-state to a third sub-state based on the detected signal from the device controller, thus realizing the handshake between the host and the device.

[0064] After the host and device handshake, the host sends a rate identification command to the device. In implementation, after the device controller transitions its state from the initial state to the third sub-state, and before responding to the data line signal output by the device's physical layer and determining the current rate state of the device controller based on the data line signal, the following steps are also included:

[0065] In response to a detection signal sent when the host state machine is in the second state;

[0066] The response signal, which characterizes the response detection signal, is sent to the host state machine so that when the host state machine detects that the response signal is a preset response signal, it controls its own state to jump from the second state to the third state; wherein, the third state characterizes the host state machine to put the device into the speed detection state;

[0067] In response to a detection signal sent when the device state machine is in the third sub-state;

[0068] The response signal, which characterizes the response detection signal, is sent to the device state machine so that when the device state machine detects that the response signal is a preset response signal, it controls its own state to jump from the third sub-state to the fourth sub-state; wherein, the fourth sub-state indicates that the device state machine puts the device into the speed detection state.

[0069] On the host side, when the host state machine is in the second state, if the host state machine detects the host controller's preset response signal as xcvrselect=2' b00 && termselect=1'b0&&opmode=2' b10, the host state machine will jump from the second state to the third state (i.e., the host state machine wants the device to be in the speed detection state).

[0070] On the device side, when the device state machine is in the third sub-state, the host controller sends a response signal, which represents the response detection signal, to the device state machine. This allows the device state machine to transition from the third sub-state to the fourth sub-state (i.e., the device state machine puts the device into speed detection mode) when it detects a preset response signal from the host (xcvrselect=2' b00 && termselect=1' b0). In this state, the fourth sub-state corresponds to the USB 2.0 DEVICE digital PHY not outputting any DP / DM signals.

[0071] In this method, the host state machine changes from the second state to the third state based on the detected signal from the host controller, and the device state machine changes from the third sub-state to the fourth sub-state based on the detected signal from the device controller, thus realizing the control of the device to be in the speed detection state.

[0072] After the control device enters the speed detection state, the speed is identified. In implementation, determining the current speed state of the device controller based on the data line signal includes:

[0073] If the values ​​of the positive and negative data signals in the data line signal are detected to be the first preset values, then the current rate state of the device controller is determined to be the first rate state.

[0074] If the values ​​of the positive and negative data signals in the data line are detected to be the second preset values, then the current rate state of the device controller is determined to be either the second rate state or the third rate state; wherein the first rate is less than the third rate, and the third rate is less than the second rate.

[0075] Since the first speed is less than the third speed, and the third speed is less than the second speed, the first speed state is called the low-speed state, the third speed state is called the high-speed state, and the second speed state is called the full-speed state. If the values ​​of the positive and negative data signals are the first preset values ​​(DP=0, DM=1), then the current speed state of the device controller is determined to be the first speed state (i.e., low-speed state). If the values ​​of the positive and negative data signals are the second preset values ​​(DP=1, DM=0), then the current speed state of the device controller is determined to be either the second speed state (full-speed state) or the third speed state (high-speed state).

[0076] This method enables the determination of whether the device controller is in a low-speed state, or to preliminarily determine whether the device controller is in a full-speed or high-speed state.

[0077] After determining that the device controller is in a low-speed state, in order to achieve low-speed matching between the host and the device, in practice, when it is determined that the current speed state of the device controller is the first speed state, the speed state of the device controller and the speed state of the host state machine are both set to the current speed state, including:

[0078] The module within the controller that performs rate adjustment adjusts its own rate to the first rate state.

[0079] When it is in the first rate state, it responds to the detection signal sent when the host state machine is in the third state;

[0080] The response signal, which characterizes the response detection signal, is sent to the host state machine so that when the host state machine detects that the response signal is a response signal characterizing that the host controller is in the first rate state, it controls its own state to jump from the third state to the first rate state.

[0081] Sending information characterizing the state of the control device state machine as the current rate state to the device state machine, so that the device state machine can control its own state to the current rate state based on the information, includes:

[0082] In response to the detection signal sent when the device state machine is in the fourth sub-state;

[0083] The response signal, which characterizes the response detection signal, is sent to the device state machine so that when the device state machine detects that the response signal is a response signal characterizing the host controller to be in the first rate state, it controls its own state to jump from the fourth sub-state to the first rate state.

[0084] Specifically, during the low-speed matching process, for the host side, when the host state machine is in the third state and detects xcvrselect=2' b10 && termselect=1' b1 from the host controller, the host state machine jumps to low-speed mode. In low-speed mode, the DP / DM output of the USB 2.0 HOST digital PHY is 0. For the device side, when the device state machine is in the fourth sub-state, if the device state machine detects xcvrselect=2' b10 && termselect=1' b1 from the host, the device state machine jumps from the fourth sub-state to low-speed mode. In low-speed mode, the DP output of the USB 2.0 DEVICE digital PHY is 0, and the DM output is 1. This method achieves speed matching between the device and the host when the device is operating at low speed.

[0085] The low-speed matching process was described above. If it is detected that the current rate state of the device controller is a second rate state (full-speed state) or a third rate state (high-speed state), in order to determine the final state of the device controller, in practice, before determining that the current rate state of the device controller is a second rate state or a third rate state, and before the rate state of both the device controller and the host state machine are in the current rate state, the method further includes:

[0086] In response to a detection signal sent when the host state machine is in the third state;

[0087] A response signal, representing the response detection signal, is sent to the host state machine. When the host state machine detects that the response signal indicates valid data, it controls its state to transition from the third state to the fourth state and outputs a chirp signal to the device controller. This allows the device controller to perform chirp state detection based on the chirp signal, responding to the detection signal sent when the device state machine is in the fourth sub-state. A response signal, representing the response detection signal, is also sent to the device state machine. When the device state machine detects that the response signal indicates the device controller is in a chirp state and that the data is valid, it controls its state to transition from the fourth sub-state to the fifth sub-state. The fourth state represents the host state machine instructing the device controller to perform chirp state detection; the fifth sub-state represents the device state machine confirming that the device controller has entered the chirp state.

[0088] In response to a detection signal sent when the host state machine is in the fourth state;

[0089] The response signal used to characterize the response detection signal is sent to the host state machine so that when the host state machine detects that the response signal is a signal that the characterizing data has become invalid, it controls its own state to jump from the fourth state to the fifth state; wherein, the fifth state indicates that the host state machine confirms that the device chirp state detection has passed and determines that the device is in the third rate state.

[0090] Specifically, for the host side, when the host state machine is in the third state, if the host state machine detects that the host's txvalidh=1'b1 && txvalid=1'b1 (data valid signal (data has 16 bits, txvalidh controls the high 8 bits, txvalid controls the low 8 bits)), it will jump to the fourth state (the state machine allows the device to perform high-speed chirp state detection). The fourth state corresponds to the alternating chirpK / J signals of the DP / DM output of the USB 2.0 HOST digital PHY.

[0091] For the device side, when the device state machine is in the fourth sub-state, if the device state machine detects that the device's xcvrselect=2' b00 && termselect=1'b1 && txvalidh=1' b1 && txvalid=1' b1, it will jump to the fifth sub-state (the state machine confirms that the device has entered the chirp state). The fifth sub-state corresponds to the USB 2.0 DEVICE digital PHY's DP output being 0 and DM output being 1.

[0092] Furthermore, on the host side, when the host state machine is in the fourth state, if the host state machine detects that txvalidh=1'b0&&txvalid=1'b0, it jumps to the fifth state (the state machine confirms that the device has passed the high-speed chirp detection, i.e., confirms that the device has entered high-speed mode). The fifth state corresponds to the DP / DM output of the USB 2.0 HOST digital PHY being 0. This method determines that the device controller is in high-speed mode.

[0093] After determining that the device controller is in a high-speed state, in order to achieve high-speed matching between the host and the device, in practice, when the device is determined to be in a third-speed state, the speed state of the device controller and the speed state of the host state machine are both set to the current speed state, including:

[0094] The module within the controller that performs rate adjustment adjusts its own rate to the third rate state.

[0095] When it is in the third rate state, it responds to the detection signal sent when the host state machine is in the fifth state;

[0096] The response signal, which characterizes the response detection signal, is sent to the host state machine so that when the host state machine detects that the response signal is a response signal characterizing that the host controller is in the third rate state, it controls its own state to jump from the fifth state to the third rate state.

[0097] Sending information characterizing the state of the control device state machine as the current rate state to the device state machine, so that the device state machine can control its own state to the current rate state based on the information, includes:

[0098] In response to the detection signal sent when the device state machine is in the fifth sub-state;

[0099] The response signal, which characterizes the response detection signal, is sent to the device state machine so that when the device state machine detects that the response signal is a response signal characterizing that the host controller is in the third rate state, it controls its own state to jump from the fifth sub-state to the third rate state.

[0100] Specifically, during the high-speed matching process, for the host side, when the host state machine is in the fifth state, if the host state machine detects that the host's xcvrselect=2'b00&&termselect=1'b0&&opmode!=2'b10, it will jump to the high-speed mode. The high-speed mode corresponds to the DP / DM output of the USB 2.0 HOST digital PHY being 0.

[0101] On the device side, when the device state machine is in the fifth sub-state, if the device state machine detects that `txvalidh=1' b0 && txvalid=1' b0`, it jumps to high-speed mode. In high-speed mode, the DP / DM of the USB 2.0 DEVICE digital PHY does not output signals. This method achieves speed matching between the device and the host when the device is operating at high speed.

[0102] The above describes the processes of low-speed identification, low-speed matching, high-speed identification, and high-speed matching. The following explains the processes of full-speed identification and full-speed matching. For the full-speed identification process, in practice, after outputting the chirp signal to the device controller, the system controls its own speed state and the host's speed state based on the current speed state of the device controller. Before the speed states of the state machines are all in the current speed state, this method also includes:

[0103] If the device does not receive a signal from the device state machine that represents the response to the chirp signal within a preset time period after it outputs a chirp signal to the device controller, then the device is determined to be in the second rate state.

[0104] The preset duration is not limited and is determined based on actual conditions. That is, if the USB 2.0 host does not detect the Chirp K signal sent by the USB 2.0 device within a certain time, it will ultimately identify the USB 2.0 device as a full-speed device. Therefore, this method determines whether the device is in full-speed mode.

[0105] After determining that the device controller is in full-speed mode, in order to achieve full-speed matching between the host and the device, in practice, when it is determined that the device is in the second-speed mode, the speed state of the device controller and the speed state of the host state machine are both set to the current speed state, including:

[0106] The module within the controller that performs rate adjustment adjusts its own rate to the second rate state.

[0107] When it is in the second rate state, it responds to the detection signal sent when the host state machine is in the fourth state;

[0108] The response signal, which characterizes the response detection signal, is sent to the host state machine so that when the host state machine detects that the response signal is a response signal characterizing that the host controller is in the second rate state, it controls its own state to jump from the fourth state to the second rate state.

[0109] Sending information characterizing the state of the control device state machine as the current rate state to the device state machine, so that the device state machine can control its own state to the current rate state based on the information, includes:

[0110] In response to the detection signal sent when the device state machine is in the fourth sub-state;

[0111] The response signal, which characterizes the response detection signal, is sent to the device state machine so that when the device state machine detects that the response signal is a response signal characterizing that the host controller is in the second rate state, it controls its own state to jump from the fourth sub-state to the second rate state.

[0112] Specifically, during the full-speed matching process, for the host side, when the host state machine is in the fourth state, after the ChirpK / J signal is sent, if the host state machine detects that the host's xcvrselect[0]=1'b1 &&termselect=1'b1, it will jump to the full-speed mode. The full-speed mode corresponds to the DP / DM output of the USB 2.0 HOST digital PHY being 0.

[0113] For the device side, when the device state machine is in the fourth sub-state, if the device state machine detects that the host's xcvrselect[0]=1' b1 && termselect=1' b1 (the host's current state is full-speed mode), then the device state machine jumps to full-speed mode. This method achieves full-speed matching between the host and the device.

[0114] The above describes the identification and matching process for low-speed, high-speed, and full-speed operation. In practice, the host may suspend or wake up, or disable bit stuffing and NRZI encoding. In these cases, it is also necessary to match the host and device speeds. In implementation, after the device state machine controls its state to transition from the fifth sub-state to the third speed state, the method further includes:

[0115] Output a command to the host state machine and device controller to indicate that it is suspended; so that the device controller can control itself to switch from the third rate state to the second rate state according to the command, in response to the detection signal sent when the device state machine is in the third rate state; send a response signal to the device state machine to indicate that it is in the second rate state, so that the device state machine can control itself to switch from the third rate state to the second rate state when it detects that the response signal is an indication that the device controller is in the second rate state.

[0116] In response to the detection signal sent when the host state machine is in the third rate state;

[0117] The response signal, which characterizes the response detection signal, is sent to the host state machine so that when the host state machine detects that the response signal is a response signal characterizing that the host controller is in the second rate state, it controls its own state to jump from the third rate state to the second rate state.

[0118] Specifically, for the host side, when the host state machine is in high-speed mode, if the host state machine detects that xcvrselect[0]=1' b1 && termselect=1' b1, it will jump to full-speed mode. In full-speed mode, the DP / DM output of the USB 2.0 HOST digital PHY is 0. For the device side, when the device state machine is in high-speed mode, if the device state machine detects that xcvrselect[0]=1' b1 && termselect=1' b1, it will jump to full-speed mode.

[0119] In this method, when both the host and the device are in a high-speed state, in the scenario where the host is suspended, the device controller, device state machine, and host state machine all change from a high-speed state to a full-speed state, thus achieving speed matching between the host and the device.

[0120] In some embodiments, after the device state machine controls its own state to transition from the fifth sub-state to the third rate state, the method further includes:

[0121] Output a command to the host state machine and device controller to indicate that bit stuffing and non-return-to-zero inversion encoding are disabled; so that the device controller controls itself to transition from the third rate state to the chirped state according to the command, in response to the detection signal sent when the device state machine is in the third rate state; send a response signal to the device state machine to indicate that the response signal indicates that the device controller is in the chirped state, so that the device state machine controls itself to transition from the third rate state to the fifth sub-state when it detects that the response signal is the response signal indicating that the device controller is in the chirped state;

[0122] In response to the detection signal sent when the host state machine is in the third rate state;

[0123] The response signal, which characterizes the response detection signal, is sent to the host state machine so that when the host state machine detects that the response signal is a response signal characterizing that the host controller is in a chirped state, it controls its own state to jump from the third rate state to the third state.

[0124] Specifically, for the host side, if the host state machine is in high-speed mode and detects that `xcvrselect=2' b00 && termselect=1' b0 && opmode =2' b10`, it jumps to the third state. In the third state, the DP / DM output of the USB 2.0 HOST digital PHY is 0. For the device side, if the device state machine is in high-speed mode and detects that `xcvrselect=2' b00 && termselect=1' b1 && txvalidh=1' b1 && txvalid=1' b1`, it jumps to the fifth sub-state. In the fifth sub-state, the DP output of the USB 2.0 DEVICE digital PHY is 0, and the DM output is 1.

[0125] In this method, when both the host and the device are at high speed, for scenarios where bit stuffing and NRZI encoding are disabled on the host, the device controller jumps from the high-speed state to the chirped state; the host state machine jumps from the high-speed state to the state machine indicating that the device needs to be in the speed detection state; the device state machine jumps from the high-speed state to the state machine indicating that the device controller has entered the chirped state, thus achieving speed matching between the host and the device.

[0126] In some embodiments, after the device controller controls its own state to transition from the fourth sub-state to the second rate state, the method further includes:

[0127] Output a command to the host state machine and the device controller to indicate its own wake-up; so that the device controller can control itself to jump from the second rate state to the third rate state according to the command, in response to the detection signal sent when the device state machine is in the second rate state; send a response signal to the device state machine to indicate the response to the detection signal, so that the device state machine can control its own state to jump from the second rate state to the third rate state when it detects that the response signal is an indication that the device controller is in the third rate state;

[0128] In response to the detection signal sent when the host state machine is in the second rate state;

[0129] The response signal, which characterizes the response detection signal, is sent to the host state machine so that when the host state machine detects that the response signal is a response signal characterizing that the host controller is in the third rate state, it controls its own state to jump from the second rate state to the third rate state.

[0130] Specifically, for the host side, when the host state machine is in full-speed mode, if it detects that `xcvrselect=2' b00 && termselect=1' b0 && opmode!=2' b10`, it switches to high-speed mode. In high-speed mode, the DP / DM output of the USB 2.0 HOST digital PHY is 0. For the device side, when the device state machine is in full-speed mode, if it detects that `xcvrselect=2' b00 && termselect=1' b0 && opmode!=2' b10`, it switches to high-speed mode. In high-speed mode, the DP / DM output of the USB 2.0 DEVICE digital PHY does not output any signals.

[0131] In this method, when both the host and the device are in full-speed mode, in the scenario of host wake-up, the device controller, device state machine and host state machine all change from full-speed mode to high-speed mode, thus achieving speed matching between the host and the device.

[0132] In some embodiments, after the device controller controls its own state to transition from the fourth sub-state to the second rate state, the method further includes:

[0133] The output is used to represent the command to disable bit stuffing and non-return-to-zero inversion encoding to the host state machine and device controller;

[0134] In response to the detection signal sent when the device state machine and the host state machine are in the second rate state;

[0135] The response signal used to characterize the response detection signal is sent to the host state machine and the device state machine respectively, so that when the host state machine detects that the response signal is a response signal characterizing that the host controller is in a chirped state, it controls its own state to jump from the second rate state to the third state; when the device state machine detects that the response signal is a response signal characterizing that the host controller is in a chirped state, it controls its own state to jump from the second rate state to the fourth sub-state.

[0136] Specifically, for the host side, when the host state machine is in full-speed mode, if the host state machine detects that `xcvrselect=2' b00 && termselect=1' b0 && opmode =2' b10`, it jumps to the third state. In the third state, the DP / DM output of the USB 2.0 HOST digital PHY is 0. For the device side, when the device state machine is in full-speed mode, if the device state machine detects that `xcvrselect=2' b00 && termselect=1' b0`, it jumps to the fourth sub-state. In the fourth sub-state, the DP / DM output of the USB 2.0 DEVICE digital PHY does not output any signals.

[0137] In this method, when both the host and the device are at full speed, for scenarios where bit stuffing and NRZI encoding are disabled on the host, the host controller transitions from the full-speed state to the chirped state; the host state machine transitions from the full-speed state to the state machine requiring the device to be in the speed detection state; the device state machine transitions from the full-speed state to the state machine requiring the device to be in the speed detection state, thus achieving speed matching between the host and the device.

[0138] Furthermore, when bit stuffing and NRZI encoding are enabled, if the host state machine is in the third state and detects that the host's xcvrselect=2' b00 &&termselect=1'b0 &&opmode!=2' b10, it will jump to high-speed mode. In high-speed mode, the DP / DM output of the USB 2.0 HOST digital PHY is 0.

[0139] To enable those skilled in the art to better understand the above scheme, the states of the host state machine and the device state machine will be explained below. Figure 4 This invention provides a schematic diagram illustrating the state changes of a host state machine during rate identification and matching, as shown in the embodiment of the invention. Figure 4As shown, the host state machine changes from the initial state to the first state, from the first state to the second state, from the third state to the fourth state, from the fourth state to the fifth state, and finally to high-speed mode; from the fourth state, it can also change to full-speed mode; the third state can also change to high-speed mode and low-speed mode; high-speed mode can also change to the third state; high-speed mode can also change to full-speed mode, and then from full-speed mode back to the third state; full-speed mode can change back to high-speed mode. Please refer to the description above for the process of state changes; it will not be repeated here.

[0140] Figure 5 This invention provides a schematic diagram of the state changes of a device state machine in rate identification and matching, as shown in the embodiment of the invention. Figure 5 As shown, the device state machine can change from the initial state to the first sub-state, the second sub-state; from the first sub-state to the third sub-state, or from the second sub-state to the third sub-state; from the third sub-state to the fourth sub-state; from the fourth sub-state to the fifth sub-state, low-speed mode, or full-speed mode; from the fifth sub-state to high-speed mode; from high-speed mode to the fifth sub-state or full-speed mode; from full-speed mode to the fourth sub-state; and from full-speed mode to high-speed mode. Please refer to the description above for the process of state changes; it will not be repeated here.

[0141] The present invention provides a solution for implementing KVM functionality using a single-board management controller. By replacing the USB 2.0 PHY with a USB 2.0 digital PHY, the speed of the USB 2.0 device can be identified without analog circuitry, simplifying the PHY design. The USB 2.0 HOST Controller and USB 2.0 DEVICE Controller monitor the DP / DM and ChirpK / J signal states to control the output of signals such as xcvrselect, termselect, opmode, txvalidh, txvalid, dppulldown, and dmpulldown on their respective UTMI interfaces. The speed identification state machine in the USB 2.0 HOST / DEVICE digital PHY completes the speed matching process between the USB 2.0 HOST and DEVICE, ultimately achieving low-speed, full-speed, and high-speed speed identification between the USB 2.0 HOST and DEVICE.

[0142] The above describes a method for rate adaptation between a Universal Serial Bus (USB) host and a device. This embodiment also provides a baseboard management controller, including: a USB host and a USB device. The circuitry of both the host physical layer and the device physical layer includes only digital circuitry. Both the host physical layer and the device physical layer also include a state machine. The host controller in the baseboard management controller is used for:

[0143] Responding to the data line signal output by the device physical layer, and determining the current rate state of the device controller based on the data line signal; wherein, the data line signal includes at least a positive data signal, a negative data signal, and a chirp signal; the data line signal is determined by the device state machine based on the signal sent by the device controller to determine its own current state, and based on the current state and the pre-established mapping relationship between the state of the device state machine and the data line signal;

[0144] The device controller controls its own rate state and the host state machine's rate state based on the current rate state.

[0145] Information representing the current rate state of the control device state machine is sent to the device state machine so that the device state machine can control its own state to the current rate state based on the information.

[0146] The baseboard management controller provided in this embodiment has the same or corresponding technical features as the Universal Serial Bus host and device rate adaptation method described above. The embodiments of the Universal Serial Bus host and device rate adaptation method have been described in detail above, and the embodiments of the baseboard management controller will not be repeated here, and the effects are the same as above.

[0147] In the above embodiments, the method for Universal Serial Bus (USB) host and device rate adaptation has been described in detail. This invention also provides embodiments of USB host and device rate adaptation devices and corresponding electronic devices. It should be noted that this invention describes the embodiments of the device portion from two perspectives: one based on functional modules, and the other based on hardware.

[0148] The Universal Serial Bus host and device rate adaptation device provided in the embodiments of the present invention, based on the functional modules, includes:

[0149] The response and determination module is used to respond to the data line signals output by the device physical layer and determine the current rate state of the device controller based on the data line signals; wherein, the data line signals include at least a positive data signal, a negative data signal, and a chirp signal; the data line signals are determined by the device state machine based on the signals sent by the device controller to determine its current state, and based on the current state and the pre-established mapping relationship between the state of the device state machine and the data line signals;

[0150] The first control module is used to control its own rate state and the rate state of the host state machine to be the current rate state according to the current rate state of the device controller.

[0151] The first sending module is used to send information representing the current rate state of the control device state machine to the device state machine, so that the device state machine can control its own state to the current rate state according to the information.

[0152] In some embodiments, the Universal Serial Bus host and device rate adaptation apparatus further includes:

[0153] The first response module is used to respond to the detection signal sent by the host state machine when the host state machine is in the initial state;

[0154] The second sending module is used to send a response signal, which represents the response detection signal, to the host state machine, so that when the host state machine detects that the response signal is a preset response signal, it controls its own state to jump from the initial state to the first state; wherein, the first state represents that the host state machine confirms that the host controller is in the state corresponding to the preset response signal.

[0155] In some embodiments, the Universal Serial Bus host and device rate adaptation apparatus further includes:

[0156] The third sending module is used to respond to a detection signal sent by the device state machine when the device state machine is in the initial state; send a response signal characterizing the response detection signal to the device state machine, so that when the device state machine detects that the response signal is a first preset response signal, it controls its own state to jump from the initial state to the first sub-state; when the device state machine detects that the response signal is a second preset response signal, it controls its own state to jump from the initial state to the second sub-state; wherein, the first sub-state characterizes the device state machine's confirmation that the device controller is in the state corresponding to the first preset response signal; the second sub-state characterizes the device state machine's confirmation that the device controller is in the state corresponding to the second preset response signal.

[0157] In some embodiments, the Universal Serial Bus host and device rate adaptation apparatus further includes:

[0158] The second response module is used to respond to the detection signal sent when the host state machine is in the first state;

[0159] The fourth sending module is used to send a response signal, which represents the response detection signal, to the host state machine, so that when the host state machine detects that the response signal is a control signal of a preset pull-down resistor, it controls its own state to jump from the first state to the second state; wherein, the second state represents the state of the host state machine controlling the handshake between the host physical layer and the device physical layer.

[0160] The fifth sending module is used by the device controller to respond to the detection signal sent by the device state machine in the first sub-state; to send a response signal representing the response detection signal to the device state machine, so that when the device state machine detects that the response signal is a preset operation mode signal, it controls its own state to jump from the first sub-state to the third sub-state and outputs the first data line signal; wherein, the third sub-state represents the handshake state between the device state machine control host physical layer and device physical layer;

[0161] The sixth sending module is used to respond to the detection signal sent by the device controller when the device state machine is in the second sub-state; and to send a response signal that characterizes the response detection signal to the device state machine so that when the device state machine detects that the response signal is a preset operation mode signal, it controls its own state to jump from the second sub-state to the third sub-state and outputs the second data line signal.

[0162] In some embodiments, the Universal Serial Bus host and device rate adaptation apparatus further includes:

[0163] The third response module is used to respond to the detection signal sent when the host state machine is in the second state;

[0164] The seventh sending module is used to send the response signal, which represents the response detection signal, to the host state machine, so that when the host state machine detects that the response signal is a preset response signal, it controls its own state to jump from the second state to the third state; wherein, the third state represents the host state machine putting the device into the speed detection state.

[0165] The fourth response module is used to respond to the detection signal sent when the device state machine is in the third sub-state;

[0166] The eighth sending module is used to send the response signal, which represents the response detection signal, to the device state machine, so that when the device state machine detects that the response signal is a preset response signal, it controls its own state to jump from the third sub-state to the fourth sub-state; wherein, the fourth sub-state represents the device state machine putting the device into the speed detection state.

[0167] In some embodiments, the determining module in the response and determining module includes:

[0168] The first determining module is used to determine the current rate state of the device controller as the first rate state if the value of the positive data signal and the value of the negative data signal in the data line signal are detected to be a first preset value.

[0169] The second determining module is used to determine the current rate state of the device controller as either a second rate state or a third rate state if the value of the positive data signal and the value of the negative data signal in the data line signal are detected to be a second preset value; wherein the first rate is less than the third rate, and the third rate is less than the second rate.

[0170] In some embodiments, when the current rate state of the device controller is determined to be a first rate state, the first control module includes:

[0171] The second control module is used to control the module within itself that performs rate adjustment to adjust its own rate to the first rate state.

[0172] The fifth response module is used to respond to the detection signal sent by the host state machine when it is in the third state while it is in the first rate state.

[0173] The ninth sending module is used to send a response signal, which represents the response detection signal, to the host state machine, so that when the host state machine detects that the response signal is a response signal representing that the host controller is in the first rate state, it controls its own state to jump from the third state to the first rate state.

[0174] In some embodiments, the first transmitting module includes:

[0175] The sixth response module is used to respond to the detection signal sent when the device state machine is in the fourth sub-state;

[0176] The tenth sending module is used to send a response signal, which represents the response detection signal, to the device state machine, so that when the device state machine detects that the response signal is a response signal representing that the host controller is in the first rate state, it controls its own state to jump from the fourth sub-state to the first rate state.

[0177] In some embodiments, when it is determined that the current rate state of the device controller is a second rate state or a third rate state, the Universal Serial Bus host and device rate adaptation device further includes:

[0178] The seventh response module is used to respond to the detection signal sent when the host state machine is in the third state;

[0179] The eleventh sending module is used to send a response signal, representing a response detection signal, to the host state machine. When the host state machine detects that the response signal indicates valid data, it controls its own state to transition from the third state to the fourth state and outputs a chirp signal to the device controller. This allows the device controller to perform chirp state detection based on the chirp signal, responding to the detection signal sent when the device state machine is in the fourth sub-state. The module also sends a response signal, representing a response detection signal, to the device state machine. When the device state machine detects that the response signal indicates the device controller is in a chirp state and that the data is valid, it controls its own state to transition from the fourth sub-state to the fifth sub-state. The fourth state represents the host state machine instructing the device controller to perform chirp state detection; the fifth sub-state represents the device state machine confirming that the device controller has entered the chirp state.

[0180] The eighth response module is used to respond to the detection signal sent when the host state machine is in the fourth state;

[0181] The twelfth sending module is used to send the response signal, which represents the response detection signal, to the host state machine, so that when the host state machine detects that the response signal represents invalid data, it controls its own state to jump from the fourth state to the fifth state; wherein, the fifth state represents that the host state machine confirms that the device chirp state detection has passed and determines that the device is in the third rate state.

[0182] In some embodiments, when it is determined that the device is in a third-rate state, the first control module includes:

[0183] The third control module is used to control the module within itself that performs rate adjustment to adjust its own rate to the third rate state.

[0184] The ninth response module is used to respond to the detection signal sent by the host state machine when it is in the fifth state while it is in the third rate state.

[0185] The thirteenth sending module is used to send a response signal, which represents the response detection signal, to the host state machine, so that when the host state machine detects that the response signal represents the host controller being in the third rate state, it controls its own state to jump from the fifth state to the third rate state.

[0186] In some embodiments, the first transmitting module includes:

[0187] The tenth response module is used to respond to the detection signal sent when the device state machine is in the fifth sub-state;

[0188] The fourteenth sending module is used to send a response signal, which represents the response detection signal, to the device state machine, so that when the device state machine detects that the response signal represents the host controller being in the third rate state, it controls its own state to jump from the fifth sub-state to the third rate state.

[0189] In some embodiments, after outputting the chirp signal to the device controller, the Universal Serial Bus host and device rate adapter further includes:

[0190] The receiving and determining module is used to determine that the device is in the second rate state if it does not receive a signal from the device state machine that represents the response to the chirp signal within a preset time period after the device controller outputs a chirp signal.

[0191] In some embodiments, when it is determined that the device is in a second rate state, the first control module includes:

[0192] The fourth control module is used to control the module within itself that performs rate adjustment to adjust its own rate to the second rate state.

[0193] The eleventh response module is used to respond to the detection signal sent by the host state machine when it is in the fourth state while it is in the second rate state.

[0194] The fifteenth sending module is used to send a response signal, which represents the response detection signal, to the host state machine, so that when the host state machine detects that the response signal represents the host controller being in the second rate state, it controls its own state to jump from the fourth state to the second rate state.

[0195] In some embodiments, the first transmitting module includes:

[0196] The twelfth response module is used to respond to the detection signal sent when the device state machine is in the fourth sub-state;

[0197] The sixteenth sending module is used to send a response signal, which represents the response detection signal, to the device state machine, so that when the device state machine detects that the response signal represents the host controller being in the second rate state, it controls its own state to jump from the fourth sub-state to the second rate state.

[0198] In some embodiments, the Universal Serial Bus host and device rate adaptation apparatus further includes:

[0199] The first output module is used to output a command representing its own suspension to the host state machine and the device controller; so that the device controller controls itself to jump from the third rate state to the second rate state according to the command, in response to the detection signal sent when the device state machine is in the third rate state; and sends a response signal representing the response to the detection signal to the device state machine, so that when the device state machine detects that the response signal is a response signal representing that the device controller is in the second rate state, it controls its own state to jump from the third rate state to the second rate state.

[0200] The thirteenth response module is used to respond to the detection signal sent when the host state machine is in the third rate state;

[0201] The seventeenth sending module is used to send a response signal, which represents the response detection signal, to the host state machine, so that when the host state machine detects that the response signal represents the host controller being in the second rate state, it controls its own state to jump from the third rate state to the second rate state.

[0202] In some embodiments, the Universal Serial Bus host and device rate adaptation apparatus further includes:

[0203] The second output module is used to output a command representing the disabling of bit stuffing and non-return-to-zero inversion encoding to the host state machine and the device controller; so that the device controller controls itself to jump from the third rate state to the chirped state according to the command, in response to the detection signal sent when the device state machine is in the third rate state; and sends a response signal representing the response to the detection signal to the device state machine, so that when the device state machine detects that the response signal is a response signal representing that the device controller is in the chirped state, it controls its own state to jump from the third rate state to the fifth sub-state;

[0204] The fourteenth response module is used to respond to the detection signal sent when the host state machine is in the third rate state;

[0205] The eighteenth transmitting module is used to send a response signal, which represents the response detection signal, to the host state machine, so that when the host state machine detects that the response signal is a response signal representing that the host controller is in a chirped state, it controls its own state to jump from the third rate state to the third state.

[0206] In some embodiments, the Universal Serial Bus host and device rate adaptation apparatus further includes:

[0207] The third output module is used to output a command representing its own wake-up to the host state machine and the device controller; so that the device controller controls itself to jump from the second rate state to the third rate state according to the command, in response to the detection signal sent when the device state machine is in the second rate state; and sends a response signal representing the response to the detection signal to the device state machine, so that when the device state machine detects that the response signal is a response signal representing that the device controller is in the third rate state, it controls its own state to jump from the second rate state to the third rate state.

[0208] The fifteenth response module is used to respond to the detection signal sent when the host state machine is in the second rate state;

[0209] The nineteenth sending module is used to send a response signal, which represents the response detection signal, to the host state machine, so that when the host state machine detects that the response signal represents the host controller being in the third rate state, it controls its own state to jump from the second rate state to the third rate state.

[0210] In some embodiments, the Universal Serial Bus host and device rate adaptation apparatus further includes:

[0211] The fourth output module is used to output commands that characterize disabling bit stuffing and non-return-to-zero inversion encoding to the host state machine and device controller;

[0212] In response to the detection signal sent when the device state machine and the host state machine are in the second rate state;

[0213] The twentieth sending module is used to send the response signal, which represents the response detection signal, to the host state machine and the device state machine respectively, so that when the host state machine detects that the response signal represents that the host controller is in a chirped state, it controls its own state to jump from the second rate state to the third state; when the device state machine detects that the response signal represents that the host controller is in a chirped state, it controls its own state to jump from the second rate state to the fourth sub-state.

[0214] Since the embodiments of the apparatus and the embodiments of the method correspond to each other, please refer to the description of the embodiments of the method for the embodiments of the apparatus. They will not be repeated here, but the effect is the same.

[0215] Figure 6 This is a structural diagram of an electronic device provided in an embodiment of the present invention. This embodiment is based on a hardware perspective, such as... Figure 6 As shown, the electronic device includes:

[0216] Memory 20 is used to store computer programs;

[0217] The processor 21 is used to implement the steps of the Universal Serial Bus host and device rate adaptation method mentioned in the above embodiments when executing a computer program.

[0218] The processor 21 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 21 may be implemented using at least one of the following hardware forms: Digital Signal Processor (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array. The processor 21 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 21 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 21 may also include an Artificial Intelligence (AI) processor, which handles computational operations related to machine learning.

[0219] The memory 20 may include one or more computer-readable storage media, which may be non-transitory. The memory 20 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 20 is used to store at least the following computer program 201, which, after being loaded and executed by the processor 21, is capable of implementing the relevant steps of the Universal Serial Bus host and device rate adaptation method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 may also include an operating system 202 and data 203, and the storage method may be temporary or permanent storage. The operating system 202 may include Windows, Unix, Linux, etc. The data 203 may include, but is not limited to, the data involved in the aforementioned Universal Serial Bus host and device rate adaptation method.

[0220] In some embodiments, the electronic device may further include a display screen 22, an input / output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.

[0221] Those skilled in the art will understand that Figure 6 The structures shown do not constitute a limitation on electronic devices and may include more or fewer components than those shown.

[0222] The electronic device provided in this embodiment of the invention includes a memory and a processor. When the processor executes a program stored in the memory, it can implement the following method: a Universal Serial Bus host and device rate adaptation method, with the same effect as above.

[0223] This invention also provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the above-described Universal Serial Bus host and device rate adaptation method.

[0224] Finally, the present invention also provides an embodiment corresponding to a computer-readable storage medium. The computer-readable storage medium stores a computer program, which, when executed by a processor, performs the steps described in the above method embodiments.

[0225] It is understood that if the methods in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0226] The computer-readable storage medium provided by this invention includes the aforementioned Universal Serial Bus host and device rate adaptation method, with the same effect.

[0227] The foregoing has provided a detailed description of the universal serial bus host and device rate adaptation method and baseboard management controller provided by the present invention. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principles of the invention, and these improvements and modifications also fall within the protection scope of the present invention.

[0228] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A method for rate adaptation between a universal serial bus host and a device, characterized in that, A host controller applied in a baseboard management controller, the baseboard management controller including a Universal Serial Bus (USB) host and a USB device, the circuitry of both the host physical layer and the device physical layer including only digital circuitry, and both the host physical layer and the device physical layer also including a state machine; the method includes: In response to the data line signal output by the device physical layer, the current rate state of the device controller is determined based on the data line signal; wherein the data line signal includes at least a positive data signal, a negative data signal, and a chirp signal; the data line signal is determined by the device state machine based on the signal sent by the device controller to determine its current state, and based on the current state and a pre-established mapping relationship between the state of the device state machine and the data line signal; The current rate state of the device controller and the current rate state of the host state machine are both determined according to the current rate state of the device controller. Information used to characterize the state of the control device state machine as the current rate state is sent to the device state machine, so that the device state machine controls its own state to the current rate state according to the information.

2. The method for rate adaptation of a universal serial bus host and device according to claim 1, characterized in that, Before responding to the data line signal output by the device physical layer and determining the current rate state of the device controller based on the data line signal, the method further includes: In response to the detection signal sent by the host state machine when it is in the initial state; A response signal, used to characterize the response detection signal, is sent to the host state machine so that when the host state machine detects that the response signal is a preset response signal, it controls its own state to jump from the initial state to the first state; wherein, the first state characterizes the host state machine's confirmation that the host controller is in the state corresponding to the preset response signal.

3. The method for rate adaptation of a universal serial bus host and device according to claim 2, characterized in that, Before responding to the data line signal output by the device physical layer and determining the current rate state of the device controller based on the data line signal, the method further includes: The device controller responds to a detection signal sent by the device state machine when the device state machine is in its initial state; it sends a response signal characterizing the response to the detection signal to the device state machine, so that if the device state machine detects that the response signal is a first preset response signal, it controls its own state to jump from the initial state to a first sub-state; if it detects that the response signal is a second preset response signal, it controls its own state to jump from the initial state to a second sub-state; wherein, the first sub-state characterizes the device state machine's confirmation that the device controller is in the state corresponding to the first preset response signal; and the second sub-state characterizes the device state machine's confirmation that the device controller is in the state corresponding to the second preset response signal.

4. The method for rate adaptation of a universal serial bus host and device according to claim 3, characterized in that, Before responding to a data line signal output from the device physical layer and determining the current rate state of the device controller based on the data line signal, the method further includes: In response to a detection signal sent when the host state machine is in the first state; A response signal, used to characterize the response detection signal, is sent to the host state machine so that when the host state machine detects that the response signal is a control signal of a preset pull-down resistor, it controls its own state to jump from the first state to the second state; wherein, the second state characterizes the state of the host state machine controlling the handshake between the host physical layer and the device physical layer; The device controller responds to the detection signal sent by the device state machine in the first sub-state; it sends a response signal characterizing the response to the detection signal to the device state machine, so that when the device state machine detects that the response signal is a preset operation mode signal, it controls its own state to jump from the first sub-state to the third sub-state and outputs the first data line signal; wherein, the third sub-state characterizes the handshake state between the device state machine control host physical layer and the device physical layer. The device controller responds to the detection signal sent by the device state machine when it is in the second sub-state; it sends a response signal, which characterizes the response to the detection signal, to the device state machine so that when the device state machine detects that the response signal is the preset operation mode signal, it controls its own state to jump from the second sub-state to the third sub-state and outputs the second data line signal.

5. The method for rate adaptation of a universal serial bus host and device according to claim 4, characterized in that, After the device controller transitions its state from the initial state to the third sub-state, and before responding to the data line signal output by the device physical layer and determining the current rate state of the device controller based on the data line signal, the method further includes: In response to a detection signal sent when the host state machine is in the second state; A response signal, which characterizes the response detection signal, is sent to the host state machine so that when the host state machine detects that the response signal is a preset response signal, it controls its own state to jump from the second state to the third state; wherein, the third state characterizes the host state machine to put the device into the speed detection state; In response to a detection signal sent when the device state machine is in the third sub-state; A response signal, which characterizes the response detection signal, is sent to the device state machine so that when the device state machine detects that the response signal is a preset response signal, it controls its own state to jump from the third sub-state to the fourth sub-state; wherein, the fourth sub-state characterizes the device state machine to put the device into a speed detection state.

6. The Universal Serial Bus host and device rate adaptation method according to claim 5, characterized in that, Determining the current rate status of the device controller based on the data line signal includes: If the values ​​of the positive and negative data signals in the data line signals are detected to be a first preset value, then the current rate state of the device controller is determined to be the first rate state. If the values ​​of the positive and negative data signals in the data line signals are detected to be a second preset value, then the current rate state of the device controller is determined to be either a second rate state or a third rate state; wherein the first rate is less than the third rate, and the third rate is less than the second rate.

7. The Universal Serial Bus host and device rate adaptation method according to claim 6, characterized in that, When the current rate state of the device controller is determined to be the first rate state, the step of controlling both the device controller's current rate state and the host state machine's rate state to be the current rate state includes: The module within the controller that performs rate adjustment adjusts its own rate to the first rate state. When it is in the first rate state, it responds to the detection signal sent when the host state machine is in the third state; A response signal, which characterizes the response detection signal, is sent to the host state machine so that when the host state machine detects that the response signal is a response signal characterizing the host controller being in the first rate state, it controls its own state to jump from the third state to the first rate state.

8. The Universal Serial Bus host and device rate adaptation method according to claim 7, characterized in that, The step of sending information characterizing the state of the control device state machine as the current rate state to the device state machine, so that the device state machine controls its own state to the current rate state according to the information, includes: In response to the detection signal sent when the device state machine is in the fourth sub-state; A response signal, used to characterize the response detection signal, is sent to the device state machine so that when the device state machine detects that the response signal is a response signal characterizing the host controller being in the first rate state, it controls its own state to jump from the fourth sub-state to the first rate state.

9. The method for rate adaptation of a universal serial bus host and device according to claim 6, characterized in that, If the current rate state of the device controller is determined to be either the second rate state or the third rate state, before controlling both the device controller's own rate state and the host state machine's rate state to be the current rate state, the method further includes: In response to a detection signal sent when the host state machine is in the third state; A response signal, representing a response detection signal, is sent to the host state machine. When the host state machine detects that the response signal indicates valid data, it controls its own state to transition from the third state to the fourth state and outputs a chirp signal to the device controller. This allows the device controller to perform chirp state detection based on the chirp signal, responding to the detection signal sent when the device state machine is in the fourth sub-state. A response signal, representing a response detection signal, is also sent to the device state machine. When the device state machine detects that the response signal indicates the device controller is in a chirp state and that the data is valid, it controls its own state to transition from the fourth sub-state to the fifth sub-state. The fourth state represents the host state machine instructing the device controller to perform chirp state detection; the fifth sub-state represents the device state machine confirming that the device controller has entered a chirp state. In response to a detection signal sent when the host state machine is in the fourth state; The response signal used to characterize the response detection signal is sent to the host state machine so that when the host state machine detects that the response signal is a signal that the characterizing data has become invalid, it controls its own state to jump from the fourth state to the fifth state; wherein, the fifth state indicates that the host state machine confirms that the device chirp state detection has passed and determines that the device is in the third rate state.

10. The Universal Serial Bus host and device rate adaptation method according to claim 9, characterized in that, When it is determined that the device is in the third rate state, the rate state of the device controller and the rate state of the host state machine are both determined to be the current rate state, including: The module within the controller that performs rate adjustment adjusts its own rate to the third rate state. When it is in the third rate state, it responds to the detection signal sent when the host state machine is in the fifth state; A response signal, which characterizes the response detection signal, is sent to the host state machine so that when the host state machine detects that the response signal is a response signal characterizing the host controller being in the third rate state, it controls its own state to jump from the fifth state to the third rate state.

11. The Universal Serial Bus host and device rate adaptation method according to claim 10, characterized in that, The step of sending information characterizing the state of the control device state machine as the current rate state to the device state machine, so that the device state machine controls its own state to the current rate state according to the information, includes: In response to the detection signal sent when the device state machine is in the fifth sub-state; The response signal, which characterizes the response detection signal, is sent to the device state machine so that when the device state machine detects that the response signal is a response signal characterizing the host controller being in the third rate state, it controls its own state to jump from the fifth sub-state to the third rate state.

12. The method for rate adaptation of a universal serial bus host and device according to claim 9, characterized in that, After outputting the chirp signal to the device controller, and before controlling its own rate state and the host state machine's rate state to be the current rate state based on the device controller's current rate state, the method further includes: If the device does not receive a signal from the device state machine that represents the response to the chirp signal within a preset time period after it outputs a chirp signal to the device controller, then the device is determined to be in the second rate state.

13. The Universal Serial Bus host and device rate adaptation method according to claim 12, characterized in that, When it is determined that the device is in the second rate state, the rate state of the device controller and the rate state of the host state machine are both determined to be the current rate state, including: The module within the controller that performs rate adjustment adjusts its own rate to the second rate state. When it is in the second rate state, it responds to the detection signal sent when the host state machine is in the fourth state; A response signal, which characterizes the response detection signal, is sent to the host state machine so that when the host state machine detects that the response signal is a response signal characterizing that the host controller is in the second rate state, it controls its own state to jump from the fourth state to the second rate state.

14. The Universal Serial Bus host and device rate adaptation method according to claim 13, characterized in that, The step of sending information characterizing the state of the control device state machine as the current rate state to the device state machine, so that the device state machine controls its own state to the current rate state according to the information, includes: In response to the detection signal sent when the device state machine is in the fourth sub-state; A response signal, which characterizes the response detection signal, is sent to the device state machine so that when the device state machine detects that the response signal is a response signal characterizing the host controller being in the second rate state, it controls its own state to jump from the fourth sub-state to the second rate state.

15. The Universal Serial Bus host and device rate adaptation method according to claim 11, characterized in that, After the device state machine controls its own state to transition from the fifth sub-state to the third rate state, the method further includes: Output a command to the host state machine and the device controller to indicate that the device controller is suspended; so that the device controller controls itself to switch from the third rate state to the second rate state according to the command, in response to a detection signal sent when the device state machine is in the third rate state; send a response signal to the device state machine to indicate that the device state machine is in the second rate state, so that the device state machine controls itself to switch from the third rate state to the second rate state when it detects that the response signal is an indication that the device controller is in the second rate state; In response to the detection signal sent when the host state machine is in the third rate state; A response signal, which characterizes the response detection signal, is sent to the host state machine so that when the host state machine detects that the response signal is a response signal characterizing that the host controller is in the second rate state, it controls its own state to jump from the third rate state to the second rate state.

16. The Universal Serial Bus host and device rate adaptation method according to claim 11, characterized in that, After the device state machine controls its own state to transition from the fifth sub-state to the third rate state, the method further includes: Output a command to the host state machine and device controller to indicate that bit stuffing and non-return-to-zero inversion encoding are disabled; so that the device controller controls itself to transition from the third rate state to the chirped state according to the command, in response to a detection signal sent when the device state machine is in the third rate state; send a response signal to the device state machine to indicate that the response signal indicates that the device controller is in the chirped state, so that the device state machine controls itself to transition from the third rate state to the fifth sub-state when it detects that the response signal is a response signal indicating that the device controller is in the chirped state; In response to the detection signal sent when the host state machine is in the third rate state; The response signal, which characterizes the response detection signal, is sent to the host state machine so that when the host state machine detects that the response signal is a response signal characterizing that the host controller is in a chirped state, it controls its own state to jump from the third rate state to the third state.

17. The Universal Serial Bus host and device rate adaptation method according to claim 14, characterized in that, After the device controller transitions its state from the fourth sub-state to the second rate state, the method further includes: Output a command representing its own wake-up to the host state machine and the device controller; so that the device controller controls itself to jump from the second rate state to the third rate state according to the command, in response to a detection signal sent when the device state machine is in the second rate state; send a response signal representing the response to the detection signal to the device state machine, so that when the device state machine detects that the response signal is a response signal representing that the device controller is in the third rate state, it controls its own state to jump from the second rate state to the third rate state; In response to the detection signal sent when the host state machine is in the second rate state; A response signal, which characterizes the response detection signal, is sent to the host state machine so that when the host state machine detects that the response signal is a response signal characterizing the host controller being in the third rate state, it controls its own state to jump from the second rate state to the third rate state.

18. The Universal Serial Bus host and device rate adaptation method according to claim 14, characterized in that, After the device controller transitions its state from the fourth sub-state to the second rate state, the method further includes: The output is used to represent the command to disable bit stuffing and non-return-to-zero inversion encoding to the host state machine and device controller; In response to the detection signal sent when the device state machine and the host state machine are in the second rate state; The response signal used to characterize the response detection signal is sent to the host state machine and the device state machine respectively, so that when the host state machine detects that the response signal is a response signal characterizing that the host controller is in a chirped state, it controls its own state to jump from the second rate state to the third state; when the device state machine detects that the response signal is a response signal characterizing that the host controller is in a chirped state, it controls its own state to jump from the second rate state to the fourth sub-state.

19. A baseboard management controller, characterized in that, include: The Universal Serial Bus (USB) host and USB device, both have physical layer circuitry consisting only of digital circuitry, and both physical layers also include state machines. The host controller in the baseboard management controller is used for: In response to the data line signal output by the device physical layer, the current rate state of the device controller is determined based on the data line signal; wherein the data line signal includes at least a positive data signal, a negative data signal, and a chirp signal; the data line signal is determined by the device state machine based on the signal sent by the device controller to determine its current state, and based on the current state and a pre-established mapping relationship between the state of the device state machine and the data line signal; The current rate state of the device controller and the current rate state of the host state machine are both determined according to the current rate state of the device controller. Information used to characterize the state of the control device state machine as the current rate state is sent to the device state machine, so that the device state machine controls its own state to the current rate state according to the information.

20. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by the processor, they implement the steps of the Universal Serial Bus host and device rate adaptation method according to any one of claims 1 to 18.

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