System-on-chip design method and device, system-on-chip and electronic equipment

Abstract

A system-on-chip design method and apparatus, a system-on-chip, and an electronic device, the system-on-chip comprising: a network-on-chip, the network-on-chip comprising a network routing component, the network routing component being arranged in a top module; and a plurality of subsystem modules, wherein on-chip interconnection is realized among the plurality of subsystem modules through the network routing component.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of chip technology, and particularly to a system-on-a-chip design method and apparatus, a system-on-a-chip, and an electronic device. Background Technology

[0002] In the physical implementation of multiprocessor on-chip systems, the constraints of module placement, timing, and area are frequently encountered, leading to multiple iterations in the backend implementation to achieve the desired optimal effect. When the system is large, it is often divided into different subsystem modules during the design phase. The physical implementation of the chip involves completing each subsystem module first, and then integrating them into the complete chip system. After the physical implementation is completed, a timing analysis of the entire chip is performed. If timing discrepancies are found, it is usually necessary to return to the frontend design for modifications. This iterative approach makes the design cycle very long. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a system-on-a-chip (SoC) comprising: an on-chip network including a network routing component, the network routing component being configured in a top-level module during front-end design; and multiple subsystem modules interconnected on-chip via the network routing component.

[0005] This disclosure also provides an electronic device including a system-on-a-chip as described in any embodiment of this disclosure.

[0006] This disclosure also provides a system-on-a-chip (SoC) design method, wherein the SoC includes multiple subsystem modules and an on-chip network that interacts with the multiple subsystem modules, the on-chip network includes a network routing component, and the SoC design method includes:

[0007] In the front-end design, a top-level module and multiple subsystem modules are designed separately, and the network routing component is set in the top-level module;

[0008] Functional verification and system simulation verification are performed on the top-level module and multiple subsystem modules to obtain register transfer level code.

[0009] This disclosure also provides an on-chip system design apparatus, including a memory; and a processor connected to the memory, the memory being used to store instructions, the processor being configured to perform the steps of an on-chip system design method as described in any embodiment of this disclosure based on the instructions stored in the memory.

[0010] The system-on-a-chip (SoC) design method and apparatus, SoC, and electronic device of this disclosure, by placing the network routing component in the top-level module and not including the network routing component in each subsystem module, ensures that all subsystem modules are only connected to the top-level module by signals, and there are no direct signal connections between multiple subsystem modules. When laying out each subsystem module, timing issues can be disregarded, and other aspects can be considered more during physical layout, such as minimizing the chip area and making clock trees and power networks easier to implement. This avoids the iterative process of having to return to the front-end design for modification due to timing discrepancies.

[0011] After reading and understanding the accompanying diagrams and detailed descriptions, other aspects can be understood. Attached Figure Description

[0012] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0013] Figure 1A and Figure 1B Schematic diagrams of on-chip network topologies for two exemplary embodiments of this disclosure;

[0014] Figure 2A and Figure 2B Schematic diagrams of the physical layout of two on-chip systems provided for exemplary embodiments of this disclosure;

[0015] Figure 2C for Figure 2B The diagram shows the on-chip network topology of the system-on-chip.

[0016] Figure 3 A flowchart illustrating an exemplary embodiment of the present disclosure of a system-on-a-chip design method;

[0017] Figure 4 A schematic diagram of a system-on-a-chip design device structure is provided for an exemplary embodiment of this disclosure;

[0018] Figure 5 A schematic diagram of another system-on-a-chip design device structure provided for an exemplary embodiment of this disclosure. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be arbitrarily combined with each other.

[0020] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" indicate that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, but do not exclude other elements or objects.

[0021] A System-on-a-Chip (SoC) is a technology that integrates a complete system onto a single chip, grouping all or part of the necessary electronic circuitry. An SoC can contain multiple microprocessors (MPUs), digital signal processors (DSPs), microcontrollers (MCUs), or their combined intellectual property (IP) cores. IP cores are Very Large Scale Integration (VLSI) modules with complex system functions that can be sold independently.

[0022] Network-on-Chip (NoC) is a novel communication method for System-on-Chip (SoC). It is a key component of multi-core technology. NoC offers a completely new on-chip communication approach, significantly outperforming traditional bus-based systems. NoC-based systems are better suited to the globally asynchronous / locally synchronous clock mechanisms used in future complex multi-core SoC designs.

[0023] The design and manufacturing processes of SoC chips are two relatively independent business processes. The SoC design process involves a complex workflow, broadly divided into three main lines: digital circuit design, analog circuit design, and embedded software design. Digital and analog circuit design pertain to the hardware implementation and require finalizing design data before actual production. Embedded software design, on the other hand, can proceed after the actual hardware circuitry is obtained. Currently, most SoC designs are based on digital circuit design, which is further divided into front-end register transfer level (RTL) implementation and back-end synthesis and placement / routing design. In the front-end RTL implementation stage of digital circuit design, hardware programming languages ​​such as Verilog or VHDL are typically used.

[0024] Currently, SoC chip design suffers from insufficient information considerations and unreasonable NoC topology. These issues make it difficult to balance the placement, timing, and area of ​​various subsystem modules during physical implementation, thereby increasing chip development cycle, development costs, and time-to-market risks.

[0025] like Figure 1A and Figure 1B As shown, this disclosure provides an on-chip system, including:

[0026] The on-chip network includes a network routing component, which is set in the top-level module.

[0027] Multiple subsystem modules are interconnected on-chip via a network routing component.

[0028] Figure 1A and Figure 1B In this example, we will introduce the subsystem modules A, B, C, D, E, and F, and the top-level module G. In actual use, the number of subsystem modules can be set as needed.

[0029] The system-on-a-chip in this embodiment of the present disclosure sets the network routing component in the top-level module, and each subsystem module does not include the network routing component. In this way, all subsystem modules are only connected to the top-level module by signal, and there is no direct signal connection between multiple subsystem modules. When laying out each subsystem module, timing issues can be disregarded. When laying out the physical layout, other aspects can be considered more, such as different layouts that minimize chip area, and making clock trees and power networks easier to implement, etc.

[0030] In some exemplary embodiments, the top-level module is designed as the register transfer level (RTL) circuit, and / or the subsystem module is designed as the secondary module for the RTL. RTL design uses a top-down design approach because this approach aligns with the order of module planning and is more conducive to modular design, allowing for parallel design work and improving module reusability. In this embodiment, the hierarchical concepts referred to in the top-level module and secondary module are logical hierarchical concepts, not chip physical hierarchical concepts.

[0031] The on-chip system provided in this embodiment considers the layout information for physical implementation in advance during the front-end design stage. When the chip design enters the physical implementation stage, timing issues related to on-chip networks will not occur, avoiding the iterative process of returning to the front-end design for modification.

[0032] In this embodiment of the disclosure, the network routing component is configured to implement on-chip interconnection between multiple subsystem modules; each subsystem module is configured to implement an independent functional unit in the on-chip system.

[0033] In this embodiment of the disclosure, in addition to network routing components, the top-level module may also include some other logical operation units to implement logical operation functions beyond those corresponding to the multiple subsystem modules.

[0034] In some exemplary embodiments, the on-chip network also includes multiple protocol converters, each of which is located in a subsystem module.

[0035] Although the protocol converter is part of the on-chip network, it is closely related to the subsystem module. In this embodiment of the disclosure, each protocol converter is set in a subsystem module and configured to convert the standard bus protocol used by the subsystem module into the data transmission format corresponding to the on-chip network.

[0036] To meet the operational requirements of different subsystem modules, the clock signal source in a system-on-a-chip is typically divided into several clock domains (CDs). Clock signals in different clock domains may be correlated or independent. If a data transmission channel exists between two clock signals, a clock domain crossing (CDC) problem arises. When digital signals are transmitted across different clock domains, they are treated as asynchronous signals by the other clock domain. If this asynchronous signal is not handled properly, metastability can occur, severely impacting the reliability and stability of the circuit system.

[0037] In the system-on-a-chip (SoC) of this disclosure, during front-end design, the protocol converter and its corresponding subsystem module are placed together. By placing each subsystem module and its corresponding protocol converter in the same clock domain, subsequent logic synthesis and clock tree synthesis are facilitated. For example, in Figure 1A In this chip, protocol converters a, b, c, d, e, and f in the on-chip network are placed in subsystem modules A, B, C, D, E, and F, respectively. By placing the protocol converters with the same clock as each subsystem module together, timing constraints and synthesis are simplified.

[0038] In some exemplary embodiments, the standard bus protocol used by the subsystem module may include at least one of the following: Advanced High Performance Bus (AHB) protocol, Advanced Peripheral Bus (APB) protocol, Advanced eXtensible Interface (AXI) protocol, etc.

[0039] The Advanced Microcontroller Bus Architecture (AMBA) is a bus protocol introduced by ARM. AMBA primarily offers AHB, APB, and AXI bus protocols for different scenarios. The AHB bus protocol is designed for high-efficiency, high-bandwidth, and fast system modules, connecting high-efficiency modules such as microprocessors, on-chip or off-chip memory modules, and DMA. The APB bus protocol is mainly used for low-speed and low-power peripherals, optimizing power consumption and complex interfaces for peripheral devices. The AXI bus protocol is a set of independent channel protocols defined to meet high-performance system design needs, primarily used in on-chip system interconnect design. The AXI bus protocol includes five channels, enabling parallel read and write operations.

[0040] In this embodiment, the data transmission format corresponding to the on-chip network can be defined in various ways, but it mainly involves packaging standard protocols into frame formats and adding routing information, enabling information transmission through the network routing component of the on-chip network. Commands and data in the bus protocol are converted into frame formats, facilitating routing by the on-chip network and enabling pipelined transmission. In specific implementations, timing can be improved by adding buffers, and cross-clock domain data transmission can be handled by adding asynchronous buffers.

[0041] In some exemplary embodiments, the network routing component includes a request switch and a response switch;

[0042] A subsystem module is configured with a corresponding request exchange and a corresponding response exchange; or, two or more subsystem modules share a corresponding request exchange and a corresponding response exchange.

[0043] In this embodiment of the disclosure, the request switch is configured to transmit request data packets among multiple subsystem modules via an on-chip network; the response switch is configured to transmit response data packets among multiple subsystem modules via an on-chip network.

[0044] In this disclosure, the on-chip system may include one or more master resources and one or more slave resources, the slave resources being used by these master resources through multiple arbitration levels. Exemplarily, a master resource corresponds to a computing core or processor. In the case of multiple master resources, all of these master resources are sometimes referred to as multi-master. Exemplarily, a slave resource corresponds to a peripheral device that can be used by one or each master resource.

[0045] When two or more subsystem modules are close to each other (e.g., less than or equal to a first distance threshold) and both of these subsystem modules are either master resources or slave resources, they can share a corresponding request exchange and a corresponding response exchange. In this embodiment, the first distance threshold is mainly determined based on the placement of the two modules during layout, the libs used, and the operating frequency of the designed circuit. Figure 1A As shown, assume that subsystem modules A, B, and D are all master resources, and subsystem modules C, E, and F are all slave resources. Subsystem modules A and B are relatively close, so they can share a corresponding request exchange and a corresponding response exchange. Subsystem modules C, D, E, and F each have their own corresponding request exchange and response exchange.

[0046] In some exemplary embodiments, the network routing component further includes multiple buffers, at least one buffer being disposed between two request switches on one or more transmission paths of the top-level module, and at least one buffer being disposed between two response switches on one or more transmission paths of the top-level module.

[0047] In this embodiment of the disclosure, by adding a buffer on one or more transmission paths, the clock skew on the corresponding transmission path can be reduced, thereby achieving the effect of optimizing timing.

[0048] In this embodiment, after configuring the top-level basic routing components, buffers need to be added to longer transmission paths in the network based on the backend pre-layout information to prevent timing issues caused by physical layout. For example, the need for buffers for each transmission path can be determined based on its path length and clock frequency. If a transmission path is long and has a high clock frequency, causing a clock offset exceeding a preset threshold, then one or more buffers need to be set for that transmission path; otherwise, no buffers are needed. In this embodiment, the specific need for buffers depends on the placement of the two modules during layout, the used libraries, and the operating frequency of the designed circuitry.

[0049] For example, Figure 1B The on-chip network topology diagram shown is in Figure 1A Based on the on-chip network topology shown, buffers were added along the longer transmission paths to improve timing. Figure 1B In this embodiment, a buffer is added to both the request and response paths between subsystem modules A / B and subsystem module F. Because this embodiment considers physical layout information during front-end design and prevents timing issues caused by physical layout by adding buffers, on-chip network-related timing problems will not occur during actual physical layout.

[0050] like Figure 1B As shown, in the design structure of this embodiment, the buffer, request exchange, and response exchange are all located in the top-level module G. The buffer, request exchange, and response exchange can be placed in the same clock domain, which facilitates subsequent logic synthesis and clock tree synthesis.

[0051] In some exemplary embodiments, the on-chip network also includes one or more asynchronous buffers, which are positioned between the subsystem module and the top-level module in a clock domain different from that of the top-level module.

[0052] In some exemplary implementations, each asynchronous buffer includes a first submodule and a second submodule, wherein the first submodule is located in the top-level module and the second submodule is located in the subsystem module.

[0053] In some exemplary embodiments, the first submodule is a read control module and the second submodule is a write control module; or, the first submodule is a write control module and the second submodule is a read control module.

[0054] Because asynchronous buffers support different clocks and resets for both read and write ends, they are an important tool for cross-clock domain data communication. In this embodiment, since all subsystem modules only have signal connections to the top-level module, asynchronous buffers can easily handle cross-clock domain data transmission between subsystem modules and the top-level module. Figure 1A As shown, subsystem module D (and subsystem module F) and top-level module G are not in the same clock domain, and an asynchronous buffer needs to be set between subsystem module D (and subsystem module F) and top-level module G. When subsystem modules and top-level module G are in the same clock domain, an asynchronous buffer does not need to be set between subsystem modules and top-level module G. For example, no asynchronous buffer needs to be added between subsystem modules A / B / C / E and top-level module G. In this embodiment of the present disclosure, there are no direct signal connections between the multiple subsystem modules; therefore, the timing issues between the multiple subsystem modules can be resolved in the top-level on-chip network.

[0055] In this embodiment of the disclosure, a portion of the asynchronous buffer (i.e., the first sub-module) is located in the top-level module, and a portion (i.e., the second sub-module) is located in the corresponding subsystem module, which can solve the cross-clock domain problem between the subsystem module and the top-level module. For example, as Figure 1B As shown, assuming that subsystem module D and top-level module G have different clock domains, and that subsystem module F and top-level module G also have different clock domains, corresponding asynchronous buffers are set up between subsystem module D and top-level module G, and between subsystem module F and top-level module G, respectively. Specifically, for the asynchronous buffer between subsystem module D and its request exchange, the write control module is located in subsystem module D, and the read control module is located in top-level module G; for the asynchronous buffer between subsystem module D and its response exchange, the write control module is located in top-level module G, and the read control module is located in subsystem module D. Conversely, for the asynchronous buffer between subsystem module F and its request exchange, the write control module is located in top-level module G, and the read control module is located in subsystem module F; for the asynchronous buffer between subsystem module F and its response exchange, the write control module is located in subsystem module F, and the read control module is located in top-level module G.

[0056] In some exemplary embodiments, the distance between the layout center of the top-level module and the chip center is smaller than the distance between the layout center of each subsystem module and the chip center, and two or more subsystem modules are laid out around the top-level module.

[0057] In some exemplary embodiments, the system-on-chip also includes an analog function block disposed on the side of at least one subsystem module away from the center of the chip.

[0058] Figure 2A This is a schematic diagram of the physical layout of a system-on-a-chip according to an embodiment of this disclosure. The circuitry of the top-level module G is concentrated in the middle of the chip, while multiple subsystem modules surround the top-level module G, placed close to the perimeter of the chip. H represents an analog functional block. This compact layout helps reduce the chip area. As can be seen, in this layout, subsystem modules A / B and ion system module E are relatively far apart, so buffers are added along the transmission path between them to improve timing. The number of buffers added can be determined based on the transmission path length and the operating frequency.

[0059] Figure 2B This is a schematic diagram of the physical layout of another on-chip system according to an embodiment of this disclosure, such as... Figure 2B As shown, in some cases (e.g., to bring each subsystem module as close as possible to its corresponding analog signal), some chip designs cannot have all subsystem modules packed together very compactly during layout. Figure 2BSubsystem module C is located on the far right, relatively far from the other subsystem modules. During front-end design, after obtaining this physical layout information, it's necessary to consider adding buffers between subsystem module C and subsystem modules A / B, and also between subsystem module C and subsystem module D (the input / output ports of subsystem module C are far from the input / output ports of subsystem module D, meaning the transmission path between subsystem module C and subsystem module D is relatively long), ultimately forming a layout like this... Figure 2C The on-chip network topology shown is arranged in this way. Figure 2B Timing issues will not occur when implementing physical layout.

[0060] This disclosure also provides an electronic device including a system-on-a-chip as described in any embodiment of this disclosure.

[0061] It is understood that the electronic device may also have more components, such as storage units and communication modules connected to the aforementioned system-on-a-chip, but this is not a limitation.

[0062] In this embodiment of the disclosure, the electronic device can be a device with data processing capabilities, such as a mobile phone, computer, tablet, server, etc. Alternatively, the electronic device can also be an independently manufactureable and producible component with data processing capabilities, such as a controller, host, graphics card, processor board, etc.

[0063] like Figure 3 As shown in the embodiments of this disclosure, a system-on-a-chip (SoC) design method is also provided. The SoC includes multiple subsystem modules and an on-chip network configured to interact with the multiple subsystem modules. The on-chip network includes a network routing component. The SoC design method includes the following steps:

[0064] Step 301: In the front-end design, design the top-level module and multiple subsystem modules respectively, and set the network routing component in the top-level module;

[0065] Step 302: Perform functional verification and system simulation verification on the top-level module and multiple subsystem modules to obtain register transfer level code.

[0066] In this embodiment of the disclosure, in addition to network routing components, the top-level module may also include some other logical operation units to implement logical operation functions beyond those corresponding to the multiple subsystem modules.

[0067] The on-chip system design method of this disclosure sets the network routing component in the top-level module, and each subsystem module does not include the network routing component. In this way, all subsystem modules are only connected to the top-level module by signal, and there is no direct signal connection between multiple subsystem modules. When laying out each subsystem module, timing issues can be disregarded. When laying out the physical layout, other aspects can be considered more, such as different layouts that minimize chip area, and making clock trees and power networks easier to implement, etc.

[0068] The on-chip system design method provided in this disclosure considers the layout information for physical implementation in advance during the front-end design stage. When the chip design enters the physical implementation stage, timing issues related to on-chip networks will not occur, avoiding the iterative process of returning to the front-end design for modification.

[0069] In some exemplary embodiments, the top-level module is a top-level module designed for RTL, and / or, the subsystem module is a secondary module designed for RTL. In the embodiments of this disclosure, the hierarchical concepts referred to in the top-level module and the secondary module are hierarchical concepts in a logical sense, rather than hierarchical concepts in the physical sense of the chip.

[0070] The complete chip design process includes the following stages: market demand analysis, architecture design, front-end design, back-end design, manufacturing, and laboratory testing.

[0071] The market demand analysis phase is mainly used to determine the specific functional and performance requirements that the chip needs to achieve.

[0072] The architecture design phase is mainly used to design architecture documents and micro-architecture documents. The architecture document is a high-level description of the system composition and chip architecture, involving high-level chip operation, pin assignment and definition, software programming model, testability, register definition, and application model. The micro-architecture document includes details of the chip's internal operation, clock and reset schemes, functional descriptions of major modules, descriptions of typical data paths, buffer requirement analysis, throughput and latency analysis, interrupt and power management, etc.

[0073] The front-end design phase includes Register Transfer Level (RTL) circuit design and verification. During the RTL design phase, the chip is divided into multiple blocks, and each block is further divided into multiple modules. A hardware description language (such as Verilog / VHDL), syntax checking tools, and other structural tools are used to ensure that all designs adhere to common basic design guidelines. After the RTL design is completed, functional verification and system simulation verification are performed during the verification phase.

[0074] The back-end design phase includes synthesis, static timing analysis (STA), gate-level simulation, and place-and-route (in some cases, synthesis and STA can be included in the front-end design phase). Synthesis includes logic synthesis and clock tree synthesis. Logic synthesis is the process of using software tools to convert RTL code (hardware description language Verilog or VHDL) into logic gates (AND gates, OR gates, and flip-flops, etc.). Clock tree synthesis (CTS) balances the delay of clock paths by establishing a clock network; essentially, it achieves timing convergence by reducing the delay differences between clock paths. Synthesis tools can generate synthesized netlists according to certain principles, such as minimum area or optimal timing characteristics.

[0075] Static timing analysis (STA) is a method used to determine whether the logic of a chip meets timing requirements after synthesis or place-and-route. After RTL code synthesis and placement, the delay parameters of logic gates and the interconnecting wires between them can be extracted; this process is called delay extraction. In synchronous design, a signal passes through multiple logic gates from the output of one flip-flop to the input of another. STA tools can calculate the maximum delay between the output of one flip-flop and the input of another. This maximum delay should be less than one clock cycle to ensure that the output signal reaches the next flip-flop within the current cycle and avoids setup time issues. STA tools also calculate the minimum delay between the output of one flip-flop and the input of another; this minimum delay ensures that the delay value is greater than the required hold time of the flip-flop.

[0076] Gate-level simulation checks the correctness of chip functionality while including timing information. In this case, all internal delays of the chip are labeled, so changes in the logic values ​​of all internal nodes and logic gates reflect the actual delays. This reflects the actual operational behavior of the chip.

[0077] During the placement and routing phase, the layout tool reads the synthesized netlist, where all logic gates appear as transistors and other basic components. After chip placement and routing, precise timing information can be extracted and fed back to the STA tool for accurate timing characteristic checks. Following this, a Design Rule Check (DRC) is performed. Once all these steps are completed, the design data can be submitted to the chip manufacturer.

[0078] In some exemplary embodiments, the network routing component includes a request switch and a response switch, wherein the request switch is configured to transmit request packets among multiple subsystem modules via an on-chip network; and the response switch is configured to transmit response packets among multiple subsystem modules via an on-chip network.

[0079] Each subsystem module is configured with a corresponding request exchange and a corresponding response exchange; or, two or more subsystem modules may share a corresponding request exchange and a corresponding response exchange.

[0080] In this disclosure, the on-chip system may include one or more master resources and one or more slave resources, the slave resources being used by these master resources through multiple arbitration levels. Exemplarily, a master resource corresponds to a computing core or processor. In the case of multiple master resources, all of these master resources are sometimes referred to as multi-master. Exemplarily, a slave resource corresponds to a peripheral device that can be used by one or each master resource.

[0081] When two or more subsystem modules are close to each other (e.g., less than or equal to a first distance threshold) and both of these subsystem modules are either master resources or slave resources, they can share a corresponding request exchange and a corresponding response exchange. In this embodiment, the first distance threshold is mainly determined based on the placement of the two modules during layout, the libs used, and the operating frequency of the designed circuit. Figure 1A As shown, assume that subsystem modules A, B, and D are all master resources, and subsystem modules C, E, and F are all slave resources. Subsystem modules A and B are relatively close, so they can share a corresponding request exchange and a corresponding response exchange. Subsystem modules C, D, E, and F each have their own corresponding request exchange and response exchange.

[0082] In some exemplary embodiments, the on-chip network may also include multiple protocol converters, each of which is located in a subsystem module and configured to convert the standard bus protocol used by the subsystem module into a data transmission format corresponding to the on-chip network.

[0083] To meet the operational requirements of different subsystem modules, the clock signal source in a system-on-a-chip is typically divided into several clock domains (CDs). Clock signals in different clock domains may be correlated or independent. If a data transmission channel exists between two clock signals, a clock domain crossing (CDC) problem arises. When digital signals are transmitted across different clock domains, they are treated as asynchronous signals by the other clock domain. If this asynchronous signal is not handled properly, metastability can occur, severely impacting the reliability and stability of the circuit system.

[0084] The system-on-chip design method of this disclosure, in the front-end design, places the protocol converter and its corresponding subsystem module together. By placing each subsystem module and its corresponding protocol converter in the same clock domain, subsequent logic synthesis and clock tree synthesis can be facilitated. For example, in Figure 1A In this chip, protocol converters a, b, c, d, e, and f in the on-chip network are placed in subsystem modules A, B, C, D, E, and F, respectively. By placing the protocol converters with the same clock as each subsystem module together, timing constraints and synthesis are simplified.

[0085] In some exemplary embodiments, the standard bus protocol used by the subsystem module may include at least one of the following: Advanced High Performance Bus (AHB) protocol, Advanced Peripheral Bus (APB) protocol, Advanced eXtensible Interface (AXI) protocol, etc.

[0086] The Advanced Microcontroller Bus Architecture (AMBA) is a bus protocol introduced by ARM. AMBA primarily offers AHB, APB, and AXI bus protocols for different scenarios. The AHB bus protocol is designed for high-efficiency, high-bandwidth, and fast system modules, connecting high-efficiency modules such as microprocessors, on-chip or off-chip memory modules, and DMA. The APB bus protocol is mainly used for low-speed and low-power peripherals, optimizing power consumption and complex interfaces for peripheral devices. The AXI bus protocol is a set of independent channel protocols defined to meet high-performance system design needs, primarily used in on-chip system interconnect design. The AXI bus protocol includes five channels, enabling parallel read and write operations.

[0087] In this embodiment, the data transmission format corresponding to the on-chip network can be defined in various ways, but it mainly involves packaging standard protocols into frame formats and adding routing information, enabling information transmission through the network routing component of the on-chip network. Commands and data in the bus protocol are converted into frame formats, facilitating routing by the on-chip network and enabling pipelined transmission. In specific implementations, timing can be improved by adding buffers, and cross-clock domain data transmission can be handled by adding asynchronous buffers.

[0088] In some exemplary embodiments, the network routing component may further include a buffer disposed between two request switches on one or more transmission paths of the top-level module, and / or between two response switches on one or more transmission paths of the top-level module, to reduce clock skew on one or more transmission paths. In this embodiment of the disclosure, by adding a buffer on one or more transmission paths, the clock skew on the corresponding transmission paths can be reduced, thereby achieving the effect of optimizing timing.

[0089] In this embodiment, after configuring the top-level basic routing components, buffers need to be added to longer transmission paths in the network based on the backend pre-layout information to prevent timing issues caused by physical layout. For example, the need for buffers for each transmission path can be determined based on its path length and clock frequency. If a transmission path is long and has a high clock frequency, causing a clock offset exceeding a preset threshold, then one or more buffers need to be set for that transmission path; otherwise, no buffers are needed. In this embodiment, the specific need for buffers depends on the placement of the two modules during layout, the used libraries, and the operating frequency of the designed circuitry.

[0090] For example, Figure 1B The on-chip network topology diagram shown is in Figure 1A Based on the on-chip network topology shown, buffers were added along the longer transmission paths to improve timing. Figure 1B In this embodiment, a buffer is added to both the request and response paths between subsystem modules A / B and subsystem module F. Because this embodiment considers physical layout information during front-end design and prevents timing issues caused by physical layout by adding buffers, on-chip network-related timing problems will not occur during actual physical layout.

[0091] like Figure 1BAs shown, in the design structure of this embodiment, the buffer, request exchange, and response exchange are all located in the top-level module G. The buffer, request exchange, and response exchange can be placed in the same clock domain, which facilitates subsequent logic synthesis and clock tree synthesis.

[0092] In some exemplary embodiments, the on-chip network may further include one or more asynchronous buffers, each asynchronous buffer including a first submodule and a second submodule, wherein the first submodule is set in the top-level module and the second submodule is set in the corresponding subsystem module.

[0093] In some exemplary embodiments, the first submodule can be a read control module and the second submodule can be a write control module; or, the first submodule can be a write control module and the second submodule can be a read control module.

[0094] Because asynchronous buffers support different clocks and resets for both read and write ends, they are an important tool for cross-clock domain data communication. In this embodiment, since all subsystem modules only have signal connections to the top-level module, asynchronous buffers can easily handle cross-clock domain data transmission between subsystem modules and the top-level module. Figure 1A As shown, subsystem module D (and subsystem module F) and top-level module G are not in the same clock domain, and an asynchronous buffer needs to be set between subsystem module D (and subsystem module F) and top-level module G. When subsystem modules and top-level module G are in the same clock domain, an asynchronous buffer does not need to be set between subsystem modules and top-level module G. For example, no asynchronous buffer needs to be added between subsystem modules A / B / C / E and top-level module G. In this embodiment of the present disclosure, there are no direct signal connections between the multiple subsystem modules; therefore, the timing issues between the multiple subsystem modules can be resolved in the top-level on-chip network.

[0095] In this embodiment of the disclosure, a portion of the asynchronous buffer (i.e., the first sub-module) is located in the top-level module, and a portion (i.e., the second sub-module) is located in the corresponding subsystem module, which can solve the cross-clock domain problem between the subsystem module and the top-level module. For example, as Figure 1BAs shown, assuming that subsystem module D and top-level module G have different clock domains, and that subsystem module F and top-level module G also have different clock domains, corresponding asynchronous buffers are set up between subsystem module D and top-level module G, and between subsystem module F and top-level module G, respectively. Specifically, for the asynchronous buffer between subsystem module D and its request exchange, the write control module is located in subsystem module D, and the read control module is located in top-level module G; for the asynchronous buffer between subsystem module D and its response exchange, the write control module is located in top-level module G, and the read control module is located in subsystem module D. Conversely, for the asynchronous buffer between subsystem module F and its request exchange, the write control module is located in top-level module G, and the read control module is located in subsystem module F; for the asynchronous buffer between subsystem module F and its response exchange, the write control module is located in subsystem module F, and the read control module is located in top-level module G.

[0096] In some exemplary embodiments, the method further includes:

[0097] Synthesize the register-transfer level code to obtain the synthesized netlist;

[0098] The synthesized netlist is placed and routed, wherein the distance between the placement center of the top-level module and the chip center is smaller than the distance between the placement center of each subsystem module and the chip center, and two or more subsystem modules are placed around the top-level module.

[0099] In some exemplary embodiments, the system-on-chip may further include analog function blocks disposed on the side of at least one subsystem module away from the center of the chip. For example, the analog function blocks may be disposed around the perimeter of the chip.

[0100] Figure 2A This is a schematic diagram of the physical layout of a system-on-a-chip according to an embodiment of this disclosure. The circuitry of the top-level module G is concentrated in the middle of the chip, while multiple subsystem modules surround the top-level module G, placed close to the perimeter of the chip. H represents an analog functional block. This compact layout helps reduce the chip area. As can be seen, in this layout, subsystem modules A / B and ion system module E are relatively far apart, so buffers are added along the transmission path between them to improve timing. The number of buffers added can be determined based on the transmission path length and the operating frequency.

[0101] Figure 2B This is a schematic diagram of the physical layout of another on-chip system according to an embodiment of this disclosure, such as... Figure 2B As shown, in some cases (e.g., to bring each subsystem module as close as possible to its corresponding analog signal), some chip designs cannot have all subsystem modules packed together very compactly during layout. Figure 2B Subsystem module C is located on the far right, relatively far from the other subsystem modules. During front-end design, after obtaining this physical layout information, it's necessary to consider adding buffers between subsystem module C and subsystem modules A / B, and also between subsystem module C and subsystem module D (the input / output ports of subsystem module C are far from the input / output ports of subsystem module D, meaning the transmission path between subsystem module C and subsystem module D is relatively long), ultimately forming a layout like this... Figure 2C The on-chip network topology shown is arranged in this way. Figure 2B Timing issues will not occur when implementing physical layout.

[0102] This disclosure also provides a system-on-a-chip (SoC) designed using the SoC design method described in any embodiment of this disclosure.

[0103] This disclosure also provides a system-on-a-chip (SoC) design apparatus. The SoC includes multiple subsystem modules and an on-chip network configured to interact with the multiple subsystem modules. The on-chip network includes a network routing component, such as... Figure 4 As shown, the on-chip system design device includes: a module design unit 401 and a verification unit 402, wherein:

[0104] Module design unit 401 is configured to design a top-level module and multiple subsystem modules, with the network routing component set in the top-level module;

[0105] Verification unit 402 is configured to perform functional verification and system simulation verification on the top-level module and multiple subsystem modules to obtain register transfer level code.

[0106] In some exemplary implementations, the top-level module is designed for RTL, and / or the subsystem module is designed for RTL.

[0107] In some exemplary embodiments, the on-chip network may also include multiple protocol converters, each of which is located in a subsystem module.

[0108] In some exemplary embodiments, the network routing component may include a request switch and a response switch;

[0109] Each subsystem module is configured with a corresponding request exchange and a corresponding response exchange; or, two or more subsystem modules may share a corresponding request exchange and a corresponding response exchange.

[0110] In some exemplary embodiments, the network routing component may also include a buffer disposed between two of the request switches on one or more transmission paths of the top-level module, and / or disposed between two of the response switches on one or more transmission paths of the top-level module, to reduce clock skew on one or more transmission paths.

[0111] In some exemplary embodiments, the on-chip network may also include one or more asynchronous buffers, each asynchronous buffer including a first submodule and a second submodule, wherein the first submodule is located in the top-level module and the second submodule is located in the subsystem module.

[0112] In some exemplary embodiments, the system-on-chip design apparatus may further include: a synthesis unit and a place-and-route unit, wherein:

[0113] The synthesis unit is configured to synthesize register-transfer level code to obtain a synthesized netlist.

[0114] The placement and routing unit is configured to place and route the synthesized netlist, wherein the distance between the placement center of the top-level module and the chip center is smaller than the distance between the placement center of each subsystem module and the chip center, and two or more subsystem modules are placed around the top-level module.

[0115] In some exemplary embodiments, the system-on-chip may also include an analog function block located on the side of at least one subsystem module away from the center of the chip.

[0116] This disclosure also provides an on-chip system design apparatus, including a memory; and a processor connected to the memory, the memory being used to store instructions, the processor being configured to perform the steps of an on-chip system design method as described in any embodiment of this disclosure based on the instructions stored in the memory.

[0117] like Figure 5 As shown, in one example, the system-on-a-chip design apparatus may include: a processor 510, a memory 520, and a bus system 530, wherein the processor 510 and the memory 520 are connected via the bus system 530, the memory 520 is used to store instructions, and the processor 510 is used to execute the instructions stored in the memory 520, so as to design a top-level module and multiple subsystem modules respectively, and a network routing component is set in the top-level module; functional verification and system simulation verification are performed on the top-level module and the multiple subsystem modules to obtain register transfer level code.

[0118] It should be understood that processor 510 can be a central processing unit (CPU), or it can be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0119] Memory 520 may include read-only memory and random access memory, and provides instructions and data to processor 510. A portion of memory 520 may also include non-volatile random access memory. For example, memory 520 may also store device type information.

[0120] In addition to a data bus, the bus system 530 may also include a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 5 The general labeled all buses as Bus System 530.

[0121] In implementation, the processing performed by the processing device can be accomplished through integrated logic circuits in the hardware of the processor 510 or through software instructions. That is, the method steps of this embodiment can be executed by a hardware processor, or by a combination of hardware and software modules within the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other storage media. This storage medium is located in memory 520, and the processor 510 reads information from memory 520 and, in conjunction with its hardware, completes the steps of the above method. To avoid repetition, further details are omitted here.

[0122] In some possible implementations, various aspects of the system-on-a-chip design method provided in this application can also be implemented as a program product, which includes program code. When the program product is run on a computer device, the program code is used to cause the computer device to perform the steps in the system-on-a-chip design method according to various exemplary embodiments of this application described above. For example, the computer device can execute the system-on-a-chip design method described in the embodiments of this application.

[0123] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0124] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0125] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit the invention. Any person skilled in the art may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope of this disclosure; however, the patent protection scope of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A system-on-a-chip, characterized in that, include: The on-chip network includes a network routing component, which is configured in a top-level module. Multiple subsystem modules are interconnected on-chip through the network routing component.

2. The system-on-a-chip according to claim 1, characterized in that, The top-level module is the top-level module for register conversion stage circuit RTL design, and / or the subsystem module is the secondary module for RTL design.

3. The system-on-a-chip according to claim 1, characterized in that, The on-chip network also includes multiple protocol converters, each of which is located in one of the subsystem modules.

4. The system-on-a-chip according to claim 1, characterized in that, The network routing components include a request switch and a response switch; Each of the subsystem modules is configured with a corresponding request exchange and a corresponding response exchange; Alternatively, two or more of the subsystem modules may share a corresponding request exchange and a corresponding response exchange.

5. The system-on-a-chip according to claim 4, characterized in that, The network routing component also includes multiple buffers, at least one of the buffers being disposed between two request switches on one or more transmission paths of the top-level module, and at least one of the buffers being disposed between two response switches on one or more transmission paths of the top-level module.

6. The system-on-a-chip according to claim 1, characterized in that, The on-chip network also includes one or more asynchronous buffers, which are located between the subsystem module and the top-level module, where the clock domain is different from that of the top-level module.

7. The system-on-a-chip according to claim 6, characterized in that, Each of the asynchronous buffers includes a first submodule and a second submodule, wherein the first submodule is located in the top-level module and the second submodule is located in the subsystem module.

8. The system-on-a-chip according to claim 7, characterized in that, The first submodule is a read control module, and the second submodule is a write control module; or, the first submodule is a write control module, and the second submodule is a read control module.

9. The system-on-a-chip according to claim 1, characterized in that, The distance between the layout center of the top-level module and the chip center is less than the distance between the layout center of each subsystem module and the chip center, and two or more subsystem modules are laid out around the top-level module.

10. The system-on-a-chip according to claim 9, characterized in that, The system-on-a-chip also includes an analog function block, which is located on the side of at least one of the subsystem modules away from the center of the chip.

11. An electronic device, characterized in that, Includes the system-on-a-chip as described in any one of claims 1 to 10.

12. A system-on-a-chip design method, characterized in that, The system-on-a-chip includes multiple subsystem modules and an on-a-chip network that interacts with the multiple subsystem modules. The on-a-chip network includes a network routing component. The method includes: A top-level module and multiple subsystem modules are designed separately, with the network routing component set in the top-level module; Functional verification and system simulation verification are performed on the top-level module and multiple subsystem modules to obtain register transfer level code.

13. The system-on-a-chip design method according to claim 12, characterized in that, The method further includes: The register-transfer level code is synthesized to obtain the synthesized netlist; The synthesized netlist is placed and routed, wherein the distance between the placement center of the top-level module and the chip center is less than the distance between the placement center of each subsystem module and the chip center, and two or more subsystem modules are placed around the top-level module.

14. A system-on-a-chip design device, characterized in that, The system includes a memory; and a processor connected to the memory, the memory being used to store instructions, the processor being configured to perform the steps of the system-on-chip design method as described in any one of claims 12 to 13 based on the instructions stored in the memory.

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