Module schematic diagram automatic design method suitable for electronic product design

Abstract

The invention discloses a module schematic diagram automatic design method suitable for electronic product design, and belongs to the technical field of electronic design automation. The method aims at solving the problems that traditional manual schematic diagram design is low in efficiency, prone to errors and highly dependent on experience of engineers. The method comprises the following steps: firstly, carrying out structured information modeling on a design demand, a design template and a to-be-generated module; secondly, according to the design requirement after modeling, all candidate main chip sets meeting the conditions are screened out from a device library; then, aiming at each candidate main chip, automatically constructing a peripheral circuit of the candidate main chip through a template matching process; and finally, calculating the general device in the template according to the parameters of the main chip and replacing the general device with an actual device with a specific model. According to the method, various module schematic diagram schemes which conform to specifications and can be optimized can be quickly and accurately generated according to a single design requirement, the automation level and efficiency of electronic design are remarkably improved, and the design threshold is reduced.

Description

Technical Field

[0001] This invention belongs to the field of electronic design automation (EDA) technology, and specifically relates to a method for automatically designing module schematics based on user requirements through template matching and component replacement. Background Technology

[0002] In modern electronic product design and manufacturing processes, schematic design is a crucial link connecting concepts with physical objects. It not only provides the core basis for the physical layout and routing of PCBs but also guides product production. As the basic unit of the overall design, a modular schematic diagram typically consists of a functional core (main chip) and a series of peripheral components (such as resistors and capacitors) to achieve an independent function, such as power conversion or wireless communication.

[0003] Currently, the design of module schematics largely relies on the expertise and manual operation of design engineers. Engineers typically spend a significant amount of time reading datasheets from various manufacturers to extract circuit design references. This process is not only inefficient but also faces numerous challenges, including:

[0004] 1. Component selection is time-consuming and labor-intensive: Faced with a massive library of components with similar functions but different characteristics, engineers need to invest a lot of energy in screening and comparing them. The selection process is tedious and prone to errors.

[0005] 2. Poor design standardization and consistency: Different engineers have different design habits, resulting in a lack of consistency in the layout, naming and symbol standards of the produced schematic diagrams.

[0006] 3. High electrical error rate: In complex designs, manually connecting a large number of pins can easily introduce electrical rule conflicts, such as pin type mismatch or missing power networks. These errors are often only discovered later, increasing rework costs.

[0007] Furthermore, while existing mainstream EDA platforms (such as AD and KiCad) are powerful, they are primarily positioned as design assistance tools and do not yet support the direct generation of module-level schematics from advanced functional requirements. Some emerging commercial software that incorporates artificial intelligence (AI) (such as Flux.ai) attempts to simplify design through human-computer question-and-answer sessions, but still requires users to have a solid professional background to judge the accuracy of AI-generated content and cannot completely avoid the illusion problem inherent in AI.

[0008] In summary, there is currently a lack of an end-to-end automated method in the market that can directly, quickly, and accurately generate schematic diagrams of multiple optional modules based on the user's macro-level design requirements. Summary of the Invention

[0009] The purpose of this invention is to overcome the shortcomings of existing technologies and provide an efficient, accurate, and automated method for automatic design of module schematics suitable for electronic product design. This method aims to liberate designers from tedious component selection and manual drawing work by modeling information throughout the entire design process and using template-based matching to achieve end-to-end generation of schematics from abstract requirements to concrete, compliant, and multi-scheme designs.

[0010] To achieve the above objectives, the present invention is implemented through the following technical solution:

[0011] An automated schematic design method for electronic products is proposed. Its core lies in modeling design requirements, design templates, and modules to be generated; selecting all suitable main chips from a component library; performing template matching for each main chip; and replacing general-purpose components with specific model components. This automates the design of the module schematic and provides multiple design options, including the following steps:

[0012] Step 1: Information Modeling. This involves performing structured information modeling of the design requirements (including functional and non-functional requirements), the design template (representing the topology of the peripheral circuit), and the final generated module schematic.

[0013] Step 2: Main Chip Selection. Based on the design requirements after modeling, search the device library and determine all candidate main chips that meet the conditions, providing a foundation for generating multiple design schemes in the future.

[0014] Step 3: Template Matching. For each candidate main chip, a series of sub-steps are performed, including: obtaining candidate templates, performing pin matching, updating module information, and checking connection integrity and compliance, to automatically construct a complete peripheral circuit.

[0015] Step 4: Component Model Replacement and Result Output. After completing the construction of the module schematic, based on the specific parameters of the main chip, calculate and replace the general components in the template with the actual model components, and finally output the schematics of all successfully designed modules.

[0016] The present invention has the following beneficial effects:

[0017] 1. Significantly improves design efficiency and automation: This invention shortens the manual design process, which originally took hours or even days, to minutes or even seconds. Through automated main chip selection, template matching, and component replacement, it greatly reduces manual intervention, achieving end-to-end generation from design requirements to multiple schematic diagrams, thus shortening the product design cycle.

[0018] 2. Offers diverse design solutions: This invention is not limited to a single result, but rather selects all possible main chips based on user needs and generates their respective schematic diagrams. Users can compare and weigh these solutions based on different dimensions such as cost, area, and performance to make the optimal decision.

[0019] 3. Ensuring the standardization and accuracy of the design: Based on standardized design templates and a preset connection compliance rule library, this invention ensures that every generated schematic diagram conforms to electrical design specifications, effectively avoiding problems such as pin connection errors and type mismatches caused by human negligence, and significantly reducing the cost of later troubleshooting and rework.

[0020] 4. Lowering the Design Threshold and Enhancing Knowledge Reuse: By solidifying the design experience of senior engineers into design templates, this invention enables junior engineers to quickly complete high-quality module designs. The establishment and reuse of design templates constitute a knowledge base for the enterprise or team, promoting the accumulation of design knowledge. Attached Figure Description

[0021] Figure 1 This invention provides a framework diagram for an automatic design method of module schematic diagrams suitable for electronic product design.

[0022] Figure 2 This is a flowchart of a template matching method provided by the present invention.

[0023] Figure 3 This is a flowchart of a pin matching method provided by the present invention.

[0024] Figure 4 This is a schematic diagram of the first module schematic scheme generated according to the method of the present invention for a specific design requirement.

[0025] Figure 5 According to the method of the present invention, it is aimed at... Figure 4 A schematic diagram of the second module schematic scheme generated based on the same design requirements. Detailed Implementation

[0026] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. These descriptions are intended to explain the invention and not limit it. (Reference) Figure 1 This invention provides an automatic design method for module schematics suitable for electronic product design, specifically including the following steps:

[0027] Step 1: Information Modeling. Information modeling is the process of transforming unstructured information from the design process into structured data that can be processed by computers, and it is the foundation for achieving automation.

[0028] Step 1.1: Design Requirements Modeling. To accurately capture user intent, design requirements are broken down into functional and non-functional requirements for modeling. Functional requirements are mandatory, while non-functional requirements are optional and used to further constrain the design. The specific content is as follows:

[0029] Demand type name Data types meaning Functional requirements Module type String Required module types Non-functional requirements brand List Expected main chip brand Non-functional requirements Projected area floating point Maximum projected area of ​​the main chip (unit: square millimeters) Non-functional requirements volume floating point Maximum volume of the main chip (unit: cubic millimeters) Non-functional requirements price floating point Maximum price of main chip (unit: yuan) Non-functional requirements Operating voltage floating point Maximum operating voltage of the main chip (unit: volts)

[0030] Step 1.2: Design Template Information Modeling. A design template is a fixed representation of an empirical circuit topology, describing the structure of a typical peripheral circuit. The design template undergoes structured modeling, specifically including:

[0031]

[0032]

[0033] Step 1.3: Module Schematic Information Modeling. The module schematic is represented in a structured manner, serving as the data structure for the final output. Specific content includes:

[0034]

[0035] Step 2: Main Chip Selection. Based on the design requirement model established in Step 1.1, a selection process is performed from a pre-defined device library containing detailed parameters. This process can be formally described as follows:

[0036] mainChips=d∈D lib |F func (d)∧F non-func (d)

[0037] In the formula, mainChips is the set of candidate main chips selected, and D lib It is a device library, F func (d) is the functional requirement matching function, F non-func (d) is the non-functional requirement matching function.

[0038] The functional requirement matching function is used to ensure that the type of the main chip is consistent with the required module type. The specific method is as follows:

[0039] F func (d)≡(d.type=moduleType)

[0040] In the formula, d.type is the type of the main chip, and moduleType is the module type in the design requirements.

[0041] In addition, the non-functional requirement matching function is used to check each non-functional requirement specified by the user, specifically as follows:

[0042]

[0043] In the formula, brand, maxProArea, maxVolume, maxPrice, and maxVoltage represent the brand, projected area, volume, price, and operating voltage in the design requirements, respectively, while d.brand, d.pArea, d.vol, d.price, and d.voltage represent the brand, projected area, volume, price, and operating voltage of the main chip, respectively.

[0044] This query yields all candidate main chips that meet the criteria, providing a basis for generating various design schemes.

[0045] Step 3: Candidate Template Acquisition and Module Initialization. This is the beginning of the template matching process. For template matching methods, please refer to [link / reference]. Figure 2 For each candidate main chip selected in step 2, the following process is executed sequentially.

[0046] Step 3.1: For the current main chip, initialize a blank functional module instance to record the device and connection information of the main chip and its peripheral circuits, and add the main chip as the first device.

[0047] Step 3.2: Query the detailed pin information of the current main chip from the device library, such as pin name and pin electrical type. For a main chip, all its pins need to be connected to the template. Therefore, by recording the usage count of each pin of the main chip and its connection information with the template, it is possible to quickly determine whether all pins of the main chip are connected. A record of the usage count and connection information is created for each pin, with the usage count initialized to 0 and the connection information initialized to empty.

[0048] Step 3.3: Search the template library based on the module type and pin name information of the current main chip. A valid candidate template must meet at least the following conditions: the module type is consistent with the main chip; and at least one pin in the template's input pin set has a name that appears in the main chip's pin list. All templates that meet these conditions constitute the candidate template set.

[0049] Step 3.4: By traversing the candidate template set, attempt to match and connect each template with the main chip. For each candidate template, check if its input pins are a subset of the main chip's pin set. If not, the template is not suitable for the current main chip and is skipped; otherwise, proceed to the next pin matching step.

[0050] Step 4: Pin matching. (See reference) Figure 3This step establishes the actual connection between the template and the main chip. First, to prevent contamination of the original data in case of a matching failure, a temporary copy of the main chip's pin usage record is created. Then, the input pin set of the current template is traversed. For each input pin of the template, a matching pin is searched for in the main chip. If the main chip has multiple matching pins, the pin with the fewest uses is selected for connection to achieve load balancing.

[0051] When attempting to connect, a redundancy check is performed: if all the main chip pins that the template requires to be connected have already been connected by other templates (i.e., the usage count of all corresponding pins is greater than 0), it means that the function provided by the template may be duplicated with the already connected templates, and it is judged as redundant. This template is skipped. The judgment is made here by the reuse status.

[0052] If it is not redundant, update the usage count (increment by 1) and connection information of the corresponding main chip pin in the temporary copy. If all input pins successfully find a match, write the update in the temporary copy into the original record created in step 3.2, and return a successful match.

[0053] Step 5: Module information update and connection integrity check.

[0054] Step 5.1: Once a candidate template successfully matches a main chip pin, add the device information and connection relationships contained in the template to the functional module initialized in Step 3.1, and establish the connection relationship between the template and the main chip. If the candidate template fails to match a main chip pin, iterate through the next candidate template.

[0055] Step 5.2: After each update, check the usage count of all pins on the main chip. If the usage count of all pins is greater than 0, it means that all pins of the main chip have been successfully connected, the peripheral circuit design of the main chip is complete, and the template matching process for this main chip can be terminated early. If, after traversing all candidate templates, there are still pins with a usage count of 0, it indicates that a complete peripheral circuit cannot be built for the main chip, and the design of the main chip is determined to be a failure.

[0056] Step 6: Connection Compliance Check. After matching the main chip with the module, all pin connections between the main chip and the module need to be checked to determine if they comply with basic pin connection rules. This step is accomplished using a preset pin connection rule library, which defines the allowed electrical types of connections, such as output and input types. By iterating through all connections, if at least one pair of pins that does not comply with the connection rules is found, the schematic design of the current main chip module is deemed non-compliant, and the design process for that main chip is terminated.

[0057] Step 7: Replace device model and output results.

[0058] Step 7.1: For different main chip models, the values ​​of each component in its peripheral circuit may differ. Therefore, it is necessary to calculate and determine the values ​​based on the main chip and template information, and then replace the actual components according to the calculation results. Iterate through each component in the module that originates from the template, searching for the parameter calculation formula or default value defined in the template information. If a calculation formula exists, calculate the specific parameter value of the component based on the main chip information and the established connection relationships; if no calculation formula exists, directly use the preset default value.

[0059] Step 7.2: Based on the specific parameter values ​​and device types obtained in Step 7.1, perform a secondary query in the device library to filter out all actual device models that meet the conditions. Typically, the model with the lowest price or the most abundant inventory is selected.

[0060] Step 7.3: Replace the corresponding general component information in the module with the actual component model information obtained from the query. At this point, a complete module schematic design is complete. Summarize and output the schematic designs successfully generated from all candidate main chips.

[0061] Example

[0062] To more clearly illustrate the application effects of the present invention, a specific embodiment is given below.

[0063] Assume the specific details of the design requirements are as follows:

[0064] name Requirements Module type AC-DC voltage conversion brand [Mornsun, Hilink, CUI] Projected area 896.43 volume 27827.6 price 354.77 Operating voltage 308.55

[0065] Based on the aforementioned requirements, this invention selected two suitable candidate main chips from the device library: the HLK-5M03 chip from Hilink and the VSK-S3-3R3U chip from CUI. This invention executed steps 3 to 7 of the process for each of these two chips, successfully completing the schematic design. Ultimately, this invention will output two design schemes.

[0066] Reference Figure 4 The paper showcases a module schematic based on the HLK-5M03 main chip, and demonstrates its implementation. In this schematic, the HLK-5M03 serves as the core, and its peripheral circuitry consists of several resistors, capacitors, fuses, and diodes. The models and parameters of these components have been calculated and determined based on the characteristics of the HLK-5M03.

[0067] Reference Figure 5The paper demonstrates a schematic diagram of a module based on the main chip VSK-S3-3R3U, and illustrates the design based on this diagram. Because the internal structure and electrical characteristics of the VSK-S3-3R3U differ from those of the HLK-5M03, the topology and device parameters of its peripheral circuits have also changed accordingly, with the addition of a polarized capacitor.

[0068] With these two parallel, complete, and production-ready schematics, designers can intuitively weigh the pros and cons from the perspectives of cost, number of components, etc., and choose the solution that best meets their project requirements without having to delve into the detailed differences between the two chips.

[0069] In summary, this invention, through systematic information modeling, intelligent matching algorithms, and automated parameter calculation and replacement, can efficiently and reliably complete the automatic generation process from an abstract design requirement to multiple specific, comparable, and selectable schematic design schemes, thus achieving a significant acceleration and optimization of electronic design.

Claims

1. An automatic design method for module schematics suitable for electronic product design, characterized in that, Includes the following steps: Step 1, Information Modeling: Perform structured information modeling on design requirements, design templates, and schematic diagrams of modules to be generated. The design requirement model includes functional and non-functional requirements, the design template model includes the applicable module types, device sets, internal connection relationships, and input and output pin sets, and the schematic diagram model of modules to be generated includes the module type, device sets, internal connection relationships, and external pin sets. Step 2, Main Chip Screening: Based on the functional and non-functional requirements in the design requirement model, a search is conducted in the preset device library to screen out all candidate main chips that meet the conditions, forming a candidate main chip set. Step 3, Template Matching: For each candidate main chip in the candidate main chip set, template matching is performed to determine its peripheral circuit. The template matching method includes obtaining candidate templates, performing pin matching, updating module information, and performing connection integrity and compliance checks. Step 4, Component Model Replacement and Scheme Generation: After successful template matching, the general components defined in the design template are replaced with actual components with specific parameters and models, ultimately generating one or more complete module schematic design schemes.

2. The method according to claim 1, characterized in that, Step 1, design requirements modeling, specifically includes: The module types of design requirements are modeled as functional requirements; The list of alternative brands for the main chip, the maximum projected area, the maximum volume, the highest price, and the maximum operating voltage are modeled as non-functional requirements.

3. The method according to claim 1, characterized in that, The template matching method in step 3 further includes: Step 3.1, Candidate Template Acquisition and Module Initialization: For the current candidate main chip, initialize a functional module for recording design results; and select a set of candidate templates from the template library according to the module type and pin information of the main chip. Step 3.2, Pin Matching: Traverse the candidate template set, and according to the preset pin connection rules, attempt to match the input pin of each candidate template with the pin of the main chip, and perform connection redundancy judgment; Step 3.3, Module Information Update: After the candidate template successfully matches the main chip pins, the device information and connection relationship information contained in the template are updated to the functional module; Step 3.4, Connection Integrity and Compliance Check: Check whether all pins of the main chip are connected, and perform compliance checks such as electrical type compatibility on all established pin connections; if the check fails, the schematic design of the current main chip is determined to be faulty.

4. The method according to claim 3, characterized in that, In step 3.1, after initializing the functional module, the process further includes: querying all pin information of the current main chip and establishing a record of the number of times each pin is used and connection information, which will be used for judgment in steps 3.2 and 3.

4.

5. The method according to claim 3, characterized in that, The pin matching in step 3.2 is specifically implemented as follows: when there are multiple available pins with the same name on the main chip, the pin that is used the least is selected for connection in order to achieve a balanced allocation of connection resources.

6. The method according to claim 3, characterized in that, The connection redundancy judgment in step 3.2 is as follows: before attempting to connect a new template, it is determined whether all the main chip pins that the template needs to connect to have been connected by other templates; if so, the new template is determined to be a redundant template, and the matching is skipped to avoid functional duplication.

7. The method according to claim 1, characterized in that, The component model replacement in step 4 further includes: Step 4.1, Parameter Calculation: Traverse each general device in the module that originates from the template, and calculate the specific parameter value of the device based on the preset parameter calculation formula or default value in the template and the main chip information. Step 4.2, Model Query and Replacement: Based on the calculated parameter values ​​and device types, query and filter the actual device models that meet the conditions in the device library, and replace the general device information in the module with their actual model information.

8. The method according to claim 7, characterized in that, The parameter calculation formula is predefined based on circuit theory and stored in the design template, and its variables come from the datasheet parameters of the main chip or the established connection relationships.

9. The method according to claim 3, characterized in that, The connection compliance check in step 3.4 is performed by comparing the electrical type of the pin pair to be checked with a preset pin connection rule library; the rule library defines compatible combinations of electrical types.

10. The method according to claim 1, characterized in that, After completing the process for all candidate main chips, the method outputs the schematic diagrams of all successfully designed modules as multiple design schemes for users to choose from.

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