Board card defect adaptive identification and positioning method and system based on deep learning

Abstract

The invention discloses a board card defect adaptive identification and positioning method and system based on deep learning, and relates to the field of deep learning, and the method comprises the steps: collecting a surface image of a to-be-detected board card; through a parallel double-branch convolutional neural network model, branch layout features are arranged, and branch discrimination features are discriminated; dividing the board card into areas according to functional areas based on the board card layout characteristics; obtaining layout characteristics of defect-free samples based on the model of the board card to be detected, and obtaining a defect data set of a known defect type; comparing the to-be-tested board card with a standard layout prototype to obtain a layout difference degree; carrying out defect judgment according to the layout difference degree, and carrying out defect area positioning; and performing defect category identification and classification, and updating a defect data set for a novel defect category. The method has the advantages that through deep learning and the double-branch convolutional neural network, the difference of board card layout is effectively identified, and the defect area is quickly positioned.

Description

Technical Field

[0001] This invention relates to the field of deep learning, and in particular to a method and system for adaptive identification and localization of board defects based on deep learning. Background Technology

[0002] With the increasing complexity of electronic devices, especially in the fields of integrated circuits and circuit board manufacturing, the identification and location of board defects has become an indispensable and crucial aspect of the production process. As electronic products evolve towards miniaturization, high density, and multifunctionality, the design and manufacturing complexity of circuit boards has surged. Subtle surface defects, such as poor solder joints, short circuits, missing components, misalignment, scratches, foreign objects, and copper foil damage, are not only difficult to observe with the naked eye but also pose a serious threat to the performance and reliability of the final product.

[0003] Current market-available adaptive identification and localization methods and systems for circuit board defects struggle to fully exploit the complex layout and local defect features of circuit boards, resulting in low identification and localization accuracy. Secondly, some systems cannot effectively process multi-view image data, often relying solely on single-view images for analysis, ignoring subtle differences in the circuit board surface at different angles. Furthermore, traditional methods typically depend on simple difference measurement methods for layout comparison and defect determination, failing to adapt to complex circuit board layouts and subtle geometric differences, leading to poor defect determination accuracy. Moreover, the lack of incremental learning mechanisms prevents effective responses to the emergence of new defects, resulting in poor system adaptability and an inability to keep pace with technological advancements. Finally, many systems do not employ modern data storage technologies such as blockchain, leading to poor security and traceability of defect data, limiting system scalability and long-term stability. Summary of the Invention

[0004] To improve existing methods and systems, this paper provides a deep learning-based adaptive identification and localization method and system for board defects. This method achieves efficient identification and localization of board defects through deep learning and a dual-branch convolutional neural network. It accurately locates defect areas by combining layout features and local defect features, and ensures the intelligence and scalability of the system through incremental learning.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A deep learning-based adaptive identification and localization method for board defects includes: The surface image of the board to be tested is acquired, including a global view image and a high-resolution local view image, and the acquired images are preprocessed. The preprocessed image is input into a parallel dual-branch convolutional neural network model. The layout branch obtains layout features related to the layout of board components and routing patterns, while the discrimination branch obtains discrimination features related to local texture anomalies and shape irregularities. Based on the board layout characteristics, the board is divided into functional areas, including functional areas, circuit areas and blank areas, and identifiers are added to the components and circuits in each area. Based on the model of the board under test, the layout features of defect-free samples are obtained from the board database as a standard layout prototype, and at the same time, a defect dataset of known defect types is obtained. The layout difference is obtained by comparing the layout of each area of ​​the board under test with that of each area of ​​the standard layout prototype. Set a layout difference threshold, determine defects based on the relationship between the layout difference and the threshold, and locate the defect area. Based on the obtained defect identifiers and defect locations, the defects are identified and classified, and the defect dataset is updated for new defect categories.

[0006] Preferably, the acquisition of the surface image of the board to be tested includes a global view image and a high-resolution local view image, and the preprocessing of the acquired image specifically includes: The camera captures global view images and captures high-resolution local view images of each area on the board surface as local view images. Preprocessing is performed on images from various perspectives, including image denoising, image enhancement, geometric correction, image registration, image cropping, and grayscale binarization.

[0007] Preferably, the step of inputting the preprocessed image into a parallel dual-branch convolutional neural network model, with the layout branch acquiring layout features related to board component layout and wiring patterns, and the discrimination branch acquiring discrimination features related to local texture anomalies and shape irregularities, specifically includes: The preprocessed image is input into a two-branch convolutional neural network model; The layout branch extracts features from the input image through multiple convolutional layers, obtaining features at different levels, including low-level edge and corner features and high-level layout patterns and wiring connection features. By using an attention mechanism, the features of specific locations in the image are enhanced, irrelevant areas are ignored, and layout features related to the layout of board components and routing patterns are obtained. The discriminative branch extracts detailed features of local regions, including defects, cracks, and irregularly shaped areas, through multiple convolutional layers; The contribution of features is determined by channel attention mechanism, and the spatial attention mechanism is used to focus on defect areas in the image to obtain discriminative features related to local texture anomalies and shape irregularities. The layout branch and the discrimination branch work in parallel, each extracting the features of interest.

[0008] Preferably, the step of dividing the board into functional areas based on board layout features, including functional areas, circuit areas, and blank areas, and adding identifiers to the components and circuits in each area specifically includes: Based on the acquired board layout features, the board is divided into functional areas, including circuit area, component area and blank area; The circuit area presents continuous and dense wiring paths, the component area is composed of rectangular, circular and irregularly shaped patterns with regular shapes, and the blank area is the unused area of ​​the board, which is an area without obvious shape. Based on the divided functional areas, each area is marked and a unique identifier is added; Based on the size and shape of each component in the component area, the components are identified and classified. Different types of components, such as resistors, capacitors, and chips, are identified and a unique identifier is added. A unique identifier is also assigned to each line in the circuit area.

[0009] Preferably, the step of obtaining the layout features of defect-free samples from the board database based on the model of the board under test as a standard layout prototype, and simultaneously obtaining a defect dataset of known defect types, specifically includes: Obtain the model data of the board under test, query the board database, and obtain the defect-free sample data for that model. Extract layout features from defect-free samples, including component layout features, trace layout features, and functional area distribution; The database is used to filter out defect datasets related to the model of the board under test, including electrical defects, geometric defects, and visual defects.

[0010] Preferably, the step of obtaining the layout difference by comparing the layout of each area of ​​the board under test with the layout of each area of ​​the standard layout prototype specifically includes: Coordinate alignment is performed based on the obtained layout features of the board under test and the standard layout prototype of the defect-free sample. Based on the aligned two boards, the geometric differences between the two are obtained by calculating the Hausdorff distance, the positional deviation of the components in the area of ​​the board under test is calculated, the curvature, connectivity and density of the lines are calculated to obtain the differences in the routing paths, and the area coverage difference between the area of ​​the board under test and the standard layout prototype is obtained. The differences in each region are quantified by difference scores, and the difference scores are weighted and averaged according to the importance of each region in the overall board to obtain the final layout difference score.

[0011] Preferably, the step of setting a layout difference threshold, determining defects based on the relationship between the layout difference and the threshold, and locating the defect area specifically includes: Set a layout difference threshold. Based on the relationship between the layout difference and the preset threshold, if it is greater than the threshold, it is judged as a defect, and the defect location is located based on the identifier. If the value is less than the threshold, the discriminative features obtained by the convolutional neural network model are matched with the data in the defect dataset, and the matching degree is calculated as the probability of the defect's existence using a similarity matching algorithm. A threshold for the probability of a defect is set. If the probability of a defect is less than the threshold, it is determined that there is no defect. If the probability is greater than the threshold, it is determined that there is a defect, and the defect location is located based on the identifier.

[0012] Preferably, the step of identifying and classifying defects based on the acquired defect identifier and defect location, and updating the defect dataset for new defect categories, specifically includes: Construct a defect category identification model and train the model based on historical data to obtain the trained defect category identification model; Input the obtained defect identifier and defect location into the defect category recognition model to obtain the defect category and generate defect labels; For newly identified defects, the model and dataset are updated by learning the new defect categories through incremental learning.

[0013] Preferably, the board database adopts a blockchain storage architecture, including: a standard layout prototype library: storing board models and layout features of each board; a defect dataset: stored in a {defect type: feature vector: location template} structure; and an update log: recording new defects and adding identifiers.

[0014] Furthermore, a deep learning-based adaptive identification and localization system for board defects is proposed, including: Image acquisition module: The module acquires global view images and local high-resolution images of the board under test through a camera; Dual-branch convolutional neural network module: The module inputs the preprocessed image into a parallel dual-branch network, extracts layout-related features such as board component layout and wiring patterns through convolutional layers, and extracts local texture anomaly features such as defects, cracks and shape irregularities through convolutional layers; Functional area division module: The module divides the board into functional areas, circuit areas and blank areas according to the board layout characteristics, and adds identifiers to each area; Standard layout comparison module: This module calculates the board layout difference by comparing the layout features with those of a defect-free sample; Defect Judgment and Location Module: The module judges defects and locates defect areas based on the comparison between layout difference and threshold, identifies defect categories through defect identifiers and locations, and generates labels; Data update module: This module incrementally learns new defect categories and updates the defect dataset; Processor: The processor is used to handle the calculation process of each formula and the construction calculation process of each model.

[0015] Compared with the prior art, the advantages of the present invention are: By acquiring images from both global and high-resolution local perspectives, and combining them with advanced image preprocessing techniques, detailed features of the circuit board can be accurately extracted. A dual-branch convolutional neural network model is employed, with the layout and discrimination branches working in parallel, effectively separating the component layout, wiring patterns, and local defect features of the circuit board, thus improving recognition accuracy. Secondly, by functional area division, the circuit board is divided into different regions, and a unique identifier is added to each region and component, further enhancing the accuracy of defect localization and classification. A standard layout prototype comparison method based on defect-free samples, combined with geometric difference measures such as Hausdorff distance, effectively identifies differences in circuit board layout and quickly locates defect areas. Finally, this method introduces incremental learning techniques, enabling continuous updates to the defect dataset to adapt to the emergence of new defect types, thereby maintaining the system's long-term efficiency and intelligence. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the method proposed in this invention; Figure 2 This is a schematic diagram illustrating the acquisition of the image of the board under test proposed in this invention; Figure 3 This is a schematic diagram of the dual-branch convolutional neural network model proposed in this invention; Figure 4 This is a schematic diagram of the functional area division proposed in this invention; Figure 5 This is a schematic diagram illustrating the method for obtaining defect datasets as proposed in this invention. Figure 6 This is a schematic diagram illustrating the method for obtaining layout differences proposed in this invention; Figure 7 This is a schematic diagram illustrating the defect area determination and location proposed in this invention; Figure 8 This is a schematic diagram illustrating the defect category classification and update proposed in this invention. Detailed Implementation

[0017] The following description is intended to disclose the invention and enable those skilled in the art to implement it. The preferred embodiments described below are merely examples, and other obvious variations will occur to those skilled in the art.

[0018] A deep learning-based adaptive identification and localization system for board defects includes: Image acquisition module: The module acquires global view images and local high-resolution images of the board under test through a camera; Dual-branch convolutional neural network module: The module inputs the preprocessed image into a parallel dual-branch network, extracts layout-related features such as board component layout and wiring patterns through convolutional layers, and extracts local texture anomaly features such as defects, cracks and shape irregularities through convolutional layers; Functional area division module: The module divides the board into functional areas, circuit areas and blank areas according to the board layout characteristics, and adds identifiers to each area; Standard layout comparison module: This module calculates the board layout difference by comparing the layout features with those of a defect-free sample; Defect Judgment and Location Module: The module judges defects and locates defect areas based on the comparison between layout difference and threshold, identifies defect categories through defect identifiers and locations, and generates labels; Data update module: This module incrementally learns new defect categories and updates the defect dataset; Processor: The processor is used to handle the calculation process of each formula and the construction calculation process of each model.

[0019] See Figure 1 As shown, the deep learning-based adaptive identification and localization method for board defects includes: Step 1: Acquire surface images of the board to be tested, including global view images and high-resolution local view images, and preprocess the acquired images; Step 2: Input the preprocessed image into a parallel dual-branch convolutional neural network model. The layout branch obtains layout features related to the layout of board components and routing patterns, while the discrimination branch obtains discrimination features related to local texture anomalies and shape irregularities. Step 3: Based on the board layout characteristics, divide the board into functional areas, including functional areas, circuit areas, and blank areas, and add identifiers to the components and circuits in each area; Step 4: Based on the model of the board to be tested, obtain the layout features of the defect-free samples from the board database as a standard layout prototype, and at the same time obtain the defect dataset of known defect types. Step 5: Obtain the layout difference by comparing the layout of each area of ​​the board under test with that of the standard layout prototype; Step 6: Set a layout difference threshold, determine defects based on the relationship between the layout difference and the threshold, and locate the defect area. Step 7: Based on the obtained defect identifier and defect location, identify and classify the defect category, and update the defect dataset for new defect categories.

[0020] See Figure 2 As shown, surface images of the board under test are acquired, including global view images and high-resolution local view images, and the acquired images are preprocessed, specifically including: The camera captures global view images and captures high-resolution local view images of each area on the board surface as local view images. Preprocessing is performed on images from various perspectives, including image denoising, image enhancement, geometric correction, image registration, image cropping, and grayscale binarization.

[0021] See Figure 3 As shown, the preprocessed image is input into a parallel dual-branch convolutional neural network model. The layout branch obtains layout features related to the layout of board components and routing patterns, while the discrimination branch obtains discrimination features related to local texture anomalies and shape irregularities. Specifically, these features include: The preprocessed image is input into a two-branch convolutional neural network model; The layout branch extracts features from the input image through multiple convolutional layers, obtaining features at different levels, including low-level edge and corner features and high-level layout patterns and wiring connection features. By using an attention mechanism, the features of specific locations in the image are enhanced, irrelevant areas are ignored, and layout features related to the layout of board components and routing patterns are obtained. The discriminative branch extracts detailed features of local regions, including defects, cracks, and irregularly shaped areas, through multiple convolutional layers; The contribution of features is determined by channel attention mechanism, and the spatial attention mechanism is used to focus on defect areas in the image to obtain discriminative features related to local texture anomalies and shape irregularities. The layout branch and the discrimination branch work in parallel, each extracting the features of interest.

[0022] Specifically, the layout branch is responsible for extracting features related to the layout and routing patterns of board components. The input image is processed through multiple convolutional layers. Each convolutional operation extracts features at different levels from the image. Low-level features, such as edges and corners, are extracted by the shallow layers of the network, while high-level features, such as layout patterns and routing connection features, are extracted by the deep layers. The attention mechanism is used to enhance the features of important regions in the image. Through the attention mechanism, the key regions in the image, such as board components and wiring connections, can be automatically focused on while ignoring irrelevant background areas. The discriminant branch is mainly responsible for extracting local texture anomalies and shape irregularities in the image. Similar to the layout branch, the discriminant branch also processes the image through multiple convolutional layers to extract features of local regions in the image, such as defects, cracks and irregularly shaped areas. These features usually contain high-frequency detail information. The goal of the discriminant branch is to accurately capture these local anomalies. Through the channel attention mechanism, the discrimination branch can weight the feature contribution of different channels, thereby highlighting those features that contribute highly to the discrimination task. Through the spatial attention mechanism, it focuses on the defective areas in the image and ignores other unimportant areas. The spatial attention mechanism weights the image features in the spatial dimension, so that the model can better identify local texture anomalies and shape irregularities. The layout branch and the discriminant branch extract features separately in parallel mode. Through this parallel processing, the two branches can effectively complement each other and jointly improve the recognition performance of the model.

[0023] See Figure 4 As shown, based on the board layout characteristics, the board is divided into functional areas, including functional areas, circuit areas, and blank areas. Identifiers are added to the components and circuits within each area. Specifically, this includes: Based on the acquired board layout features, the board is divided into functional areas, including circuit area, component area and blank area; The circuit area presents continuous and dense wiring paths, the component area is composed of rectangular, circular and irregularly shaped patterns with regular shapes, and the blank area is the unused area of ​​the board, which is an area without obvious shape. Based on the divided functional areas, each area is marked and a unique identifier is added; Based on the size and shape of each component in the component area, the components are identified and classified. Different types of components, such as resistors, capacitors, and chips, are identified and a unique identifier is added. A unique identifier is also assigned to each line in the circuit area.

[0024] Specifically, based on the obtained board layout characteristics, the functional areas of the board are divided, mainly including the following areas: the circuit area consists of continuous and dense wiring paths, representing the connected parts of the circuit; the component area consists of patterns with regular shapes (rectangles, circles, irregular shapes), representing the components installed on the board; the blank area is the unused area of ​​the board, which is an area without obvious shape, texture and structure. Image segmentation (such as semantic segmentation based on deep learning, traditional threshold segmentation, etc.) is used to divide the image. For the circuit area, the circuit path is extracted by identifying continuous lines in the image. For the component area, the components are identified by detecting regular geometric shapes (such as rectangles and circles). The blank area is automatically classified as a blank area by detecting areas without structure or pattern. After each functional area is divided, the area is marked and a unique identifier is added to the components and lines in each area. In the component area, the components are identified and classified according to their size, shape and position, and a unique identifier is assigned to each component. In the line area, each line is identified according to its connection characteristics and topology, and a unique identifier is assigned to each line.

[0025] See Figure 5 As shown, based on the model of the board under test, the layout features of defect-free samples are obtained from the board database as a standard layout prototype. Simultaneously, a defect dataset with known defect types is obtained, specifically including: Obtain the model data of the board under test, query the board database, and obtain the defect-free sample data for that model. Extract layout features from defect-free samples, including component layout features, trace layout features, and functional area distribution; The database is used to filter out defect datasets related to the model of the board under test, including electrical defects, geometric defects, and visual defects.

[0026] Specifically, the model data of the board under test is queried from the board database to ensure accurate acquisition of relevant information of the target board, including detailed identifiers such as model and version. For the model of the board under test, a defect-free sample dataset is queried and obtained from the board database. From the defect-free samples, the following layout features are extracted for each sample: Component layout features: describing the position, quantity and arrangement of various components on the board; Trace layout features: reflecting the wiring paths, connection methods and circuit topology on the board; Functional area distribution: identifying the position and range of different functional areas on the board, such as the power supply area and the signal processing area. Further filtering of the database yielded defect datasets related to the model of the board under test, mainly including the following types of defects: Electrical defects: such as short circuits, open circuits, and other electrical performance issues; Geometric defects: such as physical shape problems caused by misalignment or improper arrangement of components; Visual defects: such as blurry or incomplete patterns on printed circuit boards, which affect visual inspection.

[0027] See Figure 6As shown, by comparing the layout of each area of ​​the board under test with that of each area of ​​the standard layout prototype, the layout difference is obtained, specifically including: Coordinate alignment is performed based on the obtained layout features of the board under test and the standard layout prototype of the defect-free sample. Based on the aligned two boards, the geometric differences between the two are obtained by calculating the Hausdorff distance, the positional deviation of the components in the area of ​​the board under test is calculated, the curvature, connectivity and density of the lines are calculated to obtain the differences in the routing paths, and the area coverage difference between the area of ​​the board under test and the standard layout prototype is obtained. The differences in each region are quantified by difference scores, and the difference scores are weighted and averaged according to the importance of each region in the overall board to obtain the final layout difference score.

[0028] Specifically, the test board and the standard layout prototype are aligned using affine or perspective transformation. The geometric differences between the aligned board and the standard layout prototype are then calculated, and the Hausdorff distance is used to measure these differences. The formula is as follows:

[0029] in, For the point set of the board under test, For the standard layout prototype region point set, this formula means: for each point exist In the middle, find the point closest to it. exist In the middle, calculate the distance, and then solve for the maximum distance of all points; Calculate the positional deviation of components in the board under test and the standard layout prototype. The position of a component is usually represented by its centroid or center of gravity. The calculation of the differences in routing paths between the board under test (DUT) and the standard layout prototype mainly focuses on curvature, connectivity, and density. Curvature is calculated by fitting a polynomial curve or using curvature calculation. Connectivity is calculated to determine whether the routing forms a complete circuit; this is determined by analyzing the topology of the routing, and the connectivity difference is quantified by calculating the difference in path connectivity. Density is calculated; density can be defined as the length or area of ​​routing within a unit area. The density difference is obtained by calculating the routing density in the DUT area and the standard layout prototype area. Differences in regional coverage are measured by calculating the ratio of the intersection to the union of two regions. To quantify the layout differences, the differences in each region are measured by difference scores. By weighted averaging of the difference scores in each region, the total difference in the entire board layout is obtained.

[0030] See Figure 7 As shown, a layout difference threshold is set, and defects are determined based on the relationship between the layout difference and the threshold. The defect area is then located. Specifically, this includes: Set a layout difference threshold. Based on the relationship between the layout difference and the preset threshold, if it is greater than the threshold, it is judged as a defect, and the defect location is located based on the identifier. If the value is less than the threshold, the discriminative features obtained by the convolutional neural network model are matched with the data in the defect dataset, and the matching degree is calculated as the probability of the defect's existence using a similarity matching algorithm. A threshold for the probability of a defect is set. If the probability of a defect is less than the threshold, it is determined that there is no defect. If the probability is greater than the threshold, it is determined that there is a defect, and the defect location is located based on the identifier.

[0031] Specifically, layout difference refers to the difference between the image to be detected and the reference image. It is typically calculated using image processing or deep learning methods. A higher layout difference indicates a more significant difference and a potential defect. A threshold is set; if the layout difference is greater than the threshold, a defect is initially identified. If the layout difference is less than the threshold, a convolutional neural network (CNN) model is used to further determine the defect. Assuming the CNN model uses a forward propagation process to acquire discriminative features of the image and outputs feature vectors, these feature vectors are matched with feature vectors in the defect dataset to calculate the probability of a defect. The probability of a defect is determined by calculating the similarity between the feature vector of the image to be detected and the feature vectors of the images in the defect dataset. Cosine similarity is used to calculate the similarity between them, with the formula:

[0032] in, For similarity, , The feature vectors are the feature vectors of the image to be detected and the feature vectors of the defect dataset. Let L2 norm be the L2 norm of the two eigenvectors; Whether through layout difference or similarity matching through CNN models, the ultimate goal is to locate the specific area of ​​the defect. Each detected defect area has an identifier, and by combining the spatial information of the image, the location of the defect area is determined through the identifier.

[0033] See Figure 8 As shown, based on the obtained defect identifier and defect location, the defects are identified and classified. For new defect categories, the defect dataset is updated, specifically including: Construct a defect category identification model and train the model based on historical data to obtain the trained defect category identification model; Input the obtained defect identifier and defect location into the defect category recognition model to obtain the defect category and generate defect labels; For newly identified defects, the model and dataset are updated by learning the new defect categories through incremental learning.

[0034] Specifically, when a new defect category is identified, incremental learning is used to update the model and expand the dataset. The new defect data is integrated with the existing dataset, and the model parameters are updated, especially for the model part of the newly added category, such as updating the output layer or fully connected layer in the neural network. Iterative training is carried out to ensure the stability and improvement of the model's performance on the overall dataset. According to the actual application, the accuracy of the model is monitored regularly, and further fine-tuning and updates are made based on new data.

[0035] It should be noted that the order of the above embodiments of the present invention is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, the above description focuses on specific embodiments of this specification. Additionally, the processes depicted in the accompanying drawings do not necessarily require a specific or sequential order to achieve the desired results. In some embodiments, multitasking and parallel processing are possible or may be advantageous.

[0036] The various embodiments in this specification are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0037] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A deep learning-based adaptive identification and localization method for board defects, characterized in that, include: The surface image of the board to be tested is acquired, including a global view image and a high-resolution local view image, and the acquired images are preprocessed. The preprocessed image is input into a parallel dual-branch convolutional neural network model. The layout branch obtains layout features related to the layout of board components and routing patterns, while the discrimination branch obtains discrimination features related to local texture anomalies and shape irregularities. Based on the board layout characteristics, the board is divided into functional areas, including functional areas, circuit areas and blank areas, and identifiers are added to the components and circuits in each area. Based on the model of the board under test, the layout features of defect-free samples are obtained from the board database as a standard layout prototype, and at the same time, a defect dataset of known defect types is obtained. The layout difference is obtained by comparing the layout of each area of ​​the board under test with that of each area of ​​the standard layout prototype. Set a layout difference threshold, determine defects based on the relationship between the layout difference and the threshold, and locate the defect area. Based on the obtained defect identifiers and defect locations, the defects are identified and classified, and the defect dataset is updated for new defect categories.

2. The deep learning-based adaptive identification and localization method for board defects according to claim 1, characterized in that, The acquisition of surface images of the board under test includes global view images and high-resolution local view images, and the preprocessing of the acquired images specifically includes: The camera captures global view images and captures high-resolution local view images of each area on the board surface as local view images. Preprocessing is performed on images from various perspectives, including image denoising, image enhancement, geometric correction, image registration, image cropping, and grayscale binarization.

3. The deep learning-based adaptive identification and localization method for board defects according to claim 1, characterized in that, The process of inputting the preprocessed image into a parallel dual-branch convolutional neural network model, with the layout branch acquiring layout features related to board component layout and wiring patterns, and the discrimination branch acquiring discrimination features related to local texture anomalies and shape irregularities, specifically includes: The preprocessed image is input into a two-branch convolutional neural network model; The layout branch extracts features from the input image through multiple convolutional layers, obtaining features at different levels, including low-level edge and corner features and high-level layout patterns and wiring connection features. By using an attention mechanism, the features of specific locations in the image are enhanced, irrelevant areas are ignored, and layout features related to the layout of board components and routing patterns are obtained. The discriminative branch extracts detailed features of local regions, including defects, cracks, and irregularly shaped areas, through multiple convolutional layers; The contribution of features is determined by channel attention mechanism, and the spatial attention mechanism is used to focus on defect areas in the image to obtain discriminative features related to local texture anomalies and shape irregularities. The layout branch and the discrimination branch work in parallel, each extracting the features of interest.

4. The deep learning-based adaptive identification and localization method for board defects according to claim 1, characterized in that, The process of dividing the board into functional areas based on board layout features, including functional areas, circuit areas, and blank areas, and adding identifiers to the components and circuits in each area, specifically includes: Based on the acquired board layout features, the board is divided into functional areas, including circuit area, component area and blank area; The circuit area presents continuous and dense wiring paths, the component area is composed of rectangular, circular and irregularly shaped patterns with regular shapes, and the blank area is the unused area of ​​the board, which is an area without obvious shape. Based on the divided functional areas, each area is marked and a unique identifier is added; Based on the size and shape of each component in the component area, the components are identified and classified. Different types of components, such as resistors, capacitors, and chips, are identified and a unique identifier is added. A unique identifier is also assigned to each line in the circuit area.

5. The deep learning-based adaptive identification and localization method for board defects according to claim 1, characterized in that, The step of obtaining the layout features of defect-free samples from the board database based on the model of the board under test as a standard layout prototype, and simultaneously obtaining a defect dataset with known defect types, specifically includes: Obtain the model data of the board under test, query the board database, and obtain the defect-free sample data for that model. Extract layout features from defect-free samples, including component layout features, trace layout features, and functional area distribution; The database is used to filter out defect datasets related to the model of the board under test, including electrical defects, geometric defects, and visual defects.

6. The deep learning-based adaptive identification and localization method for board defects according to claim 1, characterized in that, The step of obtaining the layout difference by comparing the layout of each area of ​​the board under test with the layout of each area of ​​the standard layout prototype specifically includes: Coordinate alignment is performed based on the obtained layout features of the board under test and the standard layout prototype of the defect-free sample. Based on the aligned two boards, the geometric differences between the two are obtained by calculating the Hausdorff distance, the positional deviation of the components in the area of ​​the board under test is calculated, the curvature, connectivity and density of the lines are calculated to obtain the differences in the routing paths, and the area coverage difference between the area of ​​the board under test and the standard layout prototype is obtained. The differences in each region are quantified by difference scores, and the difference scores are weighted and averaged according to the importance of each region in the overall board to obtain the final layout difference score.

7. The deep learning-based adaptive identification and localization method for board defects according to claim 1, characterized in that, The process of setting a layout difference threshold, determining defects based on the relationship between the layout difference and the threshold, and locating defect areas specifically includes: Set a layout difference threshold. Based on the relationship between the layout difference and the preset threshold, if it is greater than the threshold, it is judged as a defect, and the defect location is located based on the identifier. If the value is less than the threshold, the discriminative features obtained by the convolutional neural network model are matched with the data in the defect dataset, and the matching degree is calculated as the probability of the defect's existence using a similarity matching algorithm. A threshold for the probability of a defect is set. If the probability of a defect is less than the threshold, it is determined that there is no defect. If the probability is greater than the threshold, it is determined that there is a defect, and the defect location is located based on the identifier.

8. The deep learning-based adaptive identification and localization method for board defects according to claim 1, characterized in that, The process of identifying and classifying defects based on the acquired defect identifiers and locations, and updating the defect dataset for new defect categories, specifically includes: Construct a defect category identification model and train the model based on historical data to obtain the trained defect category identification model; Input the obtained defect identifier and defect location into the defect category recognition model to obtain the defect category and generate defect labels; For newly identified defects, the model and dataset are updated by learning the new defect categories through incremental learning.

9. The deep learning-based adaptive identification and localization method for board defects according to claim 7, characterized in that, The board database adopts a blockchain storage architecture, including: a standard layout prototype library: storing board models and layout features of each board; a defect dataset: stored in the structure of {defect type: feature vector: location template}; and an update log: recording new defects and adding identifiers.

10. A deep learning-based adaptive identification and localization system for board defects, used to implement the deep learning-based adaptive identification and localization method for board defects as described in any one of claims 1-9, characterized in that, include: Image acquisition module: The module acquires global view images and local high-resolution images of the board under test through a camera; Dual-branch convolutional neural network module: The module inputs the preprocessed image into a parallel dual-branch network, extracts layout-related features such as board component layout and wiring patterns through convolutional layers, and extracts local texture anomaly features such as defects, cracks and shape irregularities through convolutional layers; Functional area division module: The module divides the board into functional areas, circuit areas and blank areas according to the board layout characteristics, and adds identifiers to each area; Standard layout comparison module: This module calculates the board layout difference by comparing the layout features with those of a defect-free sample; Defect Judgment and Location Module: The module judges defects and locates defect areas based on the comparison between layout difference and threshold, identifies defect categories through defect identifiers and locations, and generates labels; Data update module: This module incrementally learns new defect categories and updates the defect dataset; Processor: The processor is used to handle the calculation process of each formula and the construction calculation process of each model.

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