Driving module and driving method, display device

Abstract

The application provides a driving module and a driving method, and a display device. The driving module comprises a timing control unit, a first logic OR gate circuit and a first level conversion unit. The third timing preset signal output by the timing control unit is superimposed into the first timing preset signal by the first logic OR gate circuit to obtain the first timing control signal, so that the number of effective levels in each period of the first timing control signal is even; and the fourth timing preset signal is superimposed into the second timing preset signal to obtain the second timing control signal, so that the number of effective levels in each period of the second timing control signal is even, thereby solving the problem that a single LS IC cannot output an odd number of effective clock signals. In addition, the third timing preset signal and the fourth timing preset signal do not affect the continuity of the plurality of first periods in the first timing preset signal and the second timing preset signal, thereby avoiding the problem of abnormal charging between frames.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display driving, in particular to a driving module and a driving method, and a display device. BACKGROUND

[0002] In recent years, with the rapid development of electronic information technology, semiconductor manufacturing process and display driving technology, the performance requirements of display devices in the consumer electronics market continue to rise. Users' pursuit of visual experience is no longer limited to resolution and color performance. Display dynamic fluency has become a key evaluation index. This directly promotes the popularization and application of high refresh rate (HRR) display technology (such as 90Hz, 120Hz, 144Hz or even higher). High refresh rate display devices can significantly reduce picture blur, eliminate picture tearing, improve dynamic picture clarity and reduce visual latency.

[0003] In the existing driving architecture, it generally includes a timing controller (TCON), a logic integrated circuit (LS IC), a gate drive circuit (such as an array substrate row drive circuit, or GOA circuit) and a source drive circuit. Among them, the timing controller is used to output a timing control signal CK, the LS IC generates a plurality of clock signals CLK based on the timing control signal CK and outputs them to the GOA circuit of the display panel to control a plurality of rows of sub-pixels to be turned on, and the source drive circuit charges the turned-on sub-pixels to display the picture.

[0004] High refresh rate requires the source drive circuit and the gate drive circuit to process and transmit data quantity several times of the standard refresh rate (such as 60Hz) in unit time. Limited by the input frequency limit of the LS IC, in the related technology, a scheme of cascading multiple LS ICs is adopted to process the timing control signal CK output by the timing controller. However, since the LS IC only supports even channel output, if the number of effective clock signals CLK that a single LS IC needs to output is odd, the output of the clock signal CLK cannot be realized. SUMMARY

[0005] To solve the above problems, the present application provides a driving module, a driving method and a display device, which can solve the problem that a single LS IC cannot output an odd number of effective clock signals.

[0006] To solve the above problems, the first technical solution provided by the present application is to provide a driving module, comprising:

[0007] a timing control unit configured to output a first pre-timed timing control signal group and a second pre-timed timing control signal group; the first pre-timed timing control signal group comprises a first pre-timed signal and a second pre-timed signal with a first period; the second pre-timed timing control signal group comprises a third pre-timed signal and a fourth pre-timed signal with a second period; wherein an active level in each of the second periods in the third pre-timed signal is located between two adjacent first periods in the first pre-timed signal; and an active level in each of the second periods in the fourth pre-timed signal is located between two adjacent first periods in the second pre-timed signal;

[0008] a first logic OR gate circuit connected to the timing control unit, configured to receive the first pre-timed timing control signal group and the second pre-timed timing control signal group; and to superimpose the active level in each of the periods in the third pre-timed signal between two adjacent first periods in the first pre-timed signal to obtain a first timing control signal, and to superimpose the active level in each of the periods in the fourth pre-timed signal between two adjacent first periods in the second pre-timed signal to obtain a second timing control signal; wherein the first timing control signal and the second timing control signal have a third period, and the number of active levels in each of the third periods is even;

[0009] a first level conversion unit connected to the first logic OR gate circuit, configured to receive the first timing control signal and the second timing control signal, and to output a first clock signal group based on the first timing control signal and the second timing control signal; wherein the first clock signal group comprises a plurality of first clock signals, the first level conversion unit determines the start time of the active level of each of the first clock signals according to the first timing control signal, and the first level conversion unit determines the end time of the active level of each of the first clock signals according to the second timing control signal.

[0010] In an embodiment, the timing control unit is further configured to output a third pre-timed timing control signal group and a fourth pre-timed timing control signal group; the third pre-timed timing control signal group comprises a fifth pre-timed signal and a sixth pre-timed signal with a fourth period; the fourth pre-timed timing control signal group comprises a seventh pre-timed signal and an eighth pre-timed signal with a fifth period; wherein an active level in each of the fifth periods in the seventh pre-timed signal is located between two adjacent fourth periods in the fifth pre-timed signal; and an active level in each of the fifth periods in the eighth pre-timed signal is located between two adjacent fourth periods in the sixth pre-timed signal;

[0011] the driving module further comprises:

[0012] a second logic OR gate circuit connected to the timing control unit, configured to receive the third pre-arranged timing control signal group and the fourth pre-arranged timing control signal group, and to superimpose the active level in each period of the seventh pre-arranged timing signal between two adjacent fourth periods of the fifth pre-arranged timing signal to obtain a third timing control signal, and to superimpose the active level in each period of the eighth pre-arranged timing signal between two adjacent fourth periods of the sixth pre-arranged timing signal to obtain a fourth timing control signal, wherein the third timing control signal and the fourth timing control signal have a sixth period, and the number of active levels in each sixth period is even;

[0013] a second level conversion unit connected to the second logic OR gate circuit, configured to receive the third timing control signal and the fourth timing control signal, and to output a second clock signal group based on the third timing control signal and the fourth timing control signal, wherein the second clock signal group includes a plurality of second clock signals, the second level conversion unit determines the start time of the active level of each second clock signal according to the third timing control signal, and the second level conversion unit determines the end time of the active level of each second clock signal according to the fourth timing control signal.

[0014] In an embodiment, the number of active levels in each period of the first pre-arranged timing signal and the second pre-arranged timing signal is odd.

[0015] The number of active levels in each period of the third pre-arranged timing signal and the fourth pre-arranged timing signal is odd.

[0016] The number of active levels in each period of the fifth pre-arranged timing signal and the sixth pre-arranged timing signal is odd.

[0017] The number of active levels in each period of the seventh pre-arranged timing signal and the eighth pre-arranged timing signal is odd.

[0018] In an embodiment, the first level conversion unit and the second level conversion unit alternately output the first clock signal and the second clock signal.

[0019] In an embodiment, the driving module further comprises a differential control unit, the differential control unit is connected to the timing control unit, the first level conversion unit and the second level conversion unit, the first level conversion unit and the second level conversion unit respectively output the generated first clock signal group and the second clock signal group to the differential control unit, and the timing control unit controls the differential control unit to alternately output the first clock signal and the second clock signal.

[0020] In an embodiment, the interval time of two adjacent first periods is equal to the interval time between two adjacent effective levels in the first period.

[0021] The interval time of two adjacent fourth periods is equal to the interval time between two adjacent effective levels in the fourth period.

[0022] In an embodiment, the first clock signals are used to charge odd-numbered rows of sub-pixels, and each effective level in the first clock signals comprises a pre-charge phase and a charge phase corresponding to a row of sub-pixels; and the second clock signals are used to charge even-numbered rows of sub-pixels, and each effective level in the second clock signals comprises a pre-charge phase and a charge phase corresponding to a row of sub-pixels.

[0023] In an embodiment, the charge phase of each effective level in different first clock signals does not overlap; the charge phase of each effective level in the second clock signals comprises a first sub-charge phase and a second sub-charge phase; the first sub-charge phase partially overlaps with the charge phase of an effective level in the first clock signal corresponding to the sub-pixels of the previous odd-numbered row, and the second sub-charge phase partially overlaps with the charge phase of an effective level in the first clock signal corresponding to the sub-pixels of the next odd-numbered row.

[0024] To solve the above problems, a second technical solution provided by the present application is to provide a display device, comprising:

[0025] A display panel comprising a plurality of rows of sub-pixels and a scan driving circuit connected to the plurality of rows of sub-pixels;

[0026] A driving module connected to the scan driving circuit, the driving module being configured to output a first clock signal group to the scan driving circuit to control the sub-pixels in at least part of the plurality of rows of sub-pixels to work, and the driving module comprises any one of the above driving modules.

[0027] To solve the above problems, a third technical solution provided by the present application is to provide a driving method, comprising:

[0028] In response to receiving a picture display signal;

[0029] outputting a first pre-sequenced timing control signal group and a second pre-sequenced timing control signal group to a first logical OR gate circuit; the first pre-sequenced timing control signal group comprises a first timing pre-sequence signal and a second timing pre-sequence signal with a first period; the second pre-sequenced timing control signal group comprises a third timing pre-sequence signal and a fourth timing pre-sequence signal with a second period; wherein an active level in each of the second period in the third timing pre-sequence signal is located between two adjacent first periods in the first timing pre-sequence signal; an active level in each of the second period in the fourth timing pre-sequence signal is located between two adjacent first periods in the second timing pre-sequence signal;

[0030] stacking, by the first logical OR gate circuit, the active level in each of the period in the third timing pre-sequence signal between two adjacent first periods in the first timing pre-sequence signal to obtain a first timing control signal; and stacking the active level in each of the period in the fourth timing pre-sequence signal between two adjacent first periods in the second timing pre-sequence signal to obtain a second timing control signal; and outputting the first timing control signal and the second timing control signal to a first level conversion unit; wherein the first timing control signal and the second timing control signal have a third period, and the number of active levels in each of the third period is even;

[0031] outputting, by the first level conversion unit, a first clock signal group based on the first timing control signal and the second timing control signal; wherein the first clock signal group comprises a plurality of first clock signals, the start time of the active level of each of the first clock signals is determined based on the first timing control signal, and the end time of the active level of each of the first clock signals is determined based on the second timing control signal.

[0032] In an embodiment, the method further comprises, after receiving the picture display signal:

[0033] outputting a third pre-sequenced timing control signal group and a fourth pre-sequenced timing control signal group to a second logical OR gate circuit; the third pre-sequenced timing control signal group comprises a fifth timing pre-sequence signal and a sixth timing pre-sequence signal with a fourth period; the fourth pre-sequenced timing control signal group comprises a seventh timing pre-sequence signal and an eighth timing pre-sequence signal with a fifth period; wherein an active level in each of the fifth period in the seventh timing pre-sequence signal is located between two adjacent fourth periods in the fifth timing pre-sequence signal; an active level in each of the fifth period in the eighth timing pre-sequence signal is located between two adjacent fourth periods in the sixth timing pre-sequence signal;

[0034] superimpose the valid level in each period of the seventh timing pre-signal between two adjacent fourth periods in the fifth timing pre-signal to obtain a third timing control signal, and superimpose the valid level in each period of the eighth timing pre-signal between two adjacent fourth periods in the sixth timing pre-signal to obtain a fourth timing control signal; and output the third timing control signal and the fourth timing control signal to a second level conversion unit; wherein the third timing control signal and the fourth timing control signal have a sixth period, and the number of valid levels in each sixth period is even;

[0035] output a second clock signal group based on the third timing control signal and the fourth timing control signal by using the second level conversion unit; wherein the second clock signal group comprises a plurality of second clock signals, the starting time of the valid level of each second clock signal is determined based on the third timing control signal, and the cutoff time of the valid level of each second clock signal is determined based on the fourth timing control signal.

[0036] The application has the following beneficial effects: in the driving module provided by the application, the first logic OR gate circuit is used to superimpose the valid level in the third timing pre-signal between two adjacent periods in the first timing pre-signal to obtain the first timing control signal, so that the number of valid levels in each period of the first timing control signal is even; and the fourth timing pre-signal is superimposed between two adjacent periods in the second timing pre-signal to obtain the second timing control signal, so that the number of valid levels in each period of the second timing control signal is even, thereby solving the problem that a single LS IC cannot output an odd number of valid clock signals. In addition, the third timing pre-signal does not affect the continuity of the plurality of first periods in the first timing pre-signal, and the fourth timing pre-signal does not affect the continuity of the plurality of first periods in the second timing pre-signal, thereby avoiding the problem of abnormal charging between frames. BRIEF DESCRIPTION OF DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0038] Figure 1 a module schematic diagram of the driving module provided by the prior art;

[0039] Figure 2 a module schematic diagram of the driving module provided by the prior art; Figure 1A driving timing diagram of the driving module shown in the embodiment of the present application;

[0040] Figure 3 A module diagram of the driving module provided in an embodiment of the present application;

[0041] Figure 4 A driving timing diagram of generating the first timing control signal and the second timing control signal provided in an embodiment of the present application;

[0042] Figure 5 A module diagram of the driving module provided in another embodiment of the present application;

[0043] Figure 6 A module diagram of the driving module provided in yet another embodiment of the present application;

[0044] Figure 7 A driving timing diagram of generating the third timing control signal and the fourth timing control signal provided in an embodiment of the present application;

[0045] Figure 8 A driving timing diagram of the driving module provided in an embodiment of the present application;

[0046] Figure 9 A driving timing simulation diagram of CLK9, CLK10 and CLK1 of the next frame provided in the present application;

[0047] Figure 10 A driving timing simulation diagram of CLK10, CLK11, CLK12 and CLK1 of the next frame provided in the present application;

[0048] Figure 11 A driving timing diagram of CLK1-CLK10 provided in an embodiment of the present application;

[0049] Figure 12 A flow diagram of the driving method provided in an embodiment of the present application;

[0050] Figure 13 A flow diagram of the driving method provided in another embodiment of the present application;

[0051] Figure 14 A module diagram of the display device provided in an embodiment of the present application.

[0052] Label Explanation:

[0053] Driving module-100; timing control unit-10; first logic or gate circuit-20; first level conversion unit-30; second logic or gate circuit-40; second level conversion unit-50; differential control unit-60;

[0054] Display device - 1000; display panel - 200. DETAILED DESCRIPTION

[0055] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0056] The terms "first", "second", "third" and the like in the present application are only for descriptive purpose, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second", "third" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "plurality" is at least two, for example, two, three, etc., unless otherwise explicitly and specifically limited. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present application are only used to explain the relative position relationship, movement condition, etc. between the components in a certain posture (as shown in the drawings), and if the certain posture changes, the directional indications also change accordingly. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but can optionally include steps or units not listed, or can optionally include other steps or units inherent to the process, method, product or device.

[0057] In this document, reference to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive of one another. A person of ordinary skill in the art will understand that the embodiments described herein can be combined with one another.

[0058] In the description of the embodiments of the present application, the term "and / or" is only a description of the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " in this document generally represents an "or" relationship between the front and rear associated objects.

[0059] In the description of the embodiments of the present application, the term "plurality" refers to more than two (including two), and similarly, "multiple groups" refers to more than two groups (including two groups).

[0060] In the description of the embodiments of the present application, unless explicitly defined and limited otherwise, the technical terms "mounting", "connecting", "connecting", "fixing" and other terms should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0061] Referring to Figure 1 and Figure 2 , Figure 1 a module schematic diagram of a driving module provided by the prior art is shown; Figure 2 a driving timing schematic diagram of the driving module shown in Figure 1 .

[0062] Taking the existing driving module of a 50-inch ultra definition (UD) product as an example, the current in-plane mask design is a 10CLK (10 clock signals) design. The existing driving module includes a timing controller and a level shifter, the timing controller outputs CLK_IN1 and CLK_IN2 signals as inputs of the level shifter, and the first rising edge of CLK_IN1 will generate a rising edge of CLK1, and the first rising edge of CLK_IN2 will generate a falling edge of CLK1, and so on, until 10 CLK outputs are completed, and then enter the cycle of another period. The input frequency requirement of the current 10CLK output level shifter for CLK_IN is ≤300KHz, wherein the input frequency = vertical scan line number * refresh rate. Therefore, if the refresh rate is 120Hz, the frequency of CLK_IN corresponding to the refresh rate is 270kHz, and if the refresh rate is 144Hz, the input frequency of CLK_IN is 324kHz, which exceeds the specification of the level shifter, so the maximum refresh rate of the product can only support 120Hz.

[0063] In order to further improve the refresh rate of the product, a scheme of cascading multiple level shifters can be adopted, and the embodiments of the present application take a scheme of cascading two level shifters as an example. Since the actual requirement is 10CLK output, a single level shifter needs to be set to 5 channels, however, since the level shifter only supports even channel (4 / 6 / 8 channel, etc.) output, it will cause the problem that a single level shifter cannot output an odd number of valid clock signals.

[0064] Referring to Figures 3-8 , Figure 3 a module schematic diagram of a driving module provided by an embodiment of the present application is shown;Figure 4 a driving timing diagram for generating the first timing control signal and the second timing control signal is provided for an embodiment of the present application; Figure 5 a module diagram of the driving module is provided for another embodiment of the present application; Figure 6 a module diagram of the driving module is provided for yet another embodiment of the present application; Figure 7 a driving timing diagram for generating the third timing control signal and the fourth timing control signal is provided for an embodiment of the present application; Figure 8 a driving timing diagram of the driving module is provided for an embodiment of the present application.

[0065] To solve the above problems, an embodiment of the present application provides a driving module 100, comprising a timing control unit 10, a first logic OR gate circuit 20 and a first level conversion unit 30.

[0066] In combination with Figure 3 and Figure 4 , the timing control unit 10 comprises a timing controller (TCON), and the timing control unit 10 is configured to output a first pre-timing control signal group and a second pre-timing control signal group; the first pre-timing control signal group comprises a first timing pre-signal CPV1 and a second timing pre-signal CPV2 with a first period, and the first period comprises a plurality of active levels; the second pre-timing control signal group comprises a third timing pre-signal CPV3 and a fourth timing pre-signal CPV4 with a second period, and the second period comprises at least one active level; wherein the active level in each second period of the third timing pre-signal CPV3 is located between two adjacent first periods of the first timing pre-signal CPV1; and the active level in each second period of the fourth timing pre-signal CPV4 is located between two adjacent first periods of the second timing pre-signal CPV2.

[0067] The first logic OR gate circuit 20 is connected to the timing control unit 10, configured to receive the first pre-timing control signal group and the second pre-timing control signal group; and superimpose the active level in each period of the third timing pre-signal CPV3 between two adjacent first periods of the first timing pre-signal CPV1 to obtain a first timing control signal CLK_IN1; and superimpose the active level in each period of the fourth timing pre-signal CPV4 between two adjacent first periods of the second timing pre-signal CPV2 to obtain a second timing control signal CLK_IN2; wherein the first timing control signal CLK_IN1 and the second timing control signal CLK_IN2 have a third period, and the number of active levels in each third period is even.

[0068] The first level conversion unit 30 includes a first level shifter (LS1), and is connected with the first logic OR gate circuit 20, and is configured to receive the first timing control signal CLK_IN1 and the second timing control signal CLK_IN2, and output a first clock signal group based on the first timing control signal CLK_IN1 and the second timing control signal CLK_IN2.

[0069] The first clock signal group includes a plurality of first clock signals CLKa, and the first level conversion unit 30 determines a starting time of an active level of each first clock signal CLKa according to the first timing control signal CLK_IN1, and determines a cutoff time of the active level of each first clock signal CLKa according to the second timing control signal CLK_IN2.

[0070] It can be understood that, since the number of active levels in each third period in the first timing control signal CLK_IN1 and the second timing control signal CLK_IN2 is even, the number of the plurality of first clock signals CLKa generated based on the first timing control signal CLK_IN1 and the second timing control signal CLK_IN2 is also even.

[0071] In combination with Figure 3 , Figure 4 and Figure 8 , taking an LS IC with 8 output channels as an example, the input frequency of the 8 output channel LS IC is 700kMz, and the LS1 is set to 6 output channels (CLKa1-CLKa6), and the actual demand is 5 CLK, so CLKa6 is redundant and will not be actually used, and will cause CLKa5 and CLKa1 of the next period to be unable to form a continuous waveform, causing abnormal interframe charging, and failing to meet the charging demand. In the embodiment of the application, the active level of CLK_IN corresponding to CLKa6 is edited separately.

[0072] Specifically, the active level of CLK_IN corresponding to CLKa6 is hidden between the active levels of CLK_IN corresponding to CLKa5 and the next CLKa1, but since the TCON does not support outputting irregular waveforms, the TCON is caused to output a first preset timing control signal group first, and output the timing of 5 CLKs of the LS IC. Then, the TCON is caused to output a second preset timing control signal group: the active level of the second preset timing control signal group is between the 5th active level and the 6th active level of the first preset timing control signal group. For the TCON, the first preset timing control signal group and the second preset timing control signal group are both regular waveforms, and are realizable, and then the first timing control signal CLK_IN1 and the second timing control signal CLK_IN2 are formed through the first logic OR gate circuit 20, and the final theoretical waveform is as follows:Figure 4 As shown in the figure, CLKa6 generated based on the first timing control signal CLK_IN1 and the second timing control signal CLK_IN2 is positioned between CLKa5 and the next CLKa1, without affecting the original output timing, and finally CLKa5 and the next CLKa1 can be continuously connected. Therefore, if the refresh rate is to be 144 Hz, the input frequency of CLK_IN corresponding thereto = 1125*144*2 = 324 kHz, which does not exceed the requirement of 700 kHz for the input frequency of the 8-output-channel LS IC. Among them, *2 is because the input frequency of the LS IC is doubled after the first pre-timing control signal group and the second pre-timing control signal group are superimposed. And if the refresh rate is to be 288 Hz, the input frequency of CLK_IN corresponding thereto = 1125*288*2 = 648 kHz, which also does not exceed the requirement of 700 kHz for the input frequency of the 8-output-channel LS IC.

[0073] Specifically, in the driving module 100 provided by the embodiment of the present application, the effective level in the third timing pre-signal CPV3 is superimposed between two adjacent periods in the first timing pre-signal CPV1 by the first logic OR gate circuit 20 to obtain the first timing control signal CLK_IN1, and the effective level in the fourth timing pre-signal CPV4 is superimposed between two adjacent periods in the second timing pre-signal CPV2 to obtain the second timing control signal CLK_IN2, so that the number of effective levels in each period in the first timing control signal CLK_IN1 and the second timing control signal CLK_IN2 is even, thereby enabling a single LS IC to generate an even number of first clock signals CLKa based on the first timing control signal CLK_IN1 and the second timing control signal CLK_IN2, and the effective levels in the third timing pre-signal CPV3 and the fourth timing pre-signal CPV4 are superimposed between two adjacent periods in the first timing pre-signal CPV1 and the second timing pre-signal CPV2, respectively, so that the third timing pre-signal CPV3 and the fourth timing pre-signal CPV4 do not affect the continuity of the plurality of first periods in the first timing pre-signal CPV1 and the second timing pre-signal CPV2, and the single LS IC can output an odd number of effective clock signals.

[0074] In an embodiment, the interval time of the two adjacent first periods is equal to the interval time between the two adjacent effective levels in the first period.

[0075] Specifically, through the above design, the synchronization of the interval of adjacent periods in each pre-timing control signal and the interval of effective levels in each period can effectively avoid the breakpoints in the transmission of the subsequently generated first clock signal CLKa, ensure the continuity of the output of the first clock signal CLKa, and thereby avoid the problem of abnormal inter-frame charging.

[0076] In an embodiment, the number of effective levels in each cycle of the first timing preset signal CPV1 and the second timing preset signal CPV2 is odd; and the number of effective levels in each cycle of the third timing preset signal CPV3 and the fourth timing preset signal CPV4 is odd.

[0077] For example, the number of effective levels in each cycle of the first timing preset signal CPV1 and the second timing preset signal CPV2 is 3, 5 or 7, etc. The number of effective levels in each cycle of the third timing preset signal CPV3 and the fourth timing preset signal CPV4 is 1 or 3, etc. so that the number of effective levels in each cycle of the first timing control signal CLK_IN1 obtained by superimposing the first timing preset signal CPV1 and the third timing preset signal CPV3 through the first logic OR gate circuit 20 is even; and the number of effective levels in each cycle of the second timing control signal CLK_IN2 obtained by superimposing the second timing preset signal CPV2 and the fourth timing preset signal CPV4 through the first logic OR gate circuit 20 is even.

[0078] In the embodiment of the present application, the number of effective levels in each cycle of the first timing preset signal CPV1 and the second timing preset signal CPV2 is 5. The number of effective levels in each cycle of the third timing preset signal CPV3 and the fourth timing preset signal CPV4 is 1, and the number of effective levels in each cycle of the first timing control signal CLK_IN1 and the second timing control signal CLK_IN2 is 6.

[0079] In addition, if the number of effective levels in each cycle of the first timing preset signal CPV1 and the second timing preset signal CPV2 is 5, and the number of effective levels in each cycle of the third timing preset signal CPV3 and the fourth timing preset signal CPV4 is 3, it is not necessary to close the excessive output channels in the LS1, thereby avoiding the design of additional circuits or components to close the excessive output channels in the LS1, increasing the cost and the complexity of the circuit.

[0080] In combination with Figures 5 to 7In an embodiment, the timing control unit 10 is further configured to output a third pre-timed timing signal group and a fourth pre-timed timing signal group; the third pre-timed timing signal group comprises a fifth pre-timed signal CPV5 and a sixth pre-timed signal CPV6 having a fourth period, the fourth period comprises a plurality of active levels; the fourth pre-timed timing signal group comprises a seventh pre-timed signal CPV7 and an eighth pre-timed signal CPV8 having a fifth period, the fifth period comprises a plurality of active levels; wherein the active level in each fifth period of the seventh pre-timed signal CPV7 is located between two adjacent fourth periods of the fifth pre-timed signal CPV5; the active level in each fifth period of the eighth pre-timed signal CPV8 is located between two adjacent fourth periods of the sixth pre-timed signal CPV6.

[0081] The driving module 100 further comprises a second logic OR gate circuit 40 and a second level shifter 50. The second logic OR gate circuit 40 is connected to the timing control unit 10, configured to receive the third pre-timed timing signal group and the fourth pre-timed timing signal group; and superimpose the active level in each period of the seventh pre-timed signal CPV7 between two adjacent fourth periods of the fifth pre-timed signal CPV5 to obtain a third timing control signal CLK_IN3; and superimpose the active level in each period of the eighth pre-timed signal CPV8 between two adjacent fourth periods of the sixth pre-timed signal CPV6 to obtain a fourth timing control signal CLK_IN4; wherein the third timing control signal CLK_IN3 and the fourth timing control signal CLK_IN4 have a sixth period, and the number of active levels in each sixth period is even.

[0082] The second level shifter 50 comprises a second level shifter (LS2), and the second level shifter 50 is connected to the second logic OR gate circuit 40, configured to receive the third timing control signal CLK_IN3 and the fourth timing control signal CLK_IN4, and output a second clock signal group based on the third timing control signal CLK_IN3 and the fourth timing control signal CLK_IN4; wherein the second clock signal group comprises a plurality of second clock signals CLKb, the second level shifter 50 determines the start time of the active level of each second clock signal CLKb according to the third timing control signal CLK_IN3, and the second level shifter 50 determines the cutoff time of the active level of each second clock signal CLKb according to the fourth timing control signal CLK_IN4.

[0083] It can be understood that, since the number of active levels in each sixth period in the third timing control signal CLK_IN3 and the fourth timing control signal CLK_IN4 is even, the number of the plurality of second clock signals CLKb generated based on the third timing control signal CLK_IN3 and the fourth timing control signal CLK_IN4 is also even.

[0084] In combination Figure 5 , Figure 7 and Figure 8 , taking the LS IC with 8 output channels as an example, the input frequency of the 8 output channel LS IC is 700kMz, and the LS2 is set to 6 output channels (CLKb1-CLKb6), while the actual demand is 5 CLK, so CLKb6 is redundant and will not be actually used, and will cause CLKb5 and CLKb1 of the next period to fail to form a continuous waveform, resulting in abnormal inter-frame charging and failing to meet the charging demand. In the embodiment of the application, the active level of CLK_IN corresponding to CLKb6 is edited separately.

[0085] Specifically, the active level of CLK_IN corresponding to CLKb6 is hidden between the active levels of CLK_IN corresponding to CLKb5 and the next CLKb1, but since the TCON does not support outputting irregular waveforms, the TCON is first caused to output a third pre-prepared timing control signal group, and output the timing of the LS IC responsible for 5 CLK. Then the TCON is caused to output a fourth pre-prepared timing control signal group: the active level of the fourth pre-prepared timing control signal group is between the 5th active level and the 6th active level of the third pre-prepared timing control signal group. For the TCON, both the third pre-prepared timing control signal group and the fourth pre-prepared timing control signal group are regular waveforms and are realizable, and then the third timing control signal CLK_IN3 and the fourth timing control signal CLK_IN4 are formed through the second logic OR gate circuit 40, and the final theoretical waveform is as follows Figure 7The CLKb6 generated based on the third timing control signal CLK_IN3 and the fourth timing control signal CLK_IN4 is positioned between the CLKb5 and the next CLKb1, without affecting the original output timing, and finally the CLKb5 and the next CLKb1 can be continuously connected. Therefore, if the refresh rate is to be 144 Hz, the input frequency of CLK_IN corresponding thereto = 1125*144*2 = 324 kHz, which does not exceed the requirement of the input frequency of 700 kHz of the 8-output-channel LS IC. Among them, *2 is because the input frequency of the LS IC is doubled after the third pre-timed control signal group and the fourth pre-timed control signal group are superimposed. And if the refresh rate is to be 288 Hz, the input frequency of CLK_IN corresponding thereto = 1125*288*2 = 648 kHz, which also does not exceed the requirement of the input frequency of 700 kHz of the 8-output-channel LS IC.

[0086] Specifically, in the driving module 100 provided by the embodiment of the present application, the effective level in the seventh timing pre-control signal CPV7 is further superimposed between two adjacent periods in the fifth timing pre-control signal CPV5 to obtain the third timing control signal CLK_IN3, and the effective level in the eighth timing pre-control signal CPV8 is superimposed between two adjacent periods in the sixth timing pre-control signal CPV6 to obtain the fourth timing control signal CLK_IN4, so that the number of effective levels in each period in the third timing control signal CLK_IN3 and the fourth timing control signal CLK_IN4 is even, thereby enabling a single LS IC to generate an even number of second clock signals CLKb based on the third timing control signal CLK_IN3 and the fourth timing control signal CLK_IN4, and by superimposing the effective levels in the seventh timing pre-control signal CPV7 and the eighth timing pre-control signal CPV8 between two adjacent periods in the fifth timing pre-control signal CPV5 and the sixth timing pre-control signal CPV6 respectively, the seventh timing pre-control signal CPV7 and the eighth timing pre-control signal CPV8 will not affect the continuity of the plurality of first periods in the fifth timing pre-control signal CPV5 and the sixth timing pre-control signal CPV6, so that the single LS IC can output an odd number of effective clock signals.

[0087] In an embodiment, the interval time of the two adjacent fourth periods is equal to the interval time between the two adjacent effective levels in the fourth period.

[0088] Specifically, by the above design, the synchronization of the interval of adjacent periods in each pre-timed control signal and the interval of effective levels in each period can effectively avoid the breakpoints in the transmission of the subsequently generated second clock signal CLKb, and ensure the continuity of the output of the second clock signal CLKb, thereby avoiding the problem of abnormal inter-frame charging.

[0089] In an embodiment, the number of valid levels in each period of the fifth timing preset signal CPV5 and the sixth timing preset signal CPV6 is odd; and the number of valid levels in each period of the seventh timing preset signal CPV7 and the eighth timing preset signal CPV8 is odd.

[0090] For example, the number of valid levels in each period of the fifth timing preset signal CPV5 and the sixth timing preset signal CPV6 is 3, 5 or 7, etc. The number of valid levels in each period of the seventh timing preset signal CPV7 and the eighth timing preset signal CPV8 is 1 or 3, etc. so that the number of valid levels in each period of the third timing control signal CLK_IN3 obtained by superimposing the fifth timing preset signal CPV5 and the seventh timing preset signal CPV7 through the second logic OR gate circuit 40 is even; and the number of valid levels in each period of the fourth timing control signal CLK_IN4 obtained by superimposing the sixth timing preset signal CPV6 and the eighth timing preset signal CPV8 through the second logic OR gate circuit 40 is even.

[0091] In the embodiment, the number of valid levels in each period of the fifth timing preset signal CPV5 and the sixth timing preset signal CPV6 is 5. The number of valid levels in each period of the seventh timing preset signal CPV7 and the eighth timing preset signal CPV8 is 1, and the number of valid levels in each period of the third timing control signal CLK_IN3 and the fourth timing control signal CLK_IN4 is 6.

[0092] In addition, if the number of valid levels in each period of the fifth timing preset signal CPV5 and the sixth timing preset signal CPV6 is 5, and the number of valid levels in each period of the seventh timing preset signal CPV7 and the eighth timing preset signal CPV8 is 3, it is not necessary to close the redundant output channels in the LS2, thereby avoiding the design of additional circuits or components to close the redundant output channels in the LS2, increasing the cost and the complexity of the circuit.

[0093] Specifically, through the above design, an even number of clock signals can be generated by a single LS IC, and the redundant clock signals are hidden between the adjacent two periods of the valid clock signals, and the redundant clock signals will not affect the original output timing, ensuring the continuity of the inter-frame charging.

[0094] In an embodiment, the first level conversion unit 30 and the second level conversion unit 50 alternately output the first clock signal CLKa and the second clock signal CLKb.

[0095] For example, the number of valid levels in each period of the fifth timing preset signal CPV5 and the sixth timing preset signal CPV6 is 3, 5 or 7, etc. The number of valid levels in each period of the seventh timing preset signal CPV7 and the eighth timing preset signal CPV8 is 1 or 3, etc. so that the number of valid levels in each period of the third timing control signal CLK_IN3 obtained by superimposing the fifth timing preset signal CPV5 and the seventh timing preset signal CPV7 through the second logic OR gate circuit 40 is even; and the number of valid levels in each period of the fourth timing control signal CLK_IN4 obtained by superimposing the sixth timing preset signal CPV6 and the eighth timing preset signal CPV8 through the second logic OR gate circuit 40 is even. Figure 8As shown, LS1 outputs CLKa1-CLKa6, LS2 outputs CLKb1-CLKb6, specifically, LS1 outputs CLK1 & CLK3 & CLK5 & CLK7 & CLK9 & CLK11, and LS2 outputs CLK2 & CLK4 & CLK6 & CLK8 & CLK10 & CLK12, so the number of clock signals output by the two LSICs becomes 12 CLK, while the actual demand is 10 CLK, so CLK11 and CLK12 are redundant and will not be used in practice, and will cause CLK10 and the next period CLK1 to fail to form a continuous waveform, causing abnormal interframe charging and failing to meet the charging demand. In the embodiment of the application, CLK11 (CLKa6) & CLK12 (CLKb6) are edited separately. The valid level of CLK_IN corresponding to CLKa6 output by LS1 is hidden between the valid level of CLK_IN corresponding to CLKa5 and the valid level of CLK_IN corresponding to CLKa1 in the next period; the valid level of CLK_IN corresponding to CLKb6 output by LS2 is hidden between the valid level of CLK_IN corresponding to CLKb5 and the valid level of CLK_IN corresponding to CLKb1 in the next period, and the final theoretical waveform is as shown in Figure 8 As shown, LS1 is responsible for the output of odd-numbered row CLK, and LS2 is responsible for the output of even-numbered row CLK, CLK11 and CLK12 are positioned between CLK10 and the next period CLK1, and do not affect the original output timing, and finally CLK10 and the next period CLK1 can be continuously connected.

[0096] The timing control unit 10 can determine the phase relationship of the first timing control signal CLK_IN1 to the fourth timing control signal CLK_IN4 by adjusting the phase relationship of the first timing pre-signal CPV1 to the eighth timing pre-signal CPV8, so as to make the first level conversion unit 30 and the second level conversion unit 50 output the clock signals corresponding thereto at different time periods. In this embodiment, the phase relationship of the first timing control signal CLK_IN1 to the fourth timing control signal CLK_IN4 is adjusted to realize the alternate output of the first clock signal CLKa and the second clock signal CLKb, and the period of the first timing control signal CLK_IN1 to the fourth timing control signal CLK_IN4 is not changed, so as to avoid the increase of the frequency of the first timing control signal CLK_IN1 to the fourth timing control signal CLK_IN4.

[0097] Alternatively, referring to Figure 6The driving module 100 can further comprise a differential control unit 60 connected to the timing control unit 10, the first level conversion unit 30 and the second level conversion unit 50. The first level conversion unit 30 and the second level conversion unit 50 respectively output the generated first clock signal group and the second clock signal group to the differential control unit 60. The timing control unit 10 controls the differential control unit 60 to alternately output the first clock signal CLKa and the second clock signal CLKb. Specifically, by further providing the differential control unit 60 to control the alternately output of the first clock signal CLKa and the second clock signal CLKb, the performance requirement of the timing control unit 10 can be reduced.

[0098] Referring to Figure 9 and Figure 10 , Figure 9 the driving timing simulation diagram of CLK9, CLK10 and CLK1 of the next frame provided by the present application; Figure 10 the driving timing simulation diagram of CLK10, CLK11, CLK12 and CLK1 of the next frame provided by the present application.

[0099] Figure 9 In the figure, CLK9 is represented by the purple waveform timing; CLK10 is represented by the red waveform timing; and CLK1 is represented by the green waveform timing. Figure 10 In the figure, CLK10 is represented by the purple waveform timing; CLK11 is represented by the red waveform timing; CLK12 is represented by the gray waveform timing; and CLK1 is represented by the green waveform timing.

[0100] In the figure, CLK9 is represented by the purple waveform timing; CLK10 is represented by the red waveform timing; and CLK1 is represented by the green waveform timing. Figure 9 and Figure 10 As can be seen, the effective level of CLK11 (a6) output by LS1 and the effective level of CLK12 (b6) output by LS2 are positioned between CLK10 (b5) and CLK1 (a1) of the next period. The timing of CLK9 to CLK10 is completely consistent with the timing of CLK10 to CLK1 of the next period, which does not affect the output timing of CLK1 to CLK10. Finally, CLK10 and CLK1 of the next period can be continuously connected, which meets the charging effect.

[0101] Referring to Figure 11 , Figure 11 the driving timing simulation diagram of CLK1-CLK10 provided by an embodiment of the present application.

[0102] Further, the plurality of first clock signals CLKa are used to charge the sub-pixels of odd rows, and the plurality of second clock signals CLKb are used to charge the sub-pixels of even rows. Each of the effective levels of the first clock signals CLKa and the second clock signals CLKb includes a pre-charging phase S1 and a charging phase S2 corresponding to a row of sub-pixels.

[0103] wherein the charging phase S2 of each valid level in different first clock signals CLKa does not overlap; the charging phase S2 of each valid level in the second clock signal CLKb comprises a first sub-charging phase S21 and a second sub-charging phase S22; the first sub-charging phase S21 partially overlaps with the charging phase S2 of the valid level of the first clock signal CLKa corresponding to the sub-pixel of the previous odd-numbered row, and the second sub-charging phase S22 partially overlaps with the charging phase S2 of the valid level of the first clock signal CLKa corresponding to the sub-pixel of the next odd-numbered row.

[0104] Specifically, the design enables the sub-pixels of the odd-numbered rows to have data corresponding to the current row, and the sub-pixels of the even-numbered rows to be charged with data of two adjacent odd-numbered rows, thereby doubling the refresh rate and reducing the blurring and ghosting of dynamic images.

[0105] wherein the transmission rate of the data driving circuit = the number of data channel columns * the number of vertical scanning rows * the number of pixel color channels * the bit depth of a single color channel * a redundancy coefficient / the number of parallel channels. Taking a UD product with a refresh rate of 144 Hz and a 1G1D as an example, the transmission rate of the data driving circuit = 4400 * 2250 * 144 * 3 * 8 * 1.03 / 12 = 2.94 GHz, and the current industry specification is 3 GHz, so 144 Hz is the limit. However, the charging method of the embodiment of the present application can double the refresh rate from 144 Hz to 288 Hz, and the transmission rate of the data driving circuit = 4400 * 1125 * 288 * 3 * 8 * 1.03 / 12 = 2.94 GHz remains unchanged. In combination with the input frequency of the first level conversion unit 30 and the second level conversion unit 50 = 1125 * 288 * 2 = 648 kHz, which does not exceed the requirement of the input frequency of 700 kMz of the 8-output-channel LS IC. Thus, the refresh rate of a 50-inch ultra definition (UD) product is increased from 120 Hz to 288 Hz, greatly improving the product competitiveness.

[0106] Referring to Figure 12 , Figure 12 A flowchart of a driving method provided by an embodiment of the present application is shown.

[0107] The embodiment of the present application further provides a driving method, comprising:

[0108] Step S1: in response to receiving a picture display signal.

[0109] Step S2: outputting a first pre-configuration timing control signal group and a second pre-configuration timing control signal group to the first logic OR gate circuit 20; the first pre-configuration timing control signal group comprises a first timing pre-configuration signal CPV1 and a second timing pre-configuration signal CPV2 with a first period; the second pre-configuration timing control signal group comprises a third timing pre-configuration signal CPV3 and a fourth timing pre-configuration signal CPV4 with a second period; wherein the active level in each second period of the third timing pre-configuration signal CPV3 is located between two adjacent first periods of the first timing pre-configuration signal CPV1; the active level in each second period of the fourth timing pre-configuration signal CPV4 is located between two adjacent first periods of the second timing pre-configuration signal CPV2.

[0110] Step S3: using the first logic OR gate circuit 20 to superimpose the active level in each period of the third timing pre-configuration signal CPV3 between two adjacent first periods of the first timing pre-configuration signal CPV1 to obtain a first timing control signal CLK_IN1; and superimpose the active level in each period of the fourth timing pre-configuration signal CPV4 between two adjacent first periods of the second timing pre-configuration signal CPV2 to obtain a second timing control signal CLK_IN2; and output the first timing control signal CLK_IN1 and the second timing control signal CLK_IN2 to the first level conversion unit 30; wherein the first timing control signal CLK_IN1 and the second timing control signal CLK_IN2 have a third period, and the number of active levels in each third period is even.

[0111] Step S4: using the first level conversion unit 30 to output a first clock signal group based on the first timing control signal CLK_IN1 and the second timing control signal CLK_IN2; wherein the first clock signal group comprises a plurality of first clock signals CLKa, the starting time of the active level of each first clock signal CLKa is determined based on the first timing control signal CLK_IN1, and the cutoff time of the active level of each first clock signal CLKa is determined based on the second timing control signal CLK_IN2.

[0112] Specifically, in the driving method provided by the embodiment of the present application, the effective levels in the third timing preset signal CPV3 are superimposed between two adjacent periods in the first timing preset signal CPV1 by the first logical OR gate circuit 20 to obtain the first timing control signal CLK_IN1, and the effective levels in the fourth timing preset signal CPV4 are superimposed between two adjacent periods in the second timing preset signal CPV2 to obtain the second timing control signal CLK_IN2, so that the number of effective levels in each period in the first timing control signal CLK_IN1 and the second timing control signal CLK_IN2 is even, thereby enabling the single LS IC to generate an even number of first clock signals CLKa based on the first timing control signal CLK_IN1 and the second timing control signal CLK_IN2, and by superimposing the effective levels in the third timing preset signal CPV3 and the fourth timing preset signal CPV4 between two adjacent periods in the first timing preset signal CPV1 and the second timing preset signal CPV2 respectively, the third timing preset signal CPV3 and the fourth timing preset signal CPV4 do not affect the continuity of the plurality of first periods in the first timing preset signal CPV1 and the second timing preset signal CPV2, so that the single LS IC can output an odd number of effective clock signals.

[0113] Referring to Figure 13 , Figure 13 a flowchart of the driving method provided by another embodiment of the present application.

[0114] In an embodiment, in response to receiving the picture display signal, the method further comprises:

[0115] Step S5: outputting a third preset timing control signal group and a fourth preset timing control signal group to the second logical OR gate circuit 40; the third preset timing control signal group includes a fifth timing preset signal CPV5 and a sixth timing preset signal CPV6 having fourth periods; the fourth preset timing control signal group includes a seventh timing preset signal CPV7 and an eighth timing preset signal CPV8 having fifth periods; wherein the effective level in each fifth period in the seventh timing preset signal CPV7 is located between two adjacent fourth periods in the fifth timing preset signal CPV5; the effective level in each fifth period in the eighth timing preset signal CPV8 is located between two adjacent fourth periods in the sixth timing preset signal CPV6.

[0116] Step S6: superimposing the active level in each period of the seventh timing preset signal CPV7 between two adjacent fourth periods in the fifth timing preset signal CPV5 by the second logic OR gate circuit 40 to obtain the third timing control signal CLK IN3, and superimposing the active level in each period of the eighth timing preset signal CPV8 between two adjacent fourth periods in the sixth timing preset signal CPV6 to obtain the fourth timing control signal CLK IN4, and outputting the third timing control signal CLK IN3 and the fourth timing control signal CLK IN4 to the second level conversion unit 50; wherein the third timing control signal CLK IN3 and the fourth timing control signal CLK IN4 have a sixth period, and the number of active levels in each sixth period is even.

[0117] Step S7: outputting a second clock signal group by the second level conversion unit 50 based on the third timing control signal CLK IN3 and the fourth timing control signal CLK IN4; wherein the second clock signal group includes a plurality of second clock signals CLKb, the start time of the active level of each second clock signal CLKb is determined based on the third timing control signal CLK IN3, and the end time of the active level of each second clock signal CLKb is determined based on the fourth timing control signal CLK IN4.

[0118] Specifically, in the driving method provided by the embodiments of the present application, the second logic OR gate circuit 40 is further used to superimpose the active level in the seventh timing preset signal CPV7 between two adjacent periods in the fifth timing preset signal CPV5 to obtain the third timing control signal CLK IN3, and superimpose the active level in the eighth timing preset signal CPV8 between two adjacent periods in the sixth timing preset signal CPV6 to obtain the fourth timing control signal CLK IN4, so that the number of active levels in each period of the third timing control signal CLK IN3 and the fourth timing control signal CLK IN4 is even, thereby enabling the single LS IC to generate an even number of second clock signals CLKb based on the third timing control signal CLK IN3 and the fourth timing control signal CLK IN4, and by superimposing the active levels in the seventh timing preset signal CPV7 and the eighth timing preset signal CPV8 between two adjacent periods in the fifth timing preset signal CPV5 and the sixth timing preset signal CPV6 respectively, the seventh timing preset signal CPV7 and the eighth timing preset signal CPV8 will not affect the continuity of the plurality of first periods in the fifth timing preset signal CPV5 and the sixth timing preset signal CPV6, so that the single LS IC can output an odd number of active clock signals.

[0119] In an embodiment, the driving method further includes:

[0120] The odd rows of sub-pixels are charged by using a plurality of first clock signals CLKa, and the even rows of sub-pixels are charged by using a plurality of second clock signals CLKb. Each of the first clock signals CLKa and the second clock signals CLKb includes a pre-charging phase S1 and a charging phase S2 corresponding to a row of sub-pixels; the charging phase S2 of each of the different first clock signals CLKa does not overlap; the charging phase S2 of each of the second clock signals CLKb includes a first sub-charging phase S21 and a second sub-charging phase S22; the first sub-charging phase S21 partially overlaps with the charging phase S2 of the effective level of the first clock signal CLKa corresponding to the sub-pixels of the previous odd row, and the second sub-charging phase S22 partially overlaps with the charging phase S2 of the effective level of the first clock signal CLKa corresponding to the sub-pixels of the next odd row.

[0121] Specifically, the driving method realizes that the sub-pixels of the odd rows have data corresponding to the current row, and the sub-pixels of the even rows are charged with data of adjacent two odd rows, so as to realize the doubling of the refresh rate, reduce the blur and ghosting phenomenon of dynamic pictures. In combination with the above steps S1 to S6, the refresh rate of the display product can be greatly improved, for example, the refresh rate of a 50-inch ultra definition (UD) product is improved from 120Hz to 288Hz, and the product competitiveness is greatly improved.

[0122] Referring to Figure 14 , Figure 14 A module schematic diagram of a display device provided by an embodiment of the present application is provided.

[0123] The present application also provides a display device 1000, which includes a display panel 200 and the driving module 100 provided by any of the above embodiments.

[0124] The display panel 200 includes a plurality of rows of sub-pixels and a scan driving circuit connected to the plurality of rows of sub-pixels; the driving module 100 is connected to the scan driving circuit, and the driving module 100 is configured to output a first clock signal group and a second clock signal group to the scan driving circuit to control at least part of the rows of sub-pixels to work.

[0125] The display device 1000 can be applied to the fields of smart phones, e-sports displays, high-end televisions, virtual reality devices, augmented reality devices, notebooks, tablet computers, etc. Specifically, the display device 1000 has a high refresh rate, can significantly reduce picture trailing (Motion Blur), eliminate picture tearing (Screen Tearing), improve dynamic picture clarity, reduce visual lag (Perceived Latency), and has other advantages.

[0126] The above are merely implementations of the embodiments of the present application, and do not limit the patent scope of the embodiments of the present application, and any equivalent structure or equivalent process transformation made by using the content of the embodiments of the present application and the drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the embodiments of the present application.

Claims

1. A driving module, characterized in that, include: A timing control unit is used to output a first set of preset timing control signals and a second set of preset timing control signals; The first pre-set timing control signal group includes a first timing pre-set signal and a second timing pre-set signal having a first period; the second pre-set timing control signal group includes a third timing pre-set signal and a fourth timing pre-set signal having a second period; wherein, the effective level in each second period of the third timing pre-set signal is located between two adjacent first periods of the first timing pre-set signal; the effective level in each second period of the fourth timing pre-set signal is located between two adjacent first periods of the second timing pre-set signal; A first logic OR gate, connected to the timing control unit, is configured to receive the first pre-set timing control signal group and the second pre-set timing control signal group; and to superimpose the effective level of each cycle of the third pre-set timing signal onto two adjacent first cycles of the first pre-set timing signal to obtain a first timing control signal; and to superimpose the effective level of each cycle of the fourth pre-set timing signal onto two adjacent first cycles of the second pre-set timing signal to obtain a second timing control signal; wherein the first timing control signal and the second timing control signal have a third cycle, and the number of effective levels in each third cycle is even; A first level conversion unit, connected to the first logic OR gate circuit, is used to receive the first timing control signal and the second timing control signal, and output a first clock signal group based on the first timing control signal and the second timing control signal; wherein, the first clock signal group includes a plurality of first clock signals, the first level conversion unit determines the start time of the effective level of each first clock signal according to the first timing control signal, and the first level conversion unit determines the end time of the effective level of each first clock signal according to the second timing control signal.

2. The driving module according to claim 1, characterized in that, The timing control unit is further configured to output a third pre-set timing control signal group and a fourth pre-set timing control signal group; the third pre-set timing control signal group includes a fifth pre-set timing signal and a sixth pre-set timing signal having a fourth cycle; the fourth pre-set timing control signal group includes a seventh pre-set timing signal and an eighth pre-set timing signal having a fifth cycle; wherein, the effective level in each fifth cycle of the seventh pre-set timing signal is located between two adjacent fourth cycles of the fifth pre-set timing signal; the effective level in each fifth cycle of the eighth pre-set timing signal is located between two adjacent fourth cycles of the sixth pre-set timing signal; The driver module also includes: A second logic OR gate, connected to the timing control unit, is used to receive the third pre-set timing control signal group and the fourth pre-set timing control signal group; and to superimpose the effective level of each cycle of the seventh pre-set timing signal onto the two adjacent fourth cycles of the fifth pre-set timing signal to obtain the third timing control signal; and to superimpose the effective level of each cycle of the eighth pre-set timing signal onto the two adjacent fourth cycles of the sixth pre-set timing signal to obtain the fourth timing control signal; wherein the third timing control signal and the fourth timing control signal have a sixth cycle, and the number of effective levels in each sixth cycle is even; The second level conversion unit, connected to the second logic OR gate circuit, is used to receive the third timing control signal and the fourth timing control signal, and output a second clock signal group based on the third timing control signal and the fourth timing control signal; wherein, the second clock signal group includes multiple second clock signals, the second level conversion unit determines the start time of the effective level of each second clock signal according to the third timing control signal, and the second level conversion unit determines the end time of the effective level of each second clock signal according to the fourth timing control signal.

3. The driving module according to claim 2, characterized in that, The number of effective levels in each cycle of both the first and second timing pre-signals is odd. The number of effective levels in each cycle of the third timing pre-set signal and the fourth timing pre-set signal is odd; The number of effective levels in each cycle of the fifth timing pre-set signal and the sixth timing pre-set signal is odd; The number of effective levels in each cycle of the seventh and eighth timing pre-signals is odd.

4. The driving module according to claim 2, characterized in that, The first level conversion unit and the second level conversion unit alternately output the first clock signal and the second clock signal.

5. The driving module according to claim 2, characterized in that, The driving module further includes a differential control unit, which is connected to the timing control unit, the first level conversion unit, and the second level conversion unit. The first level conversion unit and the second level conversion unit respectively output the generated first clock signal group and the second clock signal group to the differential control unit. The timing control unit controls the differential control unit to alternately output the first clock signal and the second clock signal.

6. The driving module according to claim 4 or 5, characterized in that, The time interval between two adjacent first cycles is equal to the time interval between two adjacent effective levels within the first cycle; The interval between two adjacent fourth cycles is equal to the interval between two adjacent effective levels within the fourth cycle.

7. The driving module according to claim 4 or 5, characterized in that, A plurality of first clock signals are used to charge sub-pixels in odd-numbered rows, and each valid level of the first clock signal includes a pre-charging phase and a charging phase for the corresponding row of sub-pixels; a plurality of second clock signals are used to charge sub-pixels in even-numbered rows, and each valid level of the second clock signal includes a pre-charging phase and a charging phase for the corresponding row of sub-pixels. Wherein, the charging phases of each valid level in the different first clock signals do not overlap; the charging phase of each valid level in the second clock signal includes a first sub-charging phase and a second sub-charging phase; the first sub-charging phase partially overlaps with the charging phase of the valid level of the first clock signal corresponding to the sub-pixel in the previous odd-numbered row, and the second sub-charging phase partially overlaps with the charging phase of the valid level of the first clock signal corresponding to the sub-pixel in the next odd-numbered row.

8. A display device, characterized in that, include: The display panel includes multiple rows of sub-pixels and a scan driving circuit connected to the multiple rows of sub-pixels; A driving module is connected to the scanning driving circuit. The driving module is used to output a first clock signal group to the scanning driving circuit to control the operation of the sub-pixels in at least a portion of the multiple rows of sub-pixels. The driving module includes the driving module according to any one of claims 1-7.

9. A driving method, characterized in that, include: In response to receiving a screen display signal; Output the first pre-set timing control signal group and the second pre-set timing control signal group to the first logic OR gate circuit; The first pre-set timing control signal group includes a first timing pre-set signal and a second timing pre-set signal having a first period; the second pre-set timing control signal group includes a third timing pre-set signal and a fourth timing pre-set signal having a second period; wherein, the effective level in each second period of the third timing pre-set signal is located between two adjacent first periods of the first timing pre-set signal; the effective level in each second period of the fourth timing pre-set signal is located between two adjacent first periods of the second timing pre-set signal; The first timing control signal is obtained by superimposing the effective level of each cycle of the third timing preset signal onto two adjacent first cycles of the first timing preset signal using the first logic OR gate circuit; and the second timing control signal is obtained by superimposing the effective level of each cycle of the fourth timing preset signal onto two adjacent first cycles of the second timing preset signal; and the first timing control signal and the second timing control signal are output to the first level conversion unit; wherein the first timing control signal and the second timing control signal have a third cycle, and the number of effective levels in each third cycle is even. A first clock signal group is output using a first level conversion unit based on the first timing control signal and the second timing control signal; wherein, the first clock signal group includes a plurality of first clock signals, the start time of the effective level of each first clock signal is determined based on the first timing control signal, and the end time of the effective level of each first clock signal is determined based on the second timing control signal.

10. The driving method according to claim 9, characterized in that, The response after receiving the screen display signal also includes: A third and a fourth pre-set timing control signal group are output to a second logic OR gate circuit; the third pre-set timing control signal group includes a fifth and a sixth pre-set timing signal with a fourth cycle; the fourth pre-set timing control signal group includes a seventh and an eighth pre-set timing signal with a fifth cycle; wherein, the effective level in each fifth cycle of the seventh pre-set timing signal is located between two adjacent fourth cycles of the fifth pre-set timing signal; the effective level in each fifth cycle of the eighth pre-set timing signal is located between two adjacent fourth cycles of the sixth pre-set timing signal; The effective levels of each cycle of the seventh timing preset signal are superimposed onto two adjacent fourth cycles of the fifth timing preset signal using the second logic OR gate circuit to obtain a third timing control signal; and the effective levels of each cycle of the eighth timing preset signal are superimposed onto two adjacent fourth cycles of the sixth timing preset signal to obtain a fourth timing control signal; and the third timing control signal and the fourth timing control signal are output to the second level conversion unit; wherein the third timing control signal and the fourth timing control signal have a sixth cycle, and the number of effective levels in each sixth cycle is even; The second level conversion unit outputs a second clock signal group based on the third timing control signal and the fourth timing control signal; wherein, the second clock signal group includes a plurality of second clock signals, the start time of the effective level of each second clock signal is determined based on the third timing control signal, and the end time of the effective level of each second clock signal is determined based on the fourth timing control signal.

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