Display device and driving method thereof

Abstract

This application provides a display device and its driving method. The display device includes a display panel and a driving circuit, the driving circuit being electrically connected to the display panel. The driving circuit includes at least one set of driving sub-circuits, each including a first level conversion circuit, a second level conversion circuit, and a discharge circuit. The first level conversion circuit is configured to output a first voltage to the output terminal of the driving sub-circuit according to a first control signal. The second level conversion circuit is configured to output a second voltage to the output terminal of the driving sub-circuit according to a second control signal. The discharge circuit is configured to release the voltage at the output terminal of the driving sub-circuit to a ground potential according to a discharge control signal. This application can output a driving signal that meets the driving requirements of a cholesteric liquid crystal display device, solving the technical problem that existing driving technologies cannot output driving signals with voltage values ​​adapted to cholesteric liquid crystal display devices. Furthermore, the voltage value and timing of the driving signal can be flexibly adjusted.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display device and its driving method. Background Technology

[0002] In display applications such as electronic paper, cholesteric liquid crystal materials typically require a driving voltage of ±40V to achieve the switching of display states.

[0003] Traditional driver ICs (Driver Integrated Circuits) typically have a voltage tolerance range of ±25V, and cannot directly output a drive voltage of ±40V. To achieve high-voltage drive, an external power supply is required in conjunction with a level shift IC (Level Shift Integrated Circuit) to convert and output a higher drive voltage.

[0004] However, existing level conversion chips typically only support a voltage range of +40V to -20V, which cannot meet the requirement of cholesteric liquid crystals for symmetrical ±40V driving voltages. Furthermore, existing level conversion chips cannot insert zero voltage of varying durations between the positive and negative high-voltage waveforms, limiting the flexibility of the driving waveform. During the research and verification phase of cholesteric liquid crystal materials, the driving waveform parameters need to be adjusted according to actual conditions, while the driving waveform parameters of existing driving technologies are relatively fixed and difficult to adjust flexibly. Customizing a dedicated driving chip for specific driving requirements would require significant development costs and a long development cycle.

[0005] Therefore, it is necessary to propose a new technical solution to solve the above-mentioned technical problems. Summary of the Invention

[0006] The purpose of this application is to provide a display device and its driving method, which aims to solve the technical problem that existing driving technology solutions cannot output voltage values ​​that are compatible with the driving signals of cholesteric liquid crystal display devices.

[0007] This application provides a display device, the display device including a display panel and a driving circuit, the driving circuit being electrically connected to the display panel, the driving circuit including at least one set of driving sub-circuits, the set of driving sub-circuits including: a first level conversion circuit configured to output a first voltage to the output terminal of the driving sub-circuit according to a first control signal; a second level conversion circuit configured to output a second voltage to the output terminal of the driving sub-circuit according to a second control signal; and a discharge circuit configured to release the voltage at the output terminal of the driving sub-circuit to a ground potential according to a discharge control signal.

[0008] In the above-mentioned display device, the first level conversion circuit includes a first transistor, a second transistor, and a first diode. The gate of the first transistor is electrically connected to a first control signal terminal, the source of the first transistor is electrically connected to a ground terminal, the drain of the first transistor is electrically connected to the gate of the second transistor, the source of the second transistor is electrically connected to a first power supply terminal, the anode of the first diode is electrically connected to the drain of the second transistor, and the cathode of the first diode is electrically connected to the output terminal of the driving sub-circuit.

[0009] In the above-described display device, the first level conversion circuit further includes a first resistor, a second resistor, a third resistor, a thirteenth resistor, and a first capacitor. The first end of the first resistor is electrically connected to the drain of the first transistor. The first end of the second resistor is electrically connected to the first power supply terminal. The second end of the first resistor is electrically connected to the gate of the second transistor. The third resistor is electrically connected between the drain of the second transistor and the ground terminal. The thirteenth resistor is electrically connected between the first control signal terminal and the gate of the first transistor. The first plate of the first capacitor is electrically connected to the gate of the second transistor. The second plate of the first capacitor is electrically connected to the ground terminal.

[0010] In the above-mentioned display device, the driving sub-circuit further includes a fifth resistor; the cathode of the first diode is electrically connected to the output terminal of the driving sub-circuit through the fifth resistor.

[0011] In the above-described display device, the second level conversion circuit includes a comparator, a third transistor, a fourth transistor, and a second diode. The non-inverting input terminal of the comparator is electrically connected to a second control signal terminal, the inverting input terminal of the comparator is electrically connected to a reference voltage terminal, the positive power supply terminal of the comparator is electrically connected to a third power supply terminal, the negative power supply terminal of the comparator is electrically connected to a fourth power supply terminal, the gate of the third transistor is electrically connected to the output terminal of the comparator, the source of the third transistor is electrically connected to the ground terminal, the drain of the third transistor is electrically connected to the gate of the fourth transistor, the source of the fourth transistor is electrically connected to the second power supply terminal, the cathode of the second diode is electrically connected to the drain of the fourth transistor, and the anode of the second diode is electrically connected to the output terminal of the driving sub-circuit.

[0012] In the above-described display device, the second level conversion circuit further includes a fourth resistor, an eighth resistor, a ninth resistor, and a second capacitor. The fourth resistor is electrically connected between the drain of the fourth transistor and the ground terminal. The first end of the eighth resistor is electrically connected to the drain of the third transistor, and the second end of the eighth resistor is electrically connected to the gate of the fourth transistor. The first end of the ninth resistor is electrically connected to the second power supply terminal, and the second end of the ninth resistor is electrically connected to the gate of the fourth transistor. The first plate of the second capacitor is electrically connected to the gate of the fourth transistor, and the second plate of the second capacitor is electrically connected to the ground terminal.

[0013] In the above-mentioned display device, the driving sub-circuit further includes an eleventh resistor; the anode of the second diode is electrically connected to the output terminal of the driving sub-circuit through the eleventh resistor.

[0014] In the above-mentioned display device, the discharge circuit includes a fifth transistor and a third diode. The gate of the fifth transistor is electrically connected to the discharge control signal terminal, the source of the fifth transistor is electrically connected to the ground terminal, the drain of the fifth transistor is electrically connected to the cathode of the third diode, and the anode of the third diode is electrically connected to the cathode of the second diode.

[0015] In the above-mentioned display device, the driving circuit includes multiple sets of driving sub-circuits, the output terminals of the multiple sets of driving sub-circuits are connected in parallel, the first power supply terminal of the first level conversion circuit of different sets of driving sub-circuits is electrically connected to a positive power supply with a different voltage value, and the second power supply terminal of the second level conversion circuit of different sets of driving sub-circuits is electrically connected to a negative power supply with a different voltage value.

[0016] In the aforementioned display device, the multiple sets of driving sub-circuits include a first set of driving sub-circuits and a second set of driving sub-circuits. The first power supply terminal of the first level conversion circuit of the first set of driving sub-circuits is electrically connected to a first positive power supply with a voltage value of 35V to 40V. The second power supply terminal of the second level conversion circuit of the first set of driving sub-circuits is electrically connected to a first negative power supply with a voltage value of -35V to -40V. The first power supply terminal of the first level conversion circuit of the second set of driving sub-circuits is electrically connected to a second positive power supply with a voltage value of 18V to 25V. The second power supply terminal of the second level conversion circuit of the second set of driving sub-circuits is electrically connected to a second negative power supply with a voltage value of -18V to -25V.

[0017] This application also provides a driving method for a display device, the display device including a display panel and a driving circuit, the driving circuit including at least one set of driving sub-circuits, the driving sub-circuit including a first level conversion circuit, a second level conversion circuit and a discharge circuit, the driving method including: when a first control signal is high, the first level conversion circuit outputs a first voltage to the output terminal of the driving sub-circuit; when a second control signal is high, the second level conversion circuit outputs a second voltage to the output terminal of the driving sub-circuit; after the first control signal changes from high to low, the discharge circuit is controlled to conduct by a discharge control signal, the discharge circuit releasing the voltage at the output terminal of the driving sub-circuit to the ground potential.

[0018] In the above driving method, the driving method further includes: controlling the first control signal to be at a low level, and the first level conversion circuit stopping the output of the first voltage; and controlling the second control signal to be at a low level, and the second level conversion circuit stopping the output of the second voltage.

[0019] In the above driving method, the driving circuit includes multiple sets of driving sub-circuits, the output terminals of the multiple sets of driving sub-circuits are connected in parallel, and the driving method further includes: at different times, the first control signal or the second control signal of different sets of driving sub-circuits is at a high level, and the output traces electrically connected to the output terminals of the multiple sets of driving sub-circuits output a first voltage and a second voltage with different voltage values.

[0020] In the above driving method, the first voltage and second voltage with different voltage values ​​output by the output traces electrically connected to the output terminals of the multiple sets of driving sub-circuits include: during a first time period, the second control signal of the first set of driving sub-circuits is at a high level, and the output traces output a second voltage of -35V to -40V; during a second time period, the first control signal of the first set of driving sub-circuits is at a high level, and the output traces output a first voltage of 35V to 40V; during a third time period, the discharge control signal of the first set of driving sub-circuits is at a high level, and the output traces output zero voltage; during a fourth time period, the second control signal of the second set of driving sub-circuits is at a high level, and the output traces output a second voltage of -18V to -25V; during a fifth time period, the first control signal of the second set of driving sub-circuits is at a high level, and the output traces output a first voltage of 18V to 25V; and during a sixth time period, the discharge control signal of the second set of driving sub-circuits is at a high level, and the output traces output zero voltage.

[0021] The technical solution of this application, by setting a first level conversion circuit, a second level conversion circuit, and a discharge circuit in the driving sub-circuit, enables the driving circuit to output a first voltage according to a first control signal, output a second voltage according to a second control signal, and release the voltage at the output terminal of the driving sub-circuit to the ground potential according to the discharge control signal. Since the first and second level conversion circuits independently output corresponding voltages to the output terminal of the driving sub-circuit according to their respective control signals, and the discharge circuit can release the voltage at the output terminal of the driving sub-circuit to the ground potential, the driving sub-circuit can output positive, negative, or zero voltage values ​​at different times. By adjusting the timing of the first, second, and discharge control signals, flexible switching between positive, negative, and zero voltages can be achieved, and the duration of each voltage can be flexibly controlled. This allows the output of a driving signal with a voltage value that meets the driving requirements of a cholesteric liquid crystal display device, solving the technical problem that existing driving technologies cannot output driving signals with voltage values ​​adapted to cholesteric liquid crystal display devices.

[0022] Furthermore, by setting a first diode and a second diode at the output terminals of the first level conversion circuit and the second level conversion circuit respectively, when the first level conversion circuit outputs a first voltage, the first diode conducts in the forward direction and the second diode is cut off in the reverse direction, thereby preventing the first voltage from flowing back into the second level conversion circuit; when the second level conversion circuit outputs a second voltage, the second diode conducts in the forward direction and the first diode is cut off in the reverse direction, thereby preventing the second voltage from flowing back into the first level conversion circuit. This avoids current backflow between the first level conversion circuit and the second level conversion circuit, improving the reliability and stability of the drive circuit.

[0023] Furthermore, when the driving circuit includes multiple sets of driving sub-circuits, and the output terminals of these multiple sets of driving sub-circuits are connected in parallel, the first power supply terminal of the first level conversion circuit of different sets of driving sub-circuits is electrically connected to a positive power supply with a different voltage value, and the second power supply terminal of the second level conversion circuit of different sets of driving sub-circuits is electrically connected to a negative power supply with a different voltage value. By controlling the first or second control signal of different sets of driving sub-circuits to a high level at different times, the output traces electrically connected to the output terminals of the multiple sets of driving sub-circuits can output first and second voltages with different voltage values. This allows for the output of multiple positive and negative voltages with different voltage values ​​on the same output trace, further improving the flexibility of the driving waveform and meeting the requirements of cholesteric liquid crystal display devices for driving signals with different voltage values ​​under different display states.

[0024] The technical solution of this application adopts a level conversion circuit composed of discrete components such as transistors and diodes, which reduces development costs and shortens the development cycle compared to custom-designed dedicated driver chips. Furthermore, by adjusting the voltage values ​​of the power supplies electrically connected to the first and second power supply terminals, as well as adjusting the timing parameters of the first control signal, the second control signal, and the discharge control signal, the voltage values ​​and timing of the drive signals can be flexibly adjusted. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of a display device provided in an embodiment of this application.

[0026] Figure 2 A circuit diagram of the driving sub-circuit of the display device provided in an embodiment of this application.

[0027] Figure 3 A schematic diagram of the driving circuit of a display device provided in an embodiment of this application.

[0028] Figure 4 Waveform diagrams of control signals and drive signals of a display device provided for embodiments of this application.

[0029] Figure 5 A waveform of the data drive signal of the display device provided in the embodiments of this application, measured in an oscilloscope.

[0030] Figure 6 A waveform of the gate drive signal of a display device provided in an embodiment of this application, measured in an oscilloscope. Detailed Implementation

[0031] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0032] The terms “first,” “second,” and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms “multiple,” and similar words mean two or more, unless otherwise expressly specified.

[0033] The technical solutions of different embodiments of this application can be combined with each other.

[0034] like Figure 1 As shown, the display device provided in the embodiments of this application includes a display panel 10 and a driving circuit 20. The display panel 10 is a cholesteric liquid crystal display panel, which includes multiple gate lines, multiple data lines, and multiple pixels arranged in an array. The multiple gate lines extend along a first direction and are spaced apart along a second direction, and the multiple data lines extend along the second direction and are spaced apart along the first direction, with the first and second directions being perpendicular to each other. Each pixel is electrically connected to one gate line and one data line. The driving circuit 20 is electrically connected to the display panel 10. The driving circuit 20 sequentially provides gate signals to the multiple gate lines and provides data signals to the multiple data lines, thereby changing the arrangement state of the cholesteric liquid crystal molecules and realizing a bistable reflective display.

[0035] The driving circuit 20 includes a power supply circuit 201, a level conversion circuit 202, and a general-purpose input / output circuit 203. The power supply circuit 201 outputs multiple sets of positive power supplies and multiple sets of negative power supplies to the level conversion circuit 202. The general-purpose input / output circuit 203 outputs control signals to the level conversion circuit 202. Based on the received power and control signals, the level conversion circuit 202 outputs data signals, gate signals, and common voltage signals to the display panel 10. The voltage range of the data signals includes ±35V, ±18V to ±21V, and 0V; the voltage of the gate signals includes 40V and -25V; and the voltage of the common voltage signal is 0V.

[0036] like Figure 2 and Figure 3 As shown, the driving circuit 20 includes at least one set of driving sub-circuits. Each set of driving sub-circuits includes a first level conversion circuit 2021, a second level conversion circuit 2022, and a discharge circuit 2023. The first level conversion circuit 2021 is configured to output a first voltage, which is positive, to the output terminal of the driving sub-circuit according to a first control signal. The second level conversion circuit 2022 is configured to output a second voltage, which is negative, to the output terminal of the driving sub-circuit according to a second control signal. The discharge circuit 2023 is configured to release the voltage at the output terminal of the driving sub-circuit to a ground potential, which is zero, according to a discharge control signal.

[0037] Within a complete drive cycle, by controlling the timing relationship of the first control signal, the second control signal, and the discharge control signal, the output terminal of the drive sub-circuit outputs a first voltage, a second voltage, or zero voltage at different times. When the first control signal is high, the first level conversion circuit 2021 is turned on, converting the positive voltage of the first power supply terminal into the first voltage and outputting it to the output terminal of the drive sub-circuit. When the second control signal is high, the second level conversion circuit 2022 is turned on, converting the negative voltage of the second power supply terminal into the second voltage and outputting it to the output terminal of the drive sub-circuit. When both the first and second control signals are low, and the discharge control signal is high, the discharge circuit 2023 is turned on, releasing the voltage at the output terminal of the drive sub-circuit to the ground potential. Through the above control logic, the output terminal of the drive sub-circuit outputs a drive waveform that alternates between positive voltage, negative voltage, and zero voltage according to a predetermined timing sequence.

[0038] Power supply circuit 201 provides positive and negative high-voltage power to the first power supply terminal of the first level conversion circuit 2021 and the second power supply terminal of the second level conversion circuit 2022. The voltage value of the first power supply terminal is in the range of 3V to 40V, and the voltage value of the second power supply terminal is in the range of -3V to -40V. General purpose input / output circuit 203 provides a first control signal, a second control signal, and a discharge control signal to the first level conversion circuit 2021, the second level conversion circuit 2022, and the discharge circuit 2023 through a general purpose input / output port. The voltage value of the control signal output from the general purpose input / output port is 3.3V or other low voltage value, which is much lower than the voltage value of the drive signal output terminal of the drive sub-circuit. The first level conversion circuit 2021 and the second level conversion circuit 2022 are used to convert the low-voltage control signal into a high-voltage drive signal.

[0039] The duration of the first voltage at the output of the driver sub-circuit is equal to the high-level duration of the first control signal, and the duration of the second voltage at the output of the driver sub-circuit is equal to the high-level duration of the second control signal. The output order of the first and second voltages at the output of the driver sub-circuit corresponds to the timing relationship between the first and second control signals. By adjusting the high-level duration and timing relationship of the first and second control signals, the duration and output order of the first and second voltages in the driving waveform can be flexibly controlled.

[0040] like Figure 2As shown, the first level conversion circuit 2021 includes a first transistor Q1, a second transistor Q2, a first diode D3, a thirteenth resistor R1, a first resistor R2, a second resistor R3, a third resistor R4, a fifth resistor R10, and a first capacitor C1. The first transistor Q1 is an N-channel field-effect transistor, and the second transistor Q2 is a P-channel field-effect transistor.

[0041] The gate of the first transistor Q1 is electrically connected to the first control signal terminal GPIO1 through the thirteenth resistor R1. The source of the first transistor Q1 is electrically connected to the ground terminal GND. The drain of the first transistor Q1 is electrically connected to the first terminal of the first resistor R2. The second terminal of the first resistor R2 is electrically connected to the gate of the second transistor Q2. The first terminal of the second resistor R3 is electrically connected to the first power supply terminal VDD1. The second terminal of the second resistor R3 is electrically connected to the gate of the second transistor Q2. The source of the second transistor Q2 is electrically connected to the first power supply terminal VDD1. The drain of the second transistor Q2 is electrically connected to the anode of the first diode D3. The first terminal of the third resistor R4 is electrically connected to the drain of the second transistor Q2. The second terminal of the third resistor R4 is electrically connected to the ground terminal GND. The cathode of the first diode D3 is electrically connected to the output terminal VOUT of the driver sub-circuit through the fifth resistor R10. The first plate of the first capacitor C1 is electrically connected to the gate of the second transistor Q2. The second plate of the first capacitor C1 is electrically connected to the ground terminal GND.

[0042] The thirteenth resistor, R1, limits the current supplied to the gate of the first transistor Q1 by the first control signal terminal GPIO1, protecting the gate of the first transistor Q1 from damage by excessive current. The first resistor R2 and the second resistor R3 are connected in series to form a voltage divider circuit, and this series circuit is electrically connected between the first power supply terminal VDD1 and the ground terminal GND. The gate of the second transistor Q2 is electrically connected to the series connection point of the first resistor R2 and the second resistor R3. The first capacitor C1 stabilizes the gate voltage of the second transistor Q2, reducing fluctuations in its gate voltage. The third resistor R4 provides a discharge path for the drain of the second transistor Q2. The fifth resistor R10 limits the current at the output terminal VOUT of the drive sub-circuit.

[0043] When the first control signal at the first control signal terminal GPIO1 is high, the first transistor Q1 is turned on, and its drain voltage is pulled down to near ground. Since the drain of the first transistor Q1 is electrically connected to the gate of the second transistor Q2 through the first resistor R2, the gate voltage of the second transistor Q2 decreases. For a P-channel MOSFET, when the gate voltage decreases relative to the source voltage, the absolute value of the gate-source voltage increases, and the P-channel MOSFET turns on. The source of the second transistor Q2 is electrically connected to the first power supply terminal VDD1. When the gate voltage of the second transistor Q2 decreases, the absolute value of its gate-source voltage increases, and the second transistor Q2 turns on. When the second transistor Q2 is on, the positive voltage at the first power supply terminal VDD1 is transmitted to the output terminal VOUT of the driver sub-circuit through the conduction path between the source and drain of the second transistor Q2, the first diode D3, and the fifth resistor R10. Since the anode of the first diode D3 is electrically connected to the drain of the second transistor Q2, and the cathode of the first diode D3 is electrically connected to the output terminal VOUT of the driver sub-circuit through the fifth resistor R10, and the voltage at the first power supply terminal VDD1 is positive, the anode potential of the first diode D3 is higher than the cathode potential, and the first diode D3 is forward-biased. The voltage value of the first voltage output by the first level conversion circuit 2021 is equal to the voltage value at the first power supply terminal VDD1 minus the forward voltage drop of the first diode D3 and the voltage drop across the fifth resistor R10.

[0044] When the first control signal at the first control signal terminal GPIO1 is low, the first transistor Q1 is turned off, and the drain of the first transistor Q1 presents a high impedance state with respect to the ground terminal GND. At this time, the first power supply terminal VDD1 provides voltage to the gate of the second transistor Q2 through the series circuit of the first resistor R2 and the second resistor R3. The ratio of the resistance values ​​of the first resistor R2 and the second resistor R3 determines the ratio of the gate voltage of the second transistor Q2 to the voltage of the first power supply terminal VDD1. By selecting appropriate resistance values ​​of the first resistor R2 and the second resistor R3, the gate voltage of the second transistor Q2 is made close to the voltage of the first power supply terminal VDD1, and the gate-source voltage of the second transistor Q2 is close to zero, so the second transistor Q2 is turned off. When the second transistor Q2 is turned off, the first power supply terminal VDD1 is isolated from the first diode D3 through the high impedance between the source and drain of the second transistor Q2, and the first power supply terminal VDD1 cannot provide current to the output terminal VOUT of the driver sub-circuit. At this time, the first level conversion circuit 2021 stops outputting the first voltage.

[0045] In one embodiment of this application, the voltage of the first power supply terminal VDD1 is 40V. The forward voltage drop of the first diode D3 is 0.7V. The resistance value of the fifth resistor R10 is selected such that the voltage drop across the fifth resistor R10 is less than 1V. At this time, the voltage value of the first voltage output by the first level conversion circuit 2021 is approximately 38V to 39V, which meets the requirement of the cholesteric liquid crystal display panel 10 for a forward driving voltage of approximately 40V.

[0046] In another embodiment of this application, the voltage value of the first power supply terminal VDD1 is in the range of 35V to 40V. By adjusting the voltage value of the first power supply terminal VDD1, the voltage value of the first voltage output by the first level conversion circuit 2021 is also adjusted accordingly to the range of approximately 34V to approximately 39V.

[0047] like Figure 2 As shown, the second level conversion circuit 2022 includes a comparator U1, a third transistor Q3, a fourth transistor Q4, a second diode D4, a sixth resistor R114, a seventh resistor R7, an eighth resistor R6, a ninth resistor R5, a fourth resistor R13, an eleventh resistor R11, a twelfth resistor R124, and a second capacitor C62. The third transistor Q3 is an N-channel field-effect transistor, and the fourth transistor Q4 is an N-channel field-effect transistor.

[0048] The non-inverting input (pin 3) of comparator U1 is electrically connected to the second control signal terminal GPIO2, and the inverting input (pin 2) is electrically connected to the reference voltage terminal VREF. The positive power supply terminal (pin 8) of comparator U1 is electrically connected to the third power supply terminal VCC, and the negative power supply terminal (pin 4) is electrically connected to the fourth power supply terminal VEE. Since comparator U1 needs to operate under high voltage, to prevent excessive voltage from damaging its internal circuitry, in practical applications, the positive and negative high voltages are stepped down to approximately +10V and -10V respectively using a voltage divider circuit, and then supplied to pins 8 and 4 of comparator U1 as the third power supply terminal VCC and the fourth power supply terminal VEE. The voltage difference between pins 8 and 4 of comparator U1 is approximately 20V.

[0049] The output of comparator U1 (pin 1) is electrically connected to the gate of the third transistor Q3 through the sixth resistor R114. Pin 1 of comparator U1 is also electrically connected to the first end of the seventh resistor R7, and the second end of the seventh resistor R7 is electrically connected to pin 8. Pins 5, 6, and 7 of comparator U1 are electrically connected to the second end of the twelfth resistor R124, and the first end of the twelfth resistor R124 is electrically connected to ground GND. The source of the third transistor Q3 is electrically connected to ground GND, and the drain of the third transistor Q3 is electrically connected to the first end of the eighth resistor R6. The second end of the eighth resistor R6 is electrically connected to the gate of the fourth transistor Q4. The first end of the ninth resistor R5 is electrically connected to the second power supply terminal VDD2, and the second end of the ninth resistor R5 is electrically connected to the gate of the fourth transistor Q4. The source of the fourth transistor Q4 is electrically connected to the second power supply terminal VDD2, and the drain of the fourth transistor Q4 is electrically connected to the cathode of the second diode D4. The first terminal of the fourth resistor R13 is electrically connected to the drain of the fourth transistor Q4, and the second terminal of the fourth resistor R13 is electrically connected to the ground terminal GND. The anode of the second diode D4 is electrically connected to the output terminal VOUT of the driver sub-circuit through the eleventh resistor R11. The first plate of the second capacitor C62 is electrically connected to the gate of the fourth transistor Q4, and the second plate of the second capacitor C62 is electrically connected to the ground terminal GND.

[0050] The reference voltage provided by the reference voltage terminal VREF is 1.8V. When the second control signal output from the second control signal terminal GPIO2 is low, the voltage value of the second control signal is 0V; when the second control signal is high, the voltage value of the second control signal is 3.3V.

[0051] When the second control signal at the second control signal terminal GPIO2 is high, the voltage value of the second control signal is 3.3V, which is greater than the reference voltage value of 1.8V. The voltage at the non-inverting input terminal (pin 3) of comparator U1 is higher than the voltage at the inverting input terminal (pin 2) of comparator U1, and the output terminal (pin 1) of comparator U1 outputs a high level. The high level at pin 1 of comparator U1 is transmitted to the gate of the third transistor Q3 through the sixth resistor R114, causing the third transistor Q3 to conduct. When the third transistor Q3 is conducted, the drain voltage of the third transistor Q3 is pulled down to near the ground potential. Since the drain of the third transistor Q3 is electrically connected to the gate of the fourth transistor Q4 through the eighth resistor R6, the gate voltage of the fourth transistor Q4 decreases. For an N-channel MOSFET, the N-channel MOSFET conducts when the gate voltage is higher than the source voltage. The source of the fourth transistor Q4 is electrically connected to the second power supply terminal VDD2, which has a negative voltage. When the gate voltage of the fourth transistor Q4 drops to near ground potential, the gate voltage of the fourth transistor Q4 increases relative to its source voltage, resulting in an increased gate-source voltage and the fourth transistor Q4 turning on. When the fourth transistor Q4 is on, the negative voltage of the second power supply terminal VDD2 is transmitted to the output terminal VOUT of the driver sub-circuit through the conduction path between the source and drain of the fourth transistor Q4, the second diode D4, and the eleventh resistor R11. Since the cathode of the second diode D4 is electrically connected to the drain of the fourth transistor Q4, and the anode of the second diode D4 is electrically connected to the output terminal VOUT of the driver sub-circuit through the eleventh resistor R11, and the voltage of the second power supply terminal VDD2 is negative, the anode potential of the second diode D4 is higher than the cathode potential, causing the second diode D4 to conduct in the forward direction. The second voltage output by the second level conversion circuit 2022 is equal to the voltage at the second power supply terminal VDD2 plus the forward voltage drop of the second diode D4 and the voltage drop across the eleventh resistor R11. Since the voltage at the second power supply terminal VDD2 is negative, the absolute value of the second voltage is equal to the absolute value of the voltage at the second power supply terminal VDD2 minus the forward voltage drop of the second diode D4 and the voltage drop across the eleventh resistor R11.

[0052] When the second control signal at the second control signal terminal GPIO2 is low, the voltage value of the second control signal is 0V, which is less than the reference voltage value of 1.8V. The voltage at the non-inverting input terminal (pin 3) of comparator U1 is lower than the voltage at the inverting input terminal (pin 2) of comparator U1, and the output terminal (pin 1) of comparator U1 outputs a low level. The low level at pin 1 of comparator U1 is transmitted to the gate of the third transistor Q3 through the sixth resistor R114, causing the third transistor Q3 to be turned off. When the third transistor Q3 is turned off, the drain of the third transistor Q3 presents a high impedance state with respect to the ground terminal GND. At this time, the second power supply terminal VDD2 provides voltage to the gate of the fourth transistor Q4 through the series circuit of the ninth resistor R5 and the eighth resistor R6. The ratio of the resistance values ​​of the ninth resistor R5 and the eighth resistor R6 determines the ratio of the gate voltage of the fourth transistor Q4 to the voltage of the second power supply terminal VDD2. By selecting appropriate resistance values ​​for the ninth resistor R5 and the eighth resistor R6, the gate voltage of the fourth transistor Q4 is made close to the voltage of the second power supply terminal VDD2, and the gate-source voltage of the fourth transistor Q4 is close to zero, thus turning off the fourth transistor Q4. When the fourth transistor Q4 is off, the second power supply terminal VDD2 is isolated from the second diode D4 through the high impedance between the source and drain of the fourth transistor Q4, and the second power supply terminal VDD2 cannot provide current to the output terminal VOUT of the driver sub-circuit. At this time, the second level conversion circuit 2022 stops outputting the second voltage.

[0053] In one embodiment of this application, the voltage value of the second power supply terminal VDD2 is -40V. The forward voltage drop of the second diode D4 is 0.7V. The resistance value of the eleventh resistor R11 is selected such that the voltage drop across the eleventh resistor R11 is less than 1V. At this time, the voltage value of the second voltage output by the second level conversion circuit 2022 is approximately -38V to -39V, which meets the requirement of the cholesteric liquid crystal display panel 10 for a negative driving voltage of approximately -40V.

[0054] In another embodiment of this application, the voltage value of the second power supply terminal VDD2 is in the range of -35V to -40V. By adjusting the voltage value of the second power supply terminal VDD2, the voltage value of the second voltage output by the second level conversion circuit 2022 is also adjusted accordingly to the range of approximately -34V to approximately -39V.

[0055] Table 1

[0056] Table 1 shows the output voltages of the first level conversion circuit 2021 and the second level conversion circuit 2022 under different control signal states. As shown in Table 1, when the first control signal of the first level conversion circuit 2021 is high, the first level conversion circuit 2021 outputs a first voltage; when the first control signal is low, the first level conversion circuit 2021 stops outputting, and the output voltage is zero. When the second control signal of the second level conversion circuit 2022 is high, the second level conversion circuit 2022 outputs a second voltage; when the second control signal is low, the second level conversion circuit 2022 stops outputting, and the output voltage is zero.

[0057] The first diode D3 and the second diode D4 in the first level conversion circuit 2021 and the second level conversion circuit 2022 serve to prevent reverse current flow. When the first level conversion circuit 2021 outputs the first voltage, the first diode D3 is forward-biased, and the first voltage is transmitted to the output terminal VOUT of the driver sub-circuit through the first diode D3. At this time, the voltage at the output terminal VOUT of the driver sub-circuit is positive. Since the anode of the second diode D4 is electrically connected to the output terminal VOUT of the driver sub-circuit through the eleventh resistor R11, and the cathode of the second diode D4 is electrically connected to the drain of the fourth transistor Q4, and the fourth transistor Q4 is in the off state, the anode potential of the second diode D4 is higher than the cathode potential of the second diode D4. In this case, the second diode D4 is in the reverse bias state and is cut off. The cutoff of the second diode D4 blocks the reverse current flow of the positive voltage at the output terminal VOUT of the driver sub-circuit to the second level conversion circuit 2022, avoiding damage to the fourth transistor Q4 and other devices in the second level conversion circuit 2022 caused by the first voltage.

[0058] When the second level conversion circuit 2022 outputs the second voltage, the second diode D4 is forward-biased, and the second voltage is transmitted to the output terminal VOUT of the driver sub-circuit through the second diode D4. At this time, the voltage at the output terminal VOUT of the driver sub-circuit is negative. Since the cathode of the first diode D3 is electrically connected to the output terminal VOUT of the driver sub-circuit through the fifth resistor R10, and the anode of the first diode D3 is electrically connected to the drain of the second transistor Q2, and the second transistor Q2 is in the off state, the cathode potential of the first diode D3 is lower than the anode potential of the first diode D3. In this case, the first diode D3 is in the reverse bias state and is cut off. The cutoff of the first diode D3 blocks the reverse flow of the negative voltage at the output terminal VOUT of the driver sub-circuit to the first level conversion circuit 2021, avoiding damage to the second transistor Q2 and other devices in the first level conversion circuit 2021 caused by the second voltage.

[0059] By setting a first diode D3 at the output terminal of the first level conversion circuit 2021 and a second diode D4 at the output terminal of the second level conversion circuit 2022, electrical isolation between the first level conversion circuit 2021 and the second level conversion circuit 2022 is achieved, thus avoiding mutual interference between the first voltage and the second voltage.

[0060] like Figure 2 As shown, the discharge circuit 2023 includes a fifth transistor Q5 and a third diode D2. The fifth transistor Q5 is an N-channel field-effect transistor. The gate of the fifth transistor Q5 is electrically connected to the discharge control signal terminal GPIO_DIS, the drain of the fifth transistor Q5 is electrically connected to the cathode of the third diode D2, and the source of the fifth transistor Q5 is electrically connected to the ground terminal GND. The anode of the third diode D2 is electrically connected to the cathode of the second diode D4.

[0061] When the first level conversion circuit 2021 outputs the first voltage, the voltage at the output terminal VOUT of the driver sub-circuit is positive. When the first control signal at the first control signal terminal GPIO1 changes from high to low, the first level conversion circuit 2021 stops outputting the first voltage. At this time, the parasitic capacitance formed between the output terminal VOUT of the driver sub-circuit and the pixel electrode of the display panel 10 still stores charge. The voltage at the output terminal VOUT of the driver sub-circuit does not immediately drop to zero, but rather decreases slowly through the natural discharge process of the parasitic capacitance. To accelerate the speed at which the voltage at the output terminal VOUT of the driver sub-circuit drops to zero, the discharge circuit 2023 is turned on after the first control signal at the first control signal terminal GPIO1 changes from high to low, quickly releasing the residual charge at the output terminal VOUT of the driver sub-circuit to the ground terminal GND.

[0062] When the discharge control signal GPIO_DIS is high, the fifth transistor Q5 is turned on. At this time, the positive voltage at the output terminal VOUT of the driver sub-circuit is transmitted to the drain of the fourth transistor Q4 through the eleventh resistor R11 and the forward-conducting second diode D4. Since the fourth transistor Q4 is in the off state, there is a high impedance between the drain of the fourth transistor Q4 and the second power supply terminal VDD2. The positive voltage at the drain of the fourth transistor Q4 is quickly discharged to the ground terminal GND through the forward-conducting third diode D2 and the turned-on fifth transistor Q5. During the discharge process, the residual charge at the output terminal VOUT of the driver sub-circuit is released to the ground terminal GND through the discharge path formed by the eleventh resistor R11, the second diode D4, the third diode D2, and the fifth transistor Q5, and the voltage at the output terminal VOUT of the driver sub-circuit quickly drops to zero.

[0063] The third diode D2 acts as a unidirectional conductor in the discharge circuit 2023. The arrangement of the third diode D2 ensures that the discharge circuit 2023 conducts only when the voltage at the output terminal VOUT of the driving sub-circuit is positive, and is cut off when the voltage at VOUT is negative or zero. When the voltage at the output terminal VOUT of the driving sub-circuit is positive, the anode potential of the third diode D2 is higher than its cathode potential, and the third diode D2 conducts in the forward direction. When the voltage at the output terminal VOUT of the driving sub-circuit is negative or zero, the anode potential of the third diode D2 is lower than or equal to its cathode potential, and the third diode D2 is cut off. The unidirectional conduction characteristic of the third diode D2 ensures that the discharge circuit 2023 only operates when it needs to release residual positive voltage charge, avoiding interference from the discharge circuit 2023 to the output voltage of the second level conversion circuit 2022.

[0064] While the first control signal at the first control signal terminal GPIO1 is high, the discharge control signal GPIO_DIS is low, the fifth transistor Q5 is off, and the discharge circuit 2023 does not operate. After the first control signal at the first control signal terminal GPIO1 transitions from high to low, the discharge control signal GPIO_DIS becomes high to ensure that the residual charge at the output terminal VOUT of the driver sub-circuit is completely released to the ground terminal GND. After the discharge phase ends, the discharge control signal GPIO_DIS returns to low, the fifth transistor Q5 is off, and the discharge circuit 2023 stops operating.

[0065] like Figure 3 As shown, in one embodiment of this application, the driving circuit 20 includes multiple sets of driving sub-circuits. The output terminals VOUT of the multiple sets of driving sub-circuits are connected in parallel and electrically connected to the same output trace, and the multiple sets of driving sub-circuits jointly provide driving signals to the same output trace. The output trace is electrically connected to the data line DL or gate line GL of the display panel 10. The first power supply terminal of the first level conversion circuit 2021 of different sets of driving sub-circuits is electrically connected to a positive power supply with different voltage values, and the second power supply terminal of the second level conversion circuit 2022 of different sets of driving sub-circuits is electrically connected to a negative power supply with different voltage values. By controlling the first control signal or the second control signal of different sets of driving sub-circuits to be high at different times, multiple first voltages and second voltages with different voltage values ​​are output on the same output trace.

[0066] The multiple driver sub-circuits include a first group of driver sub-circuits and a second group of driver sub-circuits. The first power supply terminal of the first level conversion circuit 2021 of the first group of driver sub-circuits is electrically connected to a first positive power supply, the voltage of which is in the range of 35V to 40V. The second power supply terminal of the second level conversion circuit 2022 of the first group of driver sub-circuits is electrically connected to a first negative power supply, the voltage of which is in the range of -35V to -40V. The first power supply terminal of the first level conversion circuit 2021 of the second group of driver sub-circuits is electrically connected to a second positive power supply, the voltage of which is in the range of 18V to 25V. The second power supply terminal of the second level conversion circuit 2022 of the second group of driver sub-circuits is electrically connected to a second negative power supply, the voltage of which is in the range of -18V to -25V.

[0067] The output terminals VOUT of the first and second driver sub-circuits are electrically connected to the output traces via their respective first diodes D3 and D4. When the first control signal of the first driver sub-circuit is high, the first level conversion circuit 2021 of the first driver sub-circuit outputs a voltage of 35V to 40V. At this time, the first diode D3 of the first driver sub-circuit is forward-biased, and the first voltage output by the first driver sub-circuit is transmitted to the output traces through the first diode D3. Since the first control signal of the second driver sub-circuit is low, the first level conversion circuit 2021 of the second driver sub-circuit stops outputting the first voltage, and the first diode D3 of the second driver sub-circuit is reverse-biased and cut off. The cutoff of the first diode D3 of the second driver sub-circuit blocks the reverse flow of the high voltage from the output traces to the second driver sub-circuit.

[0068] When the second control signal of the first group of driver sub-circuits is high, the second level conversion circuit 2022 of the first group of driver sub-circuits outputs a second voltage of -35V to -40V. At this time, the second diode D4 of the first group of driver sub-circuits is forward-biased, and the second voltage output by the first group of driver sub-circuits is transmitted to the output trace through the second diode D4. Since the second control signal of the second group of driver sub-circuits is low, the second level conversion circuit 2022 of the second group of driver sub-circuits stops outputting the second voltage, and the second diode D4 of the second group of driver sub-circuits is reverse-biased and cut off. The cutoff of the second diode D4 of the second group of driver sub-circuits blocks the reverse flow of negative voltage from the output trace to the second group of driver sub-circuits.

[0069] When the first control signal of the second group of driver sub-circuits is high, the first level conversion circuit 2021 of the second group of driver sub-circuits outputs a first voltage of 18V to 25V. At this time, the first diode D3 of the second group of driver sub-circuits is forward-biased, and the first voltage output by the second group of driver sub-circuits is transmitted to the output trace through the first diode D3. Since the first control signal of the first group of driver sub-circuits is low, the first level conversion circuit 2021 of the first group of driver sub-circuits stops outputting the first voltage, and the first diode D3 of the first group of driver sub-circuits is reverse-biased and cut off.

[0070] When the second control signal of the second group of driver sub-circuits is high, the second level conversion circuit 2022 of the second group of driver sub-circuits outputs a second voltage of -18V to -25V. At this time, the second diode D4 of the second group of driver sub-circuits is forward-biased, and the second voltage output by the second group of driver sub-circuits is transmitted to the output trace through the second diode D4. Since the second control signal of the first group of driver sub-circuits is low, the second level conversion circuit 2022 of the first group of driver sub-circuits stops outputting the second voltage, and the second diode D4 of the first group of driver sub-circuits is reverse-biased and cut off.

[0071] When the first control signal of the first group of driving sub-circuits or the second group of driving sub-circuits changes from high level to low level, the discharge control signal corresponding to the first group of driving sub-circuits or the second group of driving sub-circuits becomes high level, causing the discharge circuit 2023 of the first group of driving sub-circuits or the second group of driving sub-circuits to be turned on. The residual positive charge of the output trace is quickly released to the ground terminal GND through the discharge circuit 2023, and the voltage of the output trace is reduced to zero voltage.

[0072] By connecting multiple sets of driver sub-circuits in parallel, the switching of output voltage values ​​from 35V to 40V (positive voltage), -35V to -40V (negative voltage), 18V to 25V (positive voltage), -18V to -25V (negative voltage), and zero voltage is achieved on the same output line.

[0073] Embodiments of this application also provide a driving method for a display device. The display device includes a display panel 10 and a driving circuit 20. The driving circuit 20 includes at least one set of driving sub-circuits, which include a first level conversion circuit 2021, a second level conversion circuit 2022, and a discharge circuit 2023. This driving method achieves switching of the voltage at the output terminal VOUT of the driving sub-circuit between a first voltage, a second voltage, and zero voltage by controlling the timing of a first control signal, a second control signal, and a discharge control signal.

[0074] The driving method includes the following steps: When the first control signal is high, the first level conversion circuit 2021 outputs the first voltage to the output terminal VOUT of the driver sub-circuit.

[0075] When the second control signal is high, the second level conversion circuit 2022 outputs the second voltage to the output terminal VOUT of the driver sub-circuit.

[0076] After the first control signal changes from high level to low level, the discharge circuit 2023 is turned on by the discharge control signal. The discharge circuit 2023 releases the voltage of the output terminal VOUT of the drive sub-circuit to the ground terminal potential.

[0077] This driving method also includes: When the first control signal is set to a low level, the first level conversion circuit 2021 stops outputting the first voltage; and when the second control signal is set to a low level, the second level conversion circuit 2022 stops outputting the second voltage.

[0078] Within a complete driving cycle, the driving method controls the level states of the first control signal, the second control signal, and the discharge control signal according to a predetermined timing sequence, causing the output terminal VOUT of the driving sub-circuit to sequentially output a first voltage, a second voltage, zero voltage, a first voltage, a second voltage, and zero voltage. By adjusting the duration of each voltage output stage, the timing sequence of the driving waveform can be flexibly controlled.

[0079] In one embodiment of this application, the driving circuit 20 includes a first set of driving sub-circuits and a second set of driving sub-circuits, with the output terminals VOUT of the first set of driving sub-circuits and the second set of driving sub-circuits connected in parallel. For example... Figure 4 As shown, the driving method includes a first voltage and a second voltage with different voltage values ​​output by the output traces that are electrically connected to the output terminals VOUT of multiple sets of driving sub-circuits at different times when the first control signal or the second control signal of different sets of driving sub-circuits is at a high level.

[0080] During the first time period P1, the second control signal of the second control signal terminal GPIO2 of the first group of driver sub-circuits is at a high level, the first control signal of the first control signal terminal GPIO1 of the first group of driver sub-circuits is at a low level, the first control signal of the first control signal terminal GPIO3 of the second group of driver sub-circuits is at a low level, and the second control signal of the second control signal terminal GPIO4 of the second group of driver sub-circuits is at a low level. At this time, the output voltage of the second level conversion circuit 2022 of the first group of driver sub-circuits is a second voltage ranging from -35V to -40V, which is sent to the output trace. The voltage of the data signal output by the output trace is -35V. The duration of the first time period P1 is 10ms.

[0081] During the second time period P2, the first control signal of the first control signal terminal GPIO1 of the first group of driver sub-circuits is at a high level, the second control signal of the second control signal terminal GPIO2 of the first group of driver sub-circuits is at a low level, the first control signal of the first control signal terminal GPIO3 of the second group of driver sub-circuits is at a low level, and the second control signal of the second control signal terminal GPIO4 of the second group of driver sub-circuits is at a low level. At this time, the output voltage of the first level conversion circuit 2021 of the first group of driver sub-circuits is a first voltage of 35V to 40V, which is sent to the output trace, and the voltage of the data signal output by the output trace is 35V. The duration of the second time period P2 is 10ms.

[0082] During the third time period P3, the first control signal of the first control signal terminal GPIO1 of the first group of driver sub-circuits is low, the second control signal of the second control signal terminal GPIO2 of the first group of driver sub-circuits is low, the first control signal of the first control signal terminal GPIO3 of the second group of driver sub-circuits is low, and the second control signal of the second control signal terminal GPIO4 of the second group of driver sub-circuits is low. During the third time period P3, the discharge control signal of the first group of driver sub-circuits is high, causing the discharge circuit 2023 of the first group of driver sub-circuits to conduct, and the residual positive voltage of the output trace is quickly released to zero voltage. Throughout the third time period P3, the voltage of the data signal output by the output trace is 0V. The duration of the third time period P3 is 20ms.

[0083] During the fourth time period P4, the first control signal of the first control signal terminal GPIO1 of the first group of driver sub-circuits is low, the second control signal of the second control signal terminal GPIO2 of the first group of driver sub-circuits is low, the second control signal of the second control signal terminal GPIO4 of the second group of driver sub-circuits is high, and the first control signal of the first control signal terminal GPIO3 of the second group of driver sub-circuits is low. At this time, the output voltage of the second level conversion circuit 2022 of the second group of driver sub-circuits is a second voltage ranging from -18V to -25V, which is sent to the output trace. The voltage of the data signal output by the output trace is -21V. The duration of the fourth time period P4 is 10ms.

[0084] During the fifth time period P5, the first control signal of the first control signal terminal GPIO1 of the first group of driver sub-circuits is low, the second control signal of the second control signal terminal GPIO2 of the first group of driver sub-circuits is low, the first control signal of the first control signal terminal GPIO3 of the second group of driver sub-circuits is high, and the second control signal of the second control signal terminal GPIO4 of the second group of driver sub-circuits is low. At this time, the output voltage of the first level conversion circuit 2021 of the second group of driver sub-circuits is a first voltage of 18V to 25V, which is sent to the output trace, and the voltage of the data signal output by the output trace is 21V. The duration of the fifth time period P5 is 10ms.

[0085] During the sixth time period P6, the first control signal of the first control signal terminal GPIO1 of the first group of driver sub-circuits is low, the second control signal of the second control signal terminal GPIO2 of the first group of driver sub-circuits is low, the first control signal of the first control signal terminal GPIO3 of the second group of driver sub-circuits is low, and the second control signal of the second control signal terminal GPIO4 of the second group of driver sub-circuits is low. During the sixth time period P6, the discharge control signal of the second group of driver sub-circuits is high, causing the discharge circuit 2023 of the second group of driver sub-circuits to conduct, and the residual positive voltage of the output trace is quickly released to zero voltage. Throughout the sixth time period P6, the voltage of the data signal output by the output trace is 0V. The duration of the sixth time period P6 is 20ms.

[0086] like Figure 4 As shown, during the first time period P1 and the second time period P2, the first control signal GPIO5 of the gate signal driving sub-circuit is high, and the second control signal GPIO6 is low, resulting in an output gate signal voltage of 40V. During the third time period P3, the first control signal GPIO5 is low, and the second control signal GPIO6 is high, resulting in an output gate signal voltage of -25V. During the fourth time period P4 and the fifth time period P5, the first control signal GPIO5 is high, and the second control signal GPIO6 is low, resulting in an output gate signal voltage of 40V. During the sixth time period P6, the first control signal GPIO5 is low, and the second control signal GPIO6 is high, resulting in an output gate signal voltage of -25V.

[0087] The above six time periods constitute a complete driving cycle, with a total duration of 80ms. By periodically repeating the control timing of the above six time periods, continuous driving of the cholesteric liquid crystal display panel is achieved.

[0088] By adjusting the duration of the first time period P1 to the sixth time period P6, the timing of the driving waveform can be flexibly controlled. By adjusting the voltage values ​​of the first positive power supply, the first negative power supply, the second positive power supply, and the second negative power supply, the voltage characteristics of the driving waveform can be flexibly controlled.

[0089] The technical solution of this application, by setting a first level conversion circuit 2021, a second level conversion circuit 2022, and a discharge circuit 2023 in the driving sub-circuit, enables the driving circuit 20 to output a first voltage according to a first control signal, output a second voltage according to a second control signal, and release the voltage at the output terminal VOUT of the driving sub-circuit to the ground potential according to the discharge control signal. Since the first level conversion circuit 2021 and the second level conversion circuit 2022 independently output corresponding voltages to the output terminal VOUT of the driving sub-circuit according to their respective control signals, and the discharge circuit 2023 releases the voltage at the output terminal VOUT of the driving sub-circuit to the ground potential, the driving sub-circuit outputs different voltage values—positive, negative, or zero—at different times. By adjusting the timing of the first control signal, the second control signal, and the discharge control signal, flexible switching between positive, negative, and zero voltages is achieved, and the duration of each voltage can be flexibly controlled.

[0090] By setting a first diode D3 and a second diode D4 at the output terminals of the first level conversion circuit 2021 and the second level conversion circuit 2022 respectively, when the first level conversion circuit 2021 outputs a first voltage, the first diode D3 is forward-biased and the second diode D4 is reverse-biased and cut off, thereby preventing the first voltage from flowing back into the second level conversion circuit 2022; when the second level conversion circuit 2022 outputs a second voltage, the second diode D4 is forward-biased and the first diode D3 is reverse-biased and cut off, thereby preventing the second voltage from flowing back into the first level conversion circuit 2021.

[0091] When the drive circuit 20 includes multiple sets of drive sub-circuits, and the output terminals VOUT of the multiple sets of drive sub-circuits are connected in parallel, the first power supply terminal of the first level conversion circuit 2021 of different sets of drive sub-circuits is electrically connected to a positive power supply with a different voltage value, and the second power supply terminal of the second level conversion circuit 2022 of different sets of drive sub-circuits is electrically connected to a negative power supply with a different voltage value. By controlling the first control signal or the second control signal of different sets of drive sub-circuits to be high at different times, the output traces electrically connected to the output terminals VOUT of the multiple sets of drive sub-circuits output first and second voltages with different voltage values.

[0092] The technical solution of this application adopts a level conversion circuit composed of discrete components such as transistors and diodes, which reduces development costs and shortens the development cycle compared to custom-designed dedicated driver chips. By adjusting the voltage values ​​of the power supplies electrically connected to the first and second power supply terminals, as well as adjusting the timing parameters of the first control signal, the second control signal, and the discharge control signal, the voltage values ​​and timing of the drive signals can be flexibly adjusted.

[0093] like Figure 5 As shown, the voltage value and timing of the drive waveform output by the drive circuit 20 of this application were verified by oscilloscope testing. In one test example, the voltage value of the first positive power supply was set to 40V, and the voltage value of the first negative power supply was set to -40V. By controlling the first control signal of the first control signal terminal GPIO1 and the second control signal terminal GPIO2 of the first group of drive sub-circuits, the highest positive voltage measured by the output trace was 40.00V, and the lowest negative voltage measured was -40.00V. The test results show that the drive circuit 20 of this application successfully achieved a symmetrical high-voltage drive output of ±40V.

[0094] like Figure 6 As shown, in another test example, an asymmetrical positive and negative power supply was configured, with the first positive power supply voltage set to 35.2V and the first negative power supply voltage set to -20V. Test results show that the measured positive high voltage output from the output trace is 35.20V, and the measured negative voltage is -20.00V. The test results demonstrate that the drive circuit 20 of this application can flexibly adapt to the switching requirements of different positive and negative high voltage values.

[0095] The embodiments of this application have been described in detail above. The content of this specification should not be construed as limiting the scope of protection of this application.

Claims

1. A display device, characterized in that, The display device includes a display panel and a driving circuit. The driving circuit is electrically connected to the display panel. The driving circuit includes at least one set of driving sub-circuits, and one set of driving sub-circuits includes: A first level conversion circuit is configured to output a first voltage to the output terminal of the driving sub-circuit according to a first control signal; A second level conversion circuit, configured to output a second voltage to the output terminal of the driving sub-circuit according to a second control signal; and A discharge circuit is configured to release the voltage at the output of the drive sub-circuit to the ground potential according to a discharge control signal.

2. The display device according to claim 1, characterized in that, The first level conversion circuit includes a first transistor, a second transistor, and a first diode. The gate of the first transistor is electrically connected to a first control signal terminal, the source of the first transistor is electrically connected to a ground terminal, the drain of the first transistor is electrically connected to the gate of the second transistor, the source of the second transistor is electrically connected to a first power supply terminal, the anode of the first diode is electrically connected to the drain of the second transistor, and the cathode of the first diode is electrically connected to the output terminal of the driving sub-circuit.

3. The display device according to claim 2, characterized in that, The first level conversion circuit further includes a first resistor, a second resistor, a third resistor, a thirteenth resistor, and a first capacitor. The first end of the first resistor is electrically connected to the drain of the first transistor. The first end of the second resistor is electrically connected to the first power supply terminal. The second end of the first resistor is electrically connected to the gate of the second transistor. The third resistor is electrically connected between the drain of the second transistor and the ground terminal. The thirteenth resistor is electrically connected between the first control signal terminal and the gate of the first transistor. The first plate of the first capacitor is electrically connected to the gate of the second transistor. The second plate of the first capacitor is electrically connected to the ground terminal.

4. The display device according to claim 2, characterized in that, The driving sub-circuit also includes a fifth resistor; The cathode of the first diode is electrically connected to the output terminal of the driving sub-circuit through the fifth resistor.

5. The display device according to claim 1, characterized in that, The second level conversion circuit includes a comparator, a third transistor, a fourth transistor, and a second diode. The non-inverting input of the comparator is electrically connected to the second control signal terminal, the inverting input of the comparator is electrically connected to the reference voltage terminal, the positive power supply terminal of the comparator is electrically connected to the third power supply terminal, the negative power supply terminal of the comparator is electrically connected to the fourth power supply terminal, the gate of the third transistor is electrically connected to the output terminal of the comparator, the source of the third transistor is electrically connected to the ground terminal, the drain of the third transistor is electrically connected to the gate of the fourth transistor, the source of the fourth transistor is electrically connected to the second power supply terminal, the cathode of the second diode is electrically connected to the drain of the fourth transistor, and the anode of the second diode is electrically connected to the output terminal of the driving sub-circuit.

6. The display device according to claim 5, characterized in that, The second level conversion circuit further includes a fourth resistor, an eighth resistor, a ninth resistor, and a second capacitor. The fourth resistor is electrically connected between the drain of the fourth transistor and the ground terminal. The first end of the eighth resistor is electrically connected to the drain of the third transistor, and the second end of the eighth resistor is electrically connected to the gate of the fourth transistor. The first end of the ninth resistor is electrically connected to the second power supply terminal, and the second end of the ninth resistor is electrically connected to the gate of the fourth transistor. The first plate of the second capacitor is electrically connected to the gate of the fourth transistor, and the second plate of the second capacitor is electrically connected to the ground terminal.

7. The display device according to claim 5, characterized in that, The driving sub-circuit also includes an eleventh resistor; The anode of the second diode is electrically connected to the output terminal of the driving sub-circuit through the eleventh resistor.

8. The display device according to claim 5, characterized in that, The discharge circuit includes a fifth transistor and a third diode. The gate of the fifth transistor is electrically connected to the discharge control signal terminal, the source of the fifth transistor is electrically connected to the ground terminal, the drain of the fifth transistor is electrically connected to the cathode of the third diode, and the anode of the third diode is electrically connected to the cathode of the second diode.

9. The display device according to claim 1, characterized in that, The driving circuit includes multiple sets of driving sub-circuits, the output terminals of the multiple sets of driving sub-circuits are connected in parallel, the first power supply terminal of the first level conversion circuit of different sets of driving sub-circuits is electrically connected to a positive power supply with a different voltage value, and the second power supply terminal of the second level conversion circuit of different sets of driving sub-circuits is electrically connected to a negative power supply with a different voltage value.

10. The display device according to claim 9, characterized in that, The multiple sets of driving sub-circuits include a first set of driving sub-circuits and a second set of driving sub-circuits. The first power supply terminal of the first level conversion circuit of the first set of driving sub-circuits is electrically connected to a first positive power supply, the voltage of which is 35V to 40V. The second power supply terminal of the second level conversion circuit of the first set of driving sub-circuits is electrically connected to a first negative power supply, the voltage of which is -35V to -40V. The first power supply terminal of the first level conversion circuit of the second group of driving sub-circuits is electrically connected to the second positive power supply, the voltage of the second positive power supply being 18V to 25V. The second power supply terminal of the second level conversion circuit of the second group of driving sub-circuits is electrically connected to the second negative power supply, the voltage of the second negative power supply being -18V to -25V.

11. A driving method for a display device, characterized in that, The display device includes a display panel and a driving circuit. The driving circuit includes at least one set of driving sub-circuits, and the driving sub-circuit includes a first level conversion circuit, a second level conversion circuit, and a discharge circuit. The driving method includes: When the first control signal is high, the first level conversion circuit outputs a first voltage to the output terminal of the driving sub-circuit; When the second control signal is high, the second level conversion circuit outputs a second voltage to the output terminal of the driving sub-circuit; After the first control signal changes from high level to low level, the discharge circuit is turned on by the discharge control signal, and the discharge circuit releases the voltage at the output terminal of the drive sub-circuit to the ground terminal potential.

12. The driving method according to claim 11, characterized in that, The driving method further includes: When the first control signal is set to a low level, the first level conversion circuit stops outputting the first voltage; and When the second control signal is set to a low level, the second level conversion circuit stops outputting the second voltage.

13. The driving method according to claim 11, characterized in that, The driving circuit includes multiple sets of driving sub-circuits, the output terminals of the multiple sets of driving sub-circuits are connected in parallel, and the driving method further includes: At different times, the first or second control signal of different groups of driving sub-circuits is at a high level, and the output traces electrically connected to the output terminals of multiple groups of driving sub-circuits output first and second voltages with different voltage values.

14. The driving method according to claim 13, characterized in that, The output traces electrically connected to the output terminals of the multiple sets of driving sub-circuits output different voltage values, including: During the first time period, the second control signal of the first group of driving sub-circuits is at a high level, and the output voltage of the output trace is a second voltage of -35V to -40V; During the second time period, the first control signal of the first group of driving sub-circuits is at a high level, and the output voltage value of the output trace is a first voltage of 35V to 40V. During the third time period, the discharge control signal of the first group of driving sub-circuits is at a high level, and the output trace outputs zero voltage. During the fourth time period, the second control signal of the second group of driving sub-circuits is at a high level, and the output voltage of the output trace is a second voltage of -18V to -25V; During the fifth time period, the first control signal of the second group of driving sub-circuits is at a high level, and the output voltage value of the output trace is a first voltage of 18V to 25V; and During the sixth time period, the discharge control signal of the second group of driving sub-circuits is at a high level, and the output trace outputs zero voltage.

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