Memory stick slt testing method, apparatus, device, and medium

Abstract

The memory SLT test method, device, equipment and medium provided by the embodiments of the present disclosure comprise: in response to receiving a test instruction signal selected by a target object, configuring a burst length parameter in a unit test period; executing an SLT test sequence under the burst length parameter, and obtaining a test report of a memory bank under the test instruction signal, wherein the SLT test sequence comprises a function verification test sequence, a stress stability test sequence and a timing calibration test sequence, and the test report comprises test data, performance index data, error log data and power consumption data; and determining a fault occurrence rate of the memory bank under the test instruction signal according to the test report. Under the DDR5 standard, the SLT tester not only supports the test of the BL16 mode, but also supports the test of the BL8 mode and the switching mode of the BL16 and BL8, greatly expanding the test coverage range and depth of the DDR5 memory bank, so that potential stability problems and performance bottlenecks can be found more comprehensively and accurately, and the effectiveness of the test is improved.

Description

Technical Field

[0001] This invention relates to the field of memory module technology and related technical fields, specifically to a memory module SLT testing method, apparatus, device, and medium. Background Technology

[0002] System Level Testing (SLT) is a crucial step in ensuring the performance and stability of DRAM modules. SLT testing simulates various operating conditions, including different frequencies, timing parameters, and data transfer modes. Burst Length (BL) is an important parameter in DRAM, defining the actual number of data bits transferred during each data transfer request (e.g., after a CAS Latency trigger). Common Burst Lengths are BL8 and BL16.

[0003] Currently, DDR5 memory technology, as a new generation memory standard, offers significant improvements in performance and efficiency compared to DDR4. The DDR5 standard introduces a more flexible Burst Length (BL) mode, supporting not only the traditional BL8 but also BL16, and theoretically even BL32. Burst Length refers to the length of data read or written by the memory controller from or to the memory chip in a single access request, measured in DDR clock cycles. BL16 mode allows for the transfer of more data at once, theoretically increasing the effective bandwidth of the memory, reducing the overhead of each data transfer, and thus improving overall system performance.

[0004] In System-Level Testing (SLT) of memory modules, verifying their stability and performance across various operating modes is crucial. The Burst Length mode of a memory module is one of the key parameters affecting its performance and stability. Existing SLT testing methodologies typically target specific Burst Length modes, such as operating the memory in BL16 mode for full functionality and stability testing. However, for DDR5 memory, testing only a single BL mode (such as BL8 or BL16) may not fully cover its performance characteristics and potential compatibility issues. In particular, in certain application scenarios, it may be necessary to dynamically adjust the BL mode according to specific needs to achieve optimal results. Therefore, how to effectively and flexibly test and verify the Burst Length mode of DDR5 memory modules in SLT testing to fully explore their performance potential and ensure their stability has become a pressing issue. Summary of the Invention

[0005] The embodiments described herein provide a method, apparatus, device, and medium for SLT testing of memory modules, addressing the problems existing in the prior art.

[0006] Firstly, based on the content of this disclosure, a method for SLT testing of memory modules is provided, including:

[0007] In response to receiving a test instruction signal for target object selection, a burst length parameter is configured within the unit test cycle, wherein the burst length parameter includes 16 bytes and 8 bytes;

[0008] The SLT test sequence is executed under the burst length parameter, and the test report of the memory module under the test instruction signal is obtained. The SLT test sequence includes a functional verification test sequence, a stress stability test sequence, and a timing calibration test sequence. The test report includes test data, performance index data, error log data, and power consumption data.

[0009] The failure rate of the memory module under the test command signal is determined based on the test report.

[0010] In some embodiments of this disclosure, configuring the burst length parameter within a unit test cycle in response to receiving a test instruction signal for target object selection includes:

[0011] In response to receiving a test instruction signal for selecting a target object, the target test mode corresponding to the test instruction signal is obtained, wherein the target test mode includes at least BL16 mode and BL8 mode;

[0012] According to the target test mode, the burst length parameter is configured within the unit test cycle. Specifically, when the target test mode is BL16 mode, the burst length parameter is configured to be 16 bytes, and when the target test mode is BL8 mode, the burst length parameter is configured to be 8 bytes.

[0013] In some embodiments of this disclosure, the target test mode further includes a BL16 and BL8 switching mode;

[0014] The method further includes:

[0015] Based on the test command signal, determine the BL16 mode sub-cycle and BL8 mode sub-cycle within the unit test cycle;

[0016] The step of configuring burst length parameters within the unit test cycle according to the target test mode includes:

[0017] When the target test mode is BL16 and BL8 switching mode, the burst length parameter is configured to 16 bytes in the BL16 mode sub-cycle of the unit test cycle, and the burst length parameter is configured to 8 bytes in the BL8 mode sub-cycle of the unit test cycle.

[0018] In some embodiments of this disclosure, when the target test mode is a BL16 and BL8 switching mode, configuring the burst length parameter to 16 bytes in the BL16 mode sub-cycle of the unit test cycle and configuring the burst length parameter to 8 bytes in the BL8 mode sub-cycle of the unit test cycle includes:

[0019] When the target test mode is the BL16 and BL8 switching mode, the switching mode and switching time node are determined according to the switching command signal included in the test command signal;

[0020] Based on the switching time node, determine the BL16 mode sub-cycle and the BL8 mode sub-cycle in the unit test cycle;

[0021] When the switching mode is the first switching mode, the burst length parameter of the BL16 mode sub-cycle before the switching time node is configured to be 16 bytes, and the burst length parameter of the BL8 mode sub-cycle after the switching time node is configured to be 8 bytes.

[0022] When the switching mode is the second switching mode, the burst length parameter of the BL8 mode sub-cycle before the switching time node is configured to be 8 bytes, and the burst length parameter of the BL16 mode sub-cycle after the switching time node is configured to be 16 bytes.

[0023] In some embodiments of this disclosure, the step of executing the SLT test sequence under the burst length parameter and obtaining the test report of the memory module under the test instruction signal includes:

[0024] Obtain the target number of SLT test sequences included in the test instruction signal;

[0025] Execute a target number of SLT test sequences under the burst length parameter, and sequentially obtain sub-test reports of the memory module under different SLT test sequences;

[0026] Based on the sub-test reports of the memory module under different SLT test sequences, determine the test report of the memory module under the test instruction signal.

[0027] In some embodiments of this disclosure, determining the failure rate of the memory module under the test instruction signal based on the test report includes:

[0028] The fault type and location of the memory module under the test command signal are determined based on the test report.

[0029] Based on the fault type and fault location, determine the fault occurrence rate of the memory module at the same fault location and the fault occurrence rate of the memory module under different fault types.

[0030] In some embodiments of this disclosure, the method further includes:

[0031] Obtain the failure rate of the memory module under different test command signals;

[0032] The stability of the memory module is determined based on the failure rate of the memory module under different test command signals.

[0033] Secondly, according to the present disclosure, a memory module SLT testing apparatus is provided, comprising:

[0034] The parameter configuration module is used to configure burst length parameters within the unit test cycle in response to receiving a test instruction signal for target object selection, wherein the burst length parameters include 16 bytes and 8 bytes;

[0035] The test report acquisition module is used to execute the SLT test sequence under the burst length parameter and acquire the test report of the memory module under the test instruction signal. The SLT test sequence includes a functional verification test sequence, a stress stability test sequence, and a timing calibration test sequence. The test report includes test data, performance index data, error log data, and power consumption data.

[0036] The failure rate determination module is used to determine the failure rate of the memory module under the test instruction signal based on the test report.

[0037] Thirdly, according to the present disclosure, a computer device is provided, comprising:

[0038] One or more processors;

[0039] Storage device for storing one or more programs.

[0040] When the one or more programs are executed by the one or more processors, the one or more processors implement the method as described in any of the first aspects.

[0041] Fourthly, according to the present disclosure, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the methods described in any of the first aspects.

[0042] The memory module SLT testing method, apparatus, device, and medium provided in this disclosure first configure burst length parameters within a unit test cycle in response to receiving a test instruction signal for target object selection; then, an SLT test sequence is executed under the burst length parameters, and a test report of the memory module under the test instruction signal is obtained. The SLT test sequence includes a functional verification test sequence, a stress stability test sequence, and a timing calibration test sequence. The test report includes test data, performance index data, error log data, and power consumption data. Finally, the failure rate of the memory module under the test instruction signal is determined based on the test report. First, based on the correspondence between test command signals and test modes, the target test mode corresponding to the test command signal is determined. Then, the burst length parameters of the SLT test machine are configured to execute the SLT test sequence under the burst length parameters. Under the DDR5 standard, the SLT test machine not only supports BL16 mode testing, but also can effectively perform BL8 mode testing and BL16 and BL8 switching mode testing. On the one hand, it greatly expands the test coverage and depth of DDR5 memory modules, thereby more comprehensively and accurately discovering potential stability problems and performance bottlenecks and improving the effectiveness of testing. On the other hand, it can achieve testing under different burst length parameters without reloading the entire test process, improving the testing efficiency of memory modules.

[0043] The above description is merely an overview of the technical solutions of the embodiments of this application. In order to better understand the technical means of the embodiments of this application and to implement them in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the embodiments of this application more obvious and understandable, specific implementation methods of this application are described below. Attached Figure Description

[0044] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0045] Figure 1 This is a flowchart illustrating a memory module SLT testing method provided in an embodiment of this disclosure;

[0046] Figure 2 This is a schematic diagram of the structure of a memory module SLT testing device provided in an embodiment of this disclosure;

[0047] Figure 3 This is a schematic diagram of the structure of a computer device provided in an embodiment of this disclosure.

[0048] In the accompanying diagram, markers with the same last two digits correspond to the same elements. It should be noted that the elements in the diagram are schematic and not drawn to scale. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0050] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0051] The term "embodiment" as used herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of the phrase "embodiment" in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0052] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists, A and B exist simultaneously, or B exists. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0053] Furthermore, in all embodiments of this disclosure, terms such as “first” and “second” are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0054] In the description of this application, unless otherwise stated, "multiple" means two or more (including two), and similarly, "multiple groups" means two or more (including two groups).

[0055] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0056] Based on the problems existing in the prior art, this disclosure provides a method for SLT testing of memory modules. Figure 1 This is a flowchart illustrating a memory module SLT testing method provided in an embodiment of this disclosure, as shown below. Figure 1 As shown, the specific process of the SLT test method for memory modules includes:

[0057] S110. In response to receiving the test instruction signal for the target object selection, configure the burst length parameter within the unit test cycle.

[0058] The burst length parameter includes 16 bytes and 8 bytes.

[0059] Burst Length (BL) refers to the number of data words actually transmitted in a single data transmission request (such as after CAS Latency). For example, BL8 indicates that 8 bytes of data are transmitted each time, and BL16 indicates that 16 bytes of data are transmitted each time.

[0060] The SLT testing method for memory modules provided in this disclosure is applied to DDR5 memory modules. Since DDR5 memory modules support BL8 and BL16, and some even support BL32, existing DDR5 memory module testing methods require configuring burst length parameters separately to test the failure probability of the memory module under a 16-byte burst length parameter and the failure probability of the memory module under an 8-byte burst length parameter. The testing processes under different burst length parameters are independent and cannot be switched. Therefore, the entire testing process needs to be reloaded under different testing modes, reducing the efficiency of memory module testing.

[0061] Based on the problems existing in the prior art, the SLT test method for memory modules provided in this disclosure embodiment can realize the testing of memory modules under different byte burst length parameters. In a single round of SLT test, the test mode is switched to "BL16 mode", "BL8 mode" or "BL16 and BL8 switching mode" according to the test instruction signal selected by the target object.

[0062] Specifically, by configuring the corresponding burst length parameters based on the test instruction signal selected for the target object, the memory module can be tested in different test modes without reloading the entire test process, thus improving the efficiency of memory module testing and filling the gap in existing technology in this area.

[0063] In one specific implementation, in response to receiving a test instruction signal for selecting a target object, configuring a burst length parameter within a unit test cycle includes: in response to receiving a test instruction signal for selecting a target object, obtaining a target test mode corresponding to the test instruction signal, wherein the target test mode includes at least BL16 mode and BL8 mode; configuring a burst length parameter within a unit test cycle according to the target test mode, wherein when the target test mode is BL16 mode, the burst length parameter is configured to be 16 bytes, and when the target test mode is BL8 mode, the burst length parameter is configured to be 8 bytes.

[0064] Specifically, there is a correspondence between test modes and test command signals. The target device can select the corresponding test command signal on the terminal device. The terminal device sends the test command signal to the SLT test according to the test command signal selected by the target device. The SLT tester first determines the target test mode corresponding to the test command signal based on the correspondence between the test command signal and the test mode, and then configures the burst length parameter of the SLT tester to execute the SLT test sequence under the burst length parameter. Under the DDR5 standard, the SLT tester not only supports BL16 mode testing, but also can effectively perform BL8 mode testing on DDR5 memory modules, greatly expanding the test coverage and depth of DDR5 memory modules.

[0065] In another specific implementation, in response to receiving a test instruction signal for selecting a target object, a burst length parameter is configured within the unit test cycle, including: in response to receiving a test instruction signal for selecting a target object, obtaining the target test mode corresponding to the test instruction signal, wherein the target test mode includes at least BL16 mode, BL8 mode, and a BL16 and BL8 switching mode; determining the BL16 mode sub-cycle and BL8 mode sub-cycle within the unit test cycle according to the test instruction signal; when the target test mode is the BL16 and BL8 switching mode, configuring the burst length parameter as 16 bytes within the BL16 mode sub-cycle of the unit test cycle, and configuring the burst length parameter as 8 bytes within the BL8 mode sub-cycle of the unit test cycle.

[0066] In the above embodiments, the target test mode includes BL16 and BL8 modes, that is, the burst length parameter configured within a unit test cycle is the same. In different unit test cycles, the mode switches from BL8 to BL16 or from BL16 to BL8 according to the test instruction signal selected by the target object. In another possible implementation, the target test mode also includes a BL16 and BL8 switching mode. In this implementation, the burst length parameter is different within the unit test cycle. Specifically, the burst length parameter is configured as 16 bytes in the BL16 mode sub-cycle of the unit test cycle and as 8 bytes in the BL8 mode sub-cycle of the unit test cycle.

[0067] As a specific implementation, when the target test mode is a BL16 and BL8 switching mode, the burst length parameter is configured to 16 bytes in the BL16 mode sub-cycle of the unit test cycle, and to 8 bytes in the BL8 mode sub-cycle of the unit test cycle. This includes: when the target test mode is a BL16 and BL8 switching mode, determining the switching mode and switching time node based on the switching instruction signal included in the test instruction signal; determining the BL16 mode sub-cycle and the BL8 mode sub-cycle of the unit test cycle based on the switching time node; when the switching mode is the first switching mode, configuring the burst length parameter to 16 bytes in the BL16 mode sub-cycle before the switching time node, and configuring the burst length parameter to 8 bytes in the BL8 mode sub-cycle after the switching time node; when the switching mode is the second switching mode, configuring the burst length parameter to 8 bytes in the BL8 mode sub-cycle before the switching time node, and configuring the burst length parameter to 16 bytes in the BL16 mode sub-cycle after the switching time node.

[0068] In this implementation, the test command signal includes a switching mode and a switching time node. The switching mode indicates whether the unit test cycle switches from BL16 mode to BL8 mode or from BL8 mode to BL16 mode. When the switching mode is the first switching mode, the unit test cycle switches from BL16 mode to BL8 mode. When the switching mode is the second switching mode, the unit test cycle switches from BL8 mode to BL16 mode. The switching time node reflects the BL16 mode sub-cycle and the BL8 mode sub-cycle within the unit test cycle. The length of the BL16 mode sub-cycle and the BL8 mode sub-cycle can be determined based on the position of the switching time node in the test cycle.

[0069] Therefore, in this embodiment, the switching mode and switching time node are first determined according to the switching instruction signal included in the test instruction signal. Then, when the switching mode is the first switching mode, the burst length parameter is configured to 16 bytes in the BL16 mode sub-cycle before the switching time node and to 8 bytes in the BL8 mode sub-cycle after the switching time node. When the switching mode is the second switching mode, the burst length parameter is configured to 8 bytes in the BL8 mode sub-cycle before the switching time node and to 16 bytes in the BL16 mode sub-cycle after the switching time node. This allows for dynamic switching of the burst length parameter of the memory module from 8 bytes to 16 bytes, or dynamic switching of the burst length parameter of the memory module from 16 bytes to 8 bytes. Testing under different burst length parameters can be achieved without reloading the entire test process.

[0070] S120. Execute the SLT test sequence under the burst length parameter and obtain the test report of the memory module under the test instruction signal.

[0071] The SLT test sequence includes a functional verification test sequence, a stress stability test sequence, and a timing calibration test sequence. The test report includes test data, performance index data, error log data, and power consumption data.

[0072] In the specific implementation, the SLT test sequence is executed under the burst length parameter, and the test report of the memory module under the test instruction signal is obtained, including: obtaining the target number of SLT test sequences included in the test instruction signal; executing the target number of SLT test sequences under the burst length parameter, and obtaining the sub-test reports of the memory module under different SLT test sequences in turn; and determining the test report of the memory module under the test instruction signal based on the sub-test reports of the memory module under different SLT test sequences.

[0073] Specifically, the test instruction signal includes the number of SLT test sequences to be executed in the unit test cycle. After configuring the burst length parameter in the unit test cycle in step S110, the target number of SLT test sequences is selected according to the target number of SLT test sequences included in the test instruction signal, and the target number of SLT test sequences are executed to test the memory module. Sub-test reports under different SLT test sequences are obtained in sequence. The sub-test reports obtained after executing the target number of SLT test sequences under the same test instruction signal are summarized to obtain the test report of the memory module under the test instruction signal.

[0074] S130. Determine the failure rate of the memory module under the test instruction signal based on the test report.

[0075] In the specific implementation, the failure probability of the memory module under the test command signal is determined according to the test report, including: determining the failure type and failure location of the memory module under the test command signal according to the test report; and determining the failure rate of the memory module at the same failure location and the failure rate of the memory module under different failure types according to the failure type and failure location.

[0076] Under the same target test mode, the memory module is tested with a target number of SLT test sequences to obtain sub-test reports of the memory module under different SLT test sequences. The sub-test reports of the memory module under different SLT test sequences include fault type and fault location information. By summarizing the fault type and fault location information of the memory module under different SLT test sequences, the fault occurrence rate of the memory module at the same fault location and the fault occurrence rate of the memory module under different fault types can be determined.

[0077] Based on the ratio of the number of identical fault location information in each sub-test report to the target number, the failure rate of the memory module at that fault location information is determined. Based on the ratio of the number of faults of the same fault type in each sub-test report to the total number of faults, the failure rate of the memory module under that fault type is determined.

[0078] Furthermore, by sequentially testing the memory module in BL16 mode, BL8 mode, and a switching mode between BL16 and BL8, test reports and failure rates were obtained for the memory module under different test modes. Based on the failure rate of the memory module under different test command signals, the stability of the memory module was determined. This method can simulate the dynamic Burst Length switching scenarios that memory modules may encounter in real-world applications, greatly expanding the testing coverage and depth of DDR5 memory modules. This allows for a more comprehensive and accurate identification of potential stability issues and performance bottlenecks, improving the effectiveness of the testing.

[0079] In a specific example, based on the test instruction signal selected by the target object for the first time, the target test mode is determined to be BL16 mode. At this time, after configuring the burst length parameter to 16 bytes, the SLT test sequence is executed, and the failure rate under the first selected test instruction signal is determined based on the obtained test report. Then, the target object selects another test instruction signal. At this time, based on the test instruction signal selected by the target object for the second time, the target test mode is determined to be BL8 mode. At this time, after configuring the burst length parameter to 8 bytes, the SLT test sequence is executed, and the failure rate under the second selected test instruction signal is determined based on the obtained test report. Since the entire test process does not need to be reloaded when executing the BL8 mode test, the testing efficiency of the memory module can be effectively improved.

[0080] It should be noted that in other possible implementations, the burst length parameter may also include 32 bytes. When the burst length parameter is 32 bytes, the process of determining the failure rate of the memory module is the same as the process when the burst length parameter is 8 bytes and 16 bytes. This disclosure embodiment will not provide a specific description of this.

[0081] In addition, when the burst length parameter also includes 32 bytes, the target test mode also includes BL16 and BL32 switching mode, as well as BL8 and BL32 switching mode. The specific working process is the same as that of BL16 and BL8 switching mode, and this embodiment will not be described in detail.

[0082] The SLT testing method for memory modules provided in this disclosure first configures burst length parameters within a unit test cycle in response to receiving a test instruction signal for target object selection; then, it executes an SLT test sequence under the burst length parameters and obtains a test report of the memory module under the test instruction signal. The SLT test sequence includes a functional verification test sequence, a stress stability test sequence, and a timing calibration test sequence. The test report includes test data, performance index data, error log data, and power consumption data. Finally, it determines the failure rate of the memory module under the test instruction signal based on the test report. First, based on the correspondence between test command signals and test modes, the target test mode corresponding to the test command signal is determined. Then, the burst length parameters of the SLT test machine are configured to execute the SLT test sequence under the burst length parameters. Under the DDR5 standard, the SLT test machine not only supports BL16 mode testing, but also can effectively perform BL8 mode testing and BL16 and BL8 switching mode testing. On the one hand, it greatly expands the test coverage and depth of DDR5 memory modules, thereby more comprehensively and accurately discovering potential stability problems and performance bottlenecks and improving the effectiveness of testing. On the other hand, it can achieve testing under different burst length parameters without reloading the entire test process, improving the testing efficiency of memory modules.

[0083] Based on the above embodiments, Figure 2 This is a schematic diagram of the structure of a memory module SLT testing device provided in an embodiment of this disclosure, as shown below. Figure 2 As shown, the SLT testing device for memory modules includes:

[0084] The parameter configuration module 210 is used to configure the burst length parameter within the unit test cycle in response to receiving the test instruction signal for target object selection. The burst length parameter includes 16 bytes and 8 bytes.

[0085] The test report acquisition module 220 is used to execute the SLT test sequence under the burst length parameter and acquire the test report of the memory module under the test instruction signal. The SLT test sequence includes the functional verification test sequence, the stress stability test sequence, and the timing calibration test sequence. The test report includes test data, performance index data, error log data, and power consumption data.

[0086] The failure rate determination module 230 is used to determine the failure rate of the memory module under the test instruction signal based on the test report.

[0087] The memory module SLT testing apparatus provided in this embodiment first configures burst length parameters within a unit test cycle in response to receiving a test instruction signal for target object selection; then, it executes an SLT test sequence under the burst length parameters and obtains a test report of the memory module under the test instruction signal. The SLT test sequence includes a functional verification test sequence, a stress stability test sequence, and a timing calibration test sequence. The test report includes test data, performance index data, error log data, and power consumption data. Finally, it determines the failure rate of the memory module under the test instruction signal based on the test report. First, based on the correspondence between test command signals and test modes, the target test mode corresponding to the test command signal is determined. Then, based on the correspondence between test modes and SLT test sequences, the SLT test sequence corresponding to the target test mode is determined. Finally, the burst length parameters of the SLT test machine are configured to execute the SLT test sequence under the burst length parameters. Under the DDR5 standard, the SLT test machine not only supports BL16 mode testing but can also effectively perform BL8 mode testing and BL16 and BL8 switching mode testing. On the one hand, this greatly expands the testing coverage and depth of DDR5 memory modules, thereby more comprehensively and accurately discovering potential stability issues and performance bottlenecks and improving the effectiveness of testing. On the other hand, testing under different burst length parameters can be achieved without reloading the entire test process, improving the efficiency of memory module testing.

[0088] In a specific implementation, configuring the burst length parameter within the unit test cycle in response to receiving the test instruction signal for target object selection includes:

[0089] In response to receiving a test instruction signal for selecting a target object, the target test mode corresponding to the test instruction signal is obtained, wherein the target test mode includes at least BL16 mode and BL8 mode;

[0090] According to the target test mode, the burst length parameter is configured within the unit test cycle. Specifically, when the target test mode is BL16 mode, the burst length parameter is configured to be 16 bytes, and when the target test mode is BL8 mode, the burst length parameter is configured to be 8 bytes.

[0091] In a specific implementation, the target test mode also includes a BL16 and BL8 switching mode;

[0092] The method further includes:

[0093] Based on the test command signal, determine the BL16 mode sub-cycle and BL8 mode sub-cycle within the unit test cycle;

[0094] The step of configuring burst length parameters within the unit test cycle according to the target test mode includes:

[0095] When the target test mode is BL16 and BL8 switching mode, the burst length parameter is configured to 16 bytes in the BL16 mode sub-cycle of the unit test cycle, and the burst length parameter is configured to 8 bytes in the BL8 mode sub-cycle of the unit test cycle.

[0096] In a specific implementation, when the target test mode is a BL16 and BL8 switching mode, configuring the burst length parameter to 16 bytes within the BL16 mode sub-cycle of the unit test cycle and configuring the burst length parameter to 8 bytes within the BL8 mode sub-cycle of the unit test cycle includes:

[0097] When the target test mode is the BL16 and BL8 switching mode, the switching mode and switching time node are determined according to the switching command signal included in the test command signal;

[0098] Based on the switching time node, determine the BL16 mode sub-cycle and the BL8 mode sub-cycle in the unit test cycle;

[0099] When the switching mode is the first switching mode, the burst length parameter of the BL16 mode sub-cycle before the switching time node is configured to be 16 bytes, and the burst length parameter of the BL8 mode sub-cycle after the switching time node is configured to be 8 bytes.

[0100] When the switching mode is the second switching mode, the burst length parameter of the BL8 mode sub-cycle before the switching time node is configured to be 8 bytes, and the burst length parameter of the BL16 mode sub-cycle after the switching time node is configured to be 16 bytes.

[0101] In a specific implementation, the step of executing the SLT test sequence under the burst length parameter and obtaining the test report of the memory module under the test instruction signal includes:

[0102] Obtain the target number of SLT test sequences included in the test instruction signal;

[0103] Execute a target number of SLT test sequences under the burst length parameter, and sequentially obtain sub-test reports of the memory module under different SLT test sequences;

[0104] Based on the sub-test reports of the memory module under different SLT test sequences, determine the test report of the memory module under the test instruction signal.

[0105] In a specific implementation, determining the failure rate of the memory module under the test command signal based on the test report includes:

[0106] The fault type and location of the memory module under the test command signal are determined based on the test report.

[0107] Based on the fault type and fault location, determine the fault occurrence rate of the memory module at the same fault location and the fault occurrence rate of the memory module under different fault types.

[0108] In a specific implementation, the method further includes:

[0109] Obtain the failure rate of the memory module under different test command signals;

[0110] The stability of the memory module is determined based on the failure rate of the memory module under different test command signals.

[0111] This application also provides a computer device, please refer to the following for details. Figure 3 , Figure 3 This is a basic structural block diagram of the computer device in this embodiment.

[0112] The computer device includes a memory 510 and a processor 520 that are interconnected via a system bus. It should be noted that only a computer device with components 510-520 is shown in the figure; however, it should be understood that it is not required to implement all the shown components, and more or fewer components may be implemented alternatively. Those skilled in the art will understand that the computer device described herein is a device capable of automatically performing numerical calculations and / or information processing according to pre-set or stored instructions, and its hardware includes, but is not limited to, microprocessors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), embedded devices, etc.

[0113] Computer devices can include desktop computers, laptops, handheld computers, and cloud servers. These devices allow for human-computer interaction with users through keyboards, mice, remote controls, touchpads, or voice-activated devices.

[0114] The memory 510 includes at least one type of readable storage medium, including non-volatile memory or volatile memory, such as flash memory, hard disk, multimedia card, card-type memory (e.g., SD or DX memory), random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic memory, magnetic disk, optical disk, etc. RAM may include static RAM or dynamic RAM. In some embodiments, the memory 510 may be an internal storage unit of a computer device, such as the hard disk or memory of the computer device. In other embodiments, the memory 510 may also be an external storage device of the computer device, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, or flash card equipped on the computer device. Of course, the memory 510 may include both internal storage units and external storage devices of the computer device. In this embodiment, the memory 510 is typically used to store the operating system and various application software installed on the computer device, such as the program code of the method described above. In addition, the memory 510 may also be used to temporarily store various types of data that have been output or will be output.

[0115] The processor 520 is typically used to perform the overall operation of a computer device. In this embodiment, the memory 510 is used to store program code or instructions, including computer operation instructions. The processor 520 is used to execute the program code or instructions stored in the memory 510 or to process data, such as program code that runs the methods described above.

[0116] In this article, the bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. This bus system can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not mean that there is only one bus or one type of bus.

[0117] Another embodiment of this application also provides a computer-readable medium, which may be a computer-readable signal medium or a computer-readable medium. A processor in a computer reads computer-readable program code stored in the computer-readable medium, enabling the processor to execute the functional actions specified in each step or combination of steps in the above method; and to generate means for implementing the functional actions specified in each block or combination of blocks in the block diagram.

[0118] Computer-readable media include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared memory or semiconductor systems, devices or apparatuses, or any suitable combination thereof, wherein the memory is used to store program code or instructions, the program code including computer operation instructions, and the processor is used to execute the program code or instructions of the above-described methods stored in the memory.

[0119] The definitions of memory and processor can be found in the description of the foregoing computer device embodiments, and will not be repeated here.

[0120] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0121] In the various embodiments of this application, the functional units or modules can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0122] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0123] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0124] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0125] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A method for testing a memory stick (SLT), characterized by, The method comprises: in response to receiving a target object selected test instruction signal, configuring a burst length parameter in a unit test period, wherein the burst length parameter comprises 16 bytes or 8 bytes; performing an SLT test sequence under the burst length parameter, and obtaining a test report of a memory bank under the test instruction signal, wherein the SLT test sequence comprises a function verification test sequence, a stress stability test sequence, and a timing calibration test sequence, and the test report comprises test data, performance index data, error log data, and power consumption data; determining a failure occurrence rate of the memory bank under the test instruction signal according to the test report; wherein, in response to receiving a target object selected test instruction signal, configuring a burst length parameter in a unit test period comprises: in response to receiving a target object selected test instruction signal, obtaining a target test mode corresponding to the test instruction signal according to a correspondence between test instruction signals and test modes, wherein the target test mode comprises at least a BL16 mode or a BL8 mode; configuring a burst length parameter in a unit test period according to the target test mode, wherein when the target test mode is the BL16 mode, the burst length parameter is configured as 16 bytes, and when the target test mode is the BL8 mode, the burst length parameter is configured as 8 bytes.

2. The method of claim 1, wherein, The target test mode further comprises a BL16 and BL8 switching mode. The method further comprises: determining a BL16 mode sub-period and a BL8 mode sub-period in a unit test period according to the test instruction signal; configuring a burst length parameter in a unit test period according to the target test mode comprises: when the target test mode is the BL16 and BL8 switching mode, configuring the burst length parameter as 16 bytes in a BL16 mode sub-period of the unit test period, and configuring the burst length parameter as 8 bytes in a BL8 mode sub-period of the unit test period.

3. The method of claim 2, wherein, When the target test mode is the BL16 and BL8 switching mode, determining a switching mode and a switching time node according to a switching instruction signal included in the test instruction signal; determining a BL16 mode sub-period in a unit test period and a BL8 mode sub-period in a unit test period according to the switching time node; when the switching mode is a first switching mode, configuring the burst length parameter as 16 bytes in a BL16 mode sub-period before the switching time node, and configuring the burst length parameter as 8 bytes in a BL8 mode sub-period after the switching time node; when the switching mode is a second switching mode, configuring the burst length parameter as 8 bytes in a BL8 mode sub-period before the switching time node, and configuring the burst length parameter as 16 bytes in a BL16 mode sub-period after the switching time node. ​ 4. The method of claim 1, wherein, The SLT test sequence is executed under the burst length parameter, and a test report of the memory bank under the test instruction signal is acquired, including: The target number of SLT test sequences included in the test instruction signal is acquired; The target number of SLT test sequences is executed under the burst length parameter, and sub-test reports of the memory bank under different SLT test sequences are sequentially acquired; The test report of the memory bank under the test instruction signal is determined according to the sub-test reports of the memory bank under different SLT test sequences.

5. The method of claim 4, wherein, The test report is used to determine the fault occurrence rate of the memory bank under the test instruction signal, including: The fault type and fault position of the memory bank under the test instruction signal are determined according to the test report; The fault occurrence rate of the memory bank at the same fault position and the fault occurrence rate of the memory bank under different fault types are determined according to the fault type and fault position.

6. The method of claim 1, wherein, The method further includes: The fault occurrence rate of the memory bank under different test instruction signals is acquired; The stability of the memory bank is determined according to the fault occurrence rate of the memory bank under different test instruction signals.

7. A memory stick (SLT) testing apparatus, characterized by comprising: It includes: The parameter configuration module is used to configure the burst length parameter in the unit test period in response to receiving the test instruction signal selected by the target object, wherein the burst length parameter includes 16 bytes or 8 bytes; The test report acquisition module is used to execute the SLT test sequence under the burst length parameter and acquire the test report of the memory bank under the test instruction signal, wherein the SLT test sequence includes a function verification test sequence, a stress stability test sequence, and a timing calibration test sequence, and the test report includes test data, performance index data, error log data, and power consumption data; The fault occurrence rate determination module is used to determine the fault occurrence rate of the memory bank under the test instruction signal according to the test report; Wherein, in response to receiving the test instruction signal selected by the target object, the burst length parameter is configured in the unit test period, including: In response to receiving the test instruction signal selected by the target object, the target test mode corresponding to the test instruction signal is acquired according to the correspondence between the test instruction signal and the test mode, wherein the target test mode at least includes BL16 mode or BL8 mode; The burst length parameter is configured in the unit test period according to the target test mode, wherein the burst length parameter is configured as 16 bytes when the target test mode is BL16 mode, and the burst length parameter is configured as 8 bytes when the target test mode is BL8 mode.

8. A computer device, comprising: It includes: One or more processors; Storage device for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors implement the method of any one of claims 1-6.

9. A computer readable storage medium having stored thereon a computer program, characterized in that, The program is executed by the processor to implement the method of any one of claims 1-6.

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