A chip with multi-step ring-shaped shallow trench isolation structure through silicon via

Abstract

The application belongs to the technical field of semiconductors, and discloses a chip with a multi-stage annular shallow trench isolation structure through silicon via. The chip comprises a silicon wafer, a through silicon via arranged in the silicon wafer, and a multi-stage annular shallow trench isolation structure arranged on the silicon wafer. An insulating layer and a conductor layer are sequentially arranged from the hole wall to the center in the through silicon via. The multi-stage annular shallow trench isolation structure comprises at least two annular shallow trenches arranged from inside to outside and coaxial with the through silicon via and a filling material filled in the annular shallow trenches. The depths of the annular shallow trenches are different. The chip has low thermal stress level, small high stress area range, and simple preparation process.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductors and relates to a chip with a multi-stage ring-shaped shallow trench isolation structure through silicon via. BACKGROUND

[0002] Three-dimensional integrated circuit (3D-IC) packaging achieved by stacking chips in the vertical direction has become one of the key technologies for improving device performance, increasing integration density and optimizing space utilization. However, with the continuous reduction of chip and packaging size, the limited silicon area significantly restricts the possibility of further improving integration density. In addition, the implementation of high-density ICs also brings many thermal mechanical reliability problems, especially thermal stress problems. Therefore, effectively increasing the functional area of the chip while ensuring thermal mechanical reliability has become a key challenge for the continuous development of 3D-IC technology.

[0003] As one of the core technologies for implementing 3D-IC, through silicon via (TSV) can provide a high aspect ratio vertical interconnection path, thereby shortening the signal transmission distance between components on different chips, and thus greatly reducing the time delay, transmission power consumption and circuit occupation area. The reliability of TSV directly determines the stability and performance of the entire 3D-IC packaging. Due to the obvious mismatch of the thermal expansion coefficients between copper (Cu), silicon dioxide (SiO2) and silicon (Si) wafers, TSV will generate significant thermal stress when subjected to temperature changes. These thermal stresses will cause mechanical stress concentration in the material, thereby causing delamination, protrusion, cracking and other reliability problems, and in severe cases, may even cause device failure. In addition, due to the piezoresistive effect, the thermal stress caused by TSV will change the carrier mobility in the silicon wafer around the hole, thereby affecting the electrical performance of the semiconductor device, leading to a decrease in its working efficiency, and even causing irreversible performance degradation. Therefore, solving the problem of thermal stress caused by TSV has become one of the key research directions for improving the reliability of 3D-IC technology.

[0004] Publication No. CN103378028A discloses a semiconductor structure with a stress protection structure, including a substrate, a stress generating element and a stress protection device. The substrate has a first surface and a second surface, which are oppositely arranged. The stress generating element is arranged in the substrate. The stress protection structure is arranged on one side of the first surface of the substrate, the stress protection structure surrounds the stress generating element, and the stress protection structure has a sealed air space inside.

[0005] Although the above-mentioned applications and the prior art can reduce the thermal stress generated by the through silicon via to a certain extent, thereby improving the integration and reliability of the device, the stress protection structure involved in the above-mentioned applications has the problems of small diameter and high aspect ratio, which not only increases the process complexity and manufacturing difficulty, but also brings many process challenges. Small diameter and high aspect ratio structure is easy to cause etching efficiency to decrease, sidewall roughness to increase, etching quality to decrease, and it is difficult to ensure the uniformity of the whole structure, resulting in local defects or performance differences. In addition, the stress protection structure itself is complex in design, which further increases the difficulty of implementing the overall process.

[0006] Therefore, it is necessary to design a three-dimensional integrated circuit chip with a through silicon via, which has low thermal stress level, small high stress area range, and simple preparation process. SUMMARY

[0007] The purpose of the present application is to at least partially solve the above-mentioned technical problems, and to provide a chip with a multi-stage annular shallow trench isolation structure through silicon via, which has the characteristics of low thermal stress level and small high stress area range.

[0008] In a first aspect, the present application provides a chip with a multi-stage annular shallow trench isolation structure through silicon via, the chip comprising:

[0009] a silicon wafer, a through silicon via arranged in the silicon wafer, and a multi-stage annular shallow trench isolation structure arranged on the silicon wafer;

[0010] an insulating layer and a conductor layer arranged in the through silicon via from the hole wall to the center in turn;

[0011] The multi-stage annular shallow trench isolation structure comprises at least two annular shallow trenches coaxial with the through silicon via and directly contacting the sidewall from inside to outside, and a filling material filled in the annular shallow trench, wherein the Young's modulus and the thermal expansion coefficient of the filling material are lower than those of the silicon wafer and the conductor layer.

[0012] The depths of the annular shallow trenches are different.

[0013] In some embodiments of the present application, the material of the silicon wafer is selected from silicon.

[0014] In some embodiments of the present application, the multi-stage annular shallow trench isolation structure has a predetermined gap between the inner side edge of the annular shallow trench close to the central axis of the through silicon via and the outer wall of the conductor layer.

[0015] In some embodiments of the present application, the predetermined gap is 1-10 μm.

[0016] In some embodiments of the present application, the widths of the annular shallow trenches are the same, and the performance is optimal.

[0017] In some embodiments of the present application, the width of the annular shallow trench is 0.5-4 μm, and the depth is 1-15 μm.

[0018] In some embodiments of the present application, the number of the annular shallow trenches is 2-4.

[0019] In some embodiments of the present application, the number of the annular shallow trenches is 2, the width of each of the annular shallow trenches is 3 μm, the depth of the annular shallow trench close to the central axis of the via is 1 μm, and the depth of the annular shallow trench far from the central axis of the via is 2 μm, and the performance is optimal.

[0020] In some embodiments of the present application, the conductor layer is a cylinder, and the radius of the bottom surface is 1-20 μm.

[0021] In some embodiments of the present application, the thickness of the insulating layer is 0.1-5 μm.

[0022] In some embodiments of the present application, the thickness of the silicon wafer is 40-100 μm.

[0023] In some embodiments of the present application, the height of the silicon wafer, the conductor layer and the insulating layer is 50-300 μm.

[0024] In some embodiments of the present application, the conductor layer is one or more of Al, Mn, Fe, Ti, Cr, Co, Ni, Cu, Ag, Au, V, Zr, Mo, Nb, W and alloys thereof, a polymer conductor, or doped polysilicon, and the insulating layer is one of silicon dioxide, benzocyclobutene and polyimide.

[0025] In some embodiments of the present application, the filling material is silicon dioxide.

[0026] The chip with the silicon through hole having the multi-stage annular shallow trench isolation structure according to the embodiments of the present application has at least one of the following advantages:

[0027] (1) By etching a plurality of annular shallow trench isolation structures coaxial with the via in the silicon wafer region and reasonably setting the size of the trenches, the thermal stress generated by the silicon through hole can be effectively reduced, the high stress area can be reduced, and the integration and thermal mechanical reliability of the silicon through hole can be improved. These shallow trench isolation structures only need to locally optimize the surface layer of the silicon wafer, compared with etching a stress protection structure deep to the bottom of the silicon wafer near the silicon through hole, more devices and components can be integrated in the silicon wafer.

[0028] (2) Avoid the complex process problem caused by the deep groove stress protection structure, thereby simplifying the manufacturing process and reducing the process difficulty. In addition, the structure also reserves more space for the deep part of the silicon wafer, which is beneficial to integrate more functional devices and improve the overall integration and manufacturability. BRIEF DESCRIPTION OF DRAWINGS

[0029] These and / or other aspects and advantages of the present application will become apparent and be more readily understood from the following description, taken in conjunction with the accompanying drawings, in which:

[0030] Figures 1-7 The structure schematic diagram of each step processing of the preparation method of the chip with 2-order annular shallow trench isolation structure silicon through hole provided by embodiment 1 of the present application is shown in the figure;

[0031] Figure 8 The three-dimensional structure diagram of the chip with 2-order annular shallow trench isolation structure silicon through hole provided by embodiment 1 of the present application is shown in the figure;

[0032] Figure 9 The cross-sectional view of the chip with 2-order annular shallow trench isolation structure silicon through hole provided by embodiment 1 of the present application is shown in the figure;

[0033] Figure 10 The cross-sectional view of the chip with 3-order annular shallow trench isolation structure silicon through hole provided by embodiment 2 of the present application is shown in the figure;

[0034] Figure 11 The cross-sectional view of the chip with 4-order annular shallow trench isolation structure silicon through hole provided by embodiment 3 of the present application is shown in the figure;

[0035] Figure 12 The three-dimensional structure diagram of a chip with single-order annular shallow trench isolation structure silicon through hole provided by the comparative example of the present application is shown in the figure;

[0036] Figure 13 The cross-sectional view of the chip with single-order annular shallow trench isolation structure silicon through hole shown in the figure is shown in the figure; Figure 12

[0037] The stress cloud atlas characterizing KOZ of the chip with single-order annular shallow trench isolation structure silicon through hole shown in the figure is shown in the figure; Figure 14 Figure 12 The stress cloud atlas characterizing KOZ of the chip with 2-order annular shallow trench isolation structure silicon through hole provided by embodiment 1 of the present application is shown in the figure;

[0038] Figure 15 The stress cloud atlas characterizing KOZ of the chip with 3-order annular shallow trench isolation structure silicon through hole provided by embodiment 2 of the present application is shown in the figure;

[0039] Figure 16 The stress cloud atlas characterizing KOZ of the chip with 4-order annular shallow trench isolation structure silicon through hole provided by embodiment 3 of the present application is shown in the figure;​

[0040] Figure 17 is a stress contour map of a chip with 4th order ring-shaped shallow trench isolation structure through silicon via provided by embodiment 3 of the present application. DETAILED DESCRIPTION

[0041] The technical solutions of the present application are further specifically described below by way of examples in conjunction with the accompanying drawings. In the description, identical or similar reference numerals indicate identical or similar components. The following description of the embodiments of the present application with reference to the accompanying drawings is intended to explain the general inventive concept of the present application and should not be construed as a limitation of the present application.

[0042] It should be noted that the terms used in the present application are generally the terms commonly used by those skilled in the art, and if they are inconsistent with the commonly used terms, the terms in the present application shall prevail.

[0043] In this document, the term "etching" refers to a process of selectively removing unwanted material from the surface of a silicon wafer by chemical or physical methods; the term "photolithography" refers to the use of ultraviolet light or other types of light sources to project a pattern onto the surface of a photoresist through a mask or projection system, and to form a specific pattern by using the chemical reaction of the photoresist; the term "chemical mechanical polishing" refers to the planarization treatment of the wafer being processed, which combines chemical action and mechanical grinding technology to achieve micron or nanometer level material removal on the surface of the polished workpiece, so as to make the surface highly planarized.

[0044] In this document, the term "thermal oxidation method" refers to a process of growing a thin film of silicon dioxide (SiO2) on the surface of silicon by exposing the silicon wafer to an oxygen or water vapor environment at high temperature; the term "electroplating method" refers to a process of reducing metal ions from an electrolyte and depositing them on the surface of a conductive object by electric current; the term "high stress area" refers to a region in which no device is allowed to be placed in order to ensure that the high stress generated by the through silicon via does not significantly affect the performance of the device, and the standard setting is to control the change of carrier mobility caused by stress within 5%.

[0045] In this document, the terms "include", "contain" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment. Without more limitation, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, article or equipment including the element. The specific meaning of the above terms in the present application can be understood on a case-by-case basis by those skilled in the art.

[0046] The following describes embodiments of the present application in detail.

[0047] Embodiment 1

[0048] Referring to Figures 1-7 , a method for manufacturing a chip with a 2-stage annular shallow trench isolation structure through silicon via according to Embodiment 1 of the present application is provided, comprising the following steps:

[0049] Step 1, referring to Figure 1 , photoresist is coated on the surface of the silicon wafer 10, and the position of the annular shallow trench 11 is defined by photolithography technology, and the annular shallow trench 11 close to the central axis of the via is made on the silicon wafer 10 by etching technology;

[0050] Step 2, referring to Figure 2 , silicon dioxide material is deposited in the annular shallow trench 11 close to the central axis of the via by chemical vapor deposition, and the excess filling material is removed by chemical mechanical polishing process to ensure the surface flatness;

[0051] Step 3, referring to Figure 3 , the above steps S1 and S2 are repeated to obtain the annular shallow trench 12 away from the central axis of the via and filled with silicon dioxide material;

[0052] Step 4, referring to Figure 4 , photoresist is coated again on the silicon wafer 10, the position of the via (TSV) is determined by photolithography technology, and the TSV hole is made in the silicon wafer 10 by etching technology, and the photoresist is removed after etching is completed, and the surface of the silicon wafer 10 is cleaned;

[0053] Step 5, referring to Figure 5 , an insulating layer 30 is deposited on the side wall of the TSV hole;

[0054] Step 6, referring to Figure 6 , copper is filled into the TSV hole, and chemical mechanical polishing treatment is performed to remove the excess conductor layer 20;

[0055] Step 7, referring to Figure 7 , wafer thinning: thinning is performed on the other side of the TSV to convert the TSV blind hole into a via, and a chip 100 with a 2-stage annular shallow trench isolation structure through silicon via is obtained.

[0056] Specifically, the etching in steps S1 and S4 uses deep reactive ion etching.

[0057] The deposition of the insulating layer 30 in step S5 uses thermal oxidation method.

[0058] The filling of copper in step S6 usually uses electroplating method.

[0059] The three-dimensional structure diagram of the chip 100 with 2-order annular shallow trench isolation structure through silicon via is shown in Figure 8 The cross-sectional view is shown in Figure 9 .

[0060] The chip 100 with 2-order annular shallow trench isolation structure through silicon via. The chip 100 with 2-order annular shallow trench isolation structure through silicon via mainly comprises a silicon wafer 10, a conductor layer 20 and an insulating layer 30. Specifically, the upper surface of the silicon wafer 10 is provided with annular shallow trenches 11 and 12 coaxial with the conductor layer 20 and directly contacting the sidewalls, and the annular shallow trenches 11 and 12 are filled with silicon dioxide.

[0061] The width of the annular shallow trench 11 is 3 μm, the depth is 1 μm, and the distance between the inner wall edge of the annular shallow trench 11 and the edge of the conductor layer 20 is 1 μm; the width of the annular shallow trench 12 is 3 μm, the depth is 2 μm; the radius of the conductor layer 20 is 5 μm; the insulating layer 30 is arranged around the central conductor layer 20, and the thickness is 0.1 μm; the thickness of the silicon wafer is 45 μm; the height of the silicon wafer 10, the conductor layer 20 and the insulating layer 30 is consistent, and is 50 μm.

[0062] Example 2

[0063] The cross-sectional view of the chip 200 with 3-order annular shallow trench isolation structure through silicon via is shown in Figure 10 .

[0064] The chip 200 with 3-order annular shallow trench isolation structure through silicon via. The chip 200 with 3-order annular shallow trench isolation structure through silicon via mainly comprises a silicon wafer 210, a conductor layer 220 and an insulating layer 230. Specifically, the upper surface of the silicon wafer 210 is provided with annular shallow trenches 211, 212 and 213 coaxial with the conductor layer 220 and directly contacting the sidewalls, and the annular shallow trenches 211, 212 and 213 are filled with silicon dioxide.

[0065] The width of the annular shallow trench 211 is 2 μm, the depth is 3 μm; the width of the annular shallow trench 212 is 3 μm, the depth is 1 μm; the width of the annular shallow trench 213 is 1 μm, the depth is 2 μm, and other parameters are the same as those of example 1.

[0066] Example 3

[0067] The cross-sectional view of the chip 300 with 4-order annular shallow trench isolation structure through silicon via is shown in Figure 11 .

[0068] The chip 300 has a four-stage annular shallow trench isolation structure via silicon vias. The chip 300 mainly comprises a silicon wafer 310, a conductor layer 320, and an insulating layer 330. Specifically, the upper surface of the silicon wafer 310 has annular shallow trenches 311-314 that are coaxial with the conductor layer 320 and directly contact its sidewalls. The annular shallow trenches 311-314 are filled with silicon dioxide.

[0069] The annular shallow trench 311 has a width of 1 μm and a depth of 4 μm; the annular shallow trench 312 has a width of 4 μm and a depth of 1 μm; the annular shallow trench 313 has a width of 3 μm and a depth of 3 μm; the annular shallow trench 314 has a width of 2 μm and a depth of 2 μm, and other parameters are the same as in Example 1.

[0070] Comparative example (a chip with a single-stage annular shallow trench isolation structure via silicon via)

[0071] The three-dimensional structure diagram of the chip 400 with a single-stage annular shallow trench isolation structure silicon via is shown below. Figure 12 As shown, the cross-sectional view is as follows Figure 13 As shown.

[0072] The chip 400 has a single-stage annular shallow trench isolation structure via. This chip 400 also includes a silicon wafer 410, a conductor layer 420, an insulating layer 430, and an annular shallow trench 411 coaxial with the conductor layer 420 on the upper surface of the silicon wafer 410. The structural difference between this chip 400 and the chip 100 with a two-stage annular shallow trench isolation structure via provided in Embodiment 1 of the present invention lies in the order and dimensional parameters of the shallow trench isolation structure formed on the silicon wafer to reduce thermal stress. Considering that other structural configurations are the same as those of the chip 100 with a two-stage annular shallow trench isolation structure via in the embodiment of the present invention, its structural parameters and fabrication process details will not be discussed further.

[0073] It should be noted that, in order to conduct the following comparative analysis, in Figures 8-13 The differences between the chip 400 with a single-order annular shallow trench isolation structure, the chip 100 with a second-order annular shallow trench isolation structure, the chip 200 with a third-order annular shallow trench isolation structure, and the chip 300 with a fourth-order annular shallow trench isolation structure in the embodiments of the present invention lie in the order and size parameters of the shallow trench isolation structure on the silicon wafer; all other structural parameters are the same.

[0074] Simulation analysis was performed using ANSYS Workbench software on chip 400 with a single-order annular shallow trench isolation structure silicon via (STI) and chips 100, 200, and 300 of the embodiments of the present invention with two-order annular shallow trench isolation structure STIs, respectively. The results are as follows: Figures 14-17 The stress contour plot shown represents the KOZ.

[0075] Figure 14 The stress cloud diagram characterizing the KOZ of the chip 400 with a single-stage annular shallow trench isolation structure provided as a comparative example is shown. As can be seen from the figure, the KOZ is maximum at 11.6 μm when a PMOS is placed and the transistor channel is parallel to the radial stress.

[0076] Figure 15 The stress cloud diagram characterizing the KOZ of the chip 100 with a second-order annular shallow trench isolation structure through-silicon via provided in Embodiment 1 of the present invention. The comparison shows that when a PMOS is placed and the transistor channel is parallel to the radial stress, the KOZ decreases to 7.2 μm (a reduction of 37.9%).

[0077] Figure 16 The stress cloud diagram characterizing the KOZ of the chip 200 with a three-stage annular shallow trench isolation structure via provided in Embodiment 2 of the present invention. Compared with the chip 400 with a single-stage annular shallow trench isolation structure via, it was found that when a PMOS was placed and the transistor channel was parallel to the radial stress, the KOZ was reduced to 8.8 μm (a reduction of 24.1%).

[0078] Figure 17 The stress cloud diagram characterizing the KOZ of the chip 300 with a 4-order annular shallow trench isolation structure through-silicon via provided in Embodiment 3 of the present invention is shown. The comparison shows that when a PMOS is placed and the transistor channel is parallel to the radial stress, the KOZ decreases to 8.1 μm (a reduction of 30.2%).

[0079] according to Figures 14-17 It is evident that among chips with multi-level annular shallow trench isolation structures in vias, those with annular shallow trench isolation structure order of 2 exhibit the best performance. Among chips with two-level annular shallow trench isolation structures in vias, the best performance is achieved when the width of each annular shallow trench is 3 μm, the depth of the annular shallow trench near the via's central axis is 1 μm, and the depth of the annular shallow trench farther from the via's central axis is 2 μm. Compared to chips with single-level annular shallow trench isolation structures in vias, when a PMOS is placed and the transistor channel is parallel to the radial stress, the KOZ is reduced to 7.2 μm, a reduction of 37.9%.

[0080] A multi-order annular shallow trench structure with depth gradient change is designed around the via region on the surface of a silicon wafer, and a material with a thermal expansion coefficient and Young's modulus significantly lower than that of the silicon wafer is filled, and a non-uniform material system with spatial gradient distribution of performance is constructed through the continuous change of the geometric parameters, and a gradient stress buffer layer is constructed. Under the action of thermal load, the gradient distribution of the performance of this material will induce a complex multi-source stress field between different material interfaces. By using the superposition effect of the stress field in space, the amplitude and range of stress adjustment can be expanded, and the thermal stress can be significantly reduced through the destructive superposition between part of the stress components, greatly reducing the high stress area (KOZ) around the TSV, and improving the integration. In addition, the gradient stress buffer design increases the stress transmission path, slows down the stress transmission speed, reduces the stress fatigue accumulation during thermal cycling, and reduces the probability of micro-crack initiation, thereby significantly improving the long-term reliability and service life of the device.

[0081] While some embodiments of the general inventive concept have been shown and described, it is to be understood that changes can be made in these embodiments without departing from the principles and spirit of the general inventive concept, the scope of which is defined in the claims and their equivalents.

Claims

1.A chip with multi-stage ring-shaped shallow trench isolation structure through silicon via, comprising: a silicon wafer, a through silicon via disposed in the silicon wafer, and a multi-stage ring-shaped shallow trench isolation structure disposed on the silicon wafer; an insulating layer and a conductor layer are disposed in the through silicon via from the hole wall to the center; the multi-stage ring-shaped shallow trench isolation structure comprises 2-4 ring-shaped shallow trenches coaxial with the through silicon via and directly contacting with the sidewall of the through silicon via from inside to outside, and a filling material filled in the ring-shaped shallow trenches, the Young's modulus and the thermal expansion coefficient of the filling material are lower than those of the silicon wafer and the conductor layer; the depth of each ring-shaped shallow trench is different; the width of the ring-shaped shallow trench is 0.5-4 μm, and the depth is 1-3 μm; the multi-stage ring-shaped shallow trench isolation structure has a preset interval between the inner edge of the ring-shaped shallow trench close to the central axis of the through silicon via and the outer wall of the conductor layer. The preset interval is 1-10 μm. The width of each ring-shaped shallow trench is the same. The number of the ring-shaped shallow trenches is 2, the width of each ring-shaped shallow trench is 3 μm, the depth of the ring-shaped shallow trench close to the central axis of the through silicon via is 1 μm, and the depth of the ring-shaped shallow trench away from the central axis of the through silicon via is 2 μm. The conductor layer is one or more of Al, Mn, Fe, Ti, Cr, Co, Ni, Cu, Ag, Au, V, Zr, Mo, Nb, W and alloys thereof, a polymer conductor, or doped polysilicon, and the insulating layer is one of silicon dioxide, benzocyclobutene and polyimide. The filling material is silicon dioxide. ​ 2. The chip of claim 1, wherein ​ 3. The chip of claim 1, wherein ​ 4. The chip of claim 1, wherein ​ 5. The chip of claim 1, wherein ​ 6. The chip of claim 1, wherein ​

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