Chip packaging structure, electronic equipment and manufacturing method of chip packaging structure

Abstract

The invention discloses a chip packaging structure, electronic equipment and a manufacturing method of the chip packaging structure. The chip packaging structure comprises a plurality of rewiring layers, an intermediate layer and a chip layer which are stacked along the thickness direction of the chip packaging structure, each re-wiring layer comprises a plurality of metalized patterns, a gap is formed between every two adjacent metalized patterns, and the chip packaging structure is provided with a through hole penetrating through the chip layer, the intermediate layer and the multiple re-wiring layers in the thickness direction; and in the area where the through holes in the multiple redistribution layers are located, the gap in one redistribution layer is covered by the projection of the metalized pattern of the other redistribution layer in the thickness direction of the chip packaging structure. The multi-layer redistribution layer can prevent laser from penetrating through the whole chip packaging structure and prevent the laser from penetrating through one side, back to the intermediate layer, of the multi-layer redistribution layer to damage other structures in the chip packaging structure.

Description

Technical Field

[0001] This application relates to the field of packaging technology, and in particular to a chip packaging structure, an electronic device, and a method for manufacturing the chip packaging structure. Background Technology

[0002] The chip package structure includes multiple different interposers, which may include silicon interposers, redistribution layers (RDLs), bridge interposers, and glass interposers. Chips, power supply modules, and connectors are integrated onto these interposers. To improve the heat dissipation performance of the chip package structure, it is also assembled with a heat sink. Through-holes for bolts are pre-laid in the chip package structure, allowing bolts to connect to the heat sinks located on both sides of the chip package structure. Simultaneously, the bolts also securely connect the various interposers, chips, power supply modules, and connectors to meet specific needs.

[0003] For complex chip packaging structures, it may be necessary to penetrate molding materials, silicon (Si), glass, polyimide (PI), and some metals. It is difficult to form through-holes in complex chip packaging structures using a single method. Complex chip packaging structures require multiple methods to form through-holes. For example, when forming through-holes, a portion of the chip packaging structure is opened using laser, and mechanical drilling is also used to ultimately form through-holes.

[0004] Currently, when lasers are used to create holes in chip packaging structures, the laser can easily burn through the chip packaging structure, causing damage or scrapping of the entire chip packaging structure. Summary of the Invention

[0005] This application provides a chip packaging structure, an electronic device, and a method for manufacturing the chip packaging structure.

[0006] In a first aspect, this application provides a chip packaging structure, comprising multiple redistribution layers, an interposer layer, and a chip layer stacked along the thickness direction of the chip packaging structure; each redistribution layer includes multiple metallized patterns, with gaps between adjacent metallized patterns; the chip packaging structure has vias penetrating the chip layer, the interposer layer, and the multiple redistribution layers along the thickness direction; in the region where the vias are located in the multiple redistribution layers, the gap in one redistribution layer is covered by the projection of the metallized pattern of another redistribution layer in the thickness direction of the chip packaging structure. In the thickness direction of the chip packaging structure, the projected area of ​​the region where the vias are located in the multiple redistribution layers is greater than the area occupied by the vias. The multiple redistribution layers are stacked along the thickness direction of the chip packaging structure, each redistribution layer consists of multiple metallized patterns, the multiple metallized patterns constituting one redistribution layer are located on the same plane, and the metallized patterns in different redistribution layers are located on different planes. The metallized patterns can be formed by depositing metal layers to form metal wiring structures, the metallized patterns can be formed by depositing metal layers and dielectric layers, or the metallized patterns can be formed by etching.

[0007] In the region where a via is located within a multi-layer redistribution layer, the gap in one redistribution layer is covered by the projection of the metallized pattern of another redistribution layer onto the thickness of the chip package structure. When a via is provided that penetrates the chip package structure along its thickness, the multi-layer redistribution layer can block the laser, preventing it from penetrating the entire chip package structure and causing damage. For example, when a via is provided along the chip package structure, the laser penetrates the chip layer and the interposer layer sequentially. The multi-layer redistribution layer can block the laser from penetrating the entire chip package structure, preventing damage to other structures on the side of the multi-layer redistribution layer away from the interposer layer.

[0008] In conjunction with the first aspect, in one possible implementation, the multilayer redistribution layer includes a first redistribution layer and a second redistribution layer stacked together. The side of the second redistribution layer facing away from the first redistribution layer is connected to an interposer layer. The first redistribution layer includes a plurality of metallized patterns spaced apart along the width direction of the chip package structure. The second redistribution layer includes a plurality of metallized patterns spaced apart along the width direction of the chip package structure. The gaps in the first redistribution layer are covered by the projection of the metallized patterns in the second redistribution layer onto the thickness direction of the chip package structure.

[0009] The first and second wiring layers are stacked along the thickness direction of the chip package structure. Since the gaps between adjacent metallized patterns in the first wiring layer are covered by the metallized patterns in the second wiring layer in the thickness direction, when drilling holes in the chip package structure using a laser...

[0010] The second wiring layer and the first wiring layer can block the laser and prevent the laser from passing through the second wiring layer and the transition structure formed by the combination of the second wiring layer. When the laser burns the chip package structure, it will form a blind via. The transition structure formed by the combination of the second wiring layer and the first wiring layer can prevent the laser from damaging other structures on the side of the second wiring layer away from the first wiring layer. The metallization pattern in the second wiring layer can be elongated, and the metallization pattern in the first wiring layer can also be elongated.

[0011] In conjunction with the first aspect, in one possible implementation, in the region where the via is located in the multilayer redistribution layer, a metallization pattern in the second redistribution layer covers the gap between two adjacent metallization patterns in the first redistribution layer along the width direction of the chip package structure, and the gap size between adjacent metallization patterns in the first redistribution layer is less than or equal to the size of the metallization pattern in the second redistribution layer along the width direction of the chip package structure.

[0012] In the region where a via is located within a multi-layer redistribution layer, the metallized patterns in the second redistribution layer and the first redistribution layer are misaligned. The gap between any two adjacent metallized patterns in the first redistribution layer is completely covered by the metallized patterns in the first redistribution layer along the thickness of the chip package structure. When a laser is used to drill a hole in the chip package structure, the transition structure formed by the first and second redistribution layers prevents the laser from penetrating the entire chip package structure, thus preventing damage to other structures on the side of the multi-layer redistribution layer away from the interposer.

[0013] In conjunction with the first aspect, in one possible implementation, the size of the metallized pattern in the first wiring layer along the width direction of the chip package structure is less than or equal to 200 μm, and the gap between any two adjacent metallized patterns in the first wiring layer is less than or equal to 200 μm; the size of the metallized pattern in the second wiring layer along the width direction of the chip package structure is less than or equal to 200 μm, and the gap between any two adjacent metallized patterns in the second wiring layer is less than or equal to 200 μm.

[0014] In conjunction with the first aspect, in one possible implementation, within the region where the vias are located in the multilayer redistribution layers, each redistribution layer includes multiple columns of metallized patterns spaced apart along the length direction of the chip package structure, and each column of metallized patterns includes multiple metallized patterns spaced apart along the width direction of the chip package structure; in the redistribution layer furthest from the interposer layer among the multilayer redistribution layers, the gap between two adjacent columns of metallized patterns is covered by the projection of the metallized patterns of other redistribution layers in the thickness direction of the chip package structure, and the gap between two adjacent metallized patterns in each column of metallized patterns is covered by the projection of the metallized patterns of other redistribution layers in the thickness direction of the chip package structure.

[0015] When drilling holes in a chip package structure using a laser, multiple redistribution layers can block the laser, preventing it from passing through the transition structure formed by the combination of multiple redistribution layers and damaging other structures located on the side of the multiple redistribution layers facing away from the interposer layer.

[0016] In conjunction with the first aspect, in one possible implementation, in two adjacent redistribution layers, the gap between two adjacent columns of metallized patterns in one redistribution layer is less than or equal to the dimension of the metallized patterns in the other redistribution layer along the length of the chip package structure; the gap between two adjacent metallized patterns in each column of metallized patterns is less than or equal to the dimension of the metallized patterns in the other redistribution layer along the width of the chip package structure. In the formation of multiple redistribution layers, the metallized patterns in one redistribution layer will not fall into the gaps between adjacent metallized patterns in another redistribution layer, making it easier to stack multiple redistribution layers.

[0017] In conjunction with the first aspect, in one possible implementation, the thickness of each redistribution layer is 1μm-50μm, the redistribution layer is not easily burned through by the laser, and the thickness range of the metallized pattern in the redistribution layer can be 1μm-50μm. The metallized pattern in the redistribution layer can meet the power-conducting requirements and the processing requirements.

[0018] In conjunction with the first aspect, in one possible implementation, the inner wall of a section of the via penetrating the chip layer, interposer layer, and multiple redistribution layers is provided with a molding protective layer. A connector is installed through the via for fixing two heat sinks. For complex chip package structures, forming vias using a single drilling method can easily damage the chip package structure. For example, directly drilling the chip package structure with a laser can easily debond the chip package structure from the glass, damaging the chip package structure. Mechanical drilling in a single pass can easily damage the interposer layer and the chip layer. In this application, when forming the via, a blind via is first formed in the chip package structure using a laser. The blind via penetrates the chip layer and interposer layer, and its bottom is located on the multiple redistribution layers. Then, a mechanical drill is used to pass through the multiple redistribution layers and the molding material of the blind via in a single pass to form the via. The diameter of the via is smaller than the diameter of the blind via. The remaining molding material in the blind via serves as a molding protective layer, which protects the interposer layer and the chip layer.

[0019] In conjunction with the first aspect, in one possible implementation, the chip package structure further includes two heat sinks and connectors. Along the thickness direction of the chip package structure, the chip layer, interposer layer, and multiple redistribution layers are located between the two heat sinks. The connectors pass through vias and are used to connect the two heat sinks. During operation, the electronic components (such as chips) within the chip package structure generate heat, which is dissipated by the heat sinks. Specifically, the heat generated by the chips and other electronic components is conducted to the heat sinks, which have good thermal conductivity to dissipate heat from the chips and other electronic components. The connectors connect the two heat sinks, thus securing them in place.

[0020] In conjunction with the first aspect, in one possible implementation, the chip package structure further includes a substrate and electronic devices located between two heat sinks. The substrate is connected to the side of the multilayer redistribution layer facing away from the interposer, and the electronic devices are connected to the side of the substrate facing away from the multilayer redistribution layer. The chip in the chip layer is connected to the substrate through the redistribution layer, and the substrate can be connected to the electronic devices, thus enabling the chip and electronic devices to be interconnected.

[0021] In conjunction with the first aspect, in one possible implementation, the chip layer includes multiple chips and a molding portion. The multiple chips are spaced apart and arranged on the surface of the interposer layer facing away from the multilayer redistribution layers, and the molding portion fills the gaps between the multiple chips. The molding portion can fix the chips to the interposer layer, improving the structural strength of the chip package structure.

[0022] Secondly, a method for manufacturing a chip packaging structure includes:

[0023] A multi-layer rewiring layer includes a first rewiring layer and a second rewiring layer stacked together;

[0024] It provides a configuration of multiple layers of redistribution layers, interposer layers, and chip layers stacked sequentially, including:

[0025] Multiple intervals are provided to set the metallized patterns to form the first rewiring layer;

[0026] Multiple spaced metallized patterns are set on the first wiring layer to form a second wiring layer, and the metallized patterns in the second wiring layer cover the gaps between adjacent metallized patterns in the first wiring layer.

[0027] An intermediary layer is placed on the side of the second wiring layer that faces away from the first wiring layer.

[0028] A chip layer is placed on the side of the interposer that faces away from the second wiring layer.

[0029] When vias are made in the chip package structure along the thickness direction of the chip package structure, the multilayer redistribution layer can block the laser from penetrating the entire chip package structure and prevent the laser from damaging other structures on the side of the multilayer redistribution away from the interposer layer.

[0030] In conjunction with the second aspect, in one possible implementation, a plurality of spaced-apart metallized patterns are disposed on the first routing layer to form the second routing layer, including:

[0031] In the width direction of the chip package structure, the size of the metallization pattern in the second wiring layer is greater than or equal to the gap size between adjacent metallization patterns in the first wiring layer.

[0032] In conjunction with the second aspect, in one possible implementation, a multi-layered redistribution layer, an interposer layer, and a chip layer are provided, stacked sequentially, including:

[0033] A multilayer redistribution layer is formed by stacking the layers sequentially. Each redistribution layer includes multiple columns of metallized patterns arranged at intervals along the length direction of the chip package structure. Each column of metallized patterns includes multiple metallized patterns arranged at intervals along the width direction of the chip package structure. The gap between two adjacent columns of metallized patterns is covered by the projection of the metallized patterns of other redistribution layers in the thickness direction of the chip package structure. The gap between two adjacent metallized patterns in each column of metallized patterns is covered by the projection of the metallized patterns of other redistribution layers in the thickness direction of the chip package structure. The gap between adjacent metallized patterns in the bottommost layer of the multilayer redistribution layer in the stacking direction is blocked by the metallized patterns of other redistribution layers.

[0034] An intermediate layer is formed on the side of the topmost layer away from the bottommost layer in the stacking direction of multi-layer rewiring;

[0035] The chip layer is placed on the side of the interposer that is away from the multilayer redistribution layer.

[0036] In conjunction with the second aspect, in one possible implementation, a multi-layered redistribution layer is formed, which includes:

[0037] In two adjacent redistribution layers, the gap between two adjacent columns of metallized patterns in one redistribution layer is less than or equal to the dimension of the metallized pattern in the other redistribution layer along the length of the chip package structure; the gap between two adjacent metallized patterns in each column of metallized patterns is less than or equal to the dimension of the metallized pattern in the other redistribution layer along the width of the chip package structure.

[0038] In conjunction with the second aspect, in one possible implementation, a via is formed by penetrating the chip layer, the interposer layer, and multiple redistribution layers, including:

[0039] By laser ablation of the chip layer, interposer layer and multiple redistribution layers, blind vias are formed in the chip packaging structure that penetrate the chip layer and interposer layer but do not penetrate the multiple redistribution layers.

[0040] Fill the blind hole with molding material;

[0041] Through-holes are formed by mechanically drilling through multiple redistribution layers and molding material.

[0042] In conjunction with the second aspect, in one possible implementation, when forming a through-hole by mechanically drilling through multiple redistribution layers and molding material:

[0043] Make the diameter of the through hole smaller than the diameter of the blind hole so that the molding material filling the blind hole acts as a molding protective layer.

[0044] Thirdly, this application also provides an electronic device, which includes a circuit board and a chip package structure as described in the first aspect disposed on the circuit board. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of this application or the background art, the accompanying drawings used in the embodiments of this application or the background art will be described below.

[0046] Figure 1 This is a schematic diagram of a chip packaging structure provided in an embodiment of this application;

[0047] Figure 2 This is a schematic diagram of the structure of a connector provided in one embodiment of this application;

[0048] Figure 3 This is a schematic diagram of the structure of a multilayer redistribution layer after through-holes are provided in an embodiment of this application;

[0049] Figure 4 A schematic diagram of the structure after providing through-holes in another multilayer redistribution layer according to an embodiment of this application;

[0050] Figure 5 A schematic diagram of the structure after providing through-holes in another multilayer redistribution layer according to an embodiment of this application;

[0051] Figure 6 A schematic diagram of the structure of a multilayer redistribution layer after providing through-holes according to an embodiment of this application;

[0052] Figure 7 A schematic diagram of the structure after providing through-holes in another multilayer redistribution layer according to an embodiment of this application;

[0053] Figure 8 A schematic diagram of the structure after providing through-holes in another multilayer redistribution layer according to an embodiment of this application;

[0054] Figure 9 This is a schematic diagram of a structure forming a multilayer wiring layer according to an embodiment of the present application;

[0055] Figure 10 This is a schematic diagram of a structure forming another multilayer wiring layer according to an embodiment of the present application;

[0056] Figure 11 This is a schematic diagram of a structure forming another multilayer wiring layer according to an embodiment of the present application;

[0057] Figure 12 This is a schematic diagram of a structure forming another multilayer wiring layer according to an embodiment of the present application;

[0058] Figure 13 This is a schematic diagram of a structure forming another multilayer wiring layer according to an embodiment of the present application;

[0059] Figure 14 This is a schematic diagram of a structure forming another multilayer wiring layer according to an embodiment of the present application;

[0060] Figure 15 This is a schematic diagram of a chip packaging structure provided in an embodiment of this application;

[0061] Figure 16 This is a schematic diagram of a main process for manufacturing a chip packaging structure according to an embodiment of this application;

[0062] Figure 17 This is a schematic diagram of a sub-process for manufacturing a chip packaging structure according to an embodiment of this application;

[0063] Figure 18 This is a schematic diagram of another sub-process for manufacturing a chip packaging structure according to an embodiment of this application.

[0064] Explanation of reference numerals in the attached figures:

[0065] 1000, Chip package structure; 100, Chip layer; 110, Chip; 120, Molded part; 200, Intermediate layer; 300, Redistribution layer; 310, First redistribution layer; 320, Second redistribution layer; 330, Metallized pattern; 400, Connector; 410, Bolt; 420, Nut; 500, Heat sink; 600, Substrate; 700, Electronic component; 800, Temporary bonding adhesive; 900, Glass; K1, Through hole; K2, Blind hole; M, Molded protective layer. Detailed Implementation

[0066] In the packaging process, complex chip package structures may contain silicon (Si), glass, polyimide (PI), and some metals simultaneously in the semi-finished product. Creating vias in such complex chip packages is problematic because the complex structure needs to be bonded to the glass during fabrication. Directly penetrating the chip package along its thickness using a laser to form vias can easily damage other structures (such as the glass) on the side of the redistribution layer away from the interposer, resulting in damage or scrapping of the entire package. Conversely, mechanically drilling vias in a single pass can easily damage the silicon interposer and the package body, which is typically made of polyimide.

[0067] In view of this, this application provides a chip packaging structure and a method for manufacturing the same. The multilayer redistribution layer in the chip packaging structure can block lasers from directly passing through the chip packaging structure, thereby preventing damage or scrapping of the chip packaging structure.

[0068] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0069] For ease of understanding, the length direction of the chip package structure 1000 is defined as the X-axis direction, the width direction of the chip package structure 1000 is defined as the Y-axis direction, and the thickness direction of the chip package structure 1000 is defined as the Z-axis direction.

[0070] Please see Figure 1 The chip package structure 1000 includes, along its thickness direction, multiple redistribution layers 300, an interposer layer 200, and a chip layer 100. The chip layer 100 includes at least one chip 110 and a molding portion 120. The molding portion 120 fills the gaps between the multiple chips 110 and fixes the chips 110 onto the interposer layer 200, thereby improving the structural strength of the chip package structure 1000.

[0071] Intermediate layer 200 can be a silicon interposer with surface traces and through-silicon vias (TSVs).

[0072] In the embodiments provided in this application, the chip package structure 1000 has a through-hole K1 extending through the chip package structure 1000 along its thickness direction. The through-hole K1 penetrates the chip layer 100, the interposer layer 200, and the multilayer redistribution layer 300. A connector 400 passes through the through-hole K1, and the portions of the connector 400 extending out of the through-hole K1 are connected to the heat sink 500 in the chip package structure 1000. The connector 400 is used to fix the heat sink 500 located on both sides of the chip package structure 1000 in its thickness direction. The connector 400 is also used to fasten other electronic devices 700 in the chip package structure 1000. The heat sink 500 can dissipate heat from the chip layer 100, the interposer layer 200, the multilayer redistribution layer 300, and the other electronic devices 700 in the chip package structure 1000. The diameter of the through-hole K1 is less than or equal to 4 mm.

[0073] The inner wall of the through hole K1, which penetrates the chip layer 100 and the interposer layer 200, is provided with a molding protective layer M. The molding protective layer M serves to protect the interposer layer 200 and the chip layer 100 and prevent the connector 400 from damaging the interposer layer 200 and the chip layer 100.

[0074] In the embodiments provided in this application, the chip package structure 1000 includes two heat sinks 500. In the thickness direction of the chip package structure 1000, the chip layer 100, the interposer layer 200, and the multilayer redistribution layer 300 are located between the two heat sinks 500. A through-hole K1 is provided with a connector 400. (See also...) Figure 1 and Figure 2 The connector 400 includes a bolt 410 and two nuts 420. The bolt 410 passes through a through hole K1, and its two ends extending out of the through hole K1 are threadedly connected to the two nuts 420 respectively. Two heat sinks 500 are located between the two nuts 420. The area where the through hole K1 is located in the multilayer redistribution layer 300 refers to location region A. The area extending along the thickness direction of the chip package structure 1000 where the two nuts 420 are located can be location region A. Any location of the chip package structure extending in the thickness direction can be location region A. This application requires that the location of the through hole K1 is within location region A, but does not specifically limit the location of the chip package structure 1000 within location region A. The two heat sinks 500 of this application can dissipate heat from the chip layer 100, the interposer layer 200, and the multilayer redistribution layer 300. For example, the heat generated by electronic components such as chip 110 is conducted to the heat sink 500, which has good thermal conductivity and dissipates heat from the electronic components such as chip 110.

[0075] The chip package structure 1000 also includes a substrate 600 and electronic devices 700, and the number of electronic devices 700 can be multiple. When the chip package structure 1000 is a finished product, the glass bonded to the chip package structure 1000 needs to be removed. The substrate 600 is connected to the side of the multilayer redistribution layer 300 facing away from the interposer layer 200, and the electronic devices 700 are connected to the side of the substrate 600 away from the multilayer redistribution layer 300. The substrate 600 can be electrically connected to the chip 110 in the chip layer 100 through the multilayer redistribution layer 300. The substrate 600 also serves to support and protect the chip 110, facilitates heat dissipation of the chip 110, and facilitates the assembly of the chip package structure 1000. In the embodiments provided in this application, the chip 110 of the chip layer 100 can be electrically connected to the electronic devices 700 through the substrate 600. For example, chip 110 in chip layer 100 is connected to substrate 600 via redistribution layer 300. Substrate 600 can be connected to electronic device 700, thus enabling connection between chip 110 and electronic device 700. The side of electronic device 700 away from substrate 600 contacts one of two heat sinks 500. The two heat sinks 500 can dissipate heat for chip layer 100, interposer layer 200, multilayer redistribution layer 300, substrate 600, and electronic device 700. The two heat sinks 500 can clamp chip layer 100, interposer layer 200, multilayer redistribution layer 300, substrate 600, and electronic device 700 via connector 400. This not only dissipates heat for chip layer 100, interposer layer 200, multilayer redistribution layer 300, substrate 600, and electronic device 700, but also secures chip layer 100, interposer layer 200, multilayer redistribution layer 300, substrate 600, and electronic device 700.

[0076] Please see Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 In the region where the via K1 is located in the multilayer redistribution layer 300, the gap of one redistribution layer 300 is covered by the projection of the metallization pattern 330 of another redistribution layer 300 in the thickness direction of the chip package structure 1000. It should be noted that the two redistribution layers here (one redistribution layer and another redistribution layer) can be two adjacent redistribution layers or two non-adjacent redistribution layers.

[0077] The multilayer redistribution layer is electrically connected to the chip through through-silicon vias. It should be noted that the multilayer redistribution layer is stacked along the thickness direction of the chip package structure. Each redistribution layer consists of multiple metallization patterns. The multiple metallization patterns that make up a redistribution layer are roughly located on the same plane. The metallization patterns in different redistribution layers are located on different planes.

[0078] Each redistribution layer 300 includes multiple metallized patterns 330, which are spaced apart to form gaps. The metallized patterns 330 can be metals with good conductivity, such as copper, titanium, gold, and aluminum. They can also be alloys formed from some of these metals, or combinations of copper, titanium, gold, and aluminum layers. It should be noted that the metallized patterns can be formed by depositing metal layers to create the metal wiring structure, by depositing a metal layer and a dielectric layer, or by etching. The metallized patterns 330 can achieve electrical connection with the chip. The structure of the metallized patterns can be elongated, block-shaped, or have other structural forms. This application does not specifically limit the structural form of the metallized patterns 330.

[0079] Before forming vias in the chip package structure 1000, a location region A is determined on the multilayer redistribution layer 300, and then a via K1 is formed in location region A. Location region A is the region where the via K1 is located in the multilayer redistribution layer 300. The projected area of ​​location region A in the thickness direction of the chip package structure 1000 is greater than the projected area of ​​via K1 in the thickness direction of the chip package structure 1000.

[0080] In the region where a via is located within a multi-layer redistribution layer, the gap in one redistribution layer is covered by the projection of the metallized pattern of another redistribution layer onto the thickness of the chip package structure. When a via is provided that penetrates the chip package structure along its thickness, the multi-layer redistribution layer can block the laser, preventing it from penetrating the entire chip package structure and causing damage. For example, when a via is provided along the chip package structure, the laser penetrates the chip layer and the interposer layer sequentially. The multi-layer redistribution layer can block the laser from penetrating the entire chip package structure, preventing damage to other structures on the side of the multi-layer redistribution layer away from the interposer layer.

[0081] In the chip package structure 1000 provided in this application, after the via K1 is formed, some of the metallized patterns 330 of the multilayer redistribution layers 300 located in the position region A may be removed. To distinguish whether the gap between one layer of redistribution layers 300 in the position region A is covered by the projection of the metallized patterns 330 of another layer of redistribution layers 300 in the thickness direction of the chip package structure 1000, one can examine the multiple metallized patterns 330 surrounding the periphery of the via K1 to see if the gap between adjacent metallized patterns of one layer of redistribution layers 300 is covered by the projection of the metallized patterns 330 of another layer of redistribution layers 300 in the thickness direction of the chip package structure 1000. In this application, if the diameter of the via K1 is 4mm, the position region A can be a circular region with a diameter greater than 4mm. The diameter of the position region A can specifically be 4.1mm, 4.5mm, 5mm, or 6mm. This application does not specifically limit the size of the diameter of the position region A. Location area A can be a rectangle with an area larger than the through hole, with a length greater than 4mm and a width greater than 4mm. Location area A can also be other regular shapes with an area larger than the through hole, or it can be an irregular shape with an area larger than the through hole.

[0082] In this application, at least in location region A, the multilayer redistribution layer 300 is misaligned so that, along the thickness direction of the chip package structure, the laser cannot penetrate the multilayer redistribution layer 300 and damage other structures on the side of the multilayer redistribution layer 300 away from the interposer layer 200.

[0083] During the manufacturing process of the chip package structure 1000, the multilayer redistribution layers 300 of the chip package structure 1000 are bonded to the glass using temporary bonding (TB) adhesive. When a blind via is formed on the chip package structure 1000 using a laser, the laser beam is directed at the chip package structure 1000 from the side of the chip layer 100 away from the interposer layer 200. The laser beam penetrates the chip layer 100 and the interposer layer 200. The multilayer redistribution layers 300 can block the laser beam from penetrating the chip package structure 1000, preventing the laser from debonding the redistribution layer 300 furthest from the interposer layer 200 from the glass, thus preventing the chip package structure 1000 from debonding from the glass and losing its structure, thereby protecting the chip package structure 1000.

[0084] In the embodiments provided in this application, there may be no gap between adjacent redistribution layers 300 in the thickness direction (Z-axis direction) of the chip packaging structure.

[0085] Please participate Figure 9In one possible implementation, the multilayer redistribution layer 300 includes a first redistribution layer 310 and a second redistribution layer 320, which are stacked together. The side of the second redistribution layer 320 away from the first redistribution layer 310 is connected to the side of the interposer layer 200 away from the chip layer 100. The first redistribution layer 310 includes a plurality of metallized patterns 330 spaced apart along the width direction of the chip package structure 1000, and the second redistribution layer 320 includes metallized patterns 330 spaced apart along the width direction of the chip package structure 1000. The metallized patterns 330 in both the first redistribution layer 310 and the second redistribution layer 320 can be strip-shaped. Specifically, the metallized patterns 330 in the first redistribution layer 310 are evenly spaced and parallel in the width direction of the chip package structure 1000, and the metallized patterns 330 in the second redistribution layer 320 are evenly spaced and parallel in the width direction of the chip package structure 1000. In the second redistribution layer 320, the metallization pattern 330 covers the gaps between adjacent metallization patterns 330 in the first redistribution layer 310 along the thickness direction of the chip package structure 1000. When a blind via is formed in the chip package structure 1000 using a laser, the laser can pass through the chip layer 100 and the interposer layer 200. However, because the metallization pattern 330 of the second redistribution layer 320 covers the gaps between adjacent metallization patterns 330 in the first redistribution layer 310 along the thickness direction of the chip package structure 1000, it can block the laser from passing through the first redistribution layer 300 and the second redistribution layer 300, thereby preventing the laser from damaging other structures on the side of the multiple redistribution layers 300 away from the interposer layer 200 in the chip package structure 1000.

[0086] In the chip package structure 1000 provided in this application, a metallized pattern 330 in the second wiring layer 320 covers the gap between two adjacent metallized patterns 330 in the second wiring layer 320 along the width direction of the chip package structure 1000. The gap size between adjacent metallized patterns 330 in the first wiring layer 310 is smaller than the size of the metallized pattern 330 in the second wiring layer 320 along the width direction of the chip package structure 1000. The size of the metallized pattern 330 in the second wiring layer 320 in the width direction of the chip package structure 1000 can be equal to the size of the metallized pattern 330 in the first wiring layer 310 in the width direction of the chip package structure 1000.

[0087] In the embodiments provided in this application, the dimensions of the first redistribution layer 310 and the second redistribution layer 320 in the thickness direction of the chip package structure 1000 are 1μm to 50μm. The dimensions of the metallized pattern 330 in the first redistribution layer 310 in the thickness direction of the chip package structure 1000 are 1μm to 50μm, and the dimensions of the metallized pattern 330 in the second redistribution layer 320 in the thickness direction of the chip package structure 1000 are 1μm to 50μm. The metallized pattern 330 in the redistribution layer 300 can meet the power supply requirements and the processing requirements.

[0088] Because the thickness of the metallized pattern 330 in the chip package structure 1000 is relatively small, it is difficult to process it into a single redistribution layer 300 with a large width and length. In the embodiments provided in this application, the dimension of the metallized pattern 330 in the first redistribution layer 310 along the width direction of the chip package structure 1000 is less than or equal to 200 μm, and the gap between any two adjacent metallized patterns 330 in the first redistribution layer 310 is less than or equal to 200 μm; the dimension of the metallized pattern 330 in the second redistribution layer 320 along the width direction of the chip package structure 1000 is less than or equal to 200 μm.

[0089] For example, please see Figure 10 The number of redistribution layers 300 can be three, and the three redistribution layers 300 are stacked sequentially along the thickness direction of the chip package structure. The redistribution layer 300 furthest from the interposer layer 200 among the three redistribution layers 300 is defined as the first redistribution layer 300, the layer connected to the first redistribution layer 300 is the second redistribution layer 300, and the layer connected to the second redistribution layer 300 is the last redistribution layer 300. Within location region A, the metallization pattern 330 in the second redistribution layer 300 covers part of the gap in the first redistribution layer in the thickness direction of the chip package structure 1000, and the last redistribution layer 300 covers the remaining gap in the first redistribution layer 300 in the thickness direction.

[0090] Please see Figure 11 , Figure 12 , Figure 13 and Figure 14 For example, the redistribution layer 300 can be four layers, which are stacked sequentially along the thickness direction of the chip package structure 1000. The redistribution layer 300 furthest from the interposer layer 200 among the four redistribution layers 300 is defined as the first redistribution layer 300. The metallization pattern 330 of the redistribution layer 300 located between the redistribution layer and the interposer layer 200 in the first redistribution layer covers the gap between the metallization pattern 330 in the first redistribution layer and the metallization pattern 330.

[0091] It should be noted that the redistribution layer 300 can also have four or more layers. For example, the redistribution layer 300 can have 5, 6, 7, 8 or 9 layers. This application does not limit the specific number of layers in the redistribution layer 300.

[0092] In the embodiments provided in this application, when the multilayer redistribution layer 300 has three or more layers, the metallization pattern 330 of each redistribution layer 300 can be block-shaped, and multiple metallization patterns 330 are arranged in an array. The cross-section of the metallization pattern 330 along the thickness direction can be rectangular, square, circular, etc., and this application does not limit the specific shape of the metallization pattern 330. The multiple metallization patterns 330 include multiple columns of metallization patterns 330 arranged at intervals along the length direction of the chip package structure 1000, with gaps between adjacent columns of metallization patterns 330. Each column of metallization patterns 330 includes multiple metallization patterns 330 arranged at intervals along the width direction of the chip package structure 1000.

[0093] In two adjacent redistribution layers 300, the gap between two adjacent columns of metallized patterns 330 along the length direction of the chip package structure 1000 in one redistribution layer 300 is less than or equal to the size of the metallized pattern 330 along the length direction of the chip package structure 1000 in the other redistribution layer 300; in two adjacent redistribution layers 300, the gap between two adjacent metallized patterns 330 along the width direction of the chip package structure 1000 in one redistribution layer 300 is less than or equal to the size of the metallized pattern 330 along the width direction of the chip package structure 1000 in the other redistribution layer 300.

[0094] The redistribution layers are stacked with staggered metallization patterns 330 in each redistribution layer. In the redistribution layer 300 located in position region A and furthest from the interposer layer 200, the gap between any two adjacent metallization patterns 330 arranged in the length direction of the chip package structure 1000 is covered by the metallization patterns 330 of other redistribution layers 300, and the gap between any two adjacent metallization patterns 330 arranged in the width direction of the chip package structure 1000 is also covered by the metallization patterns 330 of other redistribution layers 300. When the chip package structure 1000 is burned by laser to form blind vias, the multi-layer redistribution layer 300 can block the laser, preventing the laser from passing through the multi-layer redistribution layer 300 and acting on the temporary bonding adhesive, thus debonding the chip package structure 1000 from the glass. The multi-layer redistribution layer 300 can also prevent the laser from directly acting on other structures on the side of the multi-layer redistribution layer 300 away from the interposer layer 200, thereby damaging the entire chip package structure 1000.

[0095] Please see Figure 15 , Figure 16 , Figure 17 and Figure 18This application also discloses a method for manufacturing the chip package structure 1000. Figure 16 The manufacturing methods include:

[0096] S100 provides multiple redistribution layers, interposer layers and chip layers stacked sequentially, each redistribution layer having multiple metallization patterns with gaps;

[0097] S200, so that in two adjacent redistribution layers, the gap between the metallization patterns in one redistribution layer is covered by the projection of the metallization patterns in the other redistribution layer in the thickness direction of the chip package structure.

[0098] S300, through the chip layer, interposer layer and multiple redistribution layers to form a via.

[0099] In the embodiments provided in this application, when providing multiple redistribution layers, interposers and chip layers stacked sequentially, specifically multiple redistribution layers, interposers and chip layers are stacked sequentially on the glass, and the redistribution layer closest to the glass in the multiple redistribution layers is connected to the glass by temporary bonding adhesive.

[0100] Figure 17 In this context, the multi-layer rewiring layer includes a first rewiring layer and a second rewiring layer stacked together.

[0101] It provides a configuration of multiple layers of redistribution layers, interposer layers, and chip layers stacked sequentially, including:

[0102] S101 provides multiple spaced metallic patterns to form a first overlay layer;

[0103] S102, a plurality of spaced metallized patterns are set on the first wiring layer to form a second wiring layer, wherein the metallized patterns in the second wiring layer cover the gaps between adjacent metallized patterns in the first wiring layer.

[0104] S103, An intermediary layer is provided on the side of the second wiring layer facing away from the first wiring layer;

[0105] S104, a chip layer is disposed on the side of the interposer that faces away from the second wiring layer.

[0106] The second wiring layer is formed by setting multiple spaced metallization patterns on the first wiring layer, including: in the width direction of the chip package structure, the size of the metallization patterns in the second wiring layer is greater than or equal to the gap size between adjacent metallization patterns in the first wiring layer.

[0107] Provides a multi-layer redistribution layer, an interposer layer, and a chip layer stacked sequentially, including:

[0108] A multilayer redistribution layer is formed by stacking the layers sequentially. Each redistribution layer includes multiple columns of metallized patterns arranged at intervals along the length direction of the chip package structure. Each column of metallized patterns includes multiple metallized patterns arranged at intervals along the width direction of the chip package structure. The gap between two adjacent columns of metallized patterns is covered by the projection of the metallized patterns of other redistribution layers in the thickness direction of the chip package structure. The gap between two adjacent metallized patterns in each column of metallized patterns is covered by the projection of the metallized patterns of other redistribution layers in the thickness direction of the chip package structure. The gap between adjacent metallized patterns in the bottommost layer of the multilayer redistribution layer in the stacking direction is blocked by the metallized patterns of other redistribution layers.

[0109] An intermediate layer is formed on the side of the topmost layer away from the bottommost layer in the stacking direction of multi-layer rewiring;

[0110] The chip layer is placed on the side of the interposer that is away from the multilayer redistribution layer.

[0111] Forming a multilayer redistribution layer stacked sequentially includes: in two adjacent redistribution layers, the gap between two adjacent columns of metallized patterns in one redistribution layer is less than or equal to the dimension of the metallized pattern in the other redistribution layer along the length direction of the chip package structure; the gap between two adjacent metallized patterns in each column of metallized patterns is less than or equal to the dimension of the metallized pattern in the other redistribution layer along the width direction of the chip package structure.

[0112] Figure 18 In this process, vias are formed by penetrating the chip layer, the interposer layer, and multiple redistribution layers, including:

[0113] S301, by laser burning of the chip layer, the interposer layer and the multiple redistribution layers, a blind via is formed in the chip package structure that penetrates the chip layer and the interposer layer but does not penetrate the multiple redistribution layers;

[0114] S302, filling molding material in blind holes;

[0115] S303 is formed by mechanically drilling through multiple redistribution layers and molding material to create through-holes.

[0116] In the embodiments provided in this application, before filling the blind via K2 with molding material and forming the through via K1 by mechanical drilling through multiple redistribution layers and molding material, the glass 900 is removed, the chip package structure 1000 is inverted, and the through via K1 is formed on the chip package structure by mechanical drilling.

[0117] When forming a through hole K1 by mechanically drilling through multiple redistribution layers 300 and molding material, the diameter of the through hole K1 is controlled so that the diameter of the through hole K1 is smaller than the diameter of the blind hole K2, so that the molding material filling the blind hole K2 serves as a molding protective layer M.

[0118] When the laser creates the blind via K2, the multilayer redistribution layers can block the laser from passing through them. In one possible implementation, during the manufacturing process of the chip package structure 1000, the middle redistribution layer furthest from the interposer layer 200 in the multilayer redistribution layers 300 is the first redistribution layer 300, which is also the lowest redistribution layer in the multilayer redistribution layers. The side of the first redistribution layer 300 furthest from the interposer layer 200 is connected to the glass 900 by temporary bonding adhesive 800. In the first redistribution layer 300 along the thickness direction, the gap between two adjacent metallized patterns 330 is covered by the metallized patterns 330 of other redistribution layers 300 in the multilayer redistribution layers 300. When the via K1 is formed in the chip package structure, the laser cannot easily pass through the multilayer redistribution layers 300 to debond the chip package structure and the glass 900. Debonding the chip package structure and the glass 900 by the laser can easily damage the chip package structure.

[0119] In the embodiments provided in this application, during mechanical drilling, the material passes through the multilayer redistribution layer 300 and then through the molding material filling the blind hole K2.

[0120] In the embodiments provided in this application, during the formation of the via K1, a blind via K2 is first created by laser. The blind via K2 penetrates the chip layer 100 and the interposer layer 200. The transition structure formed by the combination of the multilayer redistribution layer 300 can prevent the laser from penetrating the entire chip package structure 1000 and damaging other structures (such as glass that has not been removed during the packaging process) on the side of the multilayer redistribution layer 300 away from the interposer layer 200.

[0121] After forming a blind via K2 on the chip packaging structure, molding material is filled into the blind via K2, and then mechanical drilling is performed to pass through multiple redistribution layers 300 and the molding material in the blind via K2 in one go, thereby forming a through via K1.

[0122] It should be noted that for a complex chip package structure 1000, forming a through hole K1 on the chip package structure 1000 using a drilling method can easily damage the chip package structure 1000. For example, using a laser to directly drill through the chip package structure 1000 can easily damage other structures on the side of the multilayer redistribution layer 300 facing away from the interposer layer 200 (such as glass that has not been removed during the packaging process), thereby damaging the entire chip package structure 1000. On the other hand, using mechanical one-time drilling can easily damage the interposer layer 200 and the chip layer 100 of the chip package structure 1000.

[0123] In the embodiments provided in this application, when forming a through-hole by mechanically drilling through the multilayer redistribution layer and the molding material filled in the blind via K2, the diameter of the through-hole is smaller than the diameter of the blind via K2, so that the molding material filling the blind via K2 serves as a molding protective layer. The diameter of the blind via K2 is larger than the diameter of the through-hole K1. It can be understood that the through-hole K1 can be divided into a first segment and a second segment. The first segment is formed on the molding material, which forms the inner wall of the first segment. During mechanical drilling, the molding material can protect the chip layer 100 and the interposer layer 200 to prevent damage to the chip 110 and the interposer layer 200 in the chip layer 100 during mechanical drilling. The diameter of the blind via K2 is larger than the diameter of the through-hole K1, and the remaining molding material in the blind via K2 serves as a molding protective layer, which protects the interposer layer 200.

[0124] This application also discloses an electronic device, which includes a circuit board and a chip package structure disposed on the circuit board, the chip package structure being electrically connected to the circuit board.

[0125] The terms "first," "second," "third," "fourth," and various numerical designations used herein are merely for descriptive convenience and are not intended to limit the scope of this application.

[0126] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0127] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A chip packaging structure, characterized in that, The chip packaging structure includes multiple redistribution layers, interposer layers, and chip layers stacked along the thickness direction of the chip packaging structure; each redistribution layer includes multiple metallization patterns, with gaps between adjacent metallization patterns; the chip packaging structure has vias penetrating the chip layer, interposer layers, and multiple redistribution layers along the thickness direction; in the region where the vias are located in the multiple redistribution layers, the gap in one redistribution layer is covered by the projection of the metallization pattern of another redistribution layer onto the thickness direction of the chip packaging structure.

2. The chip packaging structure as described in claim 1, characterized in that, The multilayer redistribution layer includes a first redistribution layer and a second redistribution layer stacked together. The side of the second redistribution layer opposite to the first redistribution layer is connected to the interposer layer. The first redistribution layer includes a plurality of metallized patterns spaced apart along the width direction of the chip package structure. The second redistribution layer includes a plurality of metallized patterns spaced apart along the width direction of the chip package structure. The gaps in the first redistribution layer are covered by the projection of the metallized patterns in the second redistribution layer onto the thickness direction of the chip package structure.

3. The chip packaging structure as described in claim 2, characterized in that, In the region where the via is located in the multilayer redistribution layer, a metallization pattern in the second redistribution layer covers the gap between two adjacent metallization patterns in the first redistribution layer along the width direction of the chip package structure. The gap size between adjacent metallization patterns in the first redistribution layer is less than or equal to the size of the metallization pattern in the second redistribution layer along the width direction of the chip package structure.

4. The chip packaging structure as described in claim 2, characterized in that, The size of the metallized pattern in the first wiring layer along the width direction of the chip package structure is less than or equal to 200 μm, and the gap between any two adjacent metallized patterns in the first wiring layer is less than or equal to 200 μm; the size of the metallized pattern in the second wiring layer along the width direction of the chip package structure is less than or equal to 200 μm, and the gap between any two adjacent metallized patterns in the second wiring layer is less than or equal to 200 μm.

5. The chip packaging structure as described in claim 1, characterized in that, In the region where the via is located in the multilayer redistribution layer, each redistribution layer includes multiple columns of metallized patterns spaced apart along the length direction of the chip package structure, and each column of metallized patterns includes multiple metallized patterns spaced apart along the width direction of the chip package structure; in the redistribution layer furthest from the interposer layer, the gap between two adjacent columns of metallized patterns is covered by the projection of the metallized patterns of other redistribution layers in the thickness direction of the chip package structure, and the gap between two adjacent metallized patterns in each column of metallized patterns is covered by the projection of the metallized patterns of other redistribution layers in the thickness direction of the chip package structure.

6. The chip packaging structure as described in claim 5, characterized in that, In two adjacent redistribution layers, the gap between two adjacent columns of metallized patterns in one redistribution layer is less than or equal to the dimension of the metallized patterns in the other redistribution layer along the length direction of the chip package structure; the gap between two adjacent metallized patterns in each column of metallized patterns is less than or equal to the dimension of the metallized patterns in the other redistribution layer along the width direction of the chip package structure.

7. The chip packaging structure according to any one of claims 1-6, characterized in that, The thickness of each redistribution layer is 1μm-50μm.

8. The chip packaging structure according to any one of claims 1-7, characterized in that, A molded protective layer is provided on the inner wall of a section of the via that penetrates the chip layer, the interposer layer, and the multilayer redistribution layer.

9. The chip packaging structure as described in claim 1, characterized in that, The chip packaging structure also includes two heat sinks and a connector. In the thickness direction of the chip packaging structure, the chip layer, the interposer layer, and the multilayer redistribution layer are located between the two heat sinks. The connector passes through the through-hole and is used to connect the two heat sinks.

10. The chip packaging structure as described in claim 9, characterized in that, The chip packaging structure also includes a substrate and electronic devices located between the two heat sinks. The substrate is connected to the side of the multilayer redistribution layer opposite to the interposer, and the electronic devices are connected to the side of the substrate opposite to the multilayer redistribution layer.

11. The chip packaging structure according to any one of claims 1-10, characterized in that, The chip layer includes multiple chips and a molded portion. The multiple chips are spaced apart and arranged on the surface of the interposer layer facing away from the multilayer redistribution layer, and the molded portion fills the gaps between the multiple chips.

12. A method for manufacturing a chip packaging structure, characterized in that, include: It provides a multi-layer redistribution layer, an interposer layer and a chip layer stacked sequentially, with each redistribution layer having multiple metallization patterns with gaps; In two adjacent redistribution layers, the gap between the metallization patterns in one redistribution layer is covered by the projection of the metallization patterns in the other redistribution layer onto the thickness direction of the chip package structure. Vias are formed by penetrating the chip layer, interposer layer, and multiple redistribution layers.

13. The manufacturing method as described in claim 12, characterized in that, A multi-layer rewiring layer includes a first rewiring layer and a second rewiring layer stacked together; The provision of multiple layers of redistribution layers, interposer layers, and chip layers stacked sequentially includes: Multiple intervals are provided to set the metallized patterns to form the first rewiring layer; Multiple spaced metallized patterns are set on the first wiring layer to form a second wiring layer, wherein the metallized patterns in the second wiring layer cover the gaps between adjacent metallized patterns in the first wiring layer. The intermediate layer is disposed on the side of the second wiring layer opposite to the first wiring layer; The chip layer is disposed on the side of the interposer layer opposite to the second redistribution layer.

14. The manufacturing method as described in claim 13, characterized in that, The step of forming a second wiring layer by setting multiple spaced metallized patterns on the first wiring layer includes: In the width direction of the chip package structure, the size of the metallized pattern in the second overlay layer is greater than or equal to the gap size between adjacent metallized patterns in the first overlay layer.

15. The manufacturing method as described in claim 12, characterized in that, The multilayer redistribution layer, interposer layer, and chip layer provided in sequence include: A multilayer redistribution layer is formed by stacking the layers sequentially. Each redistribution layer includes multiple columns of metallized patterns spaced apart along the length direction of the chip package structure. Each column of metallized patterns includes multiple metallized patterns spaced apart along the width direction of the chip package structure. The gap between two adjacent columns of metallized patterns is covered by the projection of the metallized patterns of other redistribution layers in the thickness direction of the chip package structure. The gap between two adjacent metallized patterns in each column of metallized patterns is covered by the projection of the metallized patterns of other redistribution layers in the thickness direction of the chip package structure. The gap between adjacent metallized patterns in the bottommost layer of the multilayer redistribution layer in the stacking direction is blocked by the metallized patterns of other redistribution layers. The intermediate layer is formed on the side of the uppermost layer away from the lowermost layer in the stacking direction of the multi-layer rewiring; The chip layer is disposed on the side of the interposer layer away from the multilayer redistribution layer.

16. The manufacturing method as described in claim 15, characterized in that, The formation of the multi-layer redistribution layer, which is stacked sequentially, includes: In two adjacent redistribution layers, the gap between two adjacent columns of metallized patterns in one redistribution layer is less than or equal to the dimension of the metallized pattern in the other redistribution layer along the length direction of the chip package structure; the gap between two adjacent metallized patterns in each column of metallized patterns is less than or equal to the dimension of the metallized pattern in the other redistribution layer along the width direction of the chip package structure.

17. The manufacturing method as described in claim 12, characterized in that, The method of forming vias through the chip layer, interposer layer, and multiple redistribution layers includes: By laser ablation of the chip layer, the interposer layer, and the multilayer redistribution layer, blind vias are formed in the chip package structure that penetrate the chip layer and the interposer layer but do not penetrate the multilayer redistribution layer. The blind hole is filled with molding material; Through-holes are formed by mechanically drilling through the multilayer redistribution layer and the molding material.

18. The manufacturing method as described in claim 17, characterized in that, When forming a through-hole by mechanically drilling through multiple redistribution layers and molding material: Make the diameter of the through hole smaller than the diameter of the blind hole so that the molding material filling the blind hole acts as a molding protective layer.

19. An electronic device, characterized in that, It includes a circuit board and a chip package structure as described in any one of claims 1-11 disposed on the circuit board.

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