Semiconductor structure and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a structure layer having an interconnection region; a stack structure on the structure layer, comprising spaced dielectric layers and ultra-low-K dielectric layers stacked along a first direction, the first direction being a thickness direction of the structure layer; a low-K dielectric layer penetrating through the stack structure along the first direction; and a conductive channel penetrating through the low-K dielectric layer along the first direction and connected to the interconnection region. In a second direction perpendicular to the first direction, the size of the spaced dielectric layer is smaller than that of the ultra-low-K dielectric layer, forming a recess, and the low-K dielectric layer fills in the recess, forming a protrusion, so that the spaced dielectric layer, the ultra-low-K dielectric layer and the low-K dielectric layer form an interlocking structure. The semiconductor structure improves the overall mechanical strength of the dielectric layers by forming the interlocking structure with the recess and the protrusion.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor manufacturing, and in particular, to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] With the development of miniaturization of semiconductor components, the integration level is continuously improved, and the parasitic effect of resistance / capacitance in circuit wiring causes more and more serious RC delay. RC delay has a greater and greater impact on the speed of devices, and currently, the RC delay phenomenon can be improved by selecting a material with a low dielectric constant (Low K) to reduce parasitic capacitance.

[0003] However, with the decrease of the low dielectric constant, the mechanical strength of the dielectric layer is getting weaker and weaker, and in subsequent etching, polishing and other processes, delamination, cracking or peeling off is prone to occur, resulting in device failure. Therefore, the industry is facing the conformal problem of being difficult to balance “low K value” and “high mechanical strength” at the node of 28 nm and below, especially at the node of 14 nm and below. SUMMARY

[0004] In view of the above problems, a semiconductor structure and a manufacturing method thereof are to be proposed.

[0005] According to an aspect of the present disclosure, a semiconductor structure is provided, comprising:

[0006] a structure layer having an interconnection region;

[0007] a laminated structure located on the structure layer, comprising spaced dielectric layers and ultra-low K dielectric layers stacked along a first direction, the first direction being a thickness direction of the structure layer;

[0008] a low K dielectric layer penetrating through the laminated structure along the first direction; and

[0009] a conductive channel penetrating through the low K dielectric layer along the first direction and connected with the interconnection region,

[0010] wherein, along a second direction, the size of the spaced dielectric layer is smaller than the size of the ultra-low K dielectric layer to form a recess, and the low K dielectric layer is filled in the recess to form a protrusion so that the spaced dielectric layer, the ultra-low K dielectric layer and the low K dielectric layer form an interlocking structure,

[0011] the second direction is perpendicular to the first direction.

[0012] Optionally, the number of the layers of the ultra-low K dielectric layers is plural, the spacer dielectric layer is located between two adjacent layers of the ultra-low K dielectric layers, and / or the number of the layers of the ultra-low K dielectric layers and the number of the layers of the spacer dielectric layers are both plural, and the plural spacer dielectric layers and the plural ultra-low K dielectric layers are alternately stacked.

[0013] Optionally, the low-K dielectric layer is further located on the stack structure.

[0014] Optionally, a protective layer is further included and located between the stack structure and the low-K dielectric layer.

[0015] According to another aspect of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising:

[0016] forming a stack structure on a structure layer, the structure layer having an interconnection region, the stack structure comprising spacer dielectric layers and ultra-low K dielectric layers stacked along a first direction, the first direction being a thickness direction of the structure layer;

[0017] etching the stack structure to form a first recess;

[0018] forming a low-K dielectric layer in the first recess;

[0019] etching the low-K dielectric layer to form a second recess; and

[0020] forming a conductive via in the second recess, the conductive via being connected to the interconnection region,

[0021] wherein along a second direction, the etching rate of the spacer dielectric layers is greater than the etching rate of the ultra-low K dielectric layers, so as to form a recess at a sidewall of the first recess, and the low-K dielectric layer forms a protrusion at the recess so that the spacer dielectric layers, the ultra-low K dielectric layers and the low-K dielectric layer constitute an interlocking structure,

[0022] the second direction is perpendicular to the first direction.

[0023] Optionally, the step of forming a low-K dielectric layer in the first recess comprises:

[0024] providing oxygen radicals in plasma form and a silicon, oxygen, carbon, hydrogen containing precursor in plasma form into a reaction chamber;

[0025] the oxygen radicals react with the silicon, oxygen, carbon, hydrogen containing precursor to form a flowable low-K dielectric layer and deposit the flowable low-K dielectric layer in the first recess; and

[0026] curing the low-K dielectric layer.

[0027] Optionally, the low-K dielectric layer is further located on the stack structure, and a chemical mechanical polishing of a conductive filling layer for forming the conductive channel is stopped on the low-K dielectric layer on the stack structure.

[0028] Optionally, before forming the low-K dielectric layer, the method further comprises forming a protective layer on the inner surface of the first recess,

[0029] Optionally, the low-K dielectric layer and the stack structure are separated by the protective layer.

[0030] Optionally, a carbon content in the spacer dielectric layer is less than a carbon content in the ultra-low-K dielectric layer, so that a rate of etching the spacer dielectric layer along the second direction is greater than a rate of etching the ultra-low-K dielectric layer.

[0031] Optionally, in the step of forming the first recess and the second recess, a photoresist is patterned by a full transparent part and a semi-transparent part of a half-tone mask, a photoetching mask is formed, and a structure below the photoetching mask is etched, so that a lower segment of the first recess and the second recess has a width less than an upper segment.

[0032] One of the above technical solutions has the following unexpected technical effects:

[0033] By disposing the stacked spacer dielectric layer, the ultra-low-K dielectric layer, and the low-K dielectric layer penetrating the stack structure on the structure layer having the interconnection region, in the second direction perpendicular to the thickness direction of the structure layer, the size of the spacer dielectric layer is less than the size of the ultra-low-K dielectric layer to form a recess, the low-K dielectric layer fills in the recess to form a protrusion, so that the spacer dielectric layer, the ultra-low-K dielectric layer, and the low-K dielectric layer form an interlocking structure, the interlocking structure of the three composite dielectric layers can improve the overall mechanical strength of the dielectric layer, in the etching, polishing, and other processes, due to the improvement of the overall mechanical strength of the dielectric layer, the dielectric layer is not easy to be damaged, and due to the existence of the ultra-low-K dielectric layer and the low-K dielectric layer, the dielectric constant is kept in a relatively low range, so that the technical solution reduces the device parasitic capacitance while ensuring the mechanical strength of the device.

[0034] In some optional embodiments, oxygen radicals in the form of plasma and silicon, oxygen, carbon, and hydrogen containing precursors in the form of plasma are provided into the reaction chamber, since the oxygen in the reaction chamber exists in the form of oxygen plasma instead of oxygen gas, in the reaction process, a high temperature is not required, and the carbon elements in the ultra-low-K dielectric layer can be prevented from being oxidized.

[0035] In some optional embodiments, the low-K dielectric layer is separated from the stack structure by the protective layer, so that the carbon elements in the ultra-low-K dielectric layer are prevented from being oxidized in the process of forming the low-K dielectric layer.

[0036] In some optional embodiments, the low-K dielectric layer is also located on the stack structure. Since the dielectric constant of the low-K dielectric layer is greater than that of the ultra-low-K dielectric layer, the mechanical strength of the low-K dielectric layer is also greater than that of the ultra-low-K dielectric layer. When the conductive filling layer is subjected to chemical mechanical polishing, it is stopped on the low-K dielectric layer above the stack structure, which can protect the stack structure below from being damaged.

[0037] In some optional embodiments, when the first recess and the second recess are formed, the photoresist is first patterned through the full-transmission part and the semi-transmission part of the half-tone mask, a photoetching mask is formed, and the structure below is etched through the photoetching mask, so that the lower segment width of part of the first recess and the second recess is less than the upper segment width. Compared with the case where the upper and lower widths are consistent with the upper segment width as the standard, this scheme can increase the proportion of the ultra-low-K dielectric layer and further reduce the dielectric constant of the overall dielectric layer.

[0038] It should be noted that the above general description and the following detailed description are only exemplary and explanatory and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0039] The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application taken in conjunction with the accompanying drawings, in which:

[0040] Figure 1 A trend diagram of interconnection delay and gate delay of a semiconductor device in the related art is shown;

[0041] Figures 2 to 9 A cross-sectional structure diagram of a forming process of a semiconductor structure for an interconnection process according to an embodiment of the present disclosure is shown;

[0042] Figure 10 A schematic diagram of a semiconductor structure according to an embodiment of the present disclosure is shown.

[0043] Legend of reference signs: 101 - substrate; 102 - interconnection region; 110 - metal layer; 120 - barrier layer; 130 - stack structure; 131 - spacer dielectric layer; 132 - ultra-low-K dielectric layer; 140 - first hard mask layer; 150 - first photoetching mask; 152 - second photoetching mask; 160 - first recess; 161 - recess; 170 - protection layer; 180 - low-K dielectric layer; 181 - protrusion; 191 - stress buffer layer; 192 - second hard mask layer; 201 - second recess; 210 - conductive filling layer; 211 and 212 - conductive channel; 10 - interlayer dielectric layer. DETAILED DESCRIPTION

[0044] The present application will be described in greater detail with reference to the accompanying drawings. In the drawings, like reference numerals can be used to denote like elements throughout the various figures. Portions of the figures can not be drawn to scale. Additionally, certain portions of the figures can be exaggerated to illustrate aspects of the present disclosure.

[0045] Many particular details of the present disclosure, such as the structure, materials, dimensions, processing acts, and techniques of the devices, are described below to provide a more thorough understanding of the present disclosure. As will be appreciated by persons skilled in the art, the present disclosure can be practiced without using these specific details.

[0046] In the meantime, certain terms have been used throughout this patent document and claims to refer to certain claim components. As one skilled in the art will appreciate, different manufacturers can refer to a component by different names. This document does not intend to distinguish between components that differ in name but not in function. In the description and in the claims of the application, each of the words "comprise" "contain" and "include," and variations thereof, mean "including but not limited to."

[0047] In addition, it is to be appreciated that the use of certain terms or phrases in the present document and claims are not intended to exclude those terms or phrases from being used in the claims, unless otherwise indicated. Furthermore, the use of the terms "first," "second," "third," etc. are not intended to denote any order or precedence, but are used to distinguish one element from another.

[0048] The present application can be embodied in various forms, some of which will be described below.

[0049] Figure 1 A trend diagram showing the interconnect delay and gate delay of a semiconductor device in the related art is shown, where the horizontal axis represents the width of the gate in nanometers (nm); the left vertical axis represents the gate delay time in picoseconds (ps); the right vertical axis represents the interconnect delay time in picoseconds (ps); the solid line curve represents the trend of the interconnect delay as the width of the gate changes; and the dashed line curve represents the trend of the gate delay as the width of the gate changes.

[0050] Referring to Figure 1With the development of miniaturization of semiconductor components, the integration level is continuously improved, the width of the gate is gradually reduced, and the gate delay time is gradually reduced. However, the parasitic effect of resistance / capacitance in the circuit connection causes more and more serious interconnection delay, also known as resistance-capacitance delay (RC Delay), which will limit the working speed of the device. The trend of RC Delay is opposite to that of gate delay, that is, the higher the integration level, the greater the RC Delay. In the related art, the line resistance can be reduced by using metal copper to make the interconnection structure, and the parasitic capacitance can be reduced by selecting a material with low dielectric constant (Low K), thereby improving the RC Delay phenomenon.

[0051] When the width of the gate is at nodes such as 45 nm, 60 nm, and 90 nm, a carbon-doped dielectric layer and an interconnection metal are formed in the back-end-of-line process step of the semiconductor device. The dielectric constant k of the carbon-doped dielectric layer is 3±0.1, and the Young's modulus E of the carbon-doped dielectric layer is about 13 Gpa. The Young's modulus E represents the mechanical strength of the dielectric layer, and the smaller the value, the smaller the mechanical strength.

[0052] When the width of the gate is at nodes such as 22 nm and 28 nm, a carbon-doped porous dielectric layer and an interconnection metal are formed in the back-end-of-line process step of the semiconductor device. Due to the increase in porosity of the carbon-doped porous dielectric layer, the dielectric constant decreases, the dielectric constant k is 2.5±0.1, and the Young's modulus E of the carbon-doped porous dielectric layer is about 7.5 Gpa. The material of the carbon-doped porous dielectric layer belongs to a low-K dielectric material (the low-K dielectric material referred to in the present disclosure refers to a dielectric material with a dielectric constant K less than 4 and greater than or equal to 2.2).

[0053] When the width of the gate is further reduced, if only the porosity of the dielectric layer is simply increased to reduce the dielectric constant, for example, an ultra-low-K dielectric material (the ultra-low-K dielectric material referred to in the present disclosure refers to a dielectric material with a dielectric constant K less than 2.2) is used, the mechanical strength of the dielectric layer will be too small, so that a damaged part will occur in the etching, polishing, and other process steps. Therefore, in order to make the dielectric layer have sufficient mechanical strength when the width of the gate is less than 14 nm, it is necessary to use some dielectric materials with relatively high dielectric constant instead, in exchange for higher mechanical strength.

[0054] When the width of the gate is at nodes such as 5 nm, 7 nm, 10 nm, and 14 nm, a carbon-doped high-density dielectric layer and an interconnection metal are formed in the back-end-of-line process step of the semiconductor device. Since the carbon-doped high-density dielectric layer is very dense, its Young's modulus E is about 20 Gpa, so the mechanical strength is relatively large. However, the dielectric constant k of the carbon-doped high-density dielectric layer is about 2.8, which is increased compared with the carbon-doped porous dielectric layer, thereby increasing the RC Delay.

[0055] In view of the above problems, the present disclosure proposes a new semiconductor structure and a manufacturing method thereof.

[0056] Figures 2 to 9 A cross-sectional structure diagram of a semiconductor structure for forming an interconnection process is shown.

[0057] Referring to Figure 2 , a semiconductor structure with an interconnection region 102 is provided. The semiconductor structure includes a substrate 101 and one or more interlayer dielectric layers and metal interconnection layers between the interlayer dielectric layers on the substrate 101, and a conductive plug is formed in the interlayer dielectric layer. An inductor, a memory cell, a through silicon via, etc. can also be formed in the interlayer dielectric layer. Figure 2 In the embodiment, only one metal layer 110 on the substrate 101 is shown, and the material of the metal layer 110 is, for example, copper. The interconnection region 102 can be located on the metal layer 110, or on the conductive plug, the inductor, the memory cell, the through silicon via, etc.

[0058] In some other embodiments, the semiconductor structure with the interconnection region 102 can also be the substrate 101 and an epitaxial layer on the substrate 101, and the interconnection region 102 can be a doped region, a through silicon via, etc. located in the substrate 101, the epitaxial layer, or on the surface of the substrate 101, the epitaxial layer. The interconnection region 102 can also be a transistor gate, a resistor, a capacitor, a memory cell, etc. located on the surface of the substrate, the epitaxial layer.

[0059] Further, a stack structure 130 is formed on the metal layer 110 of the structure layer, and the stack structure 130 includes spacer dielectric layers 131 and ultra-low-K dielectric layers 132 stacked along a first direction, which is the thickness direction of the structure layer. In the embodiment, the number of the ultra-low-K dielectric layers 132 is two, and the spacer dielectric layer 131 is located between the two adjacent ultra-low-K dielectric layers 132. In some alternative embodiments, the spacer dielectric layer 131 is located at the bottom of the stack structure 130, and the ultra-low-K dielectric layer 132 is located on the spacer dielectric layer 131. In some other alternative embodiments, the spacer dielectric layer 131 and the ultra-low-K dielectric layer 132 are both multi-layered and stacked alternately.

[0060] The material of the spacer dielectric layer 131 includes a carbon-doped oxide layer. In some embodiments, the spacer dielectric layer 131 is a low-carbon oxide layer, which has a carbon content less than that of the ultra-low-K dielectric layer 132. The material of the ultra-low-K dielectric layer 132 is, for example, a porous dielectric material, including one or a combination of Si-based porous dielectric material, C-based porous dielectric material, and organic polymer porous dielectric material. The Si-based porous dielectric material includes, for example, silica aerogel, nanoporous silica, microporous silica, etc. The C-based porous dielectric material includes, for example, porous diamond material. The organic polymer porous dielectric material includes, for example, polyimide porous material, polyethylene porous material, polysilazane porous material. The material of the ultra-low-K dielectric layer 132 can also be one or a combination of SICO, porous SICOH, carbon, carbon aerogel, oxide aerogel. In the present embodiment, the dielectric constant K of the ultra-low-K dielectric layer 132 is not greater than 2.2. Preferably, the dielectric constant K of the ultra-low-K dielectric layer 132 is not greater than 2.

[0061] In some preferred embodiments, a barrier layer 120 is further formed between the metal layer 110 and the stack structure 130, for blocking diffusion of metal elements in the metal layer 110 into the stack structure 130, wherein the material of the barrier layer 120 includes SICN.

[0062] In some other preferred embodiments, a first hard mask layer 140 is further deposited on the stack structure 130, which is, for example, an oxide layer.

[0063] Further, a first lithography mask 150 is formed on the stack structure 130, as shown in Figure 2 .

[0064] In this step, photoresist is first coated on the first hard mask layer 140, and then the photoresist is patterned by the full-transmission and semi-transmission parts of the half-tone mask, to form the first lithography mask 150, wherein, Figure 2 the left side and the middle two are patterned by the full-transmission part; the left half of the right one is patterned by the semi-transmission part. See Figure 2 and Figure 3 , the first lithography mask 150 is the etching position of the first groove 160 in the subsequent step, and the left half of the right first lithography mask 150 also corresponds to the etching position of the first groove 160, but the etching depth is smaller due to the blocking of the first lithography mask 150.

[0065] Further, the stack structure 130 is etched to form the first groove 160, as shown in Figure 3 .

[0066] In this step, the first photo mask 150 is etched together to remove the first photo mask 150. In the second direction, the etching rate of the spacer dielectric layer 131 is greater than the etching rate of the ultra low K dielectric layer 132 to form a recess 161 or called a re-entrant structure at the sidewall of the first recess 160, wherein the second direction is perpendicular to the first direction. The first recess 160 can be a trench structure or a via structure, and the position corresponds to the interconnect region 102. The number of the first recess 160 is multiple, wherein the left half of the rightmost first recess 160 in the figure corresponds to the first photo mask 150 which is patterned by a semi-transparent part, so that the lower section width of the part of the first recess 160 is less than the upper section width. Figure 3

[0067] Further, a protective layer 170 is formed on the surface of the semiconductor structure, as shown in the figure. Figure 4 The protective layer 170 covers the inner surface of the first recess 160 and the first hard mask layer 140.

[0068] In this step, an organic metal compound OMCTS (octamethylcyclotetrasiloxane) is used as a reactant to form the protective layer 170, and the reaction does not involve oxygen, but the material of the protective layer 170 formed finally is silicon oxide, which is to prevent the carbon in the ultra low K dielectric layer 132 from being oxidized by oxygen during the reaction. The material of the protective layer 170 is not limited to silicon oxide, and also includes silicon nitride and other substances. In some other embodiments, the protective layer 170 can also not be formed.

[0069] Further, a low K dielectric layer 180 is formed, as shown in the figure. Figure 5 The low K dielectric layer 180 is located above the stack structure 130 to cover the protective layer 170, and fills in the first recess 160, and the low K dielectric layer 180 forms a protrusion 181 at the recess.

[0070] In this step, first, a remote plasma is used to provide oxygen radicals in the form of plasma and silicon, oxygen, carbon, hydrogen containing precursors in the form of plasma into the reaction chamber; then, the oxygen radicals react with the silicon, oxygen, carbon, hydrogen containing precursors to generate a flowable low K dielectric layer 180 and deposit in the first recess 160 and above the stack structure 130; finally, ultraviolet irradiation or annealing process solidifies the flowable low K dielectric layer 180. The reaction in the chamber is without oxygen, which is to prevent the carbon in the ultra low K dielectric layer 132 from being oxidized by oxygen during the reaction. The protective layer 170 is used to protect the stack structure 130 in this step, and separates the low K dielectric layer 180 from the stack structure.

[0071] ​The material of the low-K dielectric layer 180 is, for example, silicon dioxide doped with fluorine, carbon, hydrogen, or the like, amorphous carbon, or an organic polymer. In this embodiment, the low-K dielectric layer 180 includes, but is not limited to, a material deposited by an FCVD / ALD / HARP / HDP / spin-on process, including, but not limited to, porous SICOH (BD2) / non-porous SICO (BD1) / oxide, and the like, with a dielectric constant K of about 2.8. The adjacent portions of the spacer dielectric layer 131, the ultra-low-K dielectric layer 132, and the low-K dielectric layer 180 have a concave-convex interlocking structure, thereby improving the overall mechanical strength of the dielectric layer. In subsequent etching, polishing, and the like, the dielectric layer is less likely to be damaged due to the improved overall mechanical strength, thereby further ensuring the performance of the product. In addition, the dielectric constant K of the ultra-low-K dielectric layer 132 is not greater than 2, and the proportion of the ultra-low-K dielectric layer 132 is controlled, so that the dielectric constant k of the overall composite dielectric layer is not greater than 2.3, and even less than 2.2 or lower.

[0072] Further, a stress buffer layer 191 and a second hard mask layer 192 are formed on the low-K dielectric layer 180, as shown in Figure 6 The material of the buffer layer 191 includes, for example, one or a combination of an oxide layer, a TEOS layer, and a TIN layer, and the second hard mask layer 192 is, for example, an oxide layer. In some other embodiments, the buffer layer 191 and the second hard mask layer 192 can also not be formed.

[0073] Further, a second photoetching mask 152 is formed on the second hard mask layer 192, as shown in Figure 6

[0074] In this step, photoresist is first applied on the second hard mask layer 192, and then the photoresist is patterned by the full-transmission and semi-transmission portions of the half-tone mask, thereby forming the second photoetching mask 152. Among them, Figure 6 The left and middle two are patterned by the full-transmission portion; the left half of the right one is patterned by the semi-transmission portion. See Figure 6 and Figure 7 The space between the second photoetching masks 152 is the etching position of the second groove 201 in the subsequent step, and the left half of the left side of the second photoetching mask 152 also corresponds to the etching position of the second groove 201, but due to the blocking of the second photoetching mask 152, the etching depth is smaller.

[0075] Further, the second hard mask layer 192, the buffer layer 191, the low-K dielectric layer 180, and the barrier layer 120 are etched to form the second groove 201, as shown in Figure 7 ​As shown, in this step, the second photoetching mask 152 is etched together to remove the second photoetching mask 152. The second groove 201 can be a trench structure or a via structure. The second groove 201 corresponds to the position of the first groove 160 and has a size smaller than the first groove 160 along the second direction. Figure 7 As shown, the upper and lower segments of the second groove 201 on the left side have substantially the same width, and the left half of the second groove 201 on the right side is formed by patterning the semi-transparent part of the second photoetching mask 152, so that the lower segment of the second groove 201 has a smaller width than the upper segment.

[0076] Further, a conductive filling layer 210 is formed to cover the second hard mask layer 192, and the conductive filling layer 210 also fills in the second groove 201, as shown in Figure 8 As shown, the material of the conductive filling layer 210 is, for example, copper.

[0077] Further, the conductive filling layer 210 is polished, and the remaining conductive filling layer 210 in the second groove forms conductive channels 211 and 212, as shown in Figure 9 As shown, the conductive channels 211 and 212 are connected to the interconnection region 102 on the metal layer 110.

[0078] In this step, the chemical mechanical polishing of the conductive filling layer 210 is stopped on the low-K dielectric layer 180 on the stack structure 130, so as to prevent the ultra-low-K dielectric layer 132 with soft material and low mechanical strength from being damaged by polishing.

[0079] In this embodiment, along the second direction, the width of the ultra-low-K dielectric layer 132 can be preset according to the layout of the back-end metal wires, for example, the width of the ultra-low-K dielectric layer 132 accounts for 70% between the conductive channels 211 and 212, so that the dielectric constant K of the overall dielectric layer is lower.

[0080] Figure 10 A schematic diagram of a semiconductor structure according to an embodiment of the present disclosure is shown.

[0081] Referring to Figure 10 , the semiconductor structure formed by the manufacturing method described above includes a structure layer having an interconnection region 102, an interlayer dielectric layer 10, and conductive channels 211 and 212. The structure layer includes a substrate 101 and a metal layer 110, the interlayer dielectric layer 10 is located on the metal layer 110, and the conductive channels 211 and 212 are connected to the interconnection region 102 on the metal layer 110 through the interlayer dielectric layer 10. In the back-end-of-line process of the semiconductor device, the metal layer 110 and the interlayer dielectric layer 10 are alternately stacked.

[0082] In this embodiment, the specific structure of the interlayer dielectric layer 10 can refer to Figure 9The description of the above embodiments, for example, includes the stack structure 130 and the low-K dielectric layer 180. The stack structure 130 is located on the structure layer, and includes the spacer dielectric layer 131 and the ultra-low-K dielectric layer 132 stacked along a first direction, which is the thickness direction of the structure layer. The low-K dielectric layer 180 is located on the stack structure 130 and penetrates the stack structure 130 along the first direction. The conductive channels 211 and 212 penetrate the low-K dielectric layer 180 along the first direction and are connected to the interconnection region 102. In the second direction perpendicular to the first direction, the size of the spacer dielectric layer 131 is smaller than the size of the ultra-low-K dielectric layer 132, forming a recess, and the low-K dielectric layer 180 fills in the recess, forming a protrusion, so that the spacer dielectric layer 131, the ultra-low-K dielectric layer 132, and the low-K dielectric layer 180 form an interlocking structure, to increase the mechanical strength of the interlayer dielectric layer 10.

[0083] In some optional embodiments, the number of layers of the ultra-low-K dielectric layer 132 is multiple, the spacer dielectric layer 131 is located between two adjacent layers of the ultra-low-K dielectric layer 132, and / or the number of layers of the spacer dielectric layer 131 and the ultra-low-K dielectric layer 132 is multiple, and the multiple spacer dielectric layers 131 and the multiple ultra-low-K dielectric layers 132 are alternately stacked. In each interlayer dielectric layer 10, along the first direction, the number of interlocking structures increases with the increase of the number of layers of the spacer dielectric layer 131 and the ultra-low-K dielectric layer 132.

[0084] In some optional embodiments, the semiconductor structure further includes a protective layer 170 located between the stack structure 130 and the low-K dielectric layer 180.

[0085] The interlayer dielectric layer 10 of the embodiments is a composite structure, including the spacer dielectric layer 131, the ultra-low-K dielectric layer 132, and the low-K dielectric layer 180, the total dielectric constant K is not greater than 2.3, and the Young's modulus E can reach about 12 Gpa, which can not only ensure the mechanical strength of the dielectric layer through the concave-convex interlocking structure, but also control the dielectric constant K below 2.3, so as to effectively reduce the RC Delay and improve the device speed and reliability.

[0086] The embodiments of the present disclosure are not limited to the specific embodiments described above, and the above description is not exhaustive of all details of the embodiments. Obviously, many modifications and variations can be made in light of the above description. The embodiments are selected and specifically described in this specification in order to better explain the principles and practical applications of the present disclosure, so that those skilled in the art can well utilize the present disclosure and make modifications based on the present disclosure. The protection scope of the present disclosure should be defined by the scope of the claims of the present disclosure and their equivalents.

Claims

1. A semiconductor structure, comprising: A structural layer having interconnection regions; A stacked structure, located on the structural layer, includes a spacer dielectric layer and an ultra-low K dielectric layer stacked along a first direction, wherein the first direction is the thickness direction of the structural layer; A low-k dielectric layer extends through the stacked structure along the first direction; as well as A conductive channel extends along the first direction through the low-k dielectric layer and connects to the interconnect region. In this configuration, along the second direction, the size of the spacer dielectric layer is smaller than the size of the ultra-low-k dielectric layer, forming a recess. The low-k dielectric layer fills the recess, forming a protrusion, so that the spacer dielectric layer, the ultra-low-k dielectric layer, and the low-k dielectric layer form an interlocking structure. The second direction is perpendicular to the first direction.

2. The semiconductor structure according to claim 1, wherein, The number of ultra-low k dielectric layers is multiple, and the spacer dielectric layer is located between two adjacent ultra-low k dielectric layers. And / or there are multiple spacer layers and multiple ultra-low K dielectric layers, with the spacer layers and the ultra-low K dielectric layers stacked alternately.

3. The semiconductor structure according to claim 1, wherein, The low-K dielectric layer is also located on the stacked structure.

4. The semiconductor structure according to claim 1 further includes a protective layer located between the stacked structure and the low-k dielectric layer.

5. A method for manufacturing a semiconductor structure, comprising: A stacked structure is formed on a structural layer having interconnection regions, the stacked structure comprising a spacer dielectric layer and an ultra-low K dielectric layer stacked along a first direction, the first direction being the thickness direction of the structural layer; The stacked structure is etched to form a first groove; A low-k dielectric layer is formed within the first groove; The low-k dielectric layer is etched to form a second groove; as well as A conductive channel is formed in the second groove, and the conductive channel is connected to the interconnect region. In this process, along the second direction, the etching rate of the spacer dielectric layer is greater than the etching rate of the ultra-low-k dielectric layer, so as to form a recess at the sidewall of the first groove. The low-k dielectric layer forms a protrusion at the recess so that the spacer dielectric layer, the ultra-low-k dielectric layer, and the low-k dielectric layer constitute an interlocking structure. The second direction is perpendicular to the first direction.

6. The manufacturing method according to claim 5, wherein, The step of forming a low-k dielectric layer in the first groove includes: The reaction chamber is supplied with plasma-form oxygen free radicals and plasma-form silicon-, oxygen-, carbon-, and hydrogen-containing precursors. The oxygen free radicals react with the silicon-, oxygen-, carbon-, and hydrogen-containing precursor to generate a flowable low-k dielectric layer, which is then deposited within the first groove; and The low-k dielectric layer is solidified.

7. The manufacturing method according to claim 5, wherein, The low-k dielectric layer is also located on the stacked structure, and the chemical mechanical polishing of the conductive filling layer used to form the conductive channel stops on the low-k dielectric layer on the stacked structure.

8. The manufacturing method according to claim 5, further comprising forming a protective layer on the inner surface of the first groove before forming the low-k dielectric layer. in, The low-K dielectric layer is separated from the stacked structure by the protective layer.

9. The manufacturing method according to any one of claims 5 to 8, wherein, The carbon content in the spacer dielectric layer is less than the carbon content in the ultra-low K dielectric layer, so that the etching rate of the spacer dielectric layer along the second direction is greater than the etching rate of the ultra-low K dielectric layer.

10. The manufacturing method according to any one of claims 5 to 8, wherein, In the steps of the first groove and the second groove, the photoresist is patterned through the fully transparent and semi-transparent portions of the halftone mask to form a photomask, and the underlying structure is etched through the photomask so that the lower width of a portion of the first groove and the second groove is smaller than the upper width.

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