A method for eliminating dc bias of bus midpoint voltage of a three-level inverter

Abstract

The disclosure provides a bus midpoint voltage DC bias elimination method of a three-level converter, which comprises the following steps: obtaining the current three-phase reference voltage of the three-level converter; determining a first three-phase modulation wave according to the three-phase reference voltage and the current modulation strategy; collecting the three-phase current direction, and determining the direction signal of the bias elimination component according to the first three-phase modulation wave and the three-phase current direction; obtaining the electrolytic capacitor voltage difference of the upper and lower DC buses of the three-level converter, and determining the amplitude signal of the bias elimination component according to the electrolytic capacitor voltage difference; determining the bias elimination component according to the product of the direction signal and the amplitude signal; determining a second three-phase modulation wave according to the bias elimination component and the first three-phase modulation wave, and generating the switching tube driving signal of each bridge arm of the three-level converter. The disclosure respectively calculates the direction signal and the amplitude signal of the bias elimination component, fully considers the influence of the current direction on the bus midpoint voltage DC bias, and effectively improves the stability of the converter.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of inverter modulation, and particularly relates to a method and device for eliminating DC bias of bus midpoint voltage of a three-level converter, a storage medium, an electronic device and a three-level converter. BACKGROUND

[0002] With the rapid development of new energy industries such as photovoltaic, wind power and energy storage, three-level converters are widely used in new energy industries due to their high output current and voltage power quality, low device loss and low cost.

[0003] The three-level converter has split DC buses, which causes the problem of bus midpoint voltage imbalance. The bus midpoint voltage imbalance can be divided into two parts: AC voltage fluctuation and DC voltage bias. Overall, the bus midpoint voltage imbalance is mainly caused by the charging and discharging current imbalance of the upper and lower bus electrolytic capacitors in the switching period due to the modulation strategy used by the three-level converter.

[0004] For the DC bias of the bus midpoint voltage of a three-phase three-level converter, it is mainly caused by the difference between the upper and lower bus electrolytic capacitor values and the cumulative difference between the current flowing through the upper and lower bus electrolytic capacitors based on the fundamental period. Hardware differences are inevitable for a three-phase three-level converter, so the method for suppressing the DC bias of the bus midpoint voltage mainly focuses on the calculation and redistribution of the voltage vector to suppress the DC bias of the bus midpoint voltage. In the traditional method for suppressing the DC bias of the bus midpoint voltage, only the relationship between the voltage difference between the upper and lower buses and the output voltage vector is considered, while the influence of the direction of the output current on the DC bias of the bus midpoint voltage when the power factor angle changes is ignored. Moreover, in a three-phase three-level converter, the bus midpoint voltage often has a three times frequency AC fluctuation, which interferes with the PI loop of the voltage difference between the upper and lower buses and affects the suppression effect of the DC bias of the bus midpoint voltage. SUMMARY

[0005] The purpose of the embodiments of the present disclosure is to provide a method and device for eliminating the DC bias of the bus midpoint voltage of a three-level converter, a storage medium, an electronic device and a three-level converter, to solve the problem of the DC bias of the bus midpoint voltage of a three-level converter in the prior art.

[0006] The embodiment of the present disclosure adopts the technical scheme as follows: a bus midpoint voltage DC bias elimination method of a three-level converter, comprising: obtaining a current three-phase reference voltage of the three-level converter; determining a first three-phase modulation wave according to the three-phase reference voltage and a current modulation strategy; collecting a three-phase current direction of the three-level converter, and determining a direction signal of a bias elimination component according to the first three-phase modulation wave and the three-phase current direction; obtaining a voltage difference of electrolytic capacitors of upper and lower DC buses of the three-level converter, and determining an amplitude signal of the bias elimination component according to the voltage difference of the electrolytic capacitors; determining the bias elimination component according to a product of the direction signal and the amplitude signal; determining a second three-phase modulation wave according to the bias elimination component and the first three-phase modulation wave, and generating a switch tube driving signal of each bridge arm in the three-level converter according to the second three-phase modulation wave.

[0007] The embodiment of the present disclosure also provides a bus midpoint voltage DC bias elimination device of a three-level converter, comprising: an obtaining module, configured to obtain a current three-phase reference voltage of the three-level converter; determine a first three-phase modulation wave according to the three-phase reference voltage and a current modulation strategy; a bias elimination component calculation module, configured to collect a three-phase current direction of the three-level converter, and determine a direction signal of a bias elimination component according to the first three-phase modulation wave and the three-phase current direction; obtain a voltage difference of electrolytic capacitors of upper and lower DC buses of the three-level converter, and determine an amplitude signal of the bias elimination component according to the voltage difference of the electrolytic capacitors; determine the bias elimination component according to a product of the direction signal and the amplitude signal; a driving module, configured to determine a second three-phase modulation wave according to the bias elimination component and the first three-phase modulation wave, and generate a switch tube driving signal of each bridge arm in the three-level converter according to the second three-phase modulation wave.

[0008] The embodiment of the present disclosure also provides a storage medium, which stores a computer program, and the computer program is executed by a processor to implement the steps of the bus midpoint voltage DC bias elimination method of the three-level converter.

[0009] The embodiment of the present disclosure also provides an electronic device, which at least comprises a memory and a processor, and the memory stores a computer program, and the processor implements the steps of the bus midpoint voltage DC bias elimination method of the three-level converter when executing the computer program stored in the memory.

[0010] The embodiment of the present disclosure also provides a three-level converter, which at least comprises the electronic device as described above.

[0011] The beneficial effects of this embodiment are as follows: by calculating the direction signal and amplitude signal of the bias elimination component separately, the influence of the current direction on the DC bias of the bus midpoint voltage is fully considered, and the DC bias of the bus midpoint voltage is eliminated when there is a 20% capacitance difference between the upper and lower bus electrolytic capacitor values, effectively improving the stability of the converter; at the same time, there is no need to judge the voltage vector region and recalculate and allocate the voltage vector to achieve the elimination of the DC bias of the bus midpoint voltage, effectively reducing the computational load of the bus midpoint voltage DC bias elimination method. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in one or more embodiments of this specification or in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of the topology of an I-NPC three-level converter;

[0014] Figure 2 This is a flowchart of the method for eliminating DC bias at the bus midpoint voltage of a three-level converter in the first embodiment of this disclosure;

[0015] Figure 3 This is a block diagram of the constant power control of the three-level converter in the first embodiment of this disclosure;

[0016] Figure 4 This is a flowchart illustrating the process of determining the direction signal of the bias cancellation component in the first embodiment of this disclosure;

[0017] Figure 5 This is a block diagram of the bus midpoint voltage control in the first embodiment of this disclosure;

[0018] Figure 6 This is a comparison diagram showing the effect of eliminating DC bias of bus midpoint voltage using the method of this embodiment and the conventional method in the first embodiment of this disclosure;

[0019] Figure 7 This is a schematic diagram of the DC bias elimination device for the bus midpoint voltage of the three-level converter in the second embodiment of this disclosure. Detailed Implementation

[0020] In order for those skilled in the art to better understand the technical solutions in the one or more embodiments of the present specification, the technical solutions in the one or more embodiments of the present specification will be clearly and completely described below in conjunction with the drawings in the one or more embodiments of the present specification. Obviously, the described embodiments are only a part of the embodiments of the present specification, rather than all the embodiments. Based on the one or more embodiments of the present specification, all other embodiments obtained by those skilled in the art without creative labor should belong to the protection scope of the present document.

[0021] With the rapid development of new energy industries such as photovoltaic, wind power, and energy storage, three-level converters are widely used in new energy industries due to their high output current and voltage power quality, low device loss, and low cost.

[0022] The three-level converter has a split DC bus, which causes the problem of bus midpoint voltage imbalance. The bus midpoint voltage imbalance can be divided into two parts: AC voltage fluctuation and DC voltage bias. Overall, the bus midpoint voltage imbalance is mainly caused by the charging and discharging current imbalance of the upper and lower bus electrolytic capacitors within the switching period due to the modulation strategy used by the three-level converter.

[0023] For the DC bias of the bus midpoint voltage of the three-phase three-level converter, it is mainly caused by the difference in the values of the upper and lower bus electrolytic capacitors and the accumulation of the current difference flowing through the upper and lower bus electrolytic capacitors based on the fundamental period. Hardware differences are inevitable for three-phase three-level converters, so the method for suppressing the DC bias of the bus midpoint voltage mainly focuses on the calculation and redistribution of the voltage vector to achieve the suppression of the DC bias of the bus midpoint voltage. In the traditional method for suppressing the DC bias of the bus midpoint voltage, only the relationship between the voltage difference of the upper and lower buses and the output voltage vector is considered, while the direction of the output current when the power factor angle changes is ignored, which also affects the DC bias of the bus midpoint voltage. Moreover, in the three-phase three-level converter, the bus midpoint voltage will have a three times frequency AC fluctuation most of the time, which will interfere with the PI loop of the voltage difference of the upper and lower buses, affecting the suppression effect of the DC bias of the bus midpoint voltage.

[0024] To solve the above problems, the first embodiment of the present disclosure provides a method for eliminating the DC bias of the bus midpoint voltage of a three-level converter, and the execution subject can be an upper controller of the three-level converter. The main function is to control the on-off of the bridge arm switch tube of the three-level converter according to different modulation strategies, and finally complete the output of the three-phase sinusoidal signal.

[0025] Figure 1 A topology diagram of an I-NPC three-level converter is shown, and the present embodiment is based on Figure 1The three-level converter is taken as an example to illustrate the method for eliminating DC bias of bus midpoint voltage. As shown in Figure 1 Each phase of the three-level converter is composed of four switching tubes and two freewheeling diodes, Cap1 and Cap2 are DC side bus capacitors, U dc is DC side voltage, S xi is the driving signal of the i-th switching tube of the x phase, i.e. x=a, b, c; s=1, 2, 3, 4. When S xi is 1, the corresponding switching tube is turned on, and when S xi is 0, the corresponding switching tube is turned off. Then, it can be obtained by analysis that the I-NPC three-phase three-level converter can output three levels: U dc / 2, 0 and -U dc / 2, respectively corresponding to the states [P], [O], [N]. The I-NPC three-phase three-level converter is connected with the LCL filter system, and the LCL filter system is divided into three parts: the inductor L1 on the side of the inverter, the filter capacitor C, and the inductor L2 on the side of the grid, and the converter is connected with the grid through the LCL filter system.

[0026] Figure 2 A flowchart of the method for eliminating DC bias of bus midpoint voltage of the three-level converter of the embodiment is shown, which mainly includes steps S10 to S60:

[0027] S10, obtaining the current three-phase reference voltage of the three-level converter.

[0028] The core function of the three-level converter is to convert the DC side voltage into three-phase alternating voltage meeting the requirements of the load or the grid. In actual application, the converter needs to cope with disturbances such as load fluctuation and DC side voltage change, so it needs to dynamically adjust the three-phase reference voltage through closed-loop control (such as voltage closed-loop and current closed-loop) to ensure stable output.

[0029] Figure 3 A constant power control block diagram of the converter in the embodiment is shown. In the embodiment, the three-phase reference voltage u a ,u b ,u c is obtained by obtaining the current loop output and the voltage feedforward output of the grid, performing summation processing, and performing inverse park transformation and inverse clark transformation, and then performing per-unit processing on the transformation result. Specifically, since the PI loop can follow the DC current without static error, the current loop of the embodiment adopts the PI loop, calculates the current given I d and I q in the dq axis according to the current grid voltage, and inputs the dq-transformed grid current into the current loop as the feedback value; at the same time, since the grid voltage fluctuates, the output of the PI loop is superimposed with the grid voltage feedforward and then subjected to per-unit processing to obtain the three-phase reference voltage.

[0030] S20, determining a first three-phase modulation wave according to the three-phase reference voltage and the current modulation strategy.

[0031] The three-phase modulation wave is a three-phase phase voltage instantaneous value waveform of the expected output of the converter, directly determines the amplitude, frequency, phase and waveform of the output voltage, and serves as a reference signal of the modulation strategy to determine the on-off time of the switching tube. In this embodiment, the first three-phase modulation wave can be preliminarily determined according to the three-phase reference voltage and the current modulation strategy to serve as a basis for eliminating the DC bias of the bus midpoint voltage.

[0032] Specifically, in the modulation strategy of the three-level converter, the zero sequence component is a kind of "flexible adjustment tool", and its core role is to optimize the three-phase reference voltage without changing the line voltage output, thereby improving the performance of the converter. Therefore, before determining the first three-phase modulation wave, the current zero sequence component is calculated according to the current modulation strategy, and then the zero sequence component is superimposed on the three-phase reference voltage to obtain the first three-phase modulation wave.

[0033] It should be noted that the calculation method of the zero sequence component is different for different modulation strategies, and the embodiment does not describe the calculation process of the specific zero sequence component. The zero sequence component can be calculated according to the commonly used calculation method of the zero sequence component according to the current modulation strategy.

[0034] S30, collecting the three-phase current direction of the three-level converter, and determining the direction signal of the bias elimination component according to the first three-phase modulation wave and the three-phase current direction.

[0035] Under normal circumstances, the first three-phase modulation wave can be used to output the switching tube driving signal of the corresponding bridge arm of the converter, but when the capacitance difference between the upper and lower bus electrolytic capacitors is too large, the current flowing through the upper and lower bus electrolytic capacitors is different, resulting in a DC bias of the bus midpoint voltage. Therefore, the embodiment determines the DC bias direction of the bus midpoint voltage according to the first three-phase modulation wave in combination with the real-time collected three-phase current direction of the three-level converter, and determines the direction signal of the bias elimination component for eliminating the bias according to the bias direction.

[0036] Specifically, after determining the first three-phase modulation wave, the intermediate value V mid,0 in the first three-phase modulation wave is determined first, then the first current signal i max,0 corresponding to the maximum value in the first three-phase modulation wave and the second current signal i min,0 corresponding to the minimum value in the first three-phase modulation wave are determined, and finally the direction signal Sign_PI of the bias elimination component is determined according to the flow as shown in Figure 4 .

[0037] In combination Figure 4 with the foregoing, in determining the Sign_PI, first detect whether the intermediate value V mid,0 is greater than 0; in the case that the intermediate value V mid,0 is greater than 0, detect whether the second current signal I min,0 is greater than 0; in the case that the second current signal I min,0 is greater than 0, determine that the direction signal Sign_PI is -1; in the case that the second current signal I min,0 is less than or equal to 0, determine that the direction signal Sign_PI is 1; in the case that the intermediate value V mid,0 is less than or equal to 0, detect whether the first current signal I max,0 is greater than 0; in the case that the first current signal I max,0 is greater than 0, determine that the direction signal Sign_PI is 1; in the case that the first current signal I max,0 is less than or equal to 0, determine that the direction signal Sign_PI is -1.

[0038] S40, obtain the electrolytic capacitor voltage difference of the upper and lower DC bus of the three-level converter, and determine the amplitude signal of the bias cancellation component according to the electrolytic capacitor voltage difference.

[0039] Step S30 realizes determination of the direction signal of the bias cancellation component, and on this basis, determination of the amplitude signal of the bias cancellation component is performed through step S40. Specifically, Figure 5 A bus midpoint voltage control block diagram is shown, i.e., the electrolytic capacitor voltage difference of the upper and lower half bus is closed-loop controlled through the construction of a PI loop, and a compensation signal is generated by PI regulation to eliminate the voltage difference, and finally the voltage balance of the upper and lower bus is realized. The PI loop of the bus midpoint voltage control is used to calculate the amplitude signal of the bias cancellation component in this embodiment, which can be specifically expressed as:

[0040] Mid_PI.out = (U dc1 -U dc2 ) × (K p + K i / s);

[0041] Wherein, Mid_PI.out represents the amplitude signal of the bias cancellation component, U dc1 represents the electrolytic capacitor voltage of the upper half bus, U dc2 represents the electrolytic capacitor voltage of the lower half bus, K p represents the proportional parameter of the bus midpoint voltage control PI loop, and K i represents the integral parameter of the bus midpoint voltage control PI loop.

[0042] S50, determine the bias cancellation component according to the product of the direction signal and the amplitude signal.

[0043] S60, determining a second three-phase modulation wave according to the bias elimination component and the first three-phase modulation wave, and generating the switch driving signal of each bridge arm in the three-level converter according to the second three-phase modulation wave.

[0044] After the direction signal Sign PI and the amplitude signal Mid PI. out are determined, the bias elimination component V midpoint , i.e.

[0045] V midpoint = Sign PI x Mid PI. out

[0046] Wherein, the amplitude signal Mid PI. out is used to determine the amplitude of the bus midpoint voltage DC bias compensation, and the direction signal Sign PI indicates the specific superposition direction of the bias elimination component during the compensation.

[0047] Finally, during the compensation, the superposition of the bias elimination component is performed on the basis of the first three-phase modulation wave to obtain the second three-phase modulation wave satisfying the bus midpoint DC bias elimination, i.e. the second three-phase modulation wave is determined according to the following formula group:

[0048] u a,CB = u a + u0 + V midpoint ;

[0049] u b,CB = u b + u0 + V midpoint ;

[0050] u c,CB = u c + u0 + V midpoint ;

[0051] Wherein, u a,UCB , u b,UCB , u c,UCB represent the second three-phase modulation wave, u a + u0, u b + u0, u c + u0 represent the first three-phase modulation wave, u a , u b , u c represent the three-phase reference voltage, u0 represents the current zero sequence component, and V midpoint represents the bias elimination component.

[0052] After the second three-phase modulation wave is obtained, the switch driving signal of each bridge arm in the three-level converter can be generated according to the second three-phase modulation wave, so as to realize the turn-on and turn-off of each switch in each phase bridge arm of the three-level converter based on the driving signal, and generate U dc / 2, 0 and -U dc / 2 three output levels, eventually generates an output voltage containing the fundamental and high-frequency voltage signal, the output voltage is filtered by the LCL filter to remove the high-frequency signal, generating a three-phase sinusoidal signal. It should be noted that the specific generation method of the drive signal of the switch tube can be directly referred to the existing drive signal generation, and the present embodiment will not be specifically described.

[0053] Figure 6 The comparative effect diagram of bus midpoint voltage DC bias elimination by the method of the embodiment and the conventional method is shown, by Figure 6 It can be seen that when the power factor is too low, the bus midpoint voltage control strategy of the conventional method (Convention Method) will cause a large DC bias in the upper and lower buses, and when switching to the method used in the embodiment (Proposed Method), the DC bias at the bus midpoint voltage can be basically eliminated, and the bus midpoint voltage only exists AC fluctuation.

[0054] The embodiment fully considers the influence of current direction on bus midpoint voltage DC bias by separately calculating the direction signal and amplitude signal of the bias elimination component, realizes the elimination of bus midpoint voltage DC bias when the electrolytic capacitor values of the upper and lower buses have a 20% capacitance difference, and effectively improves the stability of the converter; At the same time, it is not necessary to judge the voltage vector region and recalculate and distribute the voltage vector to eliminate the bus midpoint voltage DC bias, which effectively reduces the calculation amount of the bus midpoint voltage DC bias elimination method.

[0055] Based on the same inventive concept, the second embodiment of the disclosure provides a bus midpoint voltage DC bias elimination device of a three-level converter, which can be installed in the upper controller of the three-level converter, and by obtaining the voltage and current of the three-level converter in real time, the bus midpoint voltage DC bias elimination of the three-level converter is completed.

[0056] Figure 7A structure diagram of a bus midpoint voltage DC bias elimination device of a three-level converter is shown, which mainly comprises: an acquisition module 10 configured to acquire a current three-phase reference voltage of the three-level converter; determine a first three-phase modulation wave according to the three-phase reference voltage and a current modulation strategy; a bias elimination component calculation module 20 configured to acquire a three-phase current direction of the three-level converter, and determine a direction signal of the bias elimination component according to the first three-phase modulation wave and the three-phase current direction; acquire an electrolytic capacitor voltage difference of upper and lower DC buses of the three-level converter, and determine an amplitude signal of the bias elimination component according to the electrolytic capacitor voltage difference; determine the bias elimination component according to a product of the direction signal and the amplitude signal; a driving module 30 configured to determine a second three-phase modulation wave according to the bias elimination component and the first three-phase modulation wave, and generate a switching tube driving signal of each bridge arm of the three-level converter according to the second three-phase modulation wave.

[0057] In some embodiments, the acquisition module 10 is specifically configured to: acquire a current current loop output and voltage feedforward output of the three-level converter; calculate a sum value of the current loop output and the voltage feedforward output; perform inverse park transformation and inverse clark transformation on the sum value, and perform unit normalization processing on the transformation result to obtain the three-phase reference voltage.

[0058] In some embodiments, the acquisition module 10 is specifically configured to: determine a current zero sequence component according to the three-phase reference voltage and the current modulation strategy; determine the first three-phase modulation wave according to a sum value of the three-phase reference voltage and the current zero sequence component.

[0059] In some embodiments, the bias elimination component calculation module 20 is specifically configured to: determine a middle value in the first three-phase modulation wave; determine a first current signal corresponding to a maximum value in the first three-phase modulation wave and a second current signal corresponding to a minimum value in the first three-phase modulation wave; detect whether the middle value is greater than 0; in the case that the middle value is greater than 0, detect whether the second current signal is greater than 0; in the case that the second current signal is greater than 0, determine that the direction signal is -1; in the case that the second current signal is less than or equal to 0, determine that the direction signal is 1; in the case that the middle value is less than or equal to 0, detect whether the first current signal is greater than 0; in the case that the first current signal is greater than 0, determine that the direction signal is 1; in the case that the first current signal is less than or equal to 0, determine that the direction signal is -1.

[0060] In some embodiments, the bias elimination component calculation module 20 is specifically configured to: determine the amplitude signal of the bias elimination component according to the following formula:

[0061] Mid_PI.out = (U dc1 -U dc2 ) × (K p + K i / s);

[0062] wherein Mid PI.out represents the amplitude signal of the offset elimination component, U dc1 represents the upper half bus electrolytic capacitor voltage, U dc2 represents the lower half bus electrolytic capacitor voltage, K p represents the proportional parameter of the bus midpoint voltage control PI loop, K i represents the integral parameter of the bus midpoint voltage control PI loop.

[0063] In some embodiments, the driving module 30 is specifically configured to determine the second three-phase modulation wave according to a formula group as follows:

[0064] u a,CB = u a + u0+ V midpoint ;

[0065] u b,CB = u b + u0+ V midpoint ;

[0066] u c,CB = u c + u0+ V midpoint ;

[0067] V midpoint = Sign PI x Mid PI.out;

[0068] wherein u a,UCB , u b,UCB , u c,UCB represent the second three-phase modulation wave, u a + u0, u b + u0, u c + u0 represent the first three-phase modulation wave, u a , u b , u c represent the three-phase reference voltage, u0 represents the current zero sequence component, V midpoint represents the offset elimination component, Sign PI represents the direction signal of the offset elimination component, and Mid PI.out represents the amplitude signal of the offset elimination component.

[0069] The embodiment fully considers the influence of the current direction on the DC bias of the bus midpoint voltage by separately calculating the direction signal and the amplitude signal of the offset elimination component, and realizes the elimination of the DC bias of the bus midpoint voltage in the case that the electrolytic capacitor values of the upper and lower buses have a 20% capacity difference, and effectively improves the stability of the converter; meanwhile, the elimination of the DC bias of the bus midpoint voltage does not need to judge the voltage vector region and recalculate and distribute the voltage vector, which effectively reduces the calculation amount of the DC bias elimination method of the bus midpoint voltage.

[0070] Based on the same inventive concept, a third embodiment of the present disclosure provides a storage medium storing a computer program, which, when executed by a processor, implements the steps of the bus midpoint voltage DC bias elimination method of the three-level converter according to the first embodiment of the present disclosure. The storage medium can be installed in an upper controller of the three-level converter, so that the upper controller executes the computer program stored in the storage medium when driving the three-level converter.

[0071] Based on the same inventive concept, a fourth embodiment of the present disclosure provides an electronic device comprising at least a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the bus midpoint voltage DC bias elimination method of the three-level converter according to the first embodiment of the present disclosure when executing the computer program stored in the memory. The electronic device can be an upper controller of the three-level converter, and when driving the three-level converter, the electronic device executes the computer program stored in the memory to eliminate the DC bias of the bus midpoint voltage.

[0072] Based on the same inventive concept, a fifth embodiment of the present disclosure provides a three-level converter comprising at least the electronic device according to the fourth embodiment of the present disclosure, which cooperates with the conventional topology of the three-level converter to use the electronic device as a driving device of the switching tubes of each bridge arm of the three-level converter, so as to eliminate the DC bias of the bus midpoint voltage of the three-level converter.

[0073] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present disclosure, but not to limit them; although the present disclosure has been described in detail with reference to the above embodiments, those skilled in the art should understand that: they can still modify the technical solutions recorded in the above embodiments, or make equivalent replacement to part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method for eliminating DC bias in the bus neutral point voltage of a three-level converter, characterized in that, include: Obtain the current three-phase reference voltage of the three-level converter; The first three-phase modulation wave is determined based on the three-phase reference voltage and the current modulation strategy; The direction of the three-phase current of the three-level converter is acquired, and the direction signal of the bias elimination component is determined based on the first three-phase modulation wave and the direction of the three-phase current. Obtain the voltage difference between the electrolytic capacitors of the upper and lower DC buses of the three-level converter, and determine the amplitude signal of the bias elimination component based on the voltage difference between the electrolytic capacitors. The offset cancellation component is determined based on the product of the direction signal and the amplitude signal; Based on the bias elimination component and the first three-phase modulation wave, the second three-phase modulation wave is determined, and the switching transistor drive signal of each bridge arm in the three-level converter is generated based on the second three-phase modulation wave. The step of determining the first three-phase modulation wave based on the three-phase reference voltage and the current modulation strategy includes: The current zero-sequence component is determined based on the three-phase reference voltage and the current modulation strategy; The first three-phase modulation wave is determined based on the sum of the three-phase reference voltage and the current zero-sequence component; The process of acquiring the three-phase current direction of the three-level converter and determining the direction signal of the bias cancellation component based on the first three-phase modulation wave and the three-phase current direction includes: Determine the median value in the first three-phase modulated wave; Determine the first current signal corresponding to the maximum value in the first three-phase modulated wave and the second current signal corresponding to the minimum value in the first three-phase modulated wave; Detect whether the intermediate value is greater than 0; If the intermediate value is greater than 0, detect whether the second current signal is greater than 0; If the second current signal is greater than 0, the direction signal is determined to be -1; If the second current signal is less than or equal to 0, the direction signal is determined to be 1; If the intermediate value is less than or equal to 0, detect whether the first current signal is greater than 0; If the first current signal is greater than 0, the direction signal is determined to be 1; If the first current signal is less than or equal to 0, the direction signal is determined to be -1.

2. The method for eliminating DC bias at the bus midpoint voltage according to claim 1, characterized in that, The process of obtaining the current three-phase reference voltage of the three-level converter includes: Obtain the current loop output and voltage feedforward output of the three-level converter; Calculate the sum of the current loop output and the voltage feedforward output; The sum is subjected to inverse Park and inverse Clark transformations, and the transformation results are then normalized to per-unit values ​​to obtain the three-phase reference voltage.

3. The method for eliminating DC bias at the bus midpoint voltage according to claim 1, characterized in that, The step of acquiring the electrolytic capacitor voltage difference between the upper and lower DC buses of the three-level converter, and determining the amplitude signal of the bias elimination component based on the electrolytic capacitor voltage difference, includes: The amplitude signal of the bias cancellation component is determined according to the following formula: in, This represents the amplitude signal of the bias cancellation component. This indicates the voltage of the electrolytic capacitor on the upper busbar. This indicates the voltage of the electrolytic capacitor on the lower half of the busbar. This represents the proportional parameter of the PI loop controlling the bus midpoint voltage. This represents the integral parameter of the PI loop controlling the bus midpoint voltage.

4. The method for eliminating DC bias at the bus midpoint voltage according to claim 3, characterized in that, The step of determining the second three-phase modulation wave based on the bias elimination component and the first three-phase modulation wave includes: The second and third phase modulation waves are determined according to the following set of formulas: in, This represents the second and third phase modulation wave. This represents the first three-phase modulated wave. This represents the three-phase reference voltage. This represents the current zero-order component. This refers to the bias elimination component. This represents the direction signal of the bias cancellation component. This represents the amplitude signal of the bias cancellation component.

5. A device for eliminating DC bias at the bus midpoint voltage of a three-level converter, characterized in that, include: The acquisition module is used to acquire the current three-phase reference voltage of the three-level converter; The first three-phase modulation wave is determined based on the three-phase reference voltage and the current modulation strategy; The bias elimination component calculation module is used to acquire the three-phase current direction of the three-level converter, and determine the direction signal of the bias elimination component based on the first three-phase modulation wave and the three-phase current direction; acquire the electrolytic capacitor voltage difference of the upper and lower DC buses of the three-level converter, and determine the amplitude signal of the bias elimination component based on the electrolytic capacitor voltage difference; and determine the bias elimination component based on the product of the direction signal and the amplitude signal. The drive module is used to determine the second three-phase modulation wave based on the bias elimination component and the first three-phase modulation wave, and to generate the switching transistor drive signal of each bridge arm in the three-level converter based on the second three-phase modulation wave. The offset elimination component calculation module is specifically used for: determining the intermediate value in the first three-phase modulation wave; determining the first current signal corresponding to the maximum value in the first three-phase modulation wave and the second current signal corresponding to the minimum value in the first three-phase modulation wave; detecting whether the intermediate value is greater than 0; if the intermediate value is greater than 0, detecting whether the second current signal is greater than 0; if the second current signal is greater than 0, determining the direction signal to be -1. When the second current signal is less than or equal to 0, the direction signal is determined to be 1; If the intermediate value is less than or equal to 0, check if the first current signal is greater than 0; if the first current signal is greater than 0, determine that the direction signal is 1. If the first current signal is less than or equal to 0, the direction signal is determined to be -1.

6. A storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the method for eliminating DC bias of the bus midpoint voltage of the three-level converter as described in any one of claims 1 to 4.

7. An electronic device, comprising at least a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program on the memory, it implements the steps of the method for eliminating DC bias of the bus midpoint voltage of the three-level converter as described in any one of claims 1 to 4.

8. A three-level converter, characterized in that, It includes at least the electronic device as described in claim 7.

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