A five-level pulse excitation signal generation circuit for piezoelectric ultrasonic transducers

Abstract

The application discloses a five-level pulse excitation signal generation circuit for a piezoelectric ultrasonic transducer, relates to the technical field of driving circuits, and comprises two cascaded H-bridge circuits; each H-bridge circuit comprises four power switching tubes; two direct-current voltage sources with different voltages are used to supply power to the two H-bridge circuits respectively; a pulse transformer is connected with the output ends of the two H-bridge circuits and used for voltage step-up; a wideband impedance matching network is used to connect the output end of the pulse transformer with the piezoelectric ultrasonic transducer; and an FPGA controller is used to generate a PWM signal and control the conduction and turn-off of the eight power switching tubes so as to output a five-level pulse signal; the multi-level high-voltage pulse excitation signal has stronger penetration capacity and more uniform energy distribution, and the energy transmission efficiency of the piezoelectric ultrasonic transducer is improved.

Description

Technical Field

[0001] This invention relates to the field of drive circuit technology, and more specifically to a five-level pulse excitation signal generation circuit for a piezoelectric ultrasonic transducer. Background Technology

[0002] A piezoelectric ultrasonic transducer is a device that utilizes the inverse and direct piezoelectric effects of piezoelectric materials to achieve the conversion between electrical energy and acoustic energy. Piezoelectric ultrasonic transducers have wide applications in medical imaging, industrial non-destructive testing, and biological health monitoring. However, piezoelectric ultrasonic transducers place high demands on their drive circuits, requiring the conversion of the DC voltage output from a high-voltage power supply into specific AC pulses. Furthermore, their drive circuits are susceptible to influences from outdoor environments and electromagnetic interference.

[0003] Traditional drive circuit topologies for piezoelectric ultrasonic transducers mainly include single-transistor drive, half-bridge drive, and full-bridge drive. Single-transistor drive can generate unidirectional spike pulses and is often used for single-pulse excitation; half-bridge drive topology can generate dual-level pulses with an amplitude of E / 2; and full-bridge drive topology can output dual-level pulses with amplitudes of +E and -E.

[0004] Therefore, it is evident that traditional piezoelectric ultrasonic transducer drive circuits can only generate dual-level pulse signals at most. Dual-level pulse signals are easily affected by factors such as outdoor electromagnetic interference in modern applications, and their penetration capability is limited by the peak voltage, resulting in low energy transmission efficiency of the piezoelectric ultrasonic transducer. Summary of the Invention

[0005] To address the shortcomings of existing technologies, such as the frequent impact of outdoor electromagnetic interference and the limitation of penetration capability by peak voltage, resulting in low energy transmission efficiency of piezoelectric ultrasonic transducers, this invention proposes a five-level pulse excitation signal generation circuit for piezoelectric ultrasonic transducers. This circuit converts two DC voltages of unequal voltage into a multi-level polar pulse excitation voltage source, which is then boosted by a pulse transformer. The resulting high-voltage pulse signal can be used to excite the piezoelectric ultrasonic transducer, thereby solving the problems existing in the prior art.

[0006] A five-level pulse excitation signal generation circuit for a piezoelectric ultrasonic transducer includes:

[0007] Two cascaded H-bridge circuits; each of the H-bridge circuits includes four power switching transistors;

[0008] Two DC voltage sources, V1 and V2, with unequal voltages, supply power to the two H-bridge circuits respectively;

[0009] An FPGA controller is used to generate a PWM signal with a dead time to control the on and off of the eight power switches, so as to output a five-level pulse excitation signal for driving the piezoelectric ultrasonic transducer: +(V1+V2), +V2, 0, -V2, -(V1+V2); wherein, the range of the dead time is determined based on the on and off delay time of the power switches of the H-bridge circuit and parasitic parameters.

[0010] Furthermore, the two cascaded H-bridge circuits are H-bridge 1 and H-bridge 2, respectively; H-bridge 1 includes switching transistors S1, S2, S3, and S4; the collectors of S1 and S2 are connected together, serving as the positive power supply terminal of H-bridge 1; the emitters of S1 and S3 are connected together, serving as the first output node of H-bridge 1; the emitters of S2 and S4 are connected together, serving as the second output node of H-bridge 1; and the emitters of S3 and S4 are connected together, serving as the negative power supply terminal of H-bridge 1.

[0011] The H-bridge 2 includes switching transistors S5, S6, S7, and S8; the collectors of S5 and S6 are connected together, serving as the positive power supply terminal of the H-bridge 2; the emitters of S5 and S7 are connected together, serving as the first output node of the H-bridge 2; the emitters of S6 and S8 are connected together, serving as the second output node of the H-bridge 2; and the emitters of S7 and S8 are connected together, serving as the negative power supply terminal of the H-bridge 2.

[0012] Furthermore, the FPGA controller controls the power switching transistors through the following logic:

[0013] When the power switches S1 and S4 in H-bridge 1 and S5 and S8 in H-bridge 2 are closed, and the remaining power switches are open, the output terminals of the two H-bridge circuits output +(V1+V2).

[0014] When power switches S3 and S4 in H-bridge 1 and power switches S5 and S8 in H-bridge 2 are closed, and all other power switches are open, the output terminals of the two H-bridge circuits output +V2.

[0015] When power switches S3 and S4 in H-bridge 1 and power switches S7 and S8 in H-bridge 2 are closed, and all other power switches are open, the output terminals of the two H-bridge circuits output 0.

[0016] When power switches S3 and S4 in H-bridge 1 and power switches S6 and S7 in H-bridge 2 are closed, and all other power switches are open, the output terminals of the two H-bridge circuits output -V2.

[0017] When the power switches S2 and S3 in H-bridge 1 and S6 and S7 in H-bridge 2 are closed, and the remaining power switches are open, the output terminals of the two H-bridge circuits output -(V1+V2).

[0018] Furthermore, the power switch is an IGBT or a MOSFET.

[0019] Furthermore, each power switch is connected in parallel with an RC snubber protection circuit to suppress turn-off losses and voltage spikes.

[0020] Furthermore, the positive terminal of the DC voltage source V1 is connected to the positive power input terminal of the H-bridge 1, and the negative terminal of the DC voltage source V1 is connected to the negative power input terminal of the H-bridge 1; the positive terminal of the DC voltage source V2 is connected to the positive power input terminal of the H-bridge 2, and the negative terminal of the DC voltage source V2 is connected to the negative power input terminal of the H-bridge 2.

[0021] Furthermore, it also includes a pulse transformer, whose input is connected to the output of two H-bridge circuits, used to boost the five-level pulse excitation signal.

[0022] Furthermore, a broadband impedance matching network is connected between the pulse transformer and the piezoelectric ultrasonic transducer.

[0023] Furthermore, it also includes an inverting superposition module connected to the broadband impedance matching network; the inverting superposition module is used to generate an inverted periodic signal with the same frequency as the five-level pulse excitation signal.

[0024] This invention provides a five-level pulse excitation signal generation circuit for piezoelectric ultrasonic transducers, which has the following advantages:

[0025] This invention uses two independent full-bridge modules connected in series to superimpose the output voltages, thereby generating a five-level pulse signal output. Pulse Width Modulation (PWM) technology is employed to precisely control the switching transistors in the H-bridge circuit and a reasonable dead time is set. By generating a corresponding PWM control signal based on the required five-level pulse excitation signal waveform, the on and off times of the switching transistors can be flexibly adjusted, accurately outputting different levels and achieving precise control of the excitation signal. Furthermore, by considering the on and off delay times of the two power switches in the H-bridge arm and the voltage hysteresis caused by circuit parasitic parameters, a reasonable dead time setting ensures that the state transitions of the eight power switches in the circuit do not conflict, and also reduces glitches in the five-level pulse excitation signal output by the circuit. Compared to dual-level pulse signals, multi-level high-voltage pulse excitation signals can improve the signal-to-noise ratio through signal encoding processing and reduce the influence of outdoor electromagnetic interference and other factors. Secondly, multi-level high-voltage pulse excitation signals have stronger penetration capabilities and more uniform energy distribution, improving the energy transmission efficiency of the piezoelectric ultrasonic transducer. Attached Figure Description

[0026] Figure 1This is an overall design diagram of the five-level pulse excitation signal in an embodiment of the present invention;

[0027] Figure 2 This is a timing diagram showing the working state of four power switching transistors (including dead time) controlled by PWM in an embodiment of the present invention;

[0028] Figure 3 This is a timing diagram of FPGA control generating PWM in an embodiment of the present invention;

[0029] Figure 4 This is a simulation diagram of five-level pulse excitation in an embodiment of the present invention;

[0030] Figure 5 This is a schematic diagram showing the comparison of the results of eliminating the tailing effect in an embodiment of the present invention. Detailed Implementation

[0031] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0032] This invention proposes a circuit topology for a five-level pulse excitation signal. By connecting two independent full-bridge modules in series to superimpose the output voltages, the inverter voltages are superimposed to generate a five-level pulse signal output.

[0033] This invention uses two cascaded H-bridge circuits to generate a five-level pulse excitation signal. Each H-bridge circuit consists of four power switching transistors (such as IGBTs or MOSFETs). By controlling the on and off states of these transistors, different output levels can be achieved. The two H-bridge circuits are designated H-bridge 1 and H-bridge 2, and their outputs are interconnected. The power supply consists of two unequal DC voltage sources, V1 and V2, which power H-bridge 1 and H-bridge 2 circuits respectively.

[0034] H-bridge 1 includes switching transistors S1, S2, S3, and S4; the collectors of S1 and S2 are connected together, serving as the positive terminal of the power supply for H-bridge 1; the emitter of S1 is connected together with the collector of the lower bridge arm switching transistor S3, forming the first output node of H-bridge 1; the emitter of S2 is connected together with the collector of the lower bridge arm switching transistor S4, forming the second output node of H-bridge 1; the emitters of S3 and S4 are connected together, serving as the negative terminal of the power supply for H-bridge 1.

[0035] H-bridge 2 includes switching transistors S5, S6, S7, and S8; the collectors of S5 and S6 are connected together, serving as the positive power supply terminal of H-bridge 2; the emitter of S5 is connected together with the collector of the lower bridge arm switching transistor S7, forming the first output node of H-bridge 2; the emitter of S6 is connected together with the collector of the lower bridge arm switching transistor S8, forming the second output node of H-bridge 2; the emitters of S7 and S8 are connected together, serving as the negative power supply terminal of H-bridge 2.

[0036] Meanwhile, each power switch (S1~S8) has an RC snubber circuit (resistor R and capacitor C in series) connected in parallel between its collector and emitter. One end of the RC snubber circuit is connected to the collector of the switch, and the other end is connected to the emitter of the switch, forming a parallel connection with the switch to suppress voltage spikes and turn-off losses when the switch is turned off.

[0037] The positive terminal of DC voltage source V1 is connected to the positive terminal of H-bridge 1 (the common collector connection of S1 and S2), and the negative terminal of DC voltage source V1 is connected to the negative power supply terminal of H-bridge 1 (the common emitter connection of S3 and S4). V1 serves as an independent DC voltage source for H-bridge 1, and the output terminal of H-bridge 1 can output three voltage levels: +V1, 0, and -V1. The positive terminal of DC voltage source V2 is connected to the positive power supply terminal of H-bridge 2 (the common collector connection of S5 and S6), and the negative terminal of DC voltage source V2 is connected to the negative power supply terminal of H-bridge 2 (the common emitter connection of S7 and S8). V2 serves as an independent DC voltage source for H-bridge 2, and the output terminal of H-bridge 2 can output three voltage levels: +V2, 0, and -V2. The output nodes of H-bridge 1 and H-bridge 2 are cascaded in series. The second output node of H-bridge 1 is directly connected to the first output node of H-bridge 2 to form a common node of the cascade. The first output node of H-bridge 1 serves as Output1 after cascading. The second output node of H-bridge 2 serves as Output2 after cascading. Output1 and Output2 serve as the final output terminals of H-bridge 1 and H-bridge 2, and can output five different voltage pulse signals: +(V1+V2), +V2, 0, -V2, and -(V1+V2).

[0038] (1) Switch control strategy:

[0039] To achieve accurate output of the five-level pulse excitation signal, precise control of the switching transistors in the H-bridge circuit is required. This invention uses an FPGA as the controller for the pulse width modulation (PWM) control signal. Employing PWM technology, it generates corresponding PWM control signals based on the required five-level pulse excitation signal waveform to control the on and off times of the switching transistors (e.g., ...). Figure 1 (As shown). During the process of controlling the closing and turning off of the eight power switches, the PWM control signal needs to set a dead time to ensure that the power switches have sufficient time to complete the state transition and to reduce voltage glitches that occur during the generation of the five-level pulse signal (such as...). Figure 2 (As shown).

[0040] The specific control logic is as follows (as shown in Table 1):

[0041] Table 1 shows the operating status of the eight power switches that generate the five-level pulse signal.

[0042]

[0043] When a +(V1+V2) level is required to be output, switches S1 and S4 of H-bridge 1 are closed, and S2 and S3 are open; switches S5 and S8 of H-bridge 2 are closed, and S6 and S7 are open.

[0044] When a +V2 level output is required, switches S3 and S4 of H-bridge 1 are closed, and S1 and S2 are open; switches S5 and S8 of H-bridge 2 are closed, and S6 and S7 are open.

[0045] When a 0-level output is required, switches S3 and S4 of H-bridge 1 are closed, and S1 and S2 are open; switches S7 and S8 of H-bridge 2 are closed, and S5 and S6 are open.

[0046] When a -V2 level output is required, switches S3 and S4 of H-bridge 1 are closed, and S1 and S2 are open; switches S6 and S7 of H-bridge 2 are closed, and S5 and S8 are open.

[0047] When a -(V1+V2) level is required, switches S2 and S3 of H-bridge 1 are closed, and S1 and S4 are open; switches S6 and S7 of H-bridge 2 are closed, and S5 and S8 are open.

[0048] The innovation of this invention lies in:

[0049] (1) Circuit structure design:

[0050] The circuit topology of cascaded H-bridges includes the specific connection methods of the two H-bridge circuits, the power distribution method, and the circuit connection methods of the H-bridge circuits with the pulse transformer and the broadband impedance matching network. The cascaded two H-bridge circuits are used to generate a five-level pulse excitation signal, which is the basic architecture for achieving the five-level pulse excitation signal output. This cascaded structure cleverly combines the voltage outputs of the two H-bridges, using two DC voltage sources V1 and V2 with unequal voltages for power supply, and can easily obtain a five-level pulse excitation signal at the output. Compared with traditional single H-bridge or other complex multi-level output circuit structures, the circuit of this invention is simple and efficient.

[0051] B. Connection method of circuit and transducer: The connection method and overall layout between the H-bridge cascade circuit and the piezoelectric ultrasonic transducer in the system are designed to achieve specific functions and performance.

[0052] C. Specific Switching Transistor and its RC Snubber Protection Circuit: During the turn-on process, the switching transistor S generates a large di / dt (current change rate), and during the turn-off process, it generates a large du / dt (voltage change rate). Both can cause damage to the switching transistor and false turn-on. Therefore, an RC snubber circuit is designed. When the switching transistor is off, the snubber capacitor C charges, limiting du / dt to reduce turn-off losses. When the switching transistor is on, the snubber capacitor C discharges through the snubber resistor R, which consumes most of the energy, reducing the power consumption of the switching transistor.

[0053] (2) Switch control strategy:

[0054] A. Precise PWM Control: Pulse Width Modulation (PWM) technology is used to precisely control the switching transistors in the H-bridge circuit. By considering the turn-on and turn-off delays of the two power switches in the H-bridge arms and the voltage hysteresis caused by circuit parasitic parameters, a reasonable dead time is set. By generating a corresponding PWM control signal based on the required five-level pulse excitation signal waveform, the turn-on and turn-off times of the switching transistors can be flexibly adjusted, thereby accurately outputting different levels and achieving precise control of the excitation signal. Furthermore, setting a reasonable dead time ensures that the state transitions between the closed and open states of the eight power switches in the circuit do not conflict, and also reduces the occurrence of glitches in the five-level pulse excitation signal output by the circuit, ensuring that the circuit and control method of this invention can be used repeatedly over a long period of time.

[0055] B. Specific control logic: A detailed and specific set of switching transistor turn-on combination logic has been developed. For each target level (+(V1+V2), +V2, 0, -V2, -(V1+V2)), there are clear rules for the power switching transistor to close and open, ensuring that the five-level pulse excitation signal can be generated stably and accurately.

[0056] The present invention has the following advantages:

[0057] (1) Expand the application scope of piezoelectric ultrasonic transducers and ensure the personal safety of users:

[0058] This invention converts DC voltage into a five-level pulse excitation signal output, which is then transformed into a high voltage after passing through a pulse transformer. The circuit designed in this invention is simpler and more portable than traditional circuits, eliminating the need for workers to carry heavy equipment when working in the field. Furthermore, the low-voltage input of this invention ensures the safety of workers using ultrasonic flaw detection equipment.

[0059] (2) Enhance the energy output of the piezoelectric ultrasonic transducer to improve its energy transmission efficiency and control accuracy:

[0060] Compared to traditional single-level or dual-level excitation, five-level pulse excitation signals offer piezoelectric ultrasonic transducers a wider range of energy options. Different level values ​​allow the transducer to output energy more precisely in different operating modes, adapting to various complex application scenarios. For example, in ultrasonic machining, by precisely controlling the five-level pulse excitation signal, the ultrasonic energy output by the transducer can be adjusted according to the processing material and process requirements, achieving finer material processing and improving processing accuracy and quality.

[0061] (3) Enhance defect detection capabilities and reduce defect detection blind spots:

[0062] The high energy and high precision of the five-level pulse excitation signal enable the transducer to detect smaller defects and weaker signal changes. In the non-destructive testing of rails, it can more accurately detect internal defects such as cracks and porosity, improving the reliability of product quality inspection.

[0063] (4) Enhance the suppression of trailing signals:

[0064] By employing antiphase superposition with a periodic signal of the same frequency as the excitation signal, the tailing phenomenon of the piezoelectric ultrasonic transducer can be suppressed. Figure 5 The thick solid line represents the tailing effect without the addition of an inverting signal, while the thin solid line represents the result of eliminating the tailing effect with the addition of an inverting voltage signal. Based on the amplitude comparison, when the original signal is added after the fifth peak of the inverting signal, the subsequent voltage peaks show a significant decrease, and the duration of the tailing effect is also significantly shortened.

[0065] like Figure 1 , Figure 3 As shown, the FPGA generates PWM control signals to control the opening and closing of eight power switching transistors. Figure 2 After the circuit of this invention is controlled by the control timing diagram shown in Table 1, it can generate a five-level pulse excitation signal as the output (the voltage difference between the outputs at Output1 and Output2). The final five-level pulse excitation signal presented by this invention (-72V, -48V, 0V, +48V, +72V) is as follows: Figure 4 As shown; then the pulse transformer raises it to the high voltage section, and the broadband impedance matching network is used to make the piezoelectric ultrasonic transducer work at the optimal operating point. The pulse transformer is represented by M1, the piezoelectric ultrasonic transducer is represented by N1, and the broadband impedance matching is represented by P1.

[0066] Five-level pulse excitation circuits and control methods, as an advanced power electronics technology, have shown significant application prospects in multiple fields due to their core advantages such as suppression of tailing phenomena, efficiency improvement, and voltage stress dispersion. For example:

[0067] (1) Industrial drives and high-power applications

[0068] Future Prospects: In the oil and gas, chemical, and manufacturing industries, five-level technology is gradually replacing traditional drive systems, enabling highly efficient and reliable motor control. For example, in the all-electric drive of pipeline compressors, five-level inverters (such as topologies based on integrated gate commutated thyristors (IGCTs)) can provide tens of megawatts of power output, supporting high-speed AC motor drives. Compared to traditional two-level or three-level systems, it can reduce harmonic distortion by more than 50%, improve system efficiency to over 95%, and simultaneously reduce hardware complexity and debugging difficulty. The introduction of digital control systems (such as FPGAs or digital signal processors (DSPs) further enhances response speed and accuracy, making it suitable for industrial scenarios requiring dynamic load adjustments.

[0069] (2) Power transmission and smart grid

[0070] Future Prospects: In the fields of high-voltage direct current (HVDC) transmission and power electronic transformers (PET), five-level technology offers a high power density solution, replacing traditional power frequency transformers. Diode-clamped or hybrid topology five-level converters can reduce the size of filter components by 50%, enabling compact designs and participating in reactive power compensation and harmonic suppression in the power grid. In smart grids, it serves as a critical interface device, supporting voltage regulation, frequency stabilization, and fault ride-through, enhancing system resilience.

[0071] (3) Railways bear the important tasks of personnel and freight transportation and are one of the important tools for people's travel and inter-regional material exchange. Whether in personnel or freight transportation, railway rails and their complex substructures need to adapt to long-term thermal expansion and contraction and maintain the stability of the transportation line. As the foundation of train operation, the rails are the part that directly bears various loads of locomotives and rolling stock. If the operating rails are not damaged for a long time, the rails are prone to sudden safety accidents such as breakage during operation, which seriously threaten the safety of train operation. Railway rails are generally laid over long distances and cannot be easily disassembled for damage inspection during use. Therefore, it is often necessary for staff to use equipment such as piezoelectric ultrasonic transducers to conduct rail inspection in outdoor environments. Therefore, this invention proposes a rail non-destructive testing system, which uses a five-level pulse excitation signal generation circuit to drive a piezoelectric ultrasonic transducer to detect internal defects in the rails, reduce the influence of outdoor noise on rail flaw detection, and improve the detection accuracy.

[0072] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A five-level pulse excitation signal generation circuit for a piezoelectric ultrasonic transducer, characterized in that, include: Two cascaded H-bridge circuits; each H-bridge circuit includes four power switches; the two cascaded H-bridge circuits are H-bridge 1 and H-bridge 2; H-bridge 1 includes switches S1, S2, S3, and S4; the collectors of S1 and S2 are connected together, serving as the positive power input terminal of H-bridge 1; the emitters of S1 and S3 are connected together, serving as the first output node of H-bridge 1; the emitters of S2 and S4 are connected together, serving as the second output node of H-bridge 1; the emitters of S3... The emitter of S4 is connected to the same terminal as the negative power supply terminal of H-bridge 1; H-bridge 2 includes switching transistors S5, S6, S7, and S8; the collector of S5 is connected to the same terminal as the positive power supply terminal of H-bridge 2; the emitter of S5 is connected to the same terminal as the collector of S7, serving as the first output node of H-bridge 2; the emitter of S6 is connected to the same terminal as the collector of S8, serving as the second output node of H-bridge 2; the emitter of S7 is connected to the same terminal as the negative power supply terminal of H-bridge 2. Two DC voltage sources, V1 and V2, with unequal voltages, supply power to the two H-bridge circuits respectively; An FPGA controller generates a PWM signal with a dead time to control the on / off state of the eight power switches, outputting a five-level pulse excitation signal for driving the piezoelectric ultrasonic transducer: +(V1+V2), +V2, 0, -V2, -(V1+V2). The dead time range is determined based on the on / off delay times of the power switches in the H-bridge circuit and parasitic parameters. The FPGA controller controls the power switches using the following logic: when power switches S1 and S4 in H-bridge 1 and S5 and S8 in H-bridge 2 are closed, the remaining power switches are open, and the outputs of both H-bridge circuits output +(V1+V2); when power switches S1 and S4 in H-bridge 1 are closed... When power switches S3, S4, and S5 and S8 in H-bridge 2 are closed, and the remaining power switches are open, the outputs of both H-bridge circuits are +V2; when power switches S3 and S4 in H-bridge 1 and S7 and S8 in H-bridge 2 are closed, and the remaining power switches are open, the outputs of both H-bridge circuits are 0; when power switches S3 and S4 in H-bridge 1 and S6 and S7 in H-bridge 2 are closed, and the remaining power switches are open, the outputs of both H-bridge circuits are -V2; when power switches S2 and S3 in H-bridge 1 and S6 and S7 in H-bridge 2 are closed, and the remaining power switches are open, the outputs of both H-bridge circuits are -(V1+V2).

2. The five-level pulse excitation signal generation circuit for a piezoelectric ultrasonic transducer according to claim 1, characterized in that, The power switch is either an IGBT or a MOSFET.

3. The five-level pulse excitation signal generation circuit for a piezoelectric ultrasonic transducer according to claim 1, characterized in that, Each power switch is connected in parallel with an RC snubber circuit to suppress turn-off losses and voltage spikes.

4. The five-level pulse excitation signal generation circuit for a piezoelectric ultrasonic transducer according to claim 1, characterized in that, The positive terminal of the DC voltage source V1 is connected to the positive power input terminal of the H-bridge 1, and the negative terminal of the DC voltage source V1 is connected to the negative power input terminal of the H-bridge 1; the positive terminal of the DC voltage source V2 is connected to the positive power input terminal of the H-bridge 2, and the negative terminal of the DC voltage source V2 is connected to the negative power input terminal of the H-bridge 2.

5. The five-level pulse excitation signal generation circuit for a piezoelectric ultrasonic transducer according to claim 1, characterized in that, It also includes a pulse transformer, whose input is connected to the output of two H-bridge circuits, used to boost the five-level pulse excitation signal.

6. A five-level pulse excitation signal generation circuit for a piezoelectric ultrasonic transducer according to claim 5, characterized in that, A broadband impedance matching network is connected between the pulse transformer and the piezoelectric ultrasonic transducer.

7. A five-level pulse excitation signal generation circuit for a piezoelectric ultrasonic transducer according to claim 6, characterized in that, It also includes an inverting superposition module connected to the broadband impedance matching network; the inverting superposition module is used to generate an inverted periodic signal with the same frequency as the five-level pulse excitation signal.

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