Addition circuit, operation circuit, circuit for performing hash algorithm and related device

Abstract

The present disclosure relates to an addition circuit, an operation circuit, a circuit for performing a hash algorithm, and related devices. An addition circuit has first and second inputs, each of which is divided into first to Nth portions in order from a low bit to a high bit, N being an integer greater than 1, corresponding to each other. The addition circuit includes: a carry logic module for calculating one or more carries, each of which corresponds to a carry generated by adding a corresponding one of the first input and a corresponding portion of the second input; a first register module for storing the first to Nth portions of the first input; a second register module for storing the first to Nth portions of the second input; a third register module for storing the one or more carries; and a sum logic module for summing the first to Nth portions of the first input, the first to Nth portions of the second input, and the one or more carries.

Description

TECHNICAL FIELD

[0001] The present disclosure generally relates to an addition circuit, an operation circuit, a circuit for performing a hash algorithm, a computing chip, and a computing device. BACKGROUND

[0002] A hash algorithm is an algorithm that takes variable-length data as input and produces a fixed-length hash value as output, and its essence is to refine information. Since 1993, the U.S. Institute of Standards and Technology has designed and published multiple versions of the Secure Hash Algorithm (SHA), and SHA-256 is one of the secure hash algorithms with a hash length of 256 bits. SUMMARY

[0003] According to a first aspect of the present disclosure, an addition circuit is provided for calculating the sum of a first number and a second number, the addition circuit having a first input representing the first number and a second input representing the second number and having an output representing the sum of the first number and the second number, each of the first input and the second input being divided into 1st to Nth parts corresponding to each other, N being an integer greater than 1, the 1st to Nth parts representing the partial bits of the input in turn from low to high, the addition circuit comprising: a carry logic module configured to calculate one or more carries, each of the one or more carries corresponding to a carry generated by adding a corresponding one of the first input and a corresponding part of the second input; a first register module configured to store the 1st to Nth parts of the first input; a second register module configured to store the 1st to Nth parts of the second input; a third register module coupled to the carry logic module and configured to store the one or more carries; a summation logic module coupled to the first to third register modules and configured to sum the 1st to Nth parts of the first input, the 1st to Nth parts of the second input, and the one or more carries, wherein the sum number output by the summation logic module represents the partial bits of the output in turn from low to high.

[0004] In some embodiments, the carry logic module is configured to calculate the one or more carries using look-ahead carry logic.

[0005] In some embodiments, the summation logic module is implemented as a plurality of ripple-carry adders in parallel.

[0006] In some embodiments, each part of each of the first input and the second input has the same number of bits.

[0007] In some embodiments, the Nth part of each of the first input and the second input has a number of bits greater than that of each of the remaining parts of the input.

[0008] In some embodiments, the carry logic module is configured to compute N-1 carries, an i-th carry of the N-1 carries corresponding to a carry resulting from adding an i-th portion of the first input and an i-th portion of the second input, i = 1, …, N-1; the first register module and the second register module each include 1st to N-th cells, and the sum logic module includes 1st to N-th adders, wherein a j-th cell of the first register module is configured to store a j-th portion of the first input, a j-th cell of the second register module is configured to store a j-th portion of the second input, and a j-th adder of the sum logic module is coupled to the j-th cell of the first register module and the j-th cell of the second register module, j = 1, …, N, wherein a 1st adder of the sum logic module is configured to sum the 1st portion of the first input and the 1st portion of the second input, wherein a k-th adder of the sum logic module is further coupled to the third register module, and the k-th adder is configured to sum the k-th portion of the first input, the k-th portion of the second input, and a k-1-th carry of the N-1 carries, k = 2, …, N.

[0009] In some embodiments, the carry logic module includes a preprocessor configured to perform an exclusive OR operation and an AND operation on each bit of the 1st to N-1st portions of the first input and a corresponding bit of the 1st to N-1st portions of the second input, respectively, in parallel, thereby generating a corresponding carry signal and a generate signal; and a carry generator configured to generate the N-1 carries using the carry signals and the generate signals generated by the preprocessor.

[0010] In some embodiments, the carry generator includes a parallel prefix network.

[0011] According to a second aspect of the present disclosure, there is provided an arithmetic circuit, comprising: a sum module comprising the adder circuit according to any of the embodiments of the first aspect of the present disclosure; and a first arithmetic module coupled to the sum module to provide a first input and a second input of the adder circuit.

[0012] In some embodiments, the arithmetic circuit includes a plurality of arithmetic stages, each of the plurality of arithmetic stages including a respective register module, and the plurality of arithmetic stages includes a first arithmetic stage and a second arithmetic stage immediately following the first arithmetic stage, the second arithmetic stage further including the first register module, the second register module, and the third register module of the adder circuit, the first arithmetic module being arranged between the first arithmetic stage and the second arithmetic stage and coupled to a first respective register module of the first arithmetic stage, the first arithmetic module being configured to operate on data from the first respective register module to produce the first input and the second input of the adder circuit, and the carry logic module of the adder circuit being arranged between the first arithmetic stage and the second arithmetic stage.

[0013] In some embodiments, the plurality of operation stages further comprises a third operation stage immediately following the second operation stage, a third respective register module of the third operation stage coupled to the sum module to receive the output of the addition circuit, and the sum logic module of the addition circuit arranged between the second operation stage and the third operation stage.

[0014] In some embodiments, the operation circuit further comprises a second operation module arranged between the second operation stage and the third operation stage and coupled to the second respective register module of the second operation stage, the second operation module configured to operate on data from the second respective register module.

[0015] In some embodiments, the sum module is a first sum module, the addition circuit is a first addition circuit, and the operation circuit further comprises a second sum module comprising a second addition circuit according to any embodiment of the first aspect of the disclosure, wherein the third operation stage further comprises a first register module, a second register module, and a third register module of the second addition circuit, the second operation module coupled to the second sum module to provide a first input and a second input of the second addition circuit, and configured to operate on data from the second respective register module to produce the first input and the second input of the second addition circuit, and a carry logic module of the second addition circuit arranged between the second operation stage and the third operation stage.

[0016] According to a third aspect of the present disclosure, there is provided a circuit for performing a hash algorithm, comprising: an input configured to receive data; and an operation configured to calculate a hash value based on the received data, and comprising a plurality of operation stages arranged in a pipeline structure, wherein: the plurality of operation stages comprises a first operation stage and a second operation stage immediately following the first operation stage, each of the first operation stage and the second operation stage comprises a 0th extension register module to a 15th extension register module configured to store 0th extension data to 15th extension data of the operation stage respectively, the 15th extension register module comprises a sum register submodule, a carry register submodule and an additional carry register submodule, the circuit further comprises a first extension data operation module arranged between the first operation stage and the second operation stage, the first extension data operation module comprises a first submodule and a second submodule, the first submodule is configured to calculate an initial sum and an initial carry based on the 0th extension data of the first operation stage and based on at least two of the 1st extension data, the 9th extension data and the 14th extension data of the first operation stage, each of the initial sum and the initial carry is divided into 1st to Nth parts corresponding to each other to comprise partial bits of each of them in turn from low to high, wherein the 1st to Nth parts of the initial sum are stored in the sum register submodule of the 15th extension register module of the second operation stage, and the 1st to Nth parts of the initial carry are stored in the carry register submodule of the 15th extension register module of the second operation stage, and the second submodule is configured to calculate N-1 carries, the i-th carry of the N-1 carries corresponds to a carry generated by adding the i-th part of the initial sum and the i-th part of the initial carry, i = 1, …, N-1, wherein the N-1 carries are stored in the additional carry register submodule of the 15th extension register module of the second operation stage.

[0017] In some embodiments, the plurality of operation stages further comprises a third operation stage immediately following the second operation stage, the third operation stage comprises a 14th extension register module configured to store the 14th extension data of the operation stage, and wherein the circuit further comprises a second extension data operation module arranged between the second operation stage and the third operation stage, the second extension data operation module comprises a third submodule, the third submodule comprises 1st to Nth adders, wherein the 1st adder is configured to sum the 1st part of the initial sum and the 1st part of the initial carry, wherein the k-th adder is configured to sum the k-th part of the initial sum, the k-th part of the initial carry and the k-1-th carry of the N-1 carries, k = 2, …, N, and wherein N sums output by the 1st to Nth adders are stored in the 14th extension register module of the third operation stage.

[0018] According to a fourth aspect of this disclosure, a computing chip is provided, including circuitry according to any embodiment of any of the first to third aspects of this disclosure.

[0019] According to a fifth aspect of this disclosure, a computing device is provided, including the computing chip described in a fourth aspect of this disclosure.

[0020] Other features and advantages of this disclosure will become clearer from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0021] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0022] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein:

[0023] Figure 1 These are schematic block diagrams showing operational circuits in some examples;

[0024] Figure 2 This is a schematic block diagram illustrating an adder circuit according to some embodiments of the present disclosure;

[0025] Figure 3 This is a schematic block diagram illustrating the carry logic module of an adder circuit according to some embodiments of the present disclosure;

[0026] Figures 4A-4C This is a schematic block diagram showing some examples of a carry lookahead adder (CLA), a parallel prefix adder (PPA), and a parallel prefix network.

[0027] Figure 5 This is a schematic block diagram illustrating the carry logic module of an adder circuit according to some embodiments of the present disclosure;

[0028] Figure 6 This is a schematic block diagram illustrating the summation logic module of an adder circuit according to some embodiments of the present disclosure;

[0029] Figure 7 This is a schematic block diagram illustrating arithmetic circuitry according to some embodiments of the present disclosure;

[0030] Figure 8 This is a schematic block diagram illustrating arithmetic circuitry according to some embodiments of the present disclosure;

[0031] Figure 9This is a schematic block diagram illustrating arithmetic circuitry according to some embodiments of the present disclosure;

[0032] Figure 10 This is a schematic block diagram illustrating arithmetic circuitry according to some embodiments of the present disclosure;

[0033] Figure 11 This is a schematic diagram illustrating an exemplary pipeline structure for executing the SHA-256 algorithm;

[0034] Figure 12 It is shown Figure 11 A schematic diagram of the first example of the extended register module of the arithmetic stage and the extended data operation module between adjacent arithmetic stages in the pipeline structure;

[0035] Figure 13 It is shown Figure 11 A schematic diagram of a second example of the extended register module of the arithmetic stage and the extended data operation module between adjacent arithmetic stages in the pipeline structure;

[0036] Figure 14 It is shown Figure 11 A schematic diagram of the third example of the extended register module of the arithmetic stage and the extended data operation module between adjacent arithmetic stages in the pipeline structure;

[0037] Figure 15 This is a schematic block diagram illustrating a circuit for performing a hash algorithm according to some embodiments of the present disclosure;

[0038] Figure 16 This is a schematic block diagram illustrating a circuit for performing a hash algorithm according to some embodiments of the present disclosure;

[0039] Figure 17 It is shown Figure 16 A schematic diagram of a first example of the extended register module of the arithmetic stage and the extended data arithmetic module between adjacent arithmetic stages in the circuit shown;

[0040] Figure 18 and Figure 19 It is shown Figure 16 A schematic diagram of a second example of the extended register module of the arithmetic stage and the extended data arithmetic module between adjacent arithmetic stages in the circuit shown;

[0041] Figure 20 and Figure 21 It is shown Figure 16 The diagram shows a third example of the extended register module of the arithmetic stage and the extended data arithmetic module between adjacent arithmetic stages in the circuit shown.

[0042] Note that in the embodiments described below, the same reference numerals are sometimes used across different figures to denote the same parts or parts having the same function, and repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0043] For ease of understanding, the positions, dimensions, and extents of the structures shown in the accompanying drawings and other materials may not represent actual positions, dimensions, and extents. Therefore, the disclosed invention is not limited to the positions, dimensions, and extents disclosed in the accompanying drawings and other materials. Furthermore, the drawings are not necessarily drawn to scale, and some features may be enlarged to show details of specific components. Detailed Implementation

[0044] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0045] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use. Those skilled in the art will understand that they are merely illustrative of exemplary ways that can be used to implement the invention, and not exhaustive.

[0046] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0047] It should be understood that, unless explicitly stated otherwise or derived from the context, when referring to the carry-over resulting from addition or summation, the carry-over usually refers to the final carry-over.

[0048] Figure 1 These are schematic diagrams of the operational circuit 10 in some examples. For example... Figure 1 As shown, the arithmetic circuit 10 includes a summing module 12. The summing module 12 is configured to sum a first number a and a second number b, thereby producing a sum s and a carry c. The arithmetic circuit 10 also includes an arithmetic module 11, which is coupled before the summing module 12 and configured to perform the operation to produce the first number a and the second number b. For example, the summing module 12 can be implemented as an adder (ADD), while the arithmetic module 11 can be implemented as a combinational logic circuit. Generally, an ADD can have two inputs and one output, thus reducing one operand; however, an ADD has more stages, more glitches, a larger area, and higher power consumption. Especially when the input of the ADD comes from a combinational logic circuit, the adder has high power consumption due to high glitches.

[0049] To this end, this disclosure provides an adder circuit that can have reduced or even eliminated glitches, thereby achieving lower power consumption. For example, such an adder circuit can be used to calculate the sum of a first number and a second number. The adder circuit can have a first input representing the first number and a second input representing the second number, and an output representing the sum of the first and second numbers. Each of the first and second inputs is correspondingly divided into portions 1 through N. For example, N can be an integer greater than 1. The portions 1 through N of each input represent the parts of that input sequentially from the least significant bit to the most significant bit. Such an addition circuit includes: a carry logic module configured to calculate one or more carries, each of which corresponds to a carry generated by adding a corresponding portion of a first input to a corresponding portion of a second input; a first register module configured to store portions 1 to N of the first input; a second register module configured to store portions 1 to N of the second input; a third register module coupled to the carry logic module and configured to store the one or more carries; and a summation logic module coupled to the first to third register modules and configured to sum the portions 1 to N of the first input, the portions 1 to N of the second input, and the one or more carries. The sum output by the summation logic module represents the portions of the output from least significant bit to most significant bit.

[0050] The circuits according to various embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. It should be understood that the actual circuit may include other additional components, but in order to avoid obscuring the essential points of the present disclosure, these additional components will not be discussed herein and are not shown in the drawings.

[0051] Figure 2 This is a schematic diagram of an adder circuit 100 according to some embodiments of the present disclosure. For example, the adder circuit 100 is configured to calculate the sum of a first number a and a second number b. The adder circuit 100 may have a first input representing the first number a and a second input representing the second number b, and an output representing the sum s of the first number a and the second number b. Each of the first input a and the second input b is correspondingly divided into portions 1 to N (N is an integer greater than 1), which represent the portion bits of the input from the least significant bit to the most significant bit. For example, the first input a includes portion a1, portion a2, ..., portion aN. N (i.e., a=[a N , a N-1 The second input b includes part 1 b1, part 2 b2, ..., part N b1. N (That is, b = [b N , b N-1The value of N can be determined according to specific needs, for example, it can be 2, 3, 4, 5, 6, 7, 8, etc.

[0052] like Figure 2 As shown, the adder circuit 100 includes a first register module 102, a second register module 104, a third register module 106, a carry logic module 108, and a summation logic module 110.

[0053] The first register module 102 is configured to store the first input 'a'. Specifically, the first register module 102 includes a first unit 1021, a second unit 1022, ..., an Nth unit 102. N Each unit is configured to store a corresponding portion of the first input a. For example, the j-th unit 102 of the first register module 102. j Configured to store the j-th part a of the first input a j (j=1, ..., N).

[0054] The second register module 104 is configured to store the second input b. Specifically, the second register module 104 includes a first unit 1041, a second unit 1042, ..., an Nth unit 104. N Each unit is configured to store a corresponding portion of the second input b. For example, the j-th unit 104 of the second register module 104... j Configured to store the j-th part of the second input b j (j=1, ..., N).

[0055] Carry logic module 108 is configured to calculate N-1 carry values ​​c1, ..., c N-1 Carry-over c1, ..., c N-1 Each of the elements in the set has one bit. The carry bits are c1, ..., c1. N-1 The i-th carry c i The i-th part a corresponding to the first input a i With the i-th part of the second input b i The carry generated by the addition (i=1, ..., N-1). For example, the carry logic module 108 can receive at least the first to N-1 parts a1, ..., a1 of the first input a. N-1 And at least the first to N-1th parts b1, ..., b of the second input b N-1 Then, the carry-lookahead logic is used to calculate the N-1 carry-c1, ..., c1. N-1 Therefore, the carry logic module 108 does not need to sum each bit of the received input, but can quickly obtain the carry at the required bit position by jumping. An exemplary implementation of the carry logic module 108 will be described in detail below with reference to the accompanying drawings.

[0056] The third register module 106 can be coupled to the carry logic module 108 and configured to store the N-1 carry c1, ..., c1. N-1 .

[0057] The summation logic module 110 is configured to calculate the sum s of a first number a and a second number b. The summation logic module 110 can be coupled to the first to third register modules 102-106 to receive the first to Nth parts a1, ..., a1 of the first input a. N The first to Nth parts of the second input b, b1, ..., b N And N-1 carry-in c1, ..., c N-1 And sum them.

[0058] For example, the summation logic module 110 includes a first adder 1101, a second adder 1102, ..., an Nth adder 110 N Each adder is coupled to a corresponding unit in the first register module 102 and a corresponding unit in the second register module 104. For example, the j-th adder 110 of the summation logic module 110... j Unit j 102 coupled to the first register module 102 j The j-th unit 104 of the second register module 104 j Thus, it can receive the j-th part a of the first input a. j The j-th part of the second input b j (j=1, ..., N).

[0059] The first adder 1101 of the summation logic module 110 is configured to sum the first part a1 of the first input a and the first part b1 of the second input b, thereby producing the first sum s1. The k-th adder 110 of the summation logic module 110... k It is also coupled to the third register module 106, so that it can receive carry c1, ..., c N-1 The (k-1)th carry c k-1 (k=2, ..., N). The k-th adder 110 k Configured to the k-th part a of the first input a k The k-th part of the second input b k With carry c of the (k-1)th position k-1 Summing, thus producing the k-th sum s k The summation logic module 110 outputs N sums s1, s2, ..., sn. N The bits from least significant to most significant represent the partial bits of the output s (i.e., s = [s...]). N , s N-1 , …, s1]).

[0060] Originally, the j-th adder 110 j (j=1, ..., N-1) for the j-th part a of the first input a j With the j-th part of the second input b j In addition to generating the sum s when summing, j Otherwise, carry c will be generated. j This carry-over c j It needs to be provided to the (j+1)th adder 110 j+1 Only then can it correctly obtain the (j+1)th part a of the first input a. j+1 The (j+1)th part of the second input b j+1 The sum of s j+1 However, carry signals often have many glitches. If we let the j-th adder be 110... j Carry c j Output to the (j+1)th adder 110 j+1 This will lead to carry c j The glitch propagates to the (j+1)th adder 110 j+1 This results in increased power consumption. In contrast, in the adder circuit taught in this disclosure, such as... Figure 2 As shown, carry c1, ..., c N-1 The carry logic module 108 calculates the value in advance and stores it in the third register module 106. Adders 1102 to 110 (Nth adder) N The inputs all come from registers, thus enabling glitch reduction or even elimination (e.g., by fine-tuning the register clock or register drive). Second adder 1102 to Nth adder 110 N All have a generous setup time lasting a full cycle with minimal glitches, resulting in reduced power consumption. Furthermore, the first adder 1101 itself has no carry from lower bits, thus exhibiting smaller glitches and lower power consumption. In the adder circuit 100, the first adder 1101 to the Nth adder 110... N All carry-in bits generated can be discarded, and the resulting sum is directly the corresponding bits of the sum s.

[0061] Therefore, with Figure 1 In contrast, adder circuit 100 separates the carry logic circuit and summation logic circuit of the adder. The carry logic can be performed in one clock cycle and the calculated carry is stored in a register, while the summation logic can be performed in the next clock cycle based on the input from the register. This reduces the glitches from the carry logic circuit to the summation logic circuit. Furthermore, the summation logic circuit of adder circuit 100 also breaks down a large-scale adder into N smaller-scale adders that can be run in parallel. Adders 1101 to 110N are listed below. N The total area can be less thanFigure 1 The area of ​​the adder in the summing module 12 is reduced, thus enabling lower power consumption.

[0062] Taking the first number 'a' and the second number 'b' as examples, each consisting of 32 bits and split into two parts (16 bits + 16 bits), the summation module 12 of the arithmetic circuit 10 requires one 32-bit adder, while the summation logic module 110 of the adder circuit 100 only requires two 16-bit adders. Generally speaking, the area of ​​one 32-bit adder may be equivalent to the area of ​​three 16-bit adders. Furthermore, a carry-lookahead adder (CLA) is often needed to implement a 32-bit adder with a smaller delay, but CLAs often consume a lot of chip area. A ripple carry adder (RCA) has a much smaller area than a CLA and is comparable to a full adder (FAA), but a 32-bit ripple carry adder has a delay of up to 32 stages, making it too slow. However, in the adder circuit taught in this disclosure, the 32-bit adder can be split into two parallel 16-bit adders (or four parallel 8-bit adders, or one parallel 8-bit adder and four 6-bit adders, etc.). These parallel, smaller-scale adders can be implemented as RCA, thereby achieving speeds close to CLA while having fewer glitches, smaller area, and lower power consumption.

[0063] Each of the first to third register modules 102-106 can, for example, be implemented as a combination of single-bit registers. The number of single-bit registers included in each register module can depend on the number of bits that the register module is to store. In some examples, the portions of each of the first input a and the second input b have the same number of bits. This can, in some cases, make the adder circuit 100 suitable for use in pipelined structures (e.g., as discussed later). Figures 17-21 The described input has a small computational delay. In some examples, two or more parts of each of the first input a and the second input b may also have different numbers of bits. In some examples, the Nth part of each of the first input a and the second input b has more bits than the remaining parts of that input (i.e., parts 1 through N-1). This can, for example, simplify or speed up carry logic calculations. In some examples, the first part of each of the first input a and the second input b has more bits than the remaining parts of that input (i.e., parts 2 through N).

[0064] Figure 3 The carry logic module 108 of an adder circuit 100 according to some embodiments of the present disclosure is shown. For example... Figure 3As shown, the carry logic module 108 may include a preprocessor 1082 and a carry generator 1084. The preprocessor 1082 may be configured to process the first to N-1 portions [a] of the first input a in parallel. N-1 Each bit of [, …, a1] and the first to N-1 parts of the second input b [b N-1 The corresponding bits of [b1, ..., b1] are XORed and ANDed respectively to generate the corresponding Propogate Signal p and Generate Signal g. The carry generator 1084 can be configured to use the Propogate Signal p and Generate Signal g generated by the preprocessor 1082 to generate carry c1, ..., c2. N-1 .

[0065] In some embodiments, the carry logic module 108 can be designed based on the construction of a carry-lookahead adder (CLA) or a parallel prefix adder (PPA). For example, refer to... Figures 4A-4C , Figure 4A and Figure 4B Example constructions of a carry-lookahead adder (CLA) and a parallel prefix adder (PPA) are shown respectively. Figures 4A-4C In this context, M represents the number of bits input to the adder. Figures 4A-4C In the example, assume that the bits of the M-bit number a are represented from least significant bit to most significant bit as A1, A2, ..., A... M-1 A M Furthermore, the bits of the M-bit number b are represented sequentially from least significant bit to most significant bit as B1, B2, ..., B... M-1 B M Furthermore, the bits of the transmitted signal p are represented sequentially from least significant bit to most significant bit as P1, P2, ..., P... M-1 P M Furthermore, the bits of the generated signal g are represented sequentially from least significant bit to most significant bit as G1, G2, ..., G... M-1 G M .like Figure 4A As shown, P v =A v ⊕B v G v =A v ·B v v = 1, 2, ..., M, where ⊕ represents the XOR operation and · represents the AND operation. For example, the carry chain of the CLA (C in The carry input is equal to the initial carry C0, C out Output the carry and it equals the final carry C. M C1 to C M-1 (for carry-over) and the formula can be calculated as follows:

[0066] C0=G0=C in ;

[0067] C1=G1+P 1· C0;

[0068] C2= G2+P2·C1= G2+P2·(G1+P1·C0)= G2+P2·G1+P2·P1·C0;

[0069] ...

[0070] C M = G M +P M ·C M-1 =……;

[0071] S v =P v ⊕C v-1 v = 1, 2, ..., M.

[0072] To reduce the depth of the AND gate, PPA further optimizes CLA. The computational flow of PPA and CLA is largely the same, except that in calculating C... v Sufficient parallel optimization was performed. Currently, several PPA variants exist, whose main design approach is to achieve a balance in terms of adder range, circuit depth, number of node outputs, and overall routing. For example, ... Figure 4B As shown, it is comparable to Figure 4A The CLA shown implements the carry generator as a parallel prefix network. Figure 4C Three parallel prefix networks are illustrated exemplarily in the case of M=16. For a detailed discussion of PPA and parallel prefix networks, see Milad Bahadori et al.'s article entitled "A comparative study on performance and reliability of 32-bit binary adders" (https: / / doi.org / 10.1016 / j.vlsi.2015.12.002), published in Integration, Vol. 53, pp. 54-67, March 2016, which is incorporated herein by reference in its entirety.

[0073] Since the carry logic module 108 does not need to obtain the carry at each bit position, nor the sum at each bit position, it can have simplified carry logic compared to CLA and PPA, and does not require a post-processor. For example, Figure 5Taking the first number 'a' and the second number 'b' as examples, each consisting of 32 bits and divided into four parts of the same number of bits (where the carry logic module 108 calculates three carry values ​​c1, c2, and c3), the carry logic module 108 modified based on PPA is shown. Carry input C in It can be set to 0. The first part of the first number 'a', a1 = [A8, A7, …, A1], and the second part, a2 = [A…]. 16 A 15 [, …, A9] and part 3 a3=[A 24 A 23 , …, A 17 ] and the first part of the second number b, b1=[B8, B7, …, B1], and the second part, b2=[B 16 B 15 [, …, B9] and part 3 b3=[B 24 B 23 , …, B 17 The first number a is input to the preprocessor 1082 of the carry logic module 108, and the fourth part a4 of the first number a = [A 32 A 31 , …, A 25 ] and the fourth part of the second number b, b4 = [B 32 B 31 B 25 This can be processed without inputting into the carry logic module 108. Therefore, Figure 5 The preprocessor 1082 in the middle is compared to, for example Figure 4B The preprocessor of the PPA shown can reduce the number of XOR gates and AND gates by 8. In other words, instead of constructing the carry logic module 108 based on a 32-bit PPA, it can be constructed based on a 24-bit PPA. Furthermore, the carry generator 1084 can use a parallel prefix network to obtain the intermediate carry C8 (as the first carry c1) and C in a skip-step manner. 16 (as the second carry c2) and C 24 (as the third carry-over c3), without needing to obtain C1 to C7, C9 to C 15 C 17 To C 23 C 25 To C 32 There is no need to obtain S1 to S2 further. 32 .

[0074] Figure 6 The summation logic module 110 of an adder circuit 100 according to some embodiments of the present disclosure is shown. Figure 6 continue Figure 5For example, the first adder 1101 to the fourth adder 1104 of the summation logic module 110 are implemented as four parallel 8-bit RCAs. The RCAs can be implemented as a cascaded combination of a full adder FAA and / or a half adder (HA) HA. For example... Figure 6 As shown, the first adder 1101 includes a cascaded combination of a half adder HA and seven full adders FAA. Each stage of this cascaded combination receives a corresponding bit of the first part a1 = [A8, A7, …, A1] of a first number a and a corresponding bit of the first part b1 = [B8, B7, …, B1] of a second number b, and outputs a corresponding bit of the sum s1 = [S8, S7, …, S1] of the first part a1 of the first number a and the first part b1 of the second number b. Alternatively, the half adder HA can also be implemented as FAA, where the carry input of the FAA can be set to 0. The carry (e.g., C) output by each stage of this cascaded combination except the last stage is... v (v=1, 2, ..., 7)) is input into the next level, and the carry C8 of the last level output of the cascade combination can be discarded.

[0075] The second adder 1102 comprises a cascaded combination of eight full adders FAA. Each stage of this cascaded combination receives the second part a2 of the first number a = [A]. 16 A 15 The corresponding digit of [A9] and the second part of the second number b, b2 = [B 16 B 15 Output the corresponding bit of [, …, B9] and output the sum of the second part a2 of the first number a and the second part b2 of the second number b, s2=[S 16 , S 15 The corresponding bit of [, …, S9]. The first stage of this cascade combination also receives C8, which is calculated in advance by the carry logic module 108 as the first carry c1. The carry (e.g., C) output by each stage of this cascade combination except the last stage. v (v=9, 10, ..., 15) is input into the next stage, and the carry C of the last stage output of this cascade combination is... 16 It can be discarded.

[0076] The third adder 1103 comprises a cascaded combination of eight full adders FAA. Each stage of this cascaded combination receives the third part a3 of the first number a = [A 24 A 23 , …, A 17 The corresponding digit of ] and the third part of the second number b, b3 = [B 24 B 23 , …, B 17Output the corresponding digit of the first number a and the third part a3 of the second number b, s3=[S 24 , S 23 , …,S 17 The corresponding bit of ] is also received by the first stage of this cascaded combination, which is calculated in advance by the carry logic module 108 as the second carry c2. 16 The carry-in (e.g., C) of the output of each stage of the cascaded combination except the last stage. v (v=17, 18, ..., 23)) is input into the next stage, and the carry C of the last stage output of this cascade combination is... 24 It can be discarded.

[0077] The fourth adder 1104 comprises a cascaded combination of eight full adders FAA. Each stage of this cascaded combination receives the fourth part a4 of the first number a = [A 32 A 31 , …, A 25 The corresponding digit of ] and the fourth part of the second number b, b4 = [B 32 B 31 , …, B 25 Output the corresponding digit of the first number a and the fourth part a4 of the second number b, s4=[S 32 , S 31 , …,S 25 The corresponding bit of ] is also received by the first stage of this cascaded combination, which is calculated in advance by the carry logic module 108 as the third carry c3. 24 The carry-in (e.g., C) of the output of each stage of the cascaded combination except the last stage. v (v=25, 26, ..., 31) is input into the next stage, and the carry C of the last stage output of this cascade combination is... 32 It can be discarded.

[0078] Therefore, the summation logic module 110 can directly output the 32-bit sum s=[S] of the first 32-bit number a and the second 32-bit number b. 32 , S 31 , …, S1).

[0079] Figure 7 An operational circuit 200 according to some embodiments of the present disclosure is shown. For example... Figure 7 As shown, the arithmetic circuit 200 includes a summing module 220 and a first arithmetic module 210 coupled to the summing module 220. The summing module 220 may include the addition circuit 100 described in any of the foregoing embodiments. The first arithmetic module 210 may provide a first input and a second input to the addition circuit 100. Figures 8-10 They are shown respectivelyFigure 7 Several non-limiting example configurations of the operational circuit 200 shown.

[0080] In some examples, the arithmetic circuit 200 includes multiple arithmetic stages. For example, these arithmetic stages can be arranged in a pipelined structure. Each arithmetic stage can include a corresponding register module.

[0081] like Figure 8 As shown, the multiple operation stages of the arithmetic circuit 200 include a first operation stage 230a and a second operation stage 230b immediately following the first operation stage 230a. The first operation stage 230a includes a first corresponding register module 232a. The second operation stage 230b includes a second corresponding register module 232b, and also includes first to third register modules 102-106 of the adder circuit of the summation module 220. A first operation module 210 is arranged between the first operation stage 230a and the second operation stage 230b and coupled to the first corresponding register module 232a of the first operation stage 230a. For example, the first operation module 210 can be configured to perform operations on data from the first corresponding register module 232a to generate a first input and a second input of the adder circuit of the summation module 220. In addition, the carry logic module 108 of the adder circuit of the summation module 220 can also be arranged between the first operation stage 230a and the second operation stage 230b.

[0082] like Figure 9 As shown, in some examples, the multiple operational stages of the arithmetic circuit 200 also include a third operational stage 230c immediately following the second operational stage 230b. The third operational stage 230c includes a third corresponding register module 232c. The third corresponding register module 232c of the third operational stage 230c can be coupled to the summing module 220 to receive the output of its adder circuit. For example, the summing logic module 110 of the adder circuit of the summing module 220 can be arranged between the second operational stage 230b and the third operational stage 230c.

[0083] like Figure 10 As shown, in some examples, the arithmetic circuit 200 further includes a second arithmetic module 240 disposed between the second arithmetic stage 230b and the third arithmetic stage 230c. The second arithmetic module 240 may be coupled to a second corresponding register module 232b of the second arithmetic stage 230b and configured to perform operations on data from the second corresponding register module 232b. For example, the second arithmetic module 240 may have the same configuration as the first arithmetic module 210.

[0084] In some examples, the arithmetic circuit 200 may also include another summing module 220', which may have the same configuration as the summing module 220. In such an example, the third arithmetic stage 230c may further include first to third register modules 102-106 of the summing module 220'. The second arithmetic module 240 may be coupled to the summing module 220' to provide the first and second inputs of its adder circuit. The second arithmetic module 240 may be configured to perform operations on data from the second corresponding register module 232b to produce the first and second inputs of the adder circuit of the summing module 220'. The carry logic module 108 of the adder circuit of the summing module 220' may also be arranged between the second arithmetic stage 230b and the third arithmetic stage 230c.

[0085] Although not shown, the first operational stage 230a may also include the first to third register modules of the adder circuit of another summing module, and the summing logic module of the adder circuit of this other summing module may also be arranged between the first operational stage 230a and the second operational stage 230b. That is, the internal configuration of each operational stage of the operational circuit 200 and the configuration between adjacent operational stages may be the same.

[0086] To present the inventive concept of this disclosure more clearly and intuitively, the SHA-256 algorithm will be briefly introduced below, and its use as a representative example of a hash algorithm will be used to describe the circuitry for executing the hash algorithm according to embodiments of this disclosure. Those skilled in the art will understand that the circuitry for executing the hash algorithm according to embodiments of this disclosure is applicable to any hash algorithm and can even be further applied to any other suitable circuitry, and is not limited to implementing the SHA-2 series algorithms such as the SHA-256 algorithm.

[0087] Figure 11 A schematic diagram of an exemplary pipeline structure for performing the SHA-256 algorithm is shown. The input to SHA-256 is a maximum length less than 2. 64 The input data is processed in 512-bit blocks, and the output is a 256-bit data digest, i.e., a hash value. To implement the SHA-256 algorithm, 64 rounds of repeated computation are required for each 512-bit data block. Therefore, a pipelined architecture with 64 computation stages can be used to process 64 sets of data in parallel. Figure 11 As shown, the pipeline architecture includes operation stages 0 to 63. Each operation stage includes eight 32-bit compressed register modules A to H for storing intermediate values ​​and sixteen 32-bit extended register modules R0 to R1 for storing extended data. 15The 0th operation stage receives the input data block, divides it into eight 32-bit data segments, stores them in compression register modules A through H, processes them, and then provides the results to the 1st operation stage. Afterward, each operation stage processes the results received from the previous stage and provides its own result to the next stage. Finally, after 64 operation stages, this pipeline structure outputs the hash result of the input data having undergone one SHA-256 algorithm operation.

[0088] The internal logic of a round of operations performed by SHA-256 at each operational level is discussed in detail below. The t-th round of operations performed at the t-th operational level is defined by the following formula (t is an integer and satisfies 0 ≤ t ≤ 63):

[0089] T1 = H + Σ1(E) + Ch(E, F, G) + K t + W t ;

[0090] T2 = Σ0(A) + Maj(A, B, C);

[0091] H = G;

[0092] G = F;

[0093] F = E;

[0094] E = D + T1;

[0095] D = C;

[0096] C = B;

[0097] B = A;

[0098] A = T1 + T2; (Equation 1)

[0099] in:

[0100] Ch(x, y, z)=(x AND y) ⊕ ((NOT x) AND z)

[0101] Maj(x, y, z)= (x AND y) ⊕ (x AND z) ⊕ (y AND z)

[0102] Σ0(x)=ROTR 2 (x) ⊕ ROTR 13 (x) ⊕ ROTR 22 (x)

[0103] Σ1(x)=ROTR 6(x) ⊕ ROTR 11 (x) ⊕ ROTR 25 (x)

[0104] Among them, ROTR n (x) represents a circular right shift of n bits on a 32-bit variable x; W t For a 32-bit word, derive it from the current 256-bit input data block; K t A 32-bit additional constant; + indicates modulo 2. 32 Add; AND is a 32-bit bitwise AND operation; NOT is the negation operation; ⊕ is the XOR operation.

[0105] Next, we will describe the 32-bit word W. t How was it derived from a 512-bit data block? t It can be obtained using the following formula:

[0106] For 0 ≤ t ≤ 15: W t Taken directly from the input data block;

[0107] For 16 ≤ t ≤ 63:

[0108] W t =σ1(W t-2 ) + W t-7 + σ0(W t-15 ) + W t-16 (Equation 2)

[0109] in:

[0110] σ0(x) = ROTR 7 (x) ⊕ ROTR 18 (x) ⊕ SHR 3 (x)

[0111] σ1(x) = ROTR 17 (x) ⊕ ROTR 19 (x) ⊕ SHR 10 (x)

[0112] Among them, ROTR n (x) represents a circular right shift of n bits on a 32-bit variable x; SHR n (x) represents shifting the 32-bit variable x to the right by n bits, filling the left side with 0s; ⊕ is the XOR operation; + is the modulo 2 operation. 32 add.

[0113] Note that the formulas for the functions Σ0(x), Σ1(x), σ0(x), and σ1(x) above are given as examples of SHA-256 for processing 32-bit data. Those skilled in the art know that in other SHA algorithms (such as SHA-512) and even other hash algorithms, these functions can be adapted to other corresponding forms to process data of other sizes (such as 64-bit data).

[0114] The following is combined with Figures 12-14 describe Figure 11 This section provides several non-restricted example configurations of the extended register modules in the arithmetic stages and the extended data operation modules between adjacent arithmetic stages within the pipelined architecture. It is understood that... Figures 12-14 Some extended register modules and extended data operation modules are depicted in gray for illustrative purposes only and are not intended to be restrictive.

[0115] Figure 12 It is shown Figure 11 A schematic diagram of the first example of the extended register module of the operation stage and the extended data operation module between adjacent operation stages in the pipeline structure.

[0116] refer to Figure 12 It requires the use of extended register modules R0, R1, R9, and R1 for each arithmetic stage. 14 The extended data in the calculation is used to calculate the extended register module R to be stored in the next operation stage. 15 Extended data in, and additional extended register modules R1 to R 15 The extended data in the register can be directly shifted to the corresponding extended register module R0 to R1 in the next operation stage. 14 In the middle. Specifically, the extended register module R of the (t+1)th operation level. 15 Extended data W15 in t+1 The 0th extended data W0 in the extended register module R0 of the t-th operation stage is processed by two 32-bit full adders FAA1 and FAA2 and one 32-bit adder ADD. t The first extended data W1 in the extended register module R1 of the t-th operation level t The σ0(W1) obtained after the σ0 operation is performed by the σ0 operator t The 9th extended data W9 in the extended register module R9 of the t-th operation level. t The extended register module R at the t-th operation level 14 Extended data W14 in t The σ1(W14) obtained after σ1 operation by the σ1 operator t The result is obtained by adding them together, i.e., W15. t+1 =W0 t +σ0(W1t +W9 t +σ1(W14 t As can be seen, from the extended register modules R0, R1, R9, and R at the t-th operation level... 14 The 0th extended data W0 t Extended Data W1 t Extended Data W9, No. 9 t Extended Data 14 W14 t The calculations need to be stored in the extended register module R of the next operation stage. 15 Extended data W15 in t+1 The computational logic stages required are as high as four, which leads to significant computational latency, limits the computational speed of the pipeline structure, and makes it difficult to achieve a low power consumption-to-computing power ratio.

[0117] In this regard, the inventors of this application noted that there is a direct connection between the extended register module R0 of the (t+1)th operation level and the extended register module R1 of the tth operation level; that is, the extended data stored in the extended register module R1 of the tth operation level is directly shifted to the extended register module R0 of the (t+1)th operation level. Therefore, the inventors of this application conceived of using this direct connection between the extended register modules R0 and R1 to transfer the extended register module R0 used for calculating the (t+2)th operation level... 15 During the process of storing extended data, the portion of the extended data in the extended register module R0 of the (t+1)th operation level (i.e., the extended data in the extended register module R1 of the t-th operation level) is moved forward to the extended register module R1 used for calculating the (t+1)th operation level. 15 The process of storing the extended data is performed simultaneously and stored in the extended register module R0 of the (t+1)th operation level. In this way, the extended register module R0 used for calculating the (t+2)th operation level can be used... 15 After decomposing the process of storing the extended data, the decomposed parts are combined with the extended register module R used to calculate the (t+1)th operation level. 15 The process of storing extended data is handled in parallel. Parallel processing reduces the number of logical operation stages required to compute the extended data in each round, thereby increasing the processing speed of the circuit and the computing chip containing it, facilitating a lower power-to-computing power ratio. Specifically, the 15th extended register module R of the (t+2)th operation stage... 15 The 15th extended data W15 stored in the middle t+2 The first extended data W1 is stored in the first extended register module R1 of the t-th operation level. t The second extended data W2 is stored in the second extended register module R2 of the t-th operation level. t The 10th extended register module R of the t-th operation level10 The 10th extended data W10 stored in the middle t and the 15th extended register module R of the t-th operation level 15 The 15th extended data W15 stored in the middle t The following relationship can be satisfied: W15 t+2 =W1 t +σ0(W2 t )+W10 t +σ1(W15 t ), where the definitions of σ0, σ1, and + are as described above.

[0118] For example, it can be based on the second extended register module R2 and the tenth extended register module R at the t-th operation level. 10 15th Extended Register Module R 15 The extended data to be stored in the 0th extended register module R0 of the (t+1)th operation level is calculated based on the extended data stored in one or both of the extended register modules and the extended data stored in the 1st extended register module R1 of the t-th operation level. Alternatively, the extended data can be calculated based on the 1st extended register module R1, the 9th extended register module R9, and the 14th extended register module R0 of the t-th operation level. 14 The extended data stored in one or both of these registers, along with the extended data stored in the 0th extended register module R0 of the t-th operation level, are used to calculate the data to be stored in the 15th extended register module R of the (t+1)-th operation level. 15 Extended data within.

[0119] Figure 13 It is shown Figure 11 A schematic diagram of a second example of the extended register module of the operation stage and the extended data operation module between adjacent operation stages in the pipeline structure.

[0120] like Figure 13 As shown, the 0th extended data W0 in the 0th extended register module R0 of the (t+1)th operation stage t+1 The first extended data W1 is stored in the first extended register module R1 of the t-th operation level. t and the second extended data W2 stored in the second extended register module R2 t Obtained. Specifically, in this example, W0 t+1 =W1 t +σ0(W2 t ).

[0121] Further as Figure 13 As shown, the 15th extended register module R of the (t+1)th operation level 15 Extended data W15 in t+1The 0th extended data W0 is stored in the 0th extended register module R0 of the t-th operation level. t The 9th extended data W9 is stored in the 9th extended register module R9. t and the 14th extended register module R 14 The 14th extended data W14 stored in the middle t Resulting. Specifically, in this example, W15 t+1 =W0 t +W9 t + σ1(W14 t ).

[0122] Further as Figure 13 As shown, the extended data stored in the i-th extended register module of the t-th operation level is directly shifted to the (i-1)-th extended register module of the (t+1)-th operation level, where 2≤i≤15 and i is an integer.

[0123] exist Figure 13 In the example shown, the number of computational logic stages required to finally compute the extended data for the (t+1)th operation stage is reduced to 3, which greatly reduces computational latency and significantly improves the computational speed of the pipeline structure.

[0124] The extended data operation module between the (t+1)th operation level and the (t+2)th operation level can be the same as the extended data operation module between the t-th operation level and the (t+1)th operation level. Further, as... Figure 13 As shown, the 15th extended register module R of the (t+2)th operation stage 15 Extended data W15 in t+2 The 0th extended data W0 is stored in the 0th extended register module R0 of the (t+1)th operation level. t+1 The 9th extended data W9 is stored in the 9th extended register module R9. t+1 and the 14th extended register module R 14 The 14th extended data W14 stored in the middle t+1 Resulting. Specifically, in this example, W15 t+2 =W0 t+1 +W9 t+1 +σ1(W14 t+1 )=W1 t +σ0(W2 t )+W10 t +σ1(W15 t ).

[0125] Figure 14 It is shown Figure 11 A schematic diagram of the third example of the extended register module of the operation stage and the extended data operation module between adjacent operation stages in the pipeline structure.

[0126] like Figure 14 As shown, the 0th extended data W0 in the 0th extended register module R0 of the (t+1)th operation stage t+1 The first extended data W1 is stored in the first extended register module R1 of the t-th operation level. t and the 10th extended register module R 10 The 10th extended data W10 stored in the middle t Obtained. Specifically, in this example, W0 t+1 =W1 t +W10 t .

[0127] Further as Figure 14 As shown, the 15th extended register module R of the (t+1)th operation level 15 Extended data W15 in t+1 The 0th extended data W0 is stored in the 0th extended register module R0 of the t-th operation level. t The first extended data W1 stored in the first extended register module R1 t and the 14th extended register module R 14 The 14th extended data W14 stored in the middle t Resulting. Specifically, in this example, W15 t+1 =W0 t +σ0(W1 t )+ σ1(W14 t ).

[0128] Further as Figure 14 As shown, the extended data stored in the i-th extended register module of the t-th operation level is directly shifted to the (i-1)-th extended register module of the (t+1)-th operation level, where 2≤i≤15 and i is an integer.

[0129] exist Figure 14 In the example shown, the number of computational logic stages required to finally compute the extended data for the (t+1)th operation stage is reduced to 3, which greatly reduces computational latency and significantly improves the computational speed of the pipeline structure.

[0130] The extended data operation module between the (t+1)th operation level and the (t+2)th operation level can be the same as the extended data operation module between the t-th operation level and the (t+1)th operation level. Further, as... Figure 14 As shown, the 15th extended register module R of the (t+2)th operation stage 15 Extended data W15 in t+2 The 0th extended data W0 is stored in the 0th extended register module R0 of the (t+1)th operation level. t+1The first extended data W1 stored in the first extended register module R1 t+1 and the 14th extended register module R 14 The 14th extended data W14 stored in the middle t+1 Resulting. Specifically, in this example, W15 t+2 =W0 t+1 +σ0(W1 t+1 )+σ1(W14 t+1 )=W1 t +σ0(W2 t )+W10 t +σ1(W15 t ).

[0131] In addition, in some examples, W0 t+1 =W1 t +σ1(W15 t And W15 t+1 =W0 t +σ0(W1 t )+W9 t Therefore, W15 t+2 =W0 t+1 +σ0(W1 t+1 )+W9 t+1 =W1 t +σ0(W2 t )+W10 t +σ1(W15 t This can be used as a reference. Figures 13-14 The configuration is implemented similarly, so I won't go into details here.

[0132] exist Figures 12-14 In some configurations, the input to the adder comes from combinational logic circuits. For example, Figure 12 The input of adder ADD in the code comes from full adder FAA2, and Figure 13 and Figure 14 The input to adder ADD1 in each of them comes from full adder FAA. Therefore, these configurations exist similar to Figure 1 The illustrated arithmetic circuit suffers from high power consumption due to glitches in the adder and delay due to numerous stages. Therefore, these configurations can be modified according to the teachings of this disclosure to achieve a pipelined structure with reduced power consumption and delay.

[0133] Figure 15A circuit 300 for performing a hash algorithm according to some embodiments of the present disclosure is shown, where arrows indicate the direction of data transmission. The circuit 300 may include an input unit 310 and an arithmetic unit 320. The input unit 310 may be configured to receive data. The arithmetic unit 320 may be configured to calculate a hash value based on the received data. The arithmetic unit 320 may include a plurality of arithmetic stages 320-0, ..., 320-63 arranged in a pipelined structure. Each arithmetic stage may include an extended register module configured to store extended data. For example, the extended register module may be implemented as a combination of single-bit registers. It should be understood that although the arithmetic unit 320 is depicted in the figures as including 64 arithmetic stages, as mentioned above, this document only provides a non-limiting example of a circuit for performing the SHA-256 algorithm, and the circuit according to the present disclosure can actually be applied to perform any hash algorithm now known or later developed (not limited to the SHA family of algorithms), and may include any suitable number of arithmetic stages. It should also be understood that the actual circuit may have additional components (such as a compression register module), but to avoid obscuring the key points of this disclosure, these other components are not shown in the accompanying drawings and are not discussed herein. Typically, the extended data of the first operational stage 320-0 of the arithmetic unit 320 can be directly taken from the data received by the input unit 310, for example, while the extended data of each operational stage starting from operational stage 320-1 can be determined, for example, based on the extended data of the previous operational stage.

[0134] Generally, the extended register modules of each of the multiple arithmetic stages 320-0, ..., 320-63 can have the same configuration. In some cases, the extended register modules of each of the multiple arithmetic stages 320-0, ..., 320-63 can have different configurations. For example, there may be one or more arithmetic stages that have one or more fewer extended register modules than other arithmetic stages. This disclosure is not limited to any of the above situations.

[0135] like Figure 15 As shown, the multiple operation stages 320-0, ..., 320-63 include a first operation stage 320-a and a second operation stage 320-b immediately following the first operation stage 320-a. In this paper, the operation stage that comes first among two adjacent operation stages in the pipeline structure can be referred to as the first operation stage, and the operation stage that comes later among two adjacent operation stages can be referred to as the second operation stage. Note that "first" and "second" are used only for distinction and not as a limitation.

[0136] Each of the first operational level 320-a and the second operational level 320-b includes an extended register module R0 to an extended register module R15, respectively configured to store extended data from the 0th to the 15th extensions of that operational level. 1515th Extended Register Module R 15 Includes the sum register submodule R 15s Carry Register Submodule R 15c and the additional carry register submodule R 15ce For example, the sum register submodule R in circuit 300 15s Carry Register Submodule R 15c and the additional carry register submodule R 15ce These can correspond to the first register module 102, the second register module 104, and the third register module 106 in the summation module 220 of the arithmetic circuit 200, respectively. Therefore, their configuration can be similar to the configuration of the first register module 102, the second register module 104, and the third register module 106 described above, and will not be elaborated here.

[0137] Further as Figure 15 As shown, circuit 300 further includes a first extended data processing module 330-a disposed between the first operational stage 320-a and the second operational stage 320-b. The first extended data processing module 330-a includes a first submodule 331 and a second submodule 332.

[0138] The first submodule 331 of the first extended data processing module 330-a can be configured to be based on the 0th extended data W0 of the first processing level 320-a. a And based on the first extended data W1 of the first operation level 320-a a Extended Data W9, No. 9 a and the 14th extended data W14 a At least two of them are used to calculate the initial sum s0 and the initial carry c0. For example, the first submodule 331 of the first extended data operation module 330-a in circuit 300 may correspond to the first operation module 210 of operation circuit 200. The initial sum s0 and the initial carry c0 can be processed as the aforementioned first number a and second number b using the teachings of this disclosure. For example, each of the initial sum s0 and the initial carry c0 is divided into parts corresponding to each other to include the first to the Nth parts (N is an integer greater than 1), which represent the part bits of each part from the least significant bit to the most significant bit. For example, s0 = [s0 N , s0 N-1 ,…, s01], and c0=[c0 N c0 N-1 , …, c01]. The first to Nth parts of the initial sum s0 [s0 N-1 [s01] can be stored in the 15th extended register module R of the second operation level 320-b. 15 The sum register submodule R 15sIn, and the first to Nth parts of the initial carry c0 [c0 N-1 [, …, c01] can be stored in the 15th extended register module R of the second operational level 320-b. 15 Carry register submodule R 15c In, for example, the sum register submodule R 15s and carry register submodule R 15c Each can include units 1 through N to store corresponding parts of the initial sum s0 and the initial carry c0, respectively. In this case, the j-th part s0 of the initial sum s0... j It can be stored in the 15th extended register module R of the second arithmetic stage 320-b 15 The sum register submodule R 15s In the j-th unit, and the j-th part of the initial carry c0 c0 j It can be stored in the 15th extended register module R of the second arithmetic stage 320-b 15 Carry register submodule R 15c In the j-th unit (j=1,…,N).

[0139] The second submodule 332 of the first extended data processing module 330-a can be configured to calculate N-1 carry-in c1, ..., c2. N-1 Carry-over c1, ..., c N-1 The i-th carry in the sum corresponds to the i-th part s0 of the initial sum s0. i The i-th part c0 of the initial carry c0 i Carry generated from addition (i=1, ..., N-1). Carry c1, ..., c N-1 Stored in the 15th extended register module R of the second arithmetic stage 320-b 15 Additional carry register submodule R 15ce For example, the second submodule 332 of the first extended data operation module 330-a in circuit 300 can correspond to the carry logic module 108 in the summation module 220 of operation circuit 200. Therefore, its configuration can be similar to the configuration of the carry logic module 108 described above, and will not be elaborated here.

[0140] In some examples, such as reference Figure 16 The multiple operation levels 320-0, ..., 320-63 also include a third operation level 320-c immediately following the second operation level 320-b. The third operation level 320-c includes a 14th extended data W14 configured to store this operation level. c 14th Extended Register Module R 14Circuit 300 also includes a second extended data processing module 330-b disposed between the second operational stage 320-b and the third operational stage 320-c. The second extended data processing module 330-b includes a third submodule 333.

[0141] The third submodule 333 of the second extended data processing module 330-b may include the first to the Nth adders. The first adder is configured to sum the first part s01 of the initial sum s0 and the first part c01 of the initial carry c0. The kth adder is configured to sum the kth part s0 of the initial sum s0. k The k-th part of the initial carry c0 k With carry c1, ..., c N-1 The (k-1)th carry c k-1 Summation (k=2, ..., N). For example, the third submodule 333 of the second extended data operation module 330-b in circuit 300 can correspond to the summation logic module 110 in the summation module 220 of operation circuit 200. Therefore, its configuration can be similar to the configuration of the summation logic module 110 described above, and will not be repeated here. The N sums output by the first to Nth adders of the third submodule 333 (which consist of the sum s of the initial sum s0 and the initial carry c0) are stored in the 14th extended register module R of the third operation stage 320-c. 14 middle.

[0142] Figures 17-21 The following are examples of applying the teachings of this disclosure to... Figures 12-14 Several non-restrictive example configurations are obtained by making corresponding modifications. This is understandable. Figures 17-21 The grayed-out depiction of some extended register modules and extended data operation modules is for illustrative purposes only and is not intended to be restrictive. Figures 17-21 In the example shown, each operation level can have the same configuration both internally and between adjacent operation levels.

[0143] like Figure 17 As shown, the first submodule 331 of the first extended data operation module 330-a between the first operation level 320-a and the second operation level 320-b includes a σ0 operator, a σ1 operator, and two full adders FAA1 and FAA2, and is configured to operate based on the 0th extended data W0 of the first operation level 320-a. a Extended Data W1 a Extended Data W9, No. 9 a and the 14th extended data W14 aCalculate the initial sum s0 and the initial carry c0. Each of the initial sum s0 and the initial carry c0 is divided into corresponding parts from the first to the Nth (N is an integer greater than 1), where each part represents a portion of the sum from the least significant bit to the most significant bit. For example, s0 = [s0 N , s0 N-1 , …, s01], and c0=[c0 N c0 N-1 The initial sum and parts of the number s0 are stored in the 15th extended register module R of the second arithmetic stage 320-b. 15 The sum register submodule R 15s In this process, the portions of the initial carry c0 are stored in the 15th extended register module R of the second arithmetic stage 320-b. 15 Carry register submodule R 15c middle.

[0144] The second submodule 332 of the first extended data processing module 330-a includes a carry logic module (CLM). The carry logic module CLM can receive at least the first to (N-1)th parts of the initial sum s0 and at least the first to (N-1)th parts of the initial carry c0, thereby generating N-1 carry c1, ..., c2. N-1 Carry-over c1, ..., c N-1 The i-th carry in the sum corresponds to the i-th part s0 of the initial sum s0. i The i-th part c0 of the initial carry c0 i The carry-in (i=1, ..., N-1) generated by the addition. These carry-ins are c1, ..., c2. N-1 Stored in the 15th extended register module R of the second arithmetic stage 320-b 15 Additional carry register submodule R 15ce middle.

[0145] The third submodule 333 of the second extended data operation module 330-b between the second operation level 320-b and the third operation level 320-c includes a sum logic module (SLM). The sum logic module SLM can receive the first to Nth parts of the initial sum s0, the first to Nth parts of the initial carry c0, and the carry c1, ..., c2. N-1 This generates N sums s1, ..., s2. N The summation logic module (SLM) includes adders 1 through N. The first adder is configured to sum the first part s01 of the initial sum s0 with the first part c01 of the initial carry c0, thus producing the sum s1. The k-th adder is configured to sum the k-th part s0 of the initial sum s0. kThe k-th part of the initial carry c0 k With carry c1, ..., c N-1 The (k-1)th carry c k-1 Summing, thus producing the sum s k (k=2, ..., N). N sums s1, ..., s2 N (The sum s of the initial sum s0 and the initial carry c0) is stored in the 14th extended register module R of the third arithmetic level 320-c. 14 middle.

[0146] Therefore, the 14th extended register module R of the third arithmetic stage 320-c 14 The 14th extended data W14 stored in the middle c With the 0th extended data W0 of the first operation level 320-a a Extended Data W1 a Extended Data W9, No. 9 a and the 14th extended data W14 a The following relationship can be satisfied: W14 c =W0 a +σ0(W1 a +W9 a +σ1(W14 a ).

[0147] Figure 17 and Figure 12 In comparison, although calculating "W0" a +σ0(W1 a +W9 a +σ1(W14 a This requires an extra round of processing time, but it doesn't have a significant negative impact on the assembly line structure. Additionally, Figure 17 This breaks the constraints of the 32-bit binary adder. On one hand, Figure 17 Will Figure 12 The separation of the carry logic circuit and the summation logic circuit in the adder ADD makes the application of RCA in a pipelined structure feasible. Specifically, originally Figure 12 If the 32-bit adder ADD is implemented as RCA, it will have 32 stages, and the resulting latency may be unacceptable. Figure 12 A 32-bit adder, ADD, is often implemented as a CLA, but CLAs are large in area, have many glitches, and consume a lot of power. Figure 17 In this context, the summation logic module (SLM) can be implemented as multiple parallel RCAs, which offers reduced area, glitches, and power consumption while achieving speeds close to those of a CLA. On the other hand, Figure 17 Will Figure 12The separation of carry and summation logic in the adder ADD reduces glitches from the carry logic to the summation logic. The inputs to the summation logic module SLM all come from registers, thus reducing or even eliminating glitches, which lowers the power consumption of circuit 300. Therefore, Figure 17 At an acceptable register area power consumption cost (e.g., in an arithmetic stage, compared to) Figure 12 30+N single-bit registers were added, of which R 15c It has 31 single-bit registers and R 15ce It has N-1 single-bit registers, which in turn result in a significant reduction in adder area / glitch power consumption.

[0148] like Figure 18 and Figure 19 As shown, the first submodule 331 of the first extended data operation module 330-a between the first operation level 320-a and the second operation level 320-b includes a σ1 arithmetic unit and a full adder FAA, and is configured to operate based on the 0th extended data W0 of the first operation level 320-a. a Extended Data W9, No. 9 a and the 14th extended data W14 a Calculate the initial sum s0 and the initial carry c0. Each of the initial sum s0 and the initial carry c0 is divided into corresponding parts from the first to the Nth (N is an integer greater than 1), where each part represents a portion of the sum from the least significant bit to the most significant bit. For example, s0 = [s0 N ,s0 N-1 , …, s01], and c0=[c0 N c0 N-1 The initial sum and parts of the number s0 are stored in the 15th extended register module R of the second arithmetic stage 320-b. 15 The sum register submodule R 15s In this process, the portions of the initial carry c0 are stored in the 15th extended register module R of the second arithmetic stage 320-b. 15 Carry register submodule R 15c middle.

[0149] The second submodule 332 of the first extended data processing module 330-a includes a carry logic module CLM. The carry logic module CLM can receive at least the first to (N-1)th parts of the initial sum s0 and at least the first to (N-1)th parts of the initial carry c0, thereby generating N-1 carry c1, ..., c2. N-1 Carry-over c1, ..., c N-1 The i-th carry in the sum corresponds to the i-th part s0 of the initial sum s0. i The i-th part c0 of the initial carry c0i The carry-in (i=1, ..., N-1) generated by the addition. These carry-ins are c1, ..., c2. N-1 Stored in the 15th extended register module R of the second arithmetic stage 320-b 15 Additional carry register submodule R 15ce middle.

[0150] The third submodule 333 of the second extended data operation module 330-b between the second operation level 320-b and the third operation level 320-c includes a summation logic module SLM. The summation logic module SLM can receive the first to Nth parts of the initial sum s0, the first to Nth parts of the initial carry c0, and the carry c1, ..., c2. N-1 This generates N sums s1, ..., s2. N The summation logic module (SLM) includes adders 1 through N. The first adder is configured to sum the first part s01 of the initial sum s0 with the first part c01 of the initial carry c0, thus producing the sum s1. The k-th adder is configured to sum the k-th part s0 of the initial sum s0. k The k-th part of the initial carry c0 k With carry c1, ..., c N-1 The (k-1)th carry c k-1 Summing, thus producing the sum s k (k=2, ..., N). N sums s1, ..., s2 N (The sum s of the initial sum s0 and the initial carry c0) is stored in the 14th extended register module R of the third arithmetic level 320-c. 14 middle.

[0151] Additionally, the 0th extended data W0 of the first operational level 320-a a The first extended data W1 of the fourth operation level 320-d is obtained by the fourth submodule 334 (which includes a σ0 arithmetic unit and an adder ADD0) of the third extended data operation module 330-d, which is immediately preceding the first operation level 320-a and is located between the first operation level 320-a and the fourth operation level 320-d. d And the second extended data W2 d The calculated value is W0. a = W1 d +σ0(W2 d ).

[0152] Therefore, the 14th extended register module R of the third arithmetic stage 320-c 14 The 14th extended data W14 stored in the middle c With the 0th extended data W0 of the first operation level 320-a a Extended Data W9, No. 9a and the 14th extended data W14 a The following relationship can be satisfied: W14 c =W0 a +W9 a +σ1(W14 a In addition, the 14th extended register module R of the third arithmetic stage 320-c 14 The 14th extended data W14 stored in the middle c With the first extended data W1 of the fourth operation level 320-d d Second extended data W2 d Extended Data W10 (10th Edition) d And the 15th extended data W15 d The following relationship can be satisfied: W14 c =W1 d +σ0(W2 d +W10 d +σ1(W15 d ), of which W15 d ={W15s d + W15c d + W15ce d W15s d W15c d W15ce d These are the 15th extended register module R of the fourth arithmetic level 320-d. 15 The sum register submodule R 15s Carry Register Submodule R 15c and the additional carry register submodule R 15ce The data stored in it.

[0153] Figure 18 and Figure 13 In comparison, although calculating "W1" d +σ0(W2 d +W10 d +σ1(W15 d This requires an extra round of processing time, but it doesn't have a significant negative impact on the assembly line structure. Additionally, Figure 18 This breaks the constraints of the 32-bit binary adder. On one hand, Figure 18 Will Figure 13 The separation of the carry logic circuit and the summation logic circuit of the adder ADD1 makes the application of RCA in a pipelined structure feasible. Specifically, originally Figure 13 If the 32-bit adder ADD1 is implemented as an RCA, it will have 32 stages, and the resulting latency may be unacceptable. Figure 13The 32-bit adder ADD1 is often implemented as a CLA, but CLAs have a large area, many glitches, and high power consumption. Figure 18 In this context, the summation logic module (SLM) can be implemented as multiple parallel RCAs, which offers reduced area, glitches, and power consumption while achieving speeds close to those of a CLA. On the other hand, Figure 18 Will Figure 13 The separation of carry and summation logic in the adder ADD1 reduces glitches from the carry logic to the summation logic. The inputs to the summation logic module SLM all come from registers, thus reducing or even eliminating glitches, which lowers the power consumption of circuit 300. Therefore, Figure 18 At an acceptable register area power consumption cost (e.g., in an arithmetic stage, compared to) Figure 13 30+N single-bit registers were added, of which R 15c It has 31 single-bit registers and R 15ce It has N-1 single-bit registers, which in turn result in a significant reduction in adder area / glitch power consumption.

[0154] like Figure 20 and Figure 21 As shown, the first submodule 331 of the first extended data operation module 330-a between the first operation level 320-a and the second operation level 320-b includes a σ0 operator, a σ1 operator, and a full adder FAA, and is configured to operate based on the 0th extended data W0 of the first operation level 320-a. a Extended Data W1 a and the 14th extended data W14 a Calculate the initial sum s0 and the initial carry c0. Each of the initial sum s0 and the initial carry c0 is divided into corresponding parts from the first to the Nth (N is an integer greater than 1), where each part represents a portion of the sum from the least significant bit to the most significant bit. For example, s0 = [s0 N , s0 N-1 , …, s01], and c0=[c0 N c0 N-1 The initial sum and parts of the number s0 are stored in the 15th extended register module R of the second arithmetic stage 320-b. 15 The sum register submodule R 15s In this process, the portions of the initial carry c0 are stored in the 15th extended register module R of the second arithmetic stage 320-b. 15 Carry register submodule R 15c middle.

[0155] The second submodule 332 of the first extended data processing module 330-a includes a carry logic module CLM. The carry logic module CLM can receive at least the first to (N-1)th parts of the initial sum s0 and at least the first to (N-1)th parts of the initial carry c0, thereby generating N-1 carry c1, ..., c2. N-1 Carry-over c1, ..., c N-1 The i-th carry in the sum corresponds to the i-th part s0 of the initial sum s0. i The i-th part c0 of the initial carry c0 i The carry-in (i=1, ..., N-1) generated by the addition. These carry-ins are c1, ..., c2. N-1 Stored in the 15th extended register module R of the second arithmetic stage 320-b 15 Additional carry register submodule R 15ce middle.

[0156] The third submodule 333 of the second extended data operation module 330-b between the second operation level 320-b and the third operation level 320-c includes a summation logic module SLM. The summation logic module SLM can receive the first to Nth parts of the initial sum s0, the first to Nth parts of the initial carry c0, and the carry c1, ..., c2. N-1 This generates N sums s1, ..., s2. N The summation logic module (SLM) includes adders 1 through N. The first adder is configured to sum the first part s01 of the initial sum s0 with the first part c01 of the initial carry c0, thus producing the sum s1. The k-th adder is configured to sum the k-th part s0 of the initial sum s0. k The k-th part of the initial carry c0 k With carry c1, ..., c N-1 The (k-1)th carry c k-1 Summing, thus producing the sum s k (k=2, ..., N). N sums s1, ..., s2 N (The sum s of the initial sum s0 and the initial carry c0) is stored in the 14th extended register module R of the third arithmetic level 320-c. 14 middle.

[0157] Additionally, the 0th extended data W0 of the first operational level 320-a a The fourth submodule 334 (which includes an adder ADD0) of the third extended data operation module 330-d, which is located between the fourth operation stage 320-d and the first operation stage 320-a, is based on the first extended data W1 of the fourth operation stage 320-d. d and the 10th extended data W10 d The calculated value is W0.a = W1 d +W10 d .

[0158] Therefore, the 14th extended register module R of the third arithmetic stage 320-c 14 The 14th extended data W14 stored in the middle c With the 0th extended data W0 of the first operation level 320-a a Extended Data W1 a and the 14th extended data W14 a The following relationship can be satisfied: W14 c =W0 a +σ0(W1 a ) +σ1(W14 a In addition, the 14th extended register module R of the third arithmetic stage 320-c 14 The 14th extended data W14 stored in the middle c With the first extended data W1 of the fourth operation level 320-d d Second extended data W2 d Extended Data W10 (10th Edition) d And the 15th extended data W15 d The following relationship can be satisfied: W14 c =W1 d +σ0(W2 d +W10 d +σ1(W15 d ), of which W15 d ={W15s d + W15c d + W15ce d W15s d W15c d W15ce d These are the 15th extended register module R of the fourth arithmetic level 320-d. 15 The sum register submodule R 15s Carry Register Submodule R 15c and the additional carry register submodule R 15ce The data stored in it.

[0159] Figure 20 and Figure 14 In comparison, although calculating "W1" d +σ0(W2 d +W10 d +σ1(W15 d This requires an extra round of processing time, but it doesn't have a significant negative impact on the assembly line structure. Additionally, Figure 20This breaks the constraints of the 32-bit binary adder. On one hand, Figure 20 Will Figure 14 The separation of the carry logic circuit and the summation logic circuit of the adder ADD1 makes the application of RCA in a pipelined structure feasible. Specifically, originally Figure 14 If the 32-bit adder ADD1 is implemented as an RCA, it will have 32 stages, and the resulting latency may be unacceptable. Figure 14 The 32-bit adder ADD1 is often implemented as a CLA, but CLAs have a large area, many glitches, and high power consumption. Figure 20 In this context, the summation logic module (SLM) can be implemented as multiple parallel RCAs, which offers reduced area, glitches, and power consumption while achieving speeds close to those of a CLA. On the other hand, Figure 20 Will Figure 14 The separation of carry and summation logic in the adder ADD1 reduces glitches from the carry logic to the summation logic. The inputs to the summation logic module SLM all come from registers, thus reducing or even eliminating glitches, which lowers the power consumption of circuit 300. Therefore, Figure 20 At an acceptable register area power consumption cost (e.g., in an arithmetic stage, compared to) Figure 14 30+N single-bit registers were added, of which R 15c It has 31 single-bit registers and R 15ce It has N-1 single-bit registers, which in turn result in a significant reduction in adder area / glitch power consumption.

[0160] In addition, it can be based on W0 t+1 =W1 t +σ1(W15 t W15 t+1 =W0 t +σ0(W1 t )+W9 t And W15 t+2 =W0 t+1 +σ0(W1 t+1 )+ W9 t+1 =W1 t +σ0(W2 t )+W10 t +σ1(W15 t (This can be extended to other embodiments. For example, in some embodiments, the first submodule 331 of the first extended data processing module 330-a can be based on the 0th extended data W0 of the first processing level 120-a.) a Extended Data W1 a And the 9th extended data W9 a Calculate the initial sum and initial carry, then proceed to a similar manner.Figure 18 , Figure 20 The initial sum and initial carry are then processed as the first and second numbers by an addition circuit according to various embodiments of the teachings of this disclosure, which will not be elaborated here.

[0161] This disclosure may also provide a computing chip including the circuitry described in any of the above embodiments. This disclosure may also provide a computing device including the computing chip described above.

[0162] The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “upper,” “lower,” “high,” “lower,” etc., used in the specification and claims, if present, are for descriptive purposes and not necessarily for describing constant relative positions. It should be understood that such terms are interchangeable where appropriate, so that embodiments of this disclosure described herein can operate, for example, in orientations different from those shown or otherwise described herein. For example, when the device in the drawings is reversed, a feature previously described as “above” other features may now be described as “below” other features. The device may also be oriented in other ways (rotated 90 degrees or in other orientations), in which case the relative spatial relationships will be interpreted accordingly.

[0163] In the specification and claims, when an element is described as being "on top of," "attached to," "connected to," "coupled to," or "in contact with" another element, the element may be directly located on top of, directly attached to, directly connected to, directly coupled to, or directly in contact with the other element, or one or more intermediate elements may be present. Conversely, when an element is described as being "directly" located on top of, directly attached to, directly connected to, directly coupled to, or directly in contact with another element, no intermediate elements are present. In the specification and claims, when a feature is arranged "adjacent" to another feature, it may mean that a feature has a portion overlapping with the adjacent feature or a portion located above or below the adjacent feature.

[0164] As used herein, the term "exemplary" means "serving as an example, instance, or illustration," and not as a "model" to be precisely copied. Any implementation described herein by example is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, this disclosure is not limited to any stated or implied theory given in the technical field, background art, summary of the invention, or detailed description. As used herein, the term "substantially" means to include any minor variations caused by design or manufacturing defects, device or component tolerances, environmental influences, and / or other factors. The term "substantially" also allows for differences from the perfect or ideal situation due to parasitic effects, noise, and other practical considerations that may exist in actual implementations.

[0165] Additionally, terms such as “first,” “second,” etc., may be used herein for reference only and are not intended to be limiting. For example, unless the context clearly indicates otherwise, the words “first,” “second,” and other such numerical terms relating to structures or elements do not imply order or sequence. It should also be understood that the term “including / comprises” as used herein indicates the presence of the indicated feature, whole, step, operation, unit, and / or component, but does not preclude the presence or addition of one or more other features, wholes, steps, operations, units, and / or components, and / or combinations thereof. In this disclosure, the term “provide” is used broadly to cover all ways of obtaining an object, and therefore “providing an object” includes, but is not limited to, “purchasing,” “preparing / manufacturing,” “arranging / setting,” “installing / assembling,” and / or “ordering” an object.

[0166] As used herein, the term “and / or” includes any and all combinations of one or more of the listed items in association. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise.

[0167] Those skilled in the art will recognize that the boundaries between the above operations are merely illustrative. Multiple operations may be combined into a single operation, a single operation may be distributed among additional operations, and operations may be performed with at least partial overlap in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be changed in various other embodiments. However, other modifications, variations, and substitutions are equally possible. Aspects and elements of all the embodiments disclosed above may be combined in any way and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this specification and the accompanying drawings should be considered illustrative rather than restrictive.

[0168] While specific embodiments of this disclosure have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. The various embodiments disclosed herein can be combined in any way without departing from the spirit and scope of this disclosure. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. An adder circuit for calculating the sum of a first number and a second number, the adder circuit having a first input representing the first number and a second input representing the second number and having an output representing the sum of the first number and the second number, each of the first and second inputs being correspondingly divided into portions 1 to N, where N is an integer greater than 1, the portions 1 to N representing portions of the input from least significant bit to most significant bit, the adder circuit comprising: The carry logic module is configured to receive the first to N-1 parts of the first input and the first to N-1 parts of the second input to calculate N-1 carry-offs, wherein the i-th carry-off in the N-1 carry-offs corresponds to the carry-off generated by adding the i-th part of the first input and the i-th part of the second input, i=1,...,N-1; The first register module is configured to store the first to Nth portions of the first input; The second register module is configured to store the first to Nth parts of the second input; The third register module is coupled to the carry logic module and is configured to store the N-1 carrys; The summation logic module is coupled to the first to third register modules and configured to sum the first to Nth portions of the first input, the first to Nth portions of the second input, and the N-1 carry-in bits. In this case, the sum output by the summation logic module represents a portion of the output bits from the least significant bit to the most significant bit.

2. The adder circuit according to claim 1, wherein, The carry logic module is configured to calculate the N-1 carries using carry-lookahead logic.

3. The adder circuit according to claim 1, wherein, The summation logic module is implemented as multiple parallel ripple carry adders.

4. The adder circuit according to claim 1, wherein, Each part of the first and second inputs has the same number of bits.

5. The adder circuit according to claim 1, wherein, The number of bits in the Nth part of each of the first and second inputs is greater than the number of bits in each of the remaining parts of the input.

6. The adder circuit according to claim 1, wherein, The first register module and the second register module each include units 1 to N, and the summation logic module includes adders 1 to N. In this configuration, the j-th unit of the first register module is configured to store the j-th portion of the first input, the j-th unit of the second register module is configured to store the j-th portion of the second input, and the j-th adder of the summation logic module is coupled to the j-th unit of the first register module and the j-th unit of the second register module, where j = 1, ..., N. Specifically, the first adder of the summation logic module is configured to sum the first part of the first input and the first part of the second input. The k-th adder of the summation logic module is also coupled to the third register module, and the k-th adder is configured to sum the k-th part of the first input, the k-th part of the second input, and the (k-1)-th carry of the N-1 carry, where k=2, ...,N.

7. The adder circuit according to claim 1, wherein, The carry logic module includes: The preprocessor is configured to perform XOR and AND operations on each bit of the first to N-1 portions of the first input and the corresponding bits of the second input in parallel, thereby generating corresponding transmission and generation signals; and The carry generator is configured to generate the N-1 carries using a transfer signal and a generation signal generated by a preprocessor.

8. The adder circuit according to claim 7, wherein, The carry generator includes a parallel prefix network.

9. An operational circuit, comprising: The summation module includes the addition circuit according to any one of claims 1 to 8; as well as A first arithmetic module coupled to the summing module to provide the first and second inputs of the adder circuit.

10. The operational circuit according to claim 9, wherein, The arithmetic circuit includes multiple arithmetic stages, each of which includes a corresponding register module. The multiple arithmetic stages include a first arithmetic stage and a second arithmetic stage immediately following the first arithmetic stage. The second arithmetic stage further includes the first register module, the second register module, and the third register module of the adder circuit. A first arithmetic module is disposed between the first and second arithmetic stages and coupled to a first corresponding register module of the first arithmetic stage. The first arithmetic module is configured to perform operations on data from the first corresponding register module, thereby generating the first and second inputs of the adder circuit. The carry logic module of the adder circuit is arranged between the first and second operational stages.

11. The operational circuit according to claim 10, wherein, The plurality of operational stages also includes a third operational stage immediately following the second operational stage, wherein a third corresponding register module of the third operational stage is coupled to the summing module to receive the output of the addition circuit, and The summation logic module of the adder circuit is arranged between the second and third operational stages.

12. The operational circuit according to claim 11, further comprising: The second arithmetic module is located between the second arithmetic stage and the third arithmetic stage and coupled to the second corresponding register module of the second arithmetic stage. The second arithmetic module is configured to perform operations on data from the second corresponding register module.

13. The operational circuit according to claim 12, wherein, The summation module is a first summation module, the addition circuit is a first addition circuit, and the arithmetic circuit further includes: The second summing module includes a second adding circuit, which is the adding circuit according to any one of claims 1 to 8. The third arithmetic stage also includes the first register module, the second register module, and the third register module of the second adder circuit. The second arithmetic module is coupled to the second summing module to provide the first and second inputs of the second adder circuit, and is configured to perform operations on data from the second corresponding register module to generate the first and second inputs of the second adder circuit. The carry logic module of the second adder circuit is arranged between the second and third operational stages.

14. A circuit for performing a hash algorithm, comprising: The input section is configured to receive data; as well as The arithmetic unit is configured to calculate hash values ​​based on received data and includes multiple arithmetic stages arranged in a pipelined architecture, wherein: The plurality of operation levels include a first operation level and a second operation level immediately following the first operation level. Each operation level in the first and second operation levels includes a 0th to a 15th extended register module, respectively configured to store 0th to 15th extended data of that operation level. The 15th extended register module includes a sum register submodule, a carry register submodule, and an additional carry register submodule. The circuit further includes a first extended data processing module disposed between the first processing stage and the second processing stage. The first extended data processing module includes a first submodule and a second submodule. The first submodule is configured to calculate an initial sum and an initial carry based on the 0th extended data of the first arithmetic level and at least two of the 1st, 9th, and 14th extended data of the first arithmetic level. Each of the initial sum and the initial carry is correspondingly divided into parts 1 to N, where N is an integer greater than 1. The parts 1 to N represent the bits of each part from least significant bit to most significant bit. The parts 1 to N of the initial sum are stored in the sum register submodule of the 15th extended register module of the second arithmetic level, and the parts 1 to N of the initial carry are stored in the carry register submodule of the 15th extended register module of the second arithmetic level. The second submodule is configured to calculate N-1 carry-in, wherein the i-th carry-in corresponds to the carry-in generated by adding the i-th part of the initial sum to the i-th part of the initial carry-in, i=1,...,N-1, and the N-1 carry-in is stored in the additional carry register submodule of the 15th extended register module of the second arithmetic level.

15. The circuit according to claim 14, wherein, The plurality of operation levels also include a third operation level immediately following the second operation level, the third operation level including a 14th extended register module configured to store the 14th extended data of the operation level, and The circuit further includes a second extended data processing module arranged between the second and third processing stages. This second extended data processing module includes a third sub-module, which comprises adders 1 through N. The first adder is configured to sum the first part of the initial sum and the first part of the initial carry. The k-th adder is configured to sum the k-th part of the initial sum, the k-th part of the initial carry, and the (k-1)-th carry from the N-1 carrys, where k = 2, ..., N. The N sums output by the first to Nth adders are stored in the 14th extended register module of the third arithmetic stage.

16. A computing chip comprising the circuitry according to any one of claims 1 to 15.

17. A computing device comprising the computing chip according to claim 16.

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