Method and device for quickly recovering communication after master-slave switching of double-CPU redundant PLC (Programmable Logic Controller)

Abstract

The invention relates to a method and a device for quickly recovering communication after master-slave switching of a double-CPU redundant PLC (programmable logic controller), which belong to the technical field of industrial automation control, and the method comprises the following steps: binding IP (internet protocol) and MAC (media access control) of a master CPU and a slave CPU through a role pairing table, executing master-slave switching operation according to CPU fault detection information and switching instruction information, and switching the master CPU and the slave CPU according to the CPU fault detection information and the switching instruction information. In the switching process, switching verification is carried out according to heartbeat response data of the master CPU and the slave CPU and slave CPU fault detection information, and master-slave configuration switching is carried out according to the role pairing table so as to complete switching of the master CPU and the slave CPU; in the switching process of the master CPU and the slave CPU, the ARP table does not need to be frequently updated, and the time consumption of communication recovery is effectively reduced.

Description

Technical Field

[0001] This invention belongs to the field of industrial automation control technology, specifically relating to a method and device for rapid communication recovery after master-slave switching of a dual-CPU redundant PLC. Background Technology

[0002] In the field of industrial control, dual-CPU redundant PLCs ensure system reliability through a master-slave architecture. The master and slave CPUs are connected to the network through independent network cards and share the same IP address. At any given time, only the master CPU is bound to this IP address, and the host computer and devices communicate with this shared IP address.

[0003] In the patent document with patent number "CN114942613B", the master CPU periodically synchronizes the ARP table to the slave CPU. During the switch, the original master CPU unloads the shared IP, and after the new master CPU is bound, it sends simulated ARP reply frames one by one according to the synchronized ARP table in order to restore the communication link. However, this method is prone to problems such as untimely or incomplete synchronization of the ARP table, resulting in a long waiting time for recovery after master-slave switch. Summary of the Invention

[0004] To address this issue, the present invention provides a method and apparatus for rapid communication recovery after master-slave switching of a dual-CPU redundant PLC, in order to solve the problem that existing master-slave CPU switching is prone to issues such as untimely or incomplete ARP table synchronization, resulting in excessively long recovery time after master-slave switching.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] In a first aspect, the present invention provides a method for rapid communication recovery after a master-slave switch in a dual-CPU redundant PLC, comprising:

[0007] Create and populate a role pairing table; the role pairing table includes the MAC address of the master CPU, the IP address of the master CPU, the MAC address of the slave CPU, and the IP address of the slave CPU;

[0008] If the trigger data meets the triggering conditions, a master-slave switchover operation is performed; the trigger data includes master CPU fault detection information and switchover instruction information.

[0009] During the master-slave switchover operation, the switchover verification is performed based on the communication data between the master CPU and the slave CPU; the communication data includes heartbeat response data and slave CPU fault detection information.

[0010] If the switching verification passes, the master-slave configuration is switched according to the role pairing table to complete the master-slave CPU switch.

[0011] Furthermore, the creation and population of the role pairing table includes:

[0012] When the PLC is powered on for the first time, the role pairing table is created in the EEPROM.

[0013] The CPU actively sends a pairing request to all devices within the same local area network; the pairing request is a broadcast link layer first Ethernet frame; the first Ethernet frame includes a broadcast MAC address, the CPU's MAC address, an Ethernet frame type, and first Ethernet data; the first Ethernet data includes the CPU's IP address, the CPU's MAC address, and a first integrity check code;

[0014] After receiving the pairing request from the slave CPU, the master CPU performs an integrity check based on the first integrity check code. If the integrity check passes, the master CPU sends a pairing response to the slave CPU. The pairing response is a link layer second Ethernet frame unicast to the slave CPU. The second Ethernet frame includes: the MAC address of the slave CPU, the MAC address of the master CPU, the Ethernet frame type, and the second Ethernet data. The second Ethernet data includes the MAC address of the master CPU, the IP address of the master CPU, the IP address of the slave CPU, the MAC address of the slave CPU, and the second integrity check code.

[0015] After receiving the pairing response from the CPU, the CPU performs an integrity check based on the second integrity check code. If the integrity check passes, the CPU's MAC address, IP address, IP address, and MAC address are written into the role pairing table.

[0016] Furthermore, the step of performing a master-slave switchover operation if the triggering data meets the triggering conditions includes:

[0017] If a fault identifier exists in the main CPU fault detection information, the trigger data will meet the trigger conditions to execute a master-slave switchover operation.

[0018] or,

[0019] If a master-slave switch instruction is received from the host computer, the master-slave switch operation will be executed if the trigger data meets the trigger conditions.

[0020] Furthermore, the switching verification based on the communication data between the master CPU and the slave CPU includes:

[0021] Master CPU verification: If the master CPU continuously receives heartbeat data from the slave CPU within a first preset time period, and there is no fault identifier in the fault detection information of the slave CPU, then the master CPU verification is successful, and the master CPU no longer sends heartbeat response data and no longer responds to requests.

[0022] CPU verification: If the slave CPU does not receive heartbeat response data from the master CPU within a second preset time period, the CPU verification is successful.

[0023] Pre-upgrade verification: The CPU broadcasts an ARP request frame. If the ARP request frame times out without a response, the pre-upgrade verification passes; if the ARP request frame receives a response, the pre-upgrade verification fails due to IP conflict.

[0024] Furthermore, if the switching verification passes, the master-slave configuration switch is performed according to the role pairing table, including:

[0025] If the master CPU verification, slave CPU verification, and pre-upgrade verification all pass, the switch verification passes, and the master-slave configuration switch is executed.

[0026] The master-slave configuration switchover process is as follows: The MAC address of the original master CPU is configured to match the MAC address of the slave CPU in the role pairing table, and the IP address of the original master CPU is configured to match the IP address of the slave CPU in the role pairing table, thus completing the role configuration switch from master to slave CPU; the MAC address of the original slave CPU is configured to match the MAC address of the master CPU in the role pairing table, and the IP address of the original slave CPU is configured to match the IP address of the master CPU in the role pairing table, thus completing the role configuration switch from slave to master CPU. The original master CPU and the original slave CPU are the master CPU and slave CPU before the master-slave configuration switchover.

[0027] Furthermore, the method also includes:

[0028] After the master-slave configuration switch is completed, the master CPU and the slave CPU each perform a first preset number of GAPR broadcasts to notify devices in the local area network to update their own ARP tables.

[0029] Furthermore, the method also includes:

[0030] After the CPU actively sends pairing requests to all devices in the same local area network, the number of response timeouts is recorded. If the number of response timeouts reaches a second preset number, the pairing failure information is reported to the host computer.

[0031] Secondly, the present invention provides a device for rapid communication recovery after a dual-CPU redundant PLC master-slave switchover, comprising:

[0032] The role binding module is used to create and populate a role pairing table; the role pairing table includes the MAC address of the master CPU, the IP address of the master CPU, the MAC address of the slave CPU, and the IP address of the slave CPU.

[0033] The triggering module is used to execute a master-slave switchover operation if the triggering data meets the triggering conditions; the triggering data includes master CPU fault detection information and switchover instruction information.

[0034] The switching verification module is used to perform switching verification based on the communication data between the master CPU and the slave CPU during the master-slave switching operation; the communication data includes heartbeat response data and slave CPU fault detection information.

[0035] The master-slave switching module is used to switch the master-slave configuration according to the role pairing table if the switching verification is successful, so as to complete the master-slave CPU switching.

[0036] Thirdly, the present invention provides an electronic device, comprising:

[0037] At least one processor; and

[0038] A memory communicatively connected to the at least one processor; wherein,

[0039] The memory stores instructions that can be executed by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform any of the aforementioned methods for rapid communication recovery after master-slave switching of a dual-CPU redundant PLC.

[0040] The present invention, by adopting the above technical solution, has at least the following beneficial effects:

[0041] A method and apparatus for rapid communication recovery after master-slave switching in a dual-CPU redundant PLC are provided. The method binds the IP and MAC addresses of the master and slave CPUs using a role pairing table. The master-slave switching operation is performed based on CPU fault detection information and switching command information. During the switching process, switching verification is performed based on heartbeat response data between the master and slave CPUs and fault detection information from the slave CPU. The master-slave configuration is switched according to the role pairing table to complete the master-slave CPU switch. During the master-slave CPU switch, frequent ARP table updates are not required, effectively reducing the time required for communication recovery.

[0042] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a flowchart illustrating a method for rapid communication recovery after master-slave switching of a dual-CPU redundant PLC, as shown in an exemplary embodiment of the present invention.

[0045] Figure 2 This is a schematic block diagram illustrating a dual-CPU redundant PLC system architecture in an exemplary embodiment of the present invention.

[0046] Figure 3 This is a flowchart illustrating the creation and population of a role pairing table as shown in an exemplary embodiment of the present invention;

[0047] Figure 4 This is a schematic diagram illustrating a switching verification according to an exemplary embodiment of the present invention;

[0048] Figure 5 This is a schematic block diagram of a dual-CPU redundant PLC communication fast recovery device after master-slave switching, as shown in an exemplary embodiment of the present invention.

[0049] Figure 6 This is a schematic diagram of an electronic device illustrated in an exemplary embodiment of the present invention.

[0050] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be described in detail below. Obviously, the described embodiments are merely some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other implementation methods obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0052] In the existing solution, the master CPU updates the slave CPU's ARP table by periodically multicasting ARP synchronization messages (approximately every 100ms). During a switchover, the original master CPU must wait for the ARP table synchronization to complete before unloading the IP address. The new master CPU relies on sending simulated ARP reply frames to each device (each switchover takes approximately 200ms to complete the update for all devices), resulting in an overall switchover time of hundreds of milliseconds. However, this solution has significant drawbacks: the opaque configuration means that only the "shared IP" and constantly changing MAC addresses are visible in the network, making it impossible to distinguish which MAC address corresponds to the current master CPU. Maintenance personnel cannot quickly locate the primary device through packet capture or monitoring, increasing the difficulty of troubleshooting. ARP dependency risk: Network packet loss or delay may cause simulated ARP reply frames to fail to reach the host computer or switch, resulting in communication interruptions lasting tens of seconds. Switch MAC table update delay: Traditional solutions rely on the switch passively learning the new master CPU's MAC address (the switch MAC table is a data table that maps device MAC addresses to switch physical ports). During this period, data packets may still be sent to the old master MAC address, causing temporary packet loss. IP Conflict Risk: If the original primary CPU fails to unload its primary IP address, the new primary CPU's binding can lead to IP conflicts. Traditional solutions lack effective detection mechanisms, potentially resulting in severe situations like dual-CPU operation. Scenario Limitations: This approach is only suitable for single-segment networks with few devices and no strict security policies. It is not suitable for pure link-layer communication networks (communication networks that identify devices via MAC addresses, not IP addresses), static ARP device scenarios (where IP and MAC addresses are fixed and cannot be dynamically updated), or complex cross-segment architectures. The core issues are incomplete ARP table synchronization and poor network device compatibility.

[0053] This invention provides a method and apparatus for rapid communication recovery after a master-slave switch in a dual-CPU redundant PLC. IP / MAC update efficiency is improved: it eliminates the need for passive learning via a switch, as the IP / MAC address is bound to the master / slave CPU roles and actively refreshed via GARP broadcast after the switch, resolving the problem of "tens of seconds of interruption due to lost simulated ARP reply frames" in existing solutions. It supports cross-network segment architectures, static ARP devices, and pure link-layer communication, whereas existing solutions are only applicable to a single network segment (e.g., CN114942613B). Maintenance efficiency is improved: by fixing the master MAC address, maintenance personnel can quickly locate the primary device by capturing packets, solving the problem of "difficult troubleshooting due to MAC address changes" in existing solutions. IP conflict risk is eliminated: the availability of the master IP is verified before the switch, avoiding dual-master CPU operation.

[0054] The methods and apparatus of the present invention will be described below through specific embodiments.

[0055] Please see Figure 1 , Figure 1This is a flowchart illustrating a method for rapid communication recovery after master-slave switching in a dual-CPU redundant PLC, as shown in an exemplary embodiment of the present invention. (See attached flowchart.) Figure 1 The method includes:

[0056] Step S11: Create and populate the character pairing table;

[0057] Step S12: If the trigger data meets the triggering conditions, then perform a master-slave switch operation;

[0058] Step S13: During the master-slave switchover operation, the switchover verification is performed based on the communication data between the master CPU and the slave CPU;

[0059] Step S14: If the switch verification passes, switch the master-slave configuration according to the role pairing table.

[0060] It should be noted that the technical solution provided in this embodiment is applicable to scenarios including but not limited to: communication recovery after master-slave switching of dual-CPU redundant PLC.

[0061] It is understood that the method provided in this embodiment binds the IP and MAC addresses of the master CPU and slave CPU through a role pairing table, performs master-slave switching operations based on CPU fault detection information and switching instruction information, verifies the switching based on the heartbeat response data between the master CPU and slave CPU and the fault detection information of the slave CPU, and performs master-slave configuration switching based on the role pairing table to complete the master-slave CPU switching; during the master-slave CPU switching process, there is no need for frequent updates to the ARP table, which effectively reduces the time spent on communication recovery.

[0062] In practical application, please refer to Figure 2 , Figure 2 This is a schematic block diagram illustrating a dual-CPU redundant PLC system architecture according to an exemplary embodiment of the present invention. See also... Figure 2 The peer device is connected to the switch network, and the switch is connected to the PLC network. The PLC has a master CPU and a slave CPU, which can be switched. When switched to master, the CPU performs the relevant I / O operations under the fieldbus.

[0063] In practice, step S11, "creating and filling the role pairing table," includes: creating a role pairing table in the EEPROM when the PLC is powered on for the first time; the CPU actively sends a pairing request to all devices within the same local area network; the pairing request is a broadcast link layer first Ethernet frame; the first Ethernet frame includes the broadcast MAC address, the CPU's MAC address, the Ethernet frame type, and the first Ethernet data; the first Ethernet data includes the CPU's IP address, MAC address, and first integrity check code; after receiving the pairing request from the CPU, the master CPU performs an integrity check based on the first integrity check code; if the integrity check passes, it sends a pairing request to the CPU. Send a pairing response; the pairing response is a unicast to the slave CPU via a link layer second Ethernet frame; the second Ethernet frame includes: the slave CPU's MAC address, the master CPU's MAC address, the Ethernet frame type, and the second Ethernet data; the second Ethernet data includes the master CPU's MAC address, the master CPU's IP address, the slave CPU's IP address, the slave CPU's MAC address, and the second integrity check code; after receiving the pairing response, the slave CPU performs integrity verification based on the second integrity check code; if the integrity verification passes, the master CPU's MAC address, master CPU's IP address, slave CPU's IP address, and slave CPU's MAC address are written into the role pairing table.

[0064] It should be noted that the MAC addresses and IP addresses of the master CPU and slave CPU are pre-stored and can be obtained by the master CPU and slave CPU. When the master CPU and slave CPU are paired, the master CPU and slave CPU will store the MAC address, IP address, MAC address and IP address of the master CPU in the role pairing table in the EEPROM in the order of master CPU MAC address, master CPU IP address, slave CPU MAC address and IP address of slave CPU. After power-on, each will directly obtain and configure the MAC address from the role pairing table according to its own master CPU or slave CPU role. The master CPU role will always use the master CPU MAC address and master CPU IP address in the role pairing table, and the slave CPU role will always use the slave CPU MAC address and slave CPU IP address in the role pairing table, thereby realizing the binding of IP / MAC address with master and slave CPU roles.

[0065] Specifically, the master-slave CPU roles are strongly bound to IP / MAC addresses. The master-slave CPU IP / MAC pairing table data structure is designed with an EEPROM / NVRAM storage structure, as follows:

[0066] typedef struct{

[0067] uint8_tmaster_mac[6]; / / Master MAC

[0068] uint32_tmaster_ip; / / Master IP

[0069] uint8_tslave_mac[6]; / / From MAC

[0070] uint32_tslave_ip; / / From IP

[0071] uint32_tcrc32; / / CRC32 checksum of the preceding field to ensure data integrity.

[0072] }role_pairing_t;

[0073] It should be noted that you should refer to [link / reference]. Figure 3 , Figure 3 This is a flowchart illustrating the creation and population of a role pairing table as shown in an exemplary embodiment of the present invention. See also: Figure 3 Upon initial power-on, 1) the role_pairing_t structure is initialized, and both the master and slave CPUs clear this structure; 2) the slave CPU requests pairing and sends a link layer Ethernet frame using raw sockets (PF_PACKET, SOCK_RAW). The Ethernet frame format is existing technology, and the format is: destination MAC address, source MAC address, Ethernet frame type, Ethernet data, and FCS checksum. Destination MAC address: FF:FF:FF:FF:FF:FF (broadcast MAC address, all devices on the same LAN, i.e., under the same switch, can receive this data frame).

[0074] Source MAC address: From the CPU MAC address;

[0075] Ethernet frame type: 0x88B0 (custom);

[0076] Ethernet data: [from CPU IP address (4B - indicating 4-byte length)][from CPU MAC address (6B)][device type 0x02 (1B)][CRC32 (4B)].

[0077] It is understood that the technical solution provided in this embodiment binds the IP and MAC of the master CPU and slave CPU through a role matching table, providing data support for subsequent switching.

[0078] In practice, step S12, "if the trigger data meets the trigger conditions, then execute the master-slave switch operation", includes: if there is a fault identifier in the master CPU fault detection information, then the trigger data meets the trigger conditions and execute the master-slave switch operation; or, if the switch instruction information received from the host computer is to execute the master-slave switch, then the trigger data meets the trigger conditions and execute the master-slave switch operation.

[0079] In practice, step S13, "performing a handover verification based on the communication data between the master CPU and the slave CPU," includes: Master CPU verification: If the master CPU continuously receives heartbeat data from the slave CPU within a first preset time period, and there is no fault indicator in the slave CPU's fault detection information, then the master CPU verification passes; Slave CPU verification: If the slave CPU does not receive heartbeat response data from the master CPU within a second preset time period, then the slave CPU verification passes; Pre-upgrade verification: The slave CPU broadcasts an ARP request frame. If the ARP request frame times out without a response, then the pre-upgrade verification passes; if the ARP request frame receives a response, then the pre-upgrade verification fails due to IP conflict.

[0080] It should be noted that the CPU fault detection will detect over-temperature, program errors, hardware failures, etc. If a relevant fault is detected, a corresponding fault identifier will be added to the CPU fault detection information; the first preset duration and the second preset duration can be set according to specific business requirements.

[0081] Specifically, please refer to Figure 4 , Figure 4 This is a schematic diagram illustrating the switching verification process in an exemplary embodiment of the present invention. See also: Figure 4 The master CPU verification logic is as follows: The master CPU must continuously receive heartbeats from the slave CPU for at least 15ms, and the status word must contain no fault indicator. This indicates that the slave CPU exists and is operating normally, and the master CPU can be downgraded to a slave CPU. If the slave CPU's status is abnormal, the switchover is abandoned, the master CPU continues to operate, and an alarm is reported, indicating that the slave CPU is operating abnormally. The slave CPU verification logic is as follows: If the slave CPU does not receive heartbeat responses from the master CPU three times consecutively (totaling 9ms), it indicates that the master CPU may have been downgraded to a slave CPU or shut down. The slave CPU needs to be upgraded to run as the master CPU and enters the pre-upgrade check phase.

[0082] It is understood that the technical solution provided in this embodiment verifies the switching process based on the heartbeat response data between the master CPU and the slave CPU and the fault detection information of the slave CPU, which can effectively improve the reliability of the switching.

[0083] In practice, step S14, "switching master-slave configurations based on the role pairing table," includes: if the master CPU verification, slave CPU verification, and pre-upgrade verification all pass, the switch verification passes, and the master-slave configuration switch is executed. The master-slave configuration switch process is as follows: the original master CPU's MAC address is configured to the slave CPU's MAC address in the role pairing table, and the original master CPU's IP address is configured to the slave CPU's IP address in the role pairing table, completing the role configuration switch from the original master CPU to the slave CPU; the original slave CPU's MAC address is configured to the master CPU's MAC address in the role pairing table, and the original slave CPU's IP address is configured to the master CPU's IP address in the role pairing table, completing the role configuration switch from the original slave CPU to the master CPU. The original master CPU and the original slave CPU are the master CPU and slave CPU before the master-slave configuration switch.

[0084] Specifically, after the master-slave configuration switch is completed, the master CPU and the slave CPU each broadcast GAPR a first preset number of times to notify devices in the local area network to update their own ARP tables; the first preset number of times can be set according to specific business needs.

[0085] It should be noted that the CPU first broadcasts a constructed ARP request frame (used to verify the availability of the master CPU's IP address) to query the master CPU's IP address. Its Ethernet frame format is as follows:

[0086] Destination MAC address: FF:FF:FF:FF:FF:FF (broadcast MAC address)

[0087] Source MAC address: 64:00:6a:01:02:04 (from CPU MAC address)

[0088] Ethernet frame type: 0x0806 (ARP data frame)

[0089] Ethernet frame data:

[0090] Hardware type: Ethernet(1),

[0091] Protocol type: IPv4 (0x0800)

[0092] Opcode: ARP request or response type; 1 for a request, 2 for a response.

[0093] Sender's MAC address: 64:00:6a:01:02:04 (from CPU MAC address)

[0094] Sender IP address: 192.168.1.101 (from CPU IP address)

[0095] Destination MAC address: 00:00:00:00:00:00

[0096] Destination IP address: 192.168.1.100 (main CPU IP address).

[0097] IP conflict detection judgment logic: Response (any device): Determines that the main CPU IP is occupied and cannot be upgraded to run as the main CPU. It continues to run as the slave CPU and reports an error indication---IP conflict; No response after timeout (20ms): Confirms availability, officially upgrades to run as the main CPU and performs GARP refresh.

[0098] It is understood that the technical solution provided in this embodiment can effectively avoid network connection errors and other problems caused by IP conflicts.

[0099] In practice, this also includes: after the CPU actively sends a pairing request to all devices in the same local area network, recording the number of response timeouts; if the number of response timeouts reaches a second preset number, then reporting the pairing failure information to the host computer.

[0100] It should be noted that the second preset number of times can be set according to specific business needs.

[0101] It is understood that the technical solution provided in this embodiment can provide an error reporting function, making maintenance more timely.

[0102] Please see Figure 5 , Figure 5 This is a schematic block diagram of a communication fast recovery device after master-slave switching of a dual-CPU redundant PLC, as illustrated in an exemplary embodiment of the present invention. See also: Figure 5 The dual-CPU redundant PLC master-slave switching communication fast recovery device 100 includes:

[0103] The role binding module 101 is used to create and populate the role pairing table; the role pairing table includes the MAC address of the master CPU, the IP address of the master CPU, the MAC address of the slave CPU, and the IP address of the slave CPU;

[0104] Trigger module 102 is used to execute master-slave switchover operation if the trigger data meets the trigger conditions; the trigger data includes master CPU fault detection information and switchover instruction information;

[0105] The switching verification module 103 is used to perform switching verification based on the communication data between the master CPU and the slave CPU during the master-slave switching operation; the communication data includes heartbeat response data and slave CPU fault detection information;

[0106] The master-slave switching module 104 is used to switch the master-slave configuration according to the role matching table if the switching verification is successful, so as to complete the switching of master and slave CPUs.

[0107] It should be noted that the device provided in this embodiment is applicable to scenarios including but not limited to: communication recovery after master-slave switching of dual-CPU redundant PLC.

[0108] It is understood that the device provided in this embodiment binds the IP and MAC addresses of the master CPU and slave CPU through a role pairing table, performs master-slave switching operations based on CPU fault detection information and switching instruction information, performs switching verification based on the heartbeat response data between the master CPU and slave CPU and the fault detection information of the slave CPU, and performs master-slave configuration switching based on the role pairing table to complete the master-slave CPU switching; during the master-slave CPU switching process, there is no need for frequent updates to the ARP table, which effectively reduces the time spent on communication recovery.

[0109] Please see Figure 6 , Figure 6 This is a schematic diagram of an electronic device illustrated in an exemplary embodiment of the present invention. See also: Figure 6 The electronic device 200 includes: at least one processor 202; and

[0110] Memory 201 is communicatively connected to at least one processor 202; wherein,

[0111] The memory 201 stores instructions that can be executed by at least one processor 202, which enables the at least one processor 202 to execute any of the above-described methods for rapid communication recovery after master-slave switching of a dual-CPU redundant PLC.

[0112] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0113] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0114] It should also be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for display, data used for analysis, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0115] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0116] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0117] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for rapid communication recovery after master-slave switching in a dual-CPU redundant PLC, characterized in that, The method includes: Create and populate a role pairing table; the role pairing table includes the MAC address of the master CPU, the IP address of the master CPU, the MAC address of the slave CPU, and the IP address of the slave CPU; If the trigger data meets the triggering conditions, a master-slave switchover operation is performed; the trigger data includes master CPU fault detection information and switchover instruction information. During the master-slave switchover operation, the switchover verification is performed based on the communication data between the master CPU and the slave CPU; the communication data includes heartbeat response data and slave CPU fault detection information. If the switching verification passes, the master-slave configuration is switched according to the role pairing table to complete the master-slave CPU switch.

2. The method according to claim 1, characterized in that, The creation and population of the role pairing table includes: When the PLC is powered on for the first time, the role pairing table is created in the EEPROM. The CPU actively sends a pairing request to all devices within the same local area network; the pairing request is a broadcast link layer first Ethernet frame; the first Ethernet frame includes a broadcast MAC address, the CPU's MAC address, an Ethernet frame type, and first Ethernet data; the first Ethernet data includes the CPU's IP address, the CPU's MAC address, and a first integrity check code; After receiving the pairing request from the slave CPU, the master CPU performs an integrity check based on the first integrity check code. If the integrity check passes, the master CPU sends a pairing response to the slave CPU. The pairing response is a link layer second Ethernet frame unicast to the slave CPU. The second Ethernet frame includes: the MAC address of the slave CPU, the MAC address of the master CPU, the Ethernet frame type, and the second Ethernet data. The second Ethernet data includes the MAC address of the master CPU, the IP address of the master CPU, the IP address of the slave CPU, the MAC address of the slave CPU, and the second integrity check code. After receiving the pairing response from the CPU, the CPU performs an integrity check based on the second integrity check code. If the integrity check passes, the CPU's MAC address, IP address, IP address, and MAC address are written into the role pairing table.

3. The method according to claim 2, characterized in that, The step of performing a master-slave switch operation if the triggering data meets the triggering conditions includes: If a fault identifier exists in the main CPU fault detection information, the trigger data will meet the trigger conditions to execute a master-slave switchover operation. or, If a master-slave switch instruction is received from the host computer, the master-slave switch operation will be executed if the trigger data meets the trigger conditions.

4. The method according to claim 2, characterized in that, The switching verification based on the communication data between the master CPU and the slave CPU includes: Master CPU verification: If the master CPU continuously receives heartbeat data from the slave CPU within a first preset time period, and there is no fault identifier in the fault detection information of the slave CPU, then the master CPU verification is successful, and the master CPU no longer sends heartbeat response data and no longer responds to requests. CPU verification: If the slave CPU does not receive heartbeat response data from the master CPU within a second preset time period, the CPU verification is successful. Pre-upgrade verification: The CPU broadcasts an ARP request frame. If the ARP request frame times out without a response, the pre-upgrade verification passes; if the ARP request frame receives a response, the pre-upgrade verification fails due to IP conflict.

5. The method according to claim 4, characterized in that, If the switching verification passes, the master-slave configuration is switched according to the role pairing table, including: If the master CPU verification, slave CPU verification, and pre-upgrade verification all pass, the switch verification passes, and the master-slave configuration switch is executed. The master-slave configuration switching process is as follows: the MAC address of the original master CPU is configured to the MAC address of the slave CPU in the role pairing table, and the IP address of the original master CPU is configured to the IP address of the slave CPU in the role pairing table, thus completing the role configuration switch from the original master CPU to the slave CPU; the MAC address of the original slave CPU is configured to the MAC address of the master CPU in the role pairing table, and the IP address of the original slave CPU is configured to the IP address of the master CPU in the role pairing table, thus completing the role configuration switch from the original slave CPU to the master CPU; the original master CPU and the original slave CPU are the master CPU and slave CPU before the master-slave configuration switch.

6. The method according to claim 5, characterized in that, The method further includes: After the master-slave configuration switch is completed, the master CPU and the slave CPU each perform a first preset number of GAPR broadcasts to notify devices in the local area network to update their own ARP tables.

7. The method according to claim 2, characterized in that, The method further includes: After the CPU actively sends pairing requests to all devices in the same local area network, the number of response timeouts is recorded. If the number of response timeouts reaches a second preset number, the pairing failure information is reported to the host computer.

8. A device for rapid communication recovery after master-slave switching of a dual-CPU redundant PLC, characterized in that, The device includes: The role binding module is used to create and populate a role pairing table; the role pairing table includes the MAC address of the master CPU, the IP address of the master CPU, the MAC address of the slave CPU, and the IP address of the slave CPU. The triggering module is used to execute a master-slave switchover operation if the triggering data meets the triggering conditions; the triggering data includes master CPU fault detection information and switchover instruction information. The switching verification module is used to perform switching verification based on the communication data between the master CPU and the slave CPU during the master-slave switching operation; the communication data includes heartbeat response data and slave CPU fault detection information. The master-slave switching module is used to switch the master-slave configuration according to the role pairing table if the switching verification is successful, so as to complete the master-slave CPU switching.

9. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-7.

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