Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device is provided. The semiconductor device includes: a substrate; a first gate insulating film on the substrate; a first gate electrode on the first gate insulating film; a first capping film on the first gate electrode; a first gate spacer in contact with the first gate insulating film, the first gate electrode, and the first capping film; an insulating gasket on the first capping film and the first gate spacer; an insulating layer on at least a portion of the first gate spacer and defining a main hole; a mask layer including a base portion on an upper surface of the insulating layer and a pillar portion extending into the main hole and contacting the substrate; and a plug disposed in the main hole and surrounded by the pillar portion of the mask layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0063494, filed on May 14, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Technology

[0004] Semiconductors contain nanoscale circuit patterns invisible to the naked eye. To create these tiny patterns, certain areas need to be etched while others are left intact. In semiconductor manufacturing, this process is called photolithography. Photolithography refers to the method of etching a design pattern onto a slab of stone and then printing it. Because the design pattern is printed, the same shape can be repeatedly replicated. In semiconductor manufacturing, these identical shapes need to be printed without any errors, even errors of tens of nanometers. The word "light" indicates that photolithography uses light to achieve this. The design pattern is etched onto a plate called a mask, and then light passes through the mask, causing only the areas through which the light passes to be focused onto the wafer by an optical system of lenses, thus printing the tiny pattern onto the wafer. The photoresist coating on the wafer reacts chemically only in the areas exposed to light, resulting in different solubility in the exposed and unexposed areas. Subsequently, the developing process allows for the selective etching of the desired patterned areas in the etching process or the selective implantation of the implant in the implantation process.

[0005] Semiconductor devices are gaining increasing importance as key components in the electronics industry due to their characteristics such as miniaturization, multifunctionality, and / or lower manufacturing costs. However, with the continuous development of the electronics industry, the trend towards higher integration levels in semiconductor devices is intensifying. To achieve higher integration levels, the linewidth of patterns in semiconductor devices is gradually decreasing. However, recently, the miniaturization of these patterns has required new exposure technologies and / or high-cost exposure technologies, making it increasingly challenging to achieve higher integration levels in semiconductor devices. Therefore, extensive research is currently underway on new integration technologies. For example, in dynamic random access memory (DRAM) devices, structures that embed word lines within the semiconductor substrate are being explored. Summary of the Invention

[0006] According to one aspect of the embodiments, a semiconductor device includes: a substrate; a first gate insulating film on the substrate; a first gate electrode on the first gate insulating film; a first capping film on the first gate electrode; a first gate spacer in contact with the first gate insulating film, the first gate electrode, and the first capping film; an insulating liner on the first capping film and the first gate spacer; an insulating layer on at least a portion of the first gate spacer and defining a main aperture; a mask layer including a base on an upper surface of the insulating layer and a pillar extending into the main aperture and contacting the substrate; and a plug disposed in the main aperture and surrounded by the pillar of the mask layer.

[0007] According to one aspect of the embodiments, a method of manufacturing a semiconductor device includes: providing a structure including an insulating layer on a substrate; forming a main via in the insulating layer; forming a mask layer in the main via; forming a plug via in the mask layer; and forming a plug in the plug via. Attached Figure Description

[0008] The above and other aspects and features will become more apparent from the following description of embodiments, with reference to the accompanying drawings.

[0009] Figure 1 This is a schematic plan view illustrating a portion of the structure of the cell array region of a semiconductor device according to an embodiment.

[0010] Figure 2A According to the embodiments along Figure 1 A cross-sectional view of a semiconductor device taken by line A-A'.

[0011] Figure 2B According to the embodiments along Figure 1 A cross-sectional view of a semiconductor device taken by line B-B'.

[0012] Figure 2C According to the embodiments along Figure 1 A cross-sectional view of a semiconductor device taken by line C-C'.

[0013] Figure 2D According to the embodiments along Figure 1 A cross-sectional view of a semiconductor device taken by line D-D'.

[0014] Figure 3 This is a cross-sectional view of a semiconductor device according to an embodiment.

[0015] Figure 4 This is a cross-sectional view of a semiconductor device according to an embodiment, and shows the main via formed in the insulating layer.

[0016] Figure 5 This is a cross-sectional view of a semiconductor device according to an embodiment, and shows a mask layer formed in the main aperture.

[0017] Figure 6 This is a cross-sectional view of a semiconductor device according to an embodiment, and shows the plug holes formed in the mask layer.

[0018] Figure 7 The diagram schematically illustrates a plan view of the plug and mask layer according to an embodiment.

[0019] Figure 8 This is an enlarged cross-sectional view of a portion of a semiconductor device according to an embodiment.

[0020] Figure 9 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0021] Figure 10 This is a cross-sectional view of a semiconductor device according to an embodiment.

[0022] Figure 11 The diagram schematically illustrates a plan view of the plug and mask layer according to an embodiment. Detailed Implementation

[0023] In the following description, embodiments will be described in detail with reference to the accompanying drawings. Each embodiment provided in the following description does not exclude association with one or more features of another example or embodiment also provided herein or not provided herein but consistent with this disclosure. It will be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it may be directly on, directly connected to, or coupled to that other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intermediate elements or layers. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of…” modify the entire list of elements when preceding the list of elements, rather than modifying individual elements in the list. For example, the expression “at least one of a, b, and c” should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. It should also be understood that even if a step or operation in the manufacture of an apparatus or structure is described earlier than another step or operation, that step or operation may be performed later than the other step or operation, unless the other step or operation is described as being performed after that step or operation.

[0024] The accompanying drawings relate to dynamic random access memory (DRAM), but this disclosure is not limited thereto.

[0025] Figure 1This is a schematic plan view illustrating a portion of the structure of the cell array region of a semiconductor device according to an embodiment. Figure 2A According to the embodiments along Figure 1 A cross-sectional view of a semiconductor device taken by line A-A'. Figure 2B According to the embodiments along Figure 1 A cross-sectional view of a semiconductor device taken by line B-B'. Figure 2C According to the embodiments along Figure 1 A cross-sectional view of a semiconductor device taken by line C-C'. Figure 2D According to the embodiments along Figure 1 A cross-sectional view of a semiconductor device taken by line D-D'.

[0026] Reference Figures 1 to 2D The semiconductor device 1 may include a cell array region CA and a core region CORE. The core region CORE may be disposed around the cell array region CA.

[0027] The cell array region CA can include multiple active regions AC. The active regions AC can be formed on a substrate (e.g., ...). Figure 2A The element separation layer in the substrate 10) (e.g., Figure 2A The component separation layer 14A is defined. The active region AC can be configured as a strip extending diagonally or obliquely.

[0028] Multiple word lines (WL) can intersect with the active region (AC) to form multiple gate electrodes. The multiple word lines (WL) can be parallel to each other and can extend in a first direction (e.g., the x-axis direction). The multiple word lines (WL) can be spaced evenly. The widths of the multiple word lines (WL) can be the same or different. The spacing between the multiple word lines (WL) can be the same or different.

[0029] Each active region AC intersects with two word lines WL and can be divided into three regions. The middle region among the three regions can be called the bit line connection region. The regions located at both ends of the three regions can be called the memory element connection regions.

[0030] Multiple bit lines BL can intersect with word lines WL. For example, multiple bit lines BL can be orthogonal to word lines WL. Each bit line BL can extend in a second direction (e.g., the y-axis direction). Each bit line BL can lie on word line WL. Multiple bit lines BL can be parallel to each other at uniform intervals. Since the active region AC extends in a tilted direction, the angle formed between word line WL and active region AC can be less than 90 degrees.

[0031] Semiconductor device 1 may include various contact structures formed on the active region AC. For example, contact structures include direct contacts DC, buried contacts BC, and bonding pads LP.

[0032] A direct contact (DC) can be a contact structure that electrically connects the active region (AC) to the bit line (BL). A buried contact (BC) can be a contact structure that connects the active region (AC) to the lower electrode of the capacitor. In the case of a buried contact (BC), the contact area between the buried contact (BC) and the active region (AC) may be small due to the layout structure. To increase the contact area, a conductive bonding pad (LP) can be introduced between the active region (AC) and the buried contact (BC). The bonding pad (LP) can be located between the buried contact (BC) and the lower electrode of the capacitor to expand the contact area between the lower electrode of the capacitor and the buried contact (BC).

[0033] Direct contacts DC can be connected to the bit line connection area of ​​the active region AC. Buried contacts BC can be connected to the memory element connection area. Bonding pads LP can be adjacent to the buried contacts BC of the active region AC. Bonding pads LP can partially or fully overlap with the buried contacts BC of the active region AC. Buried contacts BC can be formed to overlap with the active region AC and the element separation layer 14A located between adjacent word lines WL and adjacent bit lines BL. Multiple buried contacts BC can be spaced apart from each other in a first direction (x-direction) and a second direction (y-direction).

[0034] The word line WL can be embedded in the substrate 10. The word line WL can be configured to cross the active region AC between direct contacts DC or between buried contacts BC.

[0035] Direct contacts (DCs) can be arranged symmetrically, thus along straight lines extending in a first direction (x-direction) and a second direction (y-direction). Buried contacts (BCs) can be arranged symmetrically, thus along straight lines extending in both the first direction (x-direction) and the second direction (y-direction). Bonding pads (LPs) can be arranged in a zigzag pattern in the second direction (y-direction) of the bit line extension. Bonding pads (LPs) can be configured to overlap with the same side of each bit line (BL) in the first direction (x-direction) of the word line (WL). For example, each bonding pad (LP) in the first column can overlap with the left side of the corresponding bit line (BL). Each bonding pad (LP) in the second column can overlap with the right side of the corresponding bit line (BL).

[0036] Semiconductor device 1 may include a substrate 10. Substrate 10 may include a cell array region CA and a core region CORE, defined by a cell region separation layer 14C. Cell array region CA may include an active region 12A. Core region CORE may include an active region 12B. Active region 12A may be defined by device separation layer 14A. Active region 12B may be defined by device separation layer 14B. Since device separation layers 14A and 14B define active regions 12A and 12B, device separation layers 14A and 14B may be disposed around active regions 12A and 12B.

[0037] The substrate 10 may be a silicon substrate or silicon-on-insulator (SOI). The substrate 10 may include silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but the embodiments are not limited thereto.

[0038] The component separation layers 14A, 14B and the cell region separation layer 14C may have a shallow trench isolation (STI) structure, which has excellent component separation characteristics.

[0039] In the cell array region CA, multiple active regions 12A can have relatively long island shapes, each active region having a short axis and a long axis, similar to... Figure 1 The active region AC is shown.

[0040] The component separation layers 14A, 14B and the cell region separation layer 14C may comprise silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof, but the embodiments are not limited thereto. Figures 2A to 2D In the diagram, the component separation layers 14A, 14B and the unit region separation layer 14C are shown as being formed as a single layer, but this is only for ease of description and the embodiments are not limited thereto. Each of the component separation layers 14A, 14B and the unit region separation layer 14C may be formed as a single insulating layer or multiple insulating layers, depending on the width of each of the component separation layers 14A, 14B and the unit region separation layer 14C.

[0041] exist Figures 2A to 2D In the illustration, the upper surface of each of the element separation layers 14A, 14B and the unit region separation layer 14C is shown as being on the same plane as the upper surface of the substrate 10, but this is only for ease of description and the embodiments are not limited thereto.

[0042] Semiconductor device 1 may include word lines with buried structures. The cell gate structure may include a cell gate insulating layer 22, a cell gate electrode 24, and a cell gate cap 26. The cell gate structure may be formed in a substrate 10 and a device separation layer 14A. The cell gate structure (e.g., cell gate insulating layer 22, cell gate electrode 24, and cell gate cap 26) may be formed to traverse the device separation layer 14A and the active region 12A defined by the device separation layer 14A. Here, the cell gate electrode 24 may correspond to the word line WL.

[0043] Reference Figure 2B The cell gate insulating layer 22 may be formed along the sidewalls and bottom surface of the cell gate trench T1 and along at least a portion of the contour of the cell gate trench T1. The cell gate insulating layer 22 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material with a dielectric constant higher than that of silicon oxide. The high-k dielectric material may include, for example, at least one of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof.

[0044] The unit gate electrode 24 can be formed on the unit gate insulating layer 22. The unit gate electrode 24 can fill a portion of the unit gate trench T1.

[0045] The unit gate electrode 24 may include at least one of, for example, a metal, a metal alloy, a conductive metal nitride, a conductive metal carbonitride, a conductive metal carbide, a metal silicide, a doped semiconductor material, a conductive metal oxynitride, and a conductive metal oxide. The unit gate electrode 24 may include at least one of, for example, TiN, TaC, TaN, TiSiN, TaSiN, TaTiN, TiAlN, TaAlN, WN, Ru, TiAl, TiAlC-N, TiAlC, TiC, TaCN, W, Al, Cu, Co, Ti, Ta, Ni, Pt, Ni-Pt, Nb, NbN, NbC, Mo, MoN, MoC, WC, Rh, Pd, Ir, Ag, Au, Zn, V, RuTiN, TiSi, TaSi, NiSi, CoSi, IrOx, RuOx, and combinations thereof.

[0046] The cell gate cap 26 may be disposed on the cell gate electrode 24 or the cell gate cap conductive layer. The cell gate cap 26 may fill the remaining space of the cell gate trench T1 after the cell gate electrode 24 is formed. The cell gate insulating layer 22 is shown as being formed along the sidewall of the cell gate cap 26, but the embodiment is not limited thereto. The cell gate cap 26 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), and combinations thereof.

[0047] A dotted region containing implanted impurities can be formed on at least one side of the cell gate structure (e.g., cell gate insulating layer 22, cell gate electrode 24, and cell gate cap 26). The dotted region can be the source / drain region of a transistor.

[0048] In the cell array region CA, cell conductive lines CL can be provided, and a cell line capping layer CLC can be provided above the cell conductive lines CL. The cell conductive lines CL and the cell line capping layer CLC together can be referred to as a "cell line structure". The cell conductive lines CL can be formed on the element separation layer 14A and the substrate 10 on which the cell gate structure (e.g., cell gate insulating layer 22, cell gate electrode 24, and cell gate capping 26) is formed. The cell conductive lines CL can intersect with the element separation layer 14A and the active region AC. The cell conductive lines CL can be formed to intersect with the cell gate structure (e.g., cell gate insulating layer 22, cell gate electrode 24, and cell gate capping 26). Here, the cell conductive lines CL can correspond to bit lines BL.

[0049] The unit conductive line CL may include multiple layers. The unit conductive line CL may include, for example, a first conductive layer 41A, a second conductive layer 42A, and a third conductive layer 43A. The first conductive layer 41A, the second conductive layer 42A, and the third conductive layer 43A may be sequentially stacked on the substrate 10 and the component separation layer 14A. The unit conductive line CL is not limited to a three-layer structure.

[0050] Each of the first conductive layer 41A, the second conductive layer 42A, and the third conductive layer 43A may include at least one of, for example, a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, a metal, and a metal alloy. For example, the first conductive layer 41A may include a doped semiconductor material (e.g., doped polysilicon, etc.), the second conductive layer 42A may include at least one of a conductive silicide compound and a conductive metal compound, and the third conductive layer 43A may include at least one of a metal and a metal alloy. However, the embodiments are not limited thereto.

[0051] The direct contact DC can electrically connect the unit conductive line CL to the substrate 10. The direct contact DC can be located at the point where the unit conductive line CL intersects with the middle portion of the elongated island-shaped active region AC. The direct contact DC can be formed on the bit line connection region of the active region AC.

[0052] Reference Figure 2A At the point where the unit conductive line CL intersects with the active region 12A of the substrate 10, the lower surface of the unit conductive line CL can contact the active region 12A. The lower surface of the unit conductive line CL extending to the active region 12A of the substrate 10 can serve as a direct contact DC. In some embodiments, the first conductive layer 41A of the unit conductive line CL that contacts the active region 12A can serve as a direct contact DC.

[0053] The unit line capping layer CLC can be disposed on the unit conductive line CL. The unit line capping layer CLC can extend along the upper surface of the unit conductive line CL in the second direction (y direction).

[0054] The cell line capping layer (CLC) may include at least one of, for example, silicon nitride, silicon oxynitride, silicon carbonitride, and silicon carbonitride.

[0055] As shown in the figure, the cell line capping layer (CLC) can have a three-layer structure. For example, the cell line capping layer (CLC) may include a cell line cap 44A, a cell line insulation layer 45A, and a first mask layer 47A.

[0056] The unit line cap 44A, the unit line insulation layer 45A, and the first mask layer 47A may include at least one of silicon nitride, silicon oxynitride, silicon carbonitride, and silicon carbonitride.

[0057] exist Figures 2A to 2D In the illustration, the cell line capping layer (CLC) is shown as having a three-layer structure, but the embodiment is not limited to this. For example, the cell line capping layer (CLC) may have a single layer, a double layer, or a structure with four or more layers.

[0058] Cell insulating films (e.g., first insulating film 31 and second insulating film 32) can be formed on the substrate 10 and the component separation layer 14A. More specifically, cell insulating films (e.g., 31 and 32) can be formed on regions of the substrate 10 offset from each of the direct contact DC, the buried contact BC, the component separation layer 14A, and the cell region separation layer 14C. Cell insulating films can be formed between the substrate 10 and the cell conductive line CL, and between the component separation layer 14A and the cell conductive line CL.

[0059] The unit insulating film can be a single film, or it can be multiple films including a first insulating film 31 and a second insulating film 32, as shown in the figure. For example, the first insulating film 31 may include a silicon oxide film, and the second insulating film 32 may include a silicon nitride film, but the embodiments are not limited thereto. For example, the unit insulating film can be a three-layer film including a silicon oxide film, a silicon nitride film, and a silicon oxide film, but the embodiments are not limited thereto.

[0060] Unit line spacers (e.g., first spacer 51, second spacer 52, third spacer 53, fourth spacer 54, and reinforcing spacer 90) may be disposed on the sidewalls of the unit line structure. In the portion of the unit conductive line CL that includes the direct contact DC, the unit line spacers (e.g., first spacer 51, second spacer 52, third spacer 53, fourth spacer 54, and reinforcing spacer 90) may be formed on the substrate 10 and the element separation layer 14A.

[0061] In the remaining portion of the unit conductive line CL where no direct contact DC is formed, unit line spacers may be provided on the unit insulating film (e.g., 31 and 32).

[0062] The cell line spacers may include multiple spacers of two or more types. In an embodiment, the cell line spacers may include multiple spacers. The multiple spacers may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbonitride (SiOCN), air, and combinations thereof. However, the embodiments are not limited thereto.

[0063] Reference Figure 2A The unit line spacers may include a first spacer 51, a second spacer 52, a third spacer 53, a fourth spacer 54, and a reinforcing spacer 90.

[0064] The first spacer 51 can cover the two side walls of the unit line structure, the inner wall of the direct contact hole (DCH), and the upper surface of the second insulating film 32.

[0065] The second spacer 52 can fill the DCH that is not filled by the first spacer 51.

[0066] The reinforcing spacer 90 may be located above the second spacer 52 and cover and reinforce the sidewalls of the first spacer 51 formed on both sides of the unit line structure.

[0067] According to this embodiment, the third spacer 53 can cover the sidewall of the reinforcing spacer 90 formed on the sidewall of the unit line structure, and includes air.

[0068] The fourth spacer 54 can cover the side surface of the third spacer 53 formed on both sides of the unit line structure and the side surface of the buried contact BC.

[0069] The first spacer 51, the second spacer 52, the fourth spacer 54, and the reinforcing spacer 90 may include silicon nitride, but the embodiments are not limited thereto.

[0070] Reference Figure 2B A partition wall 48A may be provided on the substrate 10 and the element separation layer 14A. The partition wall 48A may be formed to overlap with the cell gate structure (e.g., cell gate insulating layer 22, cell gate electrode 24, and cell gate cap 26) formed in the substrate 10 and the element separation layer 14A. The partition wall 48A may be disposed between cell line structures extending along a second direction (y direction). The partition wall 48A may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, but the embodiments are not limited thereto.

[0071] At least a portion of the buried contact BC may be embedded in the substrate. The lower surface of the buried contact BC may be lower than the upper surface of the substrate 10. For example... Figure 2A As shown, the upper surface of the buried contact BC may be higher than the upper surface of the substrate 10, but the embodiments are not limited to this.

[0072] The buried contact BC can be disposed between adjacent cell conductive lines CL along a first direction (x-direction). The buried contact BC can also be disposed between adjacent partition walls 48A along a second direction (y-direction). The buried contact BC can overlap with the substrate 10 and the element separation layer 14A between adjacent cell conductive lines CL. The buried contact BC can be connected to the memory element connection area of ​​the active region AC.

[0073] The buried contact BC may include, for example, at least one of a doped semiconductor material, a conductive silicide compound, a conductive metal nitride, and a metal. The buried contact BC may include, for example, doped polycrystalline silicon as a doped semiconductor material. The buried contact BC may include polycrystalline silicon doped with, for example, phosphorus, arsenic, boron, or combinations thereof.

[0074] Cell spacers 58 can be provided to cover the sidewalls of the cell line spacers on both sides of the cell line structure and the sidewalls of the partition wall 48A that contacts the bonding pad LP. (Refer to...) Figure 2A In some embodiments, when a portion of the cell line spacer is etched during the formation of the buried contact hole (BCH), the cell line spacer 58 can be formed to cover the upper portion of the cell line spacer located below the cell line capping layer CLC.

[0075] As described below, the cell spacer 58 formed in the cell array region CA can be formed before the plug via CPH is formed. The plug spacer 59 and the cell spacer 58 can be formed at different times. Therefore, the cell spacer 58 can be formed thinner, and the plug spacer 59 can be formed thicker to ensure sufficient spacing from the core gate structure. The thickness can be the width along the direction horizontal to the substrate 10.

[0076] The bonding pad LP can be formed on the buried contact BC. The bonding pad LP can be electrically connected to the buried contact BC. The bonding pad LP can be connected to the memory element connection area of ​​the active area AC.

[0077] The bonding pad LP can overlap with a portion of the upper surface of the unit line structure.

[0078] Reference Figure 2A The bonding pad LP may include a first conductive barrier layer 64A and a seventh conductive layer 66A. The first conductive barrier layer 64A may have, for example, a Ti, TiN, or Ti / TiN stacked structure. The seventh conductive layer 66A may include at least one of, for example, a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, a conductive metal carbide, a metal, and a metal alloy.

[0079] A pad separation insulating layer 70 can be formed on the bonding pads LP and the cell line structure. For example, the pad separation insulating layer 70 can be disposed on the cell line capping layer CLC. The pad separation insulating layer 70 can define bonding pads LP forming multiple isolation regions. The pad separation insulating layer 70 may not cover the upper surface of the bonding pads LP. The pad separation insulating layer 70 can separate adjacent bonding pads LP. For example, based on the upper surface of the substrate 10, the height of the upper surface of the bonding pads LP can be the same as the height of the upper surface of the pad separation insulating layer 70.

[0080] The pad separation insulating layer 70 may include an insulating material and electrically separates the plurality of bonding pads LP from each other. For example, the pad separation insulating layer 70 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and silicon carbonitride.

[0081] Reference Figure 2A The component separation layer 14B may be formed in the substrate 10 of the core region CORE. The component separation layer 14B may define the active region 12B in the core region CORE. The upper surface of the component separation layer 14B is shown as being in the same plane as the upper surface of the substrate 10, but the embodiment is not limited thereto.

[0082] The core gate structure can be disposed on the substrate 10 of the core region CORE. The core gate structure can be disposed on the active region 12B defined by the element separation layer 14B.

[0083] The core gate structure may include a gate insulating film 33B, gate electrodes (e.g., a fourth conductive layer 41B, a fifth conductive layer 42B, and a sixth conductive layer 43B), and a capping film 44B, which are sequentially stacked on the substrate 10. The core gate structure may include gate spacers 56 disposed on the sidewalls of the gate electrodes (e.g., 41B, 42B, and 43B) and the sidewalls of the capping film 44B.

[0084] The gate electrode may include a fourth conductive layer 41B, a fifth conductive layer 42B, and a sixth conductive layer 43B, which are sequentially stacked on the gate insulating film 33B. For example, no additional conductive layer may be provided between the gate electrode and the gate insulating film 33B. In another example, for instance, an additional conductive layer, such as a work function conductive layer, may be provided between the gate electrode and the gate insulating film 33B.

[0085] Although two core gate structures are shown disposed between adjacent element separation layers 14B, this is only for ease of description and the embodiments are not limited thereto.

[0086] An insulating pad 45 can be disposed on the substrate 10. The insulating pad 45 can be formed along the contour of the core gate structure. The insulating pad 45 can also be formed on the etched sidewalls and top surface of the first insulating film 31 and the second insulating film 32, the first conductive layer to the third conductive layer, and the capping layer after etching the cell conductive lines on the cell region separation layer 14C. In this case, the gate spacer 56 formed during the formation of the gate spacer 56 can be located between the insulating pad 45 and the etched sidewalls of the first insulating film 31 and the second insulating film 32, the first conductive layer to the third conductive layer, and the capping layer.

[0087] The insulating pad 45 may include at least one of silicon nitride, silicon oxynitride, silicon carbonitride, and silicon carbonitride.

[0088] An insulating layer 46 may be formed between multiple core gate structures. According to some embodiments, the insulating layer 46 may be disposed on the insulating pad 45 when the insulating pad 45 is formed. The insulating layer 46 may also be formed on the cell region separation layer 14C.

[0089] The insulating layer 46 can be formed of an insulating material with excellent gap-filling properties. The insulating layer 46 may include oxides. The insulating layer 46 can be formed of, for example, borosilicate glass (BPSG) film, high-density plasma (HDP) oxide film, O3-TEOS film, undoped silicate glass (USG), or Tonsilzane (TOSZ) material. The insulating layer 46 may include silicon oxide formed from TOSZ material.

[0090] The upper surface of the insulating layer 46 may lie in the same plane as the insulating pad 45 along the upper surface of the core gate structure, but the embodiments are not limited thereto. According to some embodiments, when the insulating pad 45 is not formed, the upper surface of the insulating layer 46 may lie in the same plane as the upper surface of the core gate structure.

[0091] A mask layer 47 can be disposed on the core gate structure and the insulating layer 46. The mask layer 47 may include a base 471 disposed on the upper side of the insulating layer 46 and a pillar 472 inserted into a main hole disposed in the insulating layer 46 and in contact with the substrate. A portion of the pillar 472 may be configured to be inserted into the substrate 10. The pillar 472 may surround the plug 60. The pillar 472 of the mask layer 47 may be disposed between the plug 60 and the gate spacer 56 to prevent the plug 60 and the gate spacer 56 from contacting each other. The mask layer 47 may protect the insulating layer 46 from the influence of the plug 60. The mask layer 47 may cover the side surface and the top surface of the gate spacer 56. The mask layer 47 may overlap with the gate spacer 56 in the z-axis direction. Simultaneously, the mask layer 47 may overlap with the gate spacer 56 in the x-axis direction.

[0092] According to some embodiments, when the insulating pad 45 is formed, the mask layer 47 may cover the insulating layer 46 and the insulating pad 45 extending along the upper surface of the core gate structure.

[0093] With the upper surface of the substrate 10 as a reference, the height of the upper surface of the mask layer 47 can be the same as the height of the upper surface of the cell line capping layer CLC.

[0094] The mask layer 47 may include a material different from that of the insulating layer 46. For example, when the insulating layer 46 includes silicon oxide, the mask layer 47 may include at least one of silicon nitride, silicon oxynitride, silicon carbonitride, and silicon carbonitride, but the embodiments are not limited thereto.

[0095] The plug 60 can be disposed on both sides of the core gate structure. The plug 60 can pass through the mask layer 47 and the insulating layer 46 and extend to the substrate 10 of the core region CORE. The plug can contact the substrate 10 of the core region CORE. Wiring can be formed on the mask layer 47. The plug and wiring can be separated by wiring separation grooves.

[0096] Since the plug 60 and the bonding pad LP are formed simultaneously, the plug can include the same material as the bonding pad LP.

[0097] The plug 60 may include a second conductive barrier layer 64B and an eighth conductive layer 66B. The second conductive barrier layer 64B may be formed simultaneously with the first conductive barrier layer 64A of the bonding pad LP, and therefore may include the same material. The eighth conductive layer 66B may be formed simultaneously with the seventh conductive layer 66A of the bonding pad LP, and therefore may include the same material.

[0098] Reference Figure 2A The insert spacer 59 may not be disposed on the lower surface of the insert 60, but may be disposed on the side wall of the insert 60. The insert spacer 59 may include at least one of, for example, silicon nitride, silicon oxynitride, silicon carbonitride, and silicon carbonitride.

[0099] The plug spacer 59 can be applied to any plug in the core region (CORE). However, the embodiments are not limited to this, and the plug spacer 59 may be provided only on the sidewalls of some plugs 60 in the core region (CORE).

[0100] The plug spacer 59 is particularly useful in highly miniaturized semiconductor devices 1 by increasing the separation distance between the plug 60 and the core gate structure. When the aperture used to form the plug is formed to be larger than the desired size, the plug spacer 59 can be used to control the size of the plug aperture. Therefore, the aspect ratio of the plug aperture to be patterned is reduced, which has the advantage of reducing the burden of the patterning process.

[0101] Figure 3 This is a cross-sectional view of a semiconductor device according to an embodiment. Figure 4 This is a cross-sectional view of a semiconductor device according to an embodiment, and shows the main via formed in the insulating layer. Figure 5 This is a cross-sectional view of a semiconductor device according to an embodiment, and shows a mask layer formed in the main aperture.

[0102] Reference Figures 3 to 5 Semiconductor device 2 may include substrate 110 (e.g., Figure 2A The substrate 10), the first gate insulating film 121 (e.g., Figure 2A The gate insulating film 33B), the first gate electrode 131, and the first capping film 141 (e.g., Figure 2A The capping film 44B), the first gate spacer 171 (e.g., Figure 2A Gate spacer 56), second gate insulating film 221, second gate electrode 231, second capping film 241, second gate spacer 271, insulating layer 120, insulating pad 130 (e.g., gate spacer 56), second gate insulating film 221, second gate electrode 231, second capping film 241, second gate spacer 271, insulating layer 120, insulating pad 130 (e.g., Figure 2A The insulating pad 45) and the mask layer 150. The first gate electrode 131 may include a first high-k dielectric film 1311 (e.g., an insulating pad 45) and a ... Figure 2A The fourth conductive layer 41B), the first metal film 1312 (e.g. Figure 2AThe fifth conductive layer 42B) and the first conductive film 1313 (e.g. Figure 2A The sixth conductive layer 43B). The second gate electrode 231 may include a second high-k dielectric film 2311, a second metal film 2312 and a second conductive film 2313.

[0103] The substrate 110 may be a silicon substrate, or may include other materials such as silicon germanium, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. The substrate 110 may be a base substrate on which an epitaxial layer is formed.

[0104] A first gate insulating film 121 may be disposed on a substrate 110. The first gate insulating film 121 may be disposed on the upper surface of the substrate 110. A second gate insulating film 221 may be disposed on the substrate 110. The second gate insulating film 221 may be disposed on the upper surface of the substrate 110. The first gate insulating film 121 and the second gate insulating film 221 may be disposed spaced apart from each other.

[0105] The first gate electrode 131 can be disposed on the first gate insulating film 121. The second gate electrode 231 can be disposed on the second gate insulating film 221.

[0106] The first sealing film 141 can be disposed on the first gate electrode 131. The second sealing film 241 can be disposed on the second gate electrode 231.

[0107] The first gate spacer 171 may be configured to contact the first gate insulating film 121, the first gate electrode 131, and the first capping film 141. The first gate spacer 171 may surround the first gate insulating film 121, the first gate electrode 131, and the first capping film 141. The second gate spacer 271 may be configured to contact the second gate insulating film 221, the second gate electrode 231, and the second capping film 241. The second gate spacer 271 may surround the second gate insulating film 221, the second gate electrode 231, and the second capping film 241.

[0108] The insulating layer 120 may cover at least a portion of the first gate spacer 171. The insulating layer 120 may include a via 140. For example, the via 140 may be defined in the insulating layer 120 and the substrate 110. The via 140 may have a columnar shape with its longitudinal direction along the z-axis. A plurality of vias 140 may be provided. The plurality of vias 140 may be spaced apart from each other in the xy-plane. The vias 140 may be recessed downward from the upper surface of the insulating layer 120. (See reference...) Figure 5 When the mask layer 150 is not filled, the master via 140 can expose the substrate 110. The insulating layer 120 may include oxide. Multiple master vias 140 may be provided, and the pillars of the mask layer 150 may be inserted into all of the multiple master vias 140.

[0109] The mask layer 150 may include a base 151 disposed on the upper side of the insulating layer 120, and a pillar 152 inserted into the main aperture 140 and in contact with the substrate 110. The mask layer 150 may include at least one of silicon nitride, silicon oxynitride, silicon carbonitride, and silicon carbonitride. The pillar 152 may surround a plug, which will be described below. The pillar 152 may have, for example, a hollow cylindrical shape. However, the shape of the pillar 152 is not limited to this.

[0110] The mask layer 150 may have a base and a pillar formed simultaneously by injecting mask layer material into the main hole 140 and simultaneously providing mask layer material on the upper surface of the insulating layer 120.

[0111] Figure 5 This is a cross-sectional view of a semiconductor device according to an embodiment, and shows the plug holes formed in the mask layer. Figure 6 This is a cross-sectional view of a semiconductor device according to an embodiment, and shows a plug disposed in a plug hole formed in a mask layer. Figure 7 The diagram schematically illustrates a plan view of the plug and mask layer according to an embodiment. Figure 8 This is an enlarged cross-sectional view of a portion of a semiconductor device according to an embodiment.

[0112] Reference Figures 6 to 8 The semiconductor device 2 may include a substrate 110, a first gate insulating film 121, a first gate electrode 131, a first capping film 141, a first gate spacer 171, a second gate insulating film 221, a second gate electrode 231, a second capping film 241, a second gate spacer 271, an insulating layer 120, a mask layer 150, and a plug 800. The first gate electrode 131 may include a first high-k dielectric film 1311, a first metal film 1312, and a first conductive film 1313. The second gate electrode 231 may include a second high-k dielectric film 2311, a second metal film 2312, and a second conductive film 2313.

[0113] A portion of the mask layer 150 can be removed. A portion of the mask layer 150 in which the pillar 152 is formed can be removed. A plug hole 160 can be formed in the pillar 152. The plug hole 160 can correspond to the space where the plug 800 is disposed. Since the plug 800 is formed in the plug hole 160, the plug 800 can be surrounded by the pillar 152.

[0114] The plug 800 can be configured to be spaced apart from the first gate spacer 171. A mask layer 150 can be provided to prevent the plug 800 from contacting the first gate spacer 171.

[0115] A plug 800 may be disposed between the first gate electrode 131 and the second gate electrode 231. A mask layer 150 may simultaneously cover both the side surface and the top surface of the first gate spacer 171. A portion of the mask layer 150 may be inserted into the substrate 110. A pillar 152 of the mask layer 150 may be located between the plug 800 and the first gate spacer 171 and is configured to prevent the plug 800 from contacting the first gate spacer 171.

[0116] The longitudinal direction of the plug 800 can be the z-axis direction. Multiple plugs 800 can be set. Multiple plugs 800 can be set to be spaced apart from each other in the xy plane.

[0117] The plug 800 may have a shape in which the diameter decreases toward the substrate 110. The pillar 152 may include a first portion 152a connected to the base 151 and in contact with the insulating layer 120, a second portion 152b connected to the first portion 152a and in contact with the insulating gasket 130, and a third portion 152c connected to the second portion 152b and in contact with the first gate spacer 171 and the second gate spacer 271. The portion of the plug 800 surrounded by the base 151 may have a first diameter d1. The portion of the plug 800 surrounded by the insulating layer 120 may have a second diameter d2. The portion of the plug 800 surrounded by the insulating gasket 130 may have a third diameter d3. The portion of the plug 800 between the first gate spacer 171 and the second gate spacer 271 may have a fourth diameter d4. The second diameter d2 may be less than or equal to the first diameter d1. The third diameter d3 may be less than or equal to the second diameter d2. The fourth diameter d4 may be less than or equal to the third diameter d3. The first portion 152a of the post 152 may be narrower than the second portion 152b of the post. The second portion 152b of the post 152 may be narrower than the third portion 152c of the post. The post 152 can prevent the plug 800 from contacting the insulating layer 120, so that the plug 800 will not deform the insulating layer 120.

[0118] The plug 800 may include a plug body 810 surrounded by a mask layer 150 and a plug head 820 connected to an end of the plug body 810 and positioned for insertion into the substrate 110. The plug body 810 may include metal. The plug head 820 may include silicon dioxide.

[0119] Figure 9 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0120] Reference Figure 9The method of manufacturing a semiconductor device may include an operation S110 of forming a master hole in an insulating layer, an operation S120 of introducing a mask layer into the master hole, an operation S130 of curing the mask layer introduced into the master hole, an operation S140 of forming a plug hole in the mask layer, and an operation S150 of inserting a plug into the plug hole.

[0121] In operation S110, a via can be formed in the insulating layer. For example, in operation S110, at least a portion of the insulating layer and the gate spacer can be removed. In operation S110, a portion of the substrate can be exposed to the outside through the via. In operation S110, a portion of the insulating pad and the gate spacer can be removed together with the insulating layer.

[0122] In operation S120, a mask layer can be formed in the main aperture. For example, operation S120 can be performed simultaneously with the process of forming a mask layer on the upper surface of the insulating layer. The base and pillar portions of the mask layer can be formed simultaneously. The process of forming the mask layer can be implemented compactly.

[0123] In operation S130, plug holes can be formed in the mask layer.

[0124] In operation S140, a plug can be formed in the plug hole. The plug can be surrounded by a mask layer.

[0125] Figure 10 This is a cross-sectional view of a semiconductor device according to an embodiment. Figure 11 The diagram schematically illustrates a plan view of the plug and mask layer according to an embodiment.

[0126] Reference Figure 10 and Figure 11 The semiconductor device 3 may include a substrate 110, a first gate insulating film 121, a first gate electrode 131, a first capping film 141, a first gate spacer 171, a second gate insulating film 233, a second gate electrode 231, a second capping film 241, a second gate spacer 271, an insulating layer 120, an insulating pad 130, a mask layer 150, and a plug 900. The first gate electrode 131 may include a first high-k dielectric film 1311, a first metal film 1312, and a first conductive film 1313. The second gate electrode 231 may include a second high-k dielectric film 2311, a second metal film 2312, and a second conductive film 2313.

[0127] The plug 900 may include a plug body 910 and a plug head 920. The plug 900 may be configured to be surrounded by a mask layer 350. The mask layer 350 may contact the first gate spacer 171. The mask layer 150 may contact the second gate insulating film 233, the second gate electrode 231, and the second capping film 241.

[0128] The longitudinal direction of the plug 900 can be the z-axis direction. Multiple plugs 900 can be set. Multiple plugs 900 can be set to be spaced apart from each other in the xy plane.

[0129] Based on the plug 900, the thickness of the portion 352b of the pillar 352 of the mask layer 350 on the second gate electrode 231 side can be formed to be greater than the thickness of the portion 352a of the pillar 352 of the mask layer 350 on the first gate electrode 131 side. The minimum distance from the plug 900 to the second gate electrode 231 can be greater than the minimum distance from the plug 900 to the first gate spacer 171. According to this structure, the distance between the plug 900 and the second gate electrode 231 can be sufficiently ensured.

[0130] Although various aspects of the embodiments have been specifically shown and described above, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the claims.

Claims

1. A semiconductor device, comprising: Substrate; A first gate insulating film is disposed on the substrate; The first gate electrode is on the first gate insulating film; The first sealing film is on the first gate electrode; The first gate spacer is in contact with the first gate insulating film, the first gate electrode and the first capping film; An insulating liner is provided on the first capping film and the first gate spacer. An insulating layer is present on at least a portion of the first gate spacer and defines a main via. A mask layer includes a base and pillars, the base being on the upper surface of the insulating layer, and the pillars extending into the main aperture and contacting the substrate; as well as A plug is disposed in the main hole and surrounded by the pillar portion of the mask layer.

2. The semiconductor device according to claim 1, wherein, The plug is spaced apart from the first gate spacer.

3. The semiconductor device according to claim 1, wherein, The pillar portion of the mask layer is located between the plug and the first gate spacer to prevent the plug from contacting the first gate spacer.

4. The semiconductor device according to claim 1, wherein, The insulating layer comprises oxide, and The mask layer includes at least one of silicon nitride, silicon oxynitride, silicon carbonitride, and silicon carbonitride.

5. The semiconductor device according to claim 1, wherein, The diameter of the plug decreases toward the substrate.

6. The semiconductor device according to claim 1, wherein, The column portion includes: The first part is connected to the base and in contact with the insulating layer; The second part is connected to the first part and contacts the insulating gasket; and The third part is connected to the second part and contacts the first gate spacer.

7. The semiconductor device according to claim 6, wherein, The diameter of the portion of the plug surrounded by the second part is smaller than the diameter of the portion of the plug surrounded by the first part.

8. The semiconductor device according to claim 6, wherein, The diameter of the portion of the plug surrounded by the third part is smaller than the diameter of the portion of the plug surrounded by the second part.

9. The semiconductor device according to claim 1, wherein, The mask layer is on the side and top surfaces of the first gate spacer.

10. The semiconductor device according to claim 1, further comprising: A second gate insulating film is disposed on the substrate; The second gate electrode is located on the second gate insulating film; The second sealing film is on the second gate electrode; as well as The second gate spacer is in contact with the second gate insulating film, the second gate electrode, and the second capping film.

11. The semiconductor device according to claim 10, wherein, The pillar portion of the mask layer is located between the plug and the first gate spacer to prevent the plug from contacting the first gate spacer and the second gate spacer.

12. The semiconductor device according to claim 1, further comprising: A second gate insulating film is disposed on the substrate; The second gate electrode is located on the second gate insulating film; as well as The second sealing film is located on the second gate electrode. The pillar portion of the mask layer is in contact with the second gate insulating film, the second gate electrode, and the second capping film.

13. The semiconductor device according to claim 12, wherein, The thickness of the portion of the pillar of the mask layer on the second gate electrode side is greater than the thickness of the portion of the pillar of the mask layer on the first gate electrode side.

14. The semiconductor device according to claim 12, wherein, The minimum distance between the plug and the second gate electrode is greater than the minimum distance between the plug and the first gate spacer.

15. The semiconductor device according to claim 14, wherein, The pillar portion of the mask layer prevents the plug from contacting the second gate insulating film, the second gate electrode, and the second capping film.

16. A method for manufacturing a semiconductor device, the method comprising: Provides a structure including an insulating layer; A main hole is formed in the insulating layer; A mask layer is formed in the main hole; Insertion holes are formed in the mask layer; as well as A plug is formed in the plug hole.

17. The method according to claim 16, wherein, Forming the main via includes removing a portion of the insulating liner and gate spacer.

18. The method according to claim 16, wherein, The plug is spaced apart from the gate spacer.

19. The method of claim 16, wherein, At least a portion of the mask layer is disposed between the plug and the gate spacer.

20. The method of claim 16, wherein, The insulating layer comprises oxide, and The mask layer includes at least one of silicon nitride, silicon oxynitride, silicon carbonitride, and silicon carbonitride.

Images