Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device and a method of manufacturing the same are provided. An example semiconductor device includes: a channel layer; the barrier layer is positioned on the channel layer; a gate electrode layer on the barrier layer and extending in a first direction parallel to an upper surface of the barrier layer; the gate semiconductor layer is positioned between the barrier layer and the gate electrode layer; and a source electrode and a drain electrode connected to the channel layer and spaced apart from the gate electrode layer in a second direction parallel to the upper surface of the barrier layer and intersecting the first direction. In a cross section taken in the second direction and a third direction perpendicular to the upper surface of the barrier layer, an angle formed by a lower surface and a side surface of the gate electrode layer is larger than an angle formed by a lower surface and a side surface of the gate semiconductor layer.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods for manufacturing the same. Background Technology

[0002] In modern society, semiconductor devices are closely related to daily life. Specifically, the importance of power semiconductor devices is increasing in various fields such as transportation (e.g., electric vehicles, railways, and trams), renewable energy systems (e.g., solar and wind power), and mobile devices. Power semiconductor devices are semiconductor devices used to handle high voltages or large currents and perform functions such as power conversion and control in high-power systems or high-output electronic devices. Power semiconductor devices have the ability to handle high power and are robust, so they can handle large currents and withstand high voltages. For example, power semiconductor devices can handle voltages from hundreds to thousands of volts and currents from tens to thousands of amperes. Power semiconductor devices can improve the efficiency of electrical energy by minimizing power consumption. In addition, power semiconductor devices can be stably driven even in environments such as high temperatures.

[0003] These power semiconductor devices can be categorized based on their materials, with examples including SiC and GaN power semiconductor devices. Using SiC or GaN instead of existing silicon wafers to fabricate power semiconductor devices compensates for the instability of silicon at high temperatures. SiC power semiconductor devices are heat-resistant and have low power consumption, making them suitable for electric vehicles, renewable energy systems, and more. GaN power semiconductor devices are more expensive but highly efficient in terms of speed, making them suitable for high-speed charging of mobile devices. Summary of the Invention

[0004] This disclosure relates to a semiconductor device in which the alignment between the gate electrode layer and the gate semiconductor layer is easy and excellent, the patterning of the gate semiconductor layer is precise, and the freedom to select etching materials for the gate electrode layer and the gate semiconductor layer is increased. Therefore, the defect problem caused by byproducts resulting from etching different materials of the gate electrode layer and the gate semiconductor layer with different etching materials can be solved. The field between the side surface of the gate semiconductor layer and the upper surface of the barrier layer can be easily controlled, and voids can be prevented when forming the field dispersion layer.

[0005] In some embodiments, a semiconductor device includes: a channel layer; a barrier layer located on the channel layer and comprising a material having a band gap different from that of the channel layer; a gate electrode layer located on the barrier layer and extending in a first direction parallel to an upper surface of the barrier layer; a gate semiconductor layer located between the barrier layer and the gate electrode layer; and a source electrode and a drain electrode connected to the channel layer and spaced apart from the gate electrode layer in a second direction parallel to the upper surface of the barrier layer and intersecting the first direction, wherein, in a cross-section taken along the second direction and in a third direction perpendicular to the upper surface of the barrier layer, the angle formed by the lower surface and side surface of the gate electrode layer is greater than the angle formed by the lower surface and side surface of the gate semiconductor layer.

[0006] In some embodiments, a semiconductor device includes: a channel layer; a barrier layer located on the channel layer and comprising a material having a band gap different from that of the channel layer; a gate electrode layer located on the barrier layer and extending in a first direction parallel to an upper surface of the barrier layer; a gate semiconductor layer located between the barrier layer and the gate electrode layer; a hard mask layer located on the gate electrode layer; and a source electrode and a drain electrode connected to the channel layer and spaced apart from the gate electrode layer in a second direction parallel to the upper surface of the barrier layer and intersecting the first direction, wherein, in a cross-section taken along the second direction and in a third direction perpendicular to the upper surface of the barrier layer, the edge formed by the upper surface and side surfaces of the hard mask layer has a rounded shape, and the length of the lower surface of the gate electrode layer in the second direction is less than the length of the upper surface of the gate semiconductor layer in the second direction and the length of the lower surface of the hard mask layer in the second direction.

[0007] In some embodiments, a method of manufacturing a semiconductor device includes: forming a channel layer on a substrate; forming a barrier layer on the channel layer, the barrier layer comprising a material having a band gap different from that of the channel layer; sequentially forming a gate semiconductor material layer, a gate electrode material layer, and a hard mask material layer on the barrier layer; forming a photoresist pattern on the hard mask material layer; etching the hard mask material layer and the gate electrode material layer with the photoresist pattern using a first etch gas to form a hard mask layer and a gate electrode layer; removing the photoresist pattern; etching the gate semiconductor material layer with the hard mask layer using a second etch gas different from the first etch gas to form a gate semiconductor layer; and forming a source electrode and a drain electrode connected to the channel layer and spaced apart from the gate electrode layer.

[0008] In semiconductor devices according to some embodiments, the alignment between the gate electrode layer and the gate semiconductor layer is easy and excellent, the pattern of the gate semiconductor layer is precise, the degree of freedom in selecting the etching materials for the gate electrode layer and the gate semiconductor layer is increased, the defect problem caused by byproducts generated by etching different materials of the gate electrode layer and the gate semiconductor layer with different etching materials can be solved, the field between the side of the gate semiconductor layer and the upper surface of the barrier layer can be easily controlled, and voids can be prevented when forming the field dispersion layer. Attached Figure Description

[0009] Figure 1 This is a top view showing an example of a semiconductor device.

[0010] Figure 2 It is along Figure 1 Example cross-sectional view taken from line A-A' in the diagram.

[0011] Figure 3 yes Figure 2 An example enlarged cross-sectional view of part P.

[0012] Figure 4 yes Figure 2 An example enlarged cross-sectional view of part P.

[0013] Figure 5 yes Figure 2 An example enlarged cross-sectional view of part P.

[0014] Figure 6 yes Figure 2 An example enlarged cross-sectional view of part P.

[0015] Figure 7 yes Figure 2 An example enlarged cross-sectional view of part P.

[0016] Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 and Figure 14 This is a cross-sectional view illustrating an example of a method for manufacturing semiconductor devices according to process sequence. Detailed Implementation

[0017] The present disclosure will be described more fully below with reference to the accompanying drawings, in which exemplary embodiments of the disclosure are illustrated. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of the present disclosure.

[0018] The accompanying drawings and descriptions should be considered illustrative in nature, not restrictive. Throughout the specification, the same reference numerals denote the same elements.

[0019] For better understanding and ease of description, the dimensions and thicknesses of each component shown in the accompanying drawings are randomly indicated, and this disclosure is not necessarily limited to what is shown. In the drawings, the thicknesses of layers, regions, etc., are exaggerated for clarity. Additionally, in the accompanying drawings, the thicknesses of some layers and regions are exaggerated for better understanding and ease of description.

[0020] What will be understood is that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it may be directly on the other element, or there may be an intermediate element present. Conversely, when an element is referred to as being "directly on" another element, there is no intermediate element present. The words "on" or "above" mean placed on or below a part of an object, and do not necessarily mean placed on the upper side of a part of an object based on the direction of gravity.

[0021] In addition, unless explicitly stated otherwise, the word “including” and its variations such as “including” or “contains” will be understood to imply the inclusion of the stated element, but not to exclude any other element.

[0022] Additionally, in this specification, the phrase "in a plane" refers to the target portion viewed from above, while the phrase "in a cross section" refers to the cross section formed by vertically cutting the target portion viewed from the side.

[0023] Furthermore, throughout the specification, the two directions parallel to and intersecting the upper surface of the substrate are defined as the first direction D1 and the second direction D2, respectively, while the direction perpendicular to the upper surface of the substrate is described as the third direction D3. For example, the first direction D1 and the second direction D2 can be perpendicular to each other.

[0024] Figure 1 This is a top view showing an example of a semiconductor device. Figure 2 It is along Figure 1 Example cross-sectional view taken from line A-A' in the diagram. Figure 3 yes Figure 2 An example enlarged cross-sectional view of part P.

[0025] To make the diagram clearer and simpler, Figure 1 The main components shown are channel layer 132, gate electrode layer 155, lower source electrode 173a, first field dispersion layer 177a and lower drain electrode 175a.

[0026] refer to Figures 1 to 3The semiconductor device includes a channel layer 132, a barrier layer 136 on the channel layer 132, a gate electrode layer 155 on the barrier layer 136, a gate semiconductor layer 152 between the barrier layer 136 and the gate electrode layer 155, and a source electrode 173 and a drain electrode 175 located on both sides of the gate electrode layer 155 and connected to the channel layer 132.

[0027] The channel layer 132 is the layer that forms a channel between the source electrode 173 and the drain electrode 175, and a two-dimensional electron gas (2DEG) 134 can be located inside the channel layer 132. The 2DEG 134 refers to a group of electrons that can move freely in two dimensions (e.g., in the xy plane) as a charge transport model used in solid-state physics, but cannot move and are tightly bound in another dimension (e.g., in the z direction). In other words, the 2DEG 134 can exist in a two-dimensional paper-like form in three-dimensional space. This 2DEG 134 mainly appears in semiconductor heterojunction structures and can appear at the interface between the channel layer 132 and the barrier layer 136 in a semiconductor device. For example, the 2DEG 134 can be generated in the portion of the channel layer 132 closest to the barrier layer 136.

[0028] The channel layer 132 may include a nitride, comprising group III-V materials such as Al, Ga, In, B, or combinations thereof. The channel layer 132 may be made of a single layer or multiple layers. For example, the channel layer 132 may include Al. x In y Ga 1-x-y N (0≤x≤1, 0≤y≤1, x+y≤1). For example, the channel layer 132 may include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or combinations thereof. The channel layer 132 may be a doped layer or an undoped layer. The thickness of the channel layer 132 may be approximately several hundred nm or less.

[0029] The channel layer 132 may be located on the substrate 110, and either the seed layer 115 or the buffer layer 120 may be located between the substrate 110 and the channel layer 132. The substrate 110, seed layer 115, and buffer layer 120 are necessary layers for forming the channel layer 132 and can be omitted in some cases. For example, when a GaN substrate is used as the channel layer 132, at least one of the substrate 110, seed layer 115, and buffer layer 120 can be omitted. Considering the relatively high cost of GaN substrates, a Si substrate 110 can be used to grow the GaN-containing channel layer 132. In this case, because the lattice structures of Si and GaN are different, it may not be easy to directly grow the channel layer 132 on the substrate 110. Therefore, the seed layer 115 and buffer layer 120 can be grown on the substrate 110 first, and then the channel layer 132 can be grown on the buffer layer 120. Additionally, at least one of the substrate 110, seed layer 115, and buffer layer 120 can be removed from the final structure of the semiconductor device after the manufacturing process has been used.

[0030] Substrate 110 may include a semiconductor material. For example, substrate 110 may include sapphire, Si, SiC, AlN, GaN, or combinations thereof. Substrate 110 may be a silicon-on-insulator (SOI) substrate. However, the material of substrate 110 is not limited to this, and any commonly used substrate can be used. In some cases, substrate 110 may include an insulating material. For example, several layers including channel layer 132 may be formed on a semiconductor substrate first, and then the semiconductor substrate may be removed and replaced with an insulating substrate.

[0031] Seed layer 115 may be located on substrate 110. Seed layer 115 may be located directly on substrate 110. However, it is not limited to this, and another predetermined layer may be further located between substrate 110 and seed layer 115. Seed layer 115 is used as a seed for growing buffer layer 120, and may be made of a lattice structure used as a seed for buffer layer 120. For example, seed layer 115 may include AlN, but is not limited to this.

[0032] Buffer layer 120 may be located on seed layer 115. Buffer layer 120 may be located directly on seed layer 115. However, it is not limited thereto, and another predetermined layer may be further located between seed layer 115 and buffer layer 120. Buffer layer 120 may be located between seed layer 115 and channel layer 132. Buffer layer 120 may include a nitride, which includes group III-V materials, such as Al, Ga, In, B, or combinations thereof. Buffer layer 120 may include Al x In y Ga 1-x-yN (0≤x≤1, 0≤y≤1, x+y≤1). For example, buffer layer 120 may include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or combinations thereof. Buffer layer 120 may be made of a single layer or multiple layers. For example, buffer layer 120 may include a superlattice layer and a high-resistivity layer.

[0033] The superlattice layer mitigates the difference in lattice constant and coefficient of thermal expansion between the substrate 110 and the channel layer 132, thereby reducing the tensile and compressive stresses generated between the substrate 110 and the channel layer 132. The high-resistivity layer can be used to prevent semiconductor device degradation by preventing leakage current from flowing through the channel layer 132. For this purpose, the high-resistivity layer can be made of a low-conductivity material to electrically insulate the substrate 110 and the channel layer 132.

[0034] A barrier layer 136 may be located on the channel layer 132. The barrier layer 136 may be directly located on the channel layer 132. However, it is not limited to this, and another predetermined layer may be further located between the channel layer 132 and the barrier layer 136. The region of the channel layer 132 overlapping with the barrier layer 136 may be a drift region DTR. The drift region DTR may be located between the source electrode 173 and the drain electrode 175. When a potential difference exists between the source electrode 173 and the drain electrode 175, charge carriers can move in the drift region DTR. The semiconductor device can be turned on / off depending on whether a voltage is applied to the gate electrode layer 155 and the magnitude of the voltage applied to the gate electrode layer 155. When a voltage greater than a threshold voltage is applied to the gate electrode layer 155 and the semiconductor device is turned on, a channel can be created in the depletion region DPR. Therefore, carrier movement may occur in the drift region DTR. If a voltage below the threshold voltage is applied to the gate electrode layer 155 or no voltage is applied, the channel path in the depletion region DPR may be blocked, and carrier movement may not occur.

[0035] Barrier layer 136 may include a nitride, which includes group III-V materials such as Al, Ga, In, B, or combinations thereof. x In y Ga 1-x-yN (0≤x≤1, 0≤y≤1, x+y≤1). For example, the barrier layer 136 may include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or combinations thereof. The band gap of the barrier layer 136 can be adjusted by the composition ratio of Al or In. The barrier layer 136 may be doped with predetermined impurities. In this case, the impurities doped into the barrier layer 136 may be p-type dopants capable of providing holes. For example, the impurities doped into the barrier layer 136 may be magnesium (Mg). By increasing or decreasing the impurity doping concentration of the barrier layer 136, the threshold voltage, on-resistance, etc. of the semiconductor device can be adjusted.

[0036] The barrier layer 136 may comprise a semiconductor material having properties different from those of the channel layer 132. The barrier layer 136 may differ from the channel layer 132 in at least one of polarization characteristics, band gap, and lattice constant. For example, the barrier layer 136 may comprise a material having a different band gap than the channel layer 132. In this case, the barrier layer 136 may have a higher band gap and a higher polarization than the channel layer 132. Through the barrier layer 136, a two-dimensional electron gas 134 can be induced in the channel layer 132, which has a relatively low polarization. In this respect, the barrier layer 136 may also be referred to as a channel supply layer or a two-dimensional electron gas supply layer. The two-dimensional electron gas 134 may be formed within a portion of the channel layer 132 located below the interface between the channel layer 132 and the barrier layer 136. The two-dimensional electron gas 134 may have very high electron mobility.

[0037] The gate electrode layer 155 may be located on the barrier layer 136. The gate electrode layer 155 may overlap a portion of the barrier layer 136 in the third direction D3. The gate electrode layer 155 may overlap a portion of the drift region DTR of the channel layer 132 in the third direction D3. The gate electrode layer 155 may be located between the source electrode 173 and the drain electrode 175 in the second direction D2. The gate electrode layer 155 may be spaced apart from the source electrode 173 and the drain electrode 175 in the second direction D2. The gate electrode layer 155 may extend in a plane along the first direction D1. That is, the gate electrode layer 155 may have a strip shape extending in a plane along the first direction D1.

[0038] The gate electrode layer 155 may include a conductive material. For example, the gate electrode layer 155 may include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal oxide nitride. For example, the gate electrode layer 155 may be made of titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten ( The gate electrode layer 155 may be composed of, but is not limited to, a single layer or multiple layers. It may also be composed of, but is not limited to, a single layer or multiple layers. (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or combinations thereof.

[0039] The gate semiconductor layer 152 is located between the barrier layer 136 and the gate electrode layer 155. That is, the gate semiconductor layer 152 may be located on the barrier layer 136, and the gate electrode layer 155 may be located on the gate semiconductor layer 152. The gate electrode layer 155 may have a Schottky contact with the gate semiconductor layer 152. However, it is not limited to this; in some cases, the gate electrode layer 155 may have an ohmic contact with the gate semiconductor layer 152. The gate semiconductor layer 152 may overlap with the gate electrode layer 155 on a third-direction D3. The upper surface US_152 of the gate semiconductor layer 152 may be completely covered by the gate electrode layer 155.

[0040] The gate semiconductor layer 152 may be located between the source electrode 173 and the drain electrode 175 in the second direction D2. The gate semiconductor layer 152 may be spaced apart from the source electrode 173 and the drain electrode 175 in the second direction D2. The gate semiconductor layer 152 may be closer to the source electrode 173 than the drain electrode 175. That is, the spacing between the gate semiconductor layer 152 and the source electrode 173 may be smaller than the spacing between the gate semiconductor layer 152 and the drain electrode 175.

[0041] The gate semiconductor layer 152 may include a nitride, which includes group III-V materials such as Al, Ga, In, B, or combinations thereof. The gate semiconductor layer 152 may include Al... x In y Ga 1-x-yN (0≤x≤1, 0≤y≤1, x+y≤1). For example, the gate semiconductor layer 152 may include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or combinations thereof. The gate semiconductor layer 152 may include a material with a band gap different from that of the barrier layer 136. For example, the gate semiconductor layer 152 may include GaN, while the barrier layer 136 may include AlGaN. The gate semiconductor layer 152 may be doped with predetermined impurities. In this case, the impurities doped into the gate semiconductor layer 152 may be p-type dopants capable of providing holes. For example, the gate semiconductor layer 152 may include GaN doped with p-type impurities. That is, the gate semiconductor layer 152 may be made of a p-GaN layer. However, it is not limited to this, and the gate semiconductor layer 152 may be a p-AlGaN layer. The impurities doped into the gate semiconductor layer 152 may be magnesium (Mg). The gate semiconductor layer 152 may be made of a single layer or multiple layers.

[0042] A depletion region DPR can be formed in the channel layer 132 via the gate semiconductor layer 152. The depletion region DPR can be located within the drift region DTR and can have a narrower width than the drift region DTR. With the gate semiconductor layer 152 having a different bandgap than the barrier layer 136 located on the barrier layer 136, the bandgap level of the portion of the barrier layer 136 overlapping with the gate semiconductor layer 152 can be increased. Therefore, the depletion region DPR can be formed in the region of the channel layer 132 overlapping with the gate semiconductor layer 152. The depletion region DPR can be a region in the channel path of the channel layer 132 where the two-dimensional electron gas 134 is not formed, or it can have a lower electron concentration than the remaining regions. That is, the depletion region DPR can refer to the region where the flow of the two-dimensional electron gas 134 is interrupted within the drift region DTR. Because the depletion region DPR is generated, current does not flow between the source electrode 173 and the drain electrode 175, and the channel path is blocked. Therefore, the semiconductor device can have normally-off characteristics.

[0043] That is, the semiconductor device can be a normally-off semiconductor device (HEMT, High Electron Mobility Transistor). In the normal state, when no voltage is applied to the gate electrode layer 155, a depletion region DPR exists, and the semiconductor device can be in a turned-off state. Although not shown, when a voltage higher than a threshold voltage is applied to the gate electrode layer 155, the depletion region DPR disappears, and the two-dimensional electron gas 134 can remain connected within the drift region DTR. That is, the two-dimensional electron gas 134 can be formed throughout the entire channel path between the source electrode 173 and the drain electrode 175, and the semiconductor device can be in a turned-on state. In summary, the semiconductor device can include semiconductor layers with different polarization characteristics, and a semiconductor layer with relatively high polarizability can induce a two-dimensional electron gas 134 in another semiconductor layer forming a heterojunction with it. This two-dimensional electron gas 134 can serve as a channel between the source electrode 173 and the drain electrode 175, and the continuation or interruption of the flow of the two-dimensional electron gas 134 can be controlled by a bias voltage applied to the gate electrode layer 155. In the gate-off state, the flow of the two-dimensional electron gas 134 is blocked, therefore, current does not flow between the source electrode 173 and the drain electrode 175. In the gate-on state, the two-dimensional electron gas 134 continues to flow, therefore, current can flow between the source electrode 173 and the drain electrode 175.

[0044] While the case of a normally-off high electron mobility transistor (HEP) has been described above, this disclosure is not limited thereto. For example, the semiconductor device can be a normally-on HEP. In the case of a normally-on HEP, the gate semiconductor layer 152 can be omitted, and therefore, the gate electrode layer 155 can be directly located on the barrier layer 136. That is, the gate electrode layer 155 can contact the barrier layer 136. In this structure, when no voltage is applied to the gate electrode layer 155, the two-dimensional electron gas 134 can serve as a channel, and current can flow between the source electrode 173 and the drain electrode 175. Furthermore, when a negative voltage is applied to the gate electrode layer 155, a depletion region DPR, in which the flow of the two-dimensional electron gas 134 is interrupted, may be generated at the bottom of the gate electrode layer 155.

[0045] The buffer layer 120, channel layer 132, barrier layer 136, and gate semiconductor layer 152 described above can be sequentially stacked on the substrate 110. In a semiconductor device, at least one of the buffer layer 120, channel layer 132, barrier layer 136, and gate semiconductor layer 152 may be omitted. The buffer layer 120, channel layer 132, barrier layer 136, and gate semiconductor layer 152 can be made of the same semiconductor material, and the material composition ratio of each layer can be different, taking into account the function of each layer and the performance required by the semiconductor device.

[0046] Please refer to later. Figures 8 to 14As described, in a semiconductor device, a photoresist pattern is etched using a first etching gas. Figure 9 The gate electrode layer 155 is formed by etching the photoresist pattern PR, removing the photoresist pattern PR, and etching the hard mask layer with a second etch gas different from the first etch gas. Figure 10 The gate semiconductor layer 152 is formed using a photoresist pattern PR to form the gate electrode layer 155 and a hard mask layer 156 to form the gate semiconductor layer 152. Therefore, the gate electrode layer 155 can be etched with a first etching gas and the gate semiconductor layer 152 can be etched with a second etching gas, thereby increasing the degree of freedom in selecting etching materials for the gate electrode layer 155 and the gate semiconductor layer 152.

[0047] Therefore, the side slopes of the gate electrode layer 155 and the gate semiconductor layer 152 can be controlled in various ways, and the field between the side surface SW_152 of the gate semiconductor layer 152 and the upper surface US_136 of the barrier layer 136 can be easily controlled.

[0048] For example, in a cross-sectional view taken along the second direction D2 and the third direction D3 (e.g., Figure 3 In this structure, the angle θ_155 formed by the lower surface BS_155 and the side surface SW_155 of the gate electrode layer 155 can be different from the angle θ_152 formed by the lower surface BS_152 and the side surface SW_152 of the gate semiconductor layer 152. For example, the angle θ_155 formed by the lower surface BS_155 and the side surface SW_155 of the gate electrode layer 155 can be greater than the angle θ_152 formed by the lower surface BS_152 and the side surface SW_152 of the gate semiconductor layer 152.

[0049] In this paper, cross-sectional views taken along the second direction D2 and the third direction D3 (e.g., Figure 3 In this configuration, the gate electrode layer 155 may have an upper surface US_155 and a lower surface BS_155 that face each other on a third direction D3 and extend along a second direction D2, and two side surfaces SW_155 that connect the upper surface US_155 and the lower surface BS_155 and extend along a third direction D3. The upper surface US_155 of the gate electrode layer 155 may face the hard mask layer 156, while the lower surface BS_155 of the gate electrode layer 155 may face the gate semiconductor layer 152. For example, the upper surface US_155 of the gate electrode layer 155 may be defined as the surface that contacts the hard mask layer 156, the lower surface BS_155 of the gate electrode layer 155 may be defined as the surface that contacts the gate semiconductor layer 152, and the two side surfaces SW_155 of the gate electrode layer 155 may be defined as the surfaces that do not contact the hard mask layer 156 and the gate semiconductor layer 152.

[0050] For example, the angle θ_155 formed between the lower surface BS_155 and the side surface SW_155 of the gate electrode layer 155 can be greater than or equal to about 60°, for example, greater than or equal to about 60°, greater than or equal to about 65°, greater than or equal to about 70°, greater than or equal to about 75°, greater than or equal to 80°, or greater than or equal to 85°, and can be less than or equal to about 90°, for example, less than or equal to about 90°, less than or equal to about 85°, less than or equal to about 80°, less than or equal to about 75°, less than or equal to about 70°, or less than or equal to 65°, and can be from 60° to about 90°.

[0051] Furthermore, the angle θ_152 formed by the lower surface BS_152 and the side surface SW_152 of the gate semiconductor layer 152 can be greater than or equal to approximately 30°, for example, greater than or equal to approximately 30°, greater than or equal to approximately 35°, greater than or equal to approximately 40°, or greater than or equal to approximately 45°, greater than or equal to approximately 50°, greater than or equal to approximately 55°, greater than or equal to approximately 60°, greater than or equal to approximately 60°, greater than or equal to approximately 65°, greater than or equal to approximately 70°, greater than or equal to approximately 75°, greater than or equal to approximately 80°. Or greater than or equal to approximately 85°, but may be less than or equal to approximately 89°, for example less than approximately 89°, less than or equal to approximately 85°, less than or equal to approximately 80°, less than or equal to approximately 75°, less than or equal to approximately 70°, less than or equal to approximately 65°, less than or equal to approximately 60°, less than or equal to approximately 60°, less than or equal to approximately 55°, less than or equal to approximately 50°, less than or equal to approximately 45°, less than or equal to approximately 40°, or less than or equal to approximately 35°, and may be from approximately 30° to approximately 89°.

[0052] Therefore, in the cross-sectional view taken along the second direction D2 and the third direction D3 (e.g., Figure 3 In the gate electrode layer 155, the length W_US_155 of the upper surface US_155 in the second direction D2 can be less than the length W_BS_155 of the lower surface BS_155 in the second direction D2. Similarly, the length W_US_152 of the upper surface US_152 of the gate semiconductor layer 152 in the second direction D2 can be less than the length W_BS_152 of the lower surface BS_152 in the second direction D2. Furthermore, the length difference in the second direction D2 between the lower surface BS_155 and the upper surface US_155 of the gate electrode layer 155 (= W_BS_155 - W_US_155) can be less than the length difference in the second direction D2 between the lower surface BS_152 and the upper surface US_152 of the gate semiconductor layer 152 (= W_BS_152 - W_US_152).

[0053] As described above, byproducts generated when etching the gate electrode layer 155 with the first etching gas may affect the etching of the gate semiconductor layer 152 with the second etching gas and cause defects. To solve this problem, after etching the gate electrode layer 155 with the first etching gas and before etching the gate semiconductor layer 152 with the second etching gas, the byproducts generated when etching the gate electrode layer 155 with the first etching gas can be removed by processes such as ashing or stripping. Therefore, the defect problem caused by byproducts generated when etching the gate electrode layer 155 and the gate semiconductor layer 152 of different materials using different etching materials can be solved.

[0054] During the removal of byproducts through processes such as ashing or stripping, the photoresist pattern PR can also be removed. In this process, the hard mask layer 156 is not removed. The hard mask layer 156 can be used as a mask in a subsequent process where the gate semiconductor layer 152 is formed using a second etch gas. When the gate semiconductor layer 152 is etched, the hard mask layer 156 is partially etched according to the etch conditions, and the hard mask layer 156 can have a rounded shape at the edges formed by the upper surface US_156 and the side surface SW_156. Because the edges of the hard mask layer 156 have a rounded shape, the angle θ_177a formed by the lower surface BS_177a1 of the landing portion 177a1 of the first field dispersion layer 177a (described later) and the lower surface BS_177a3 of the connecting portion 177a3 can be adjusted to prevent voids from forming during the formation of the first field dispersion layer 177a.

[0055] Therefore, the semiconductor device may further include a hard mask layer 156 located on the gate electrode layer 155. However, when the gate semiconductor layer 152 is etched, the hard mask layer 156 may be removed depending on the etching conditions.

[0056] If the hard mask layer 156 comprises the same material as the first protective layer 140, which will be described later, the boundary between the hard mask layer 156 and the first protective layer 140 may be indistinguishable. In this case, because the distance in the third direction D3 from the upper surface US_155 of the gate electrode layer 155 to the lower surface of the overlapping portion 177a2 of the first field dispersion layer 177a includes the distance of the first protective layer 140 in the third direction D3 and the distance of the hard mask layer 156 in the third direction D3, the distance in the third direction D3 from the upper surface US_155 of the gate electrode layer 155 to the lower surface of the overlapping portion 177a2 of the first field dispersion layer 177a can be greater than the distance in the third direction D3 from the upper surface US_136 of the barrier layer 136 to the lower surface of the landing portion 177a1 of the first field dispersion layer 177a.

[0057] A cross-sectional view taken along the second direction D2 and the third direction D3 (e.g., Figure 3 In the first protective layer 140 and the first field dispersion layer 177a, the hard mask layer 156 may have an upper surface US_156 and a lower surface BS_156 facing each other in the third direction D3 and extending along the second direction D2, and two side surfaces SW_156 connecting the upper surface US_156 and the lower surface BS_156 and extending along the third direction D3. The upper surface US_156 of the hard mask layer 156 may face the overlapping portion 177a2 of the first protective layer 140 and the first field dispersion layer 177a, while the lower surface BS_156 of the hard mask layer 156 may face the gate electrode layer 155.

[0058] The upper surface US_156 of the hard mask layer 156 can extend from the midpoint of the hard mask layer 156 in the second direction D2 to both ends of the second direction D2. The upper surface US_156 of the hard mask layer 156 can have different heights in the second direction D2. For example, the difference between the heights of the two ends of the upper surface US_156 of the hard mask layer 156 in the second direction D2 and the height at the midpoint of the second direction D2 can be within ±30%, ±20%, ±10%, ±5%, or ±1% of the height at the midpoint of the second direction D2, and points where the height relative to the height at the midpoint of the second direction D2 exceeds ±30%, ±20%, ±10%, ±5%, or ±1% can correspond to the side surface SW_156 of the hard mask layer 156.

[0059] The lower surface BS_156 of the hard mask layer 156 can extend from the midpoint of the second direction D2 to both ends of the second direction D2. The lower surface BS_156 of the hard mask layer 156 can have different heights in the second direction D2. For example, the difference between the heights of the two ends of the upper surface BS_156 of the hard mask layer 156 in the second direction D2 and the height at the midpoint of the second direction D2 can be within ±30%, ±20%, ±10%, ±5%, or ±1% of the height at the midpoint of the second direction D2, and points where the height relative to the height at the midpoint of the second direction D2 exceeds ±30%, ±20%, ±10%, ±5%, or ±1% can correspond to the side surface SW_156 of the hard mask layer 156.

[0060] A cross-sectional view taken along the second direction D2 and the third direction D3 (e.g., Figure 3 In the hard mask layer 156, the edge formed by the upper surface US_156 and the side surface SW_156 can have a rounded shape. In other words, the edge formed by the upper surface US_156 and the side surface SW_156 of the hard mask layer 156 can not have a sharp corner shape, but can have an obliquely rounded shape, and can have curvature, for example.

[0061] Therefore, the angle θ_156U formed between the upper surface US_156 and the side surface SW_156 of the hard mask layer 156 can decrease as the distance from the upper surface US_156 of the hard mask layer 156 in the third direction D3 increases. In this paper, the angle θ_156U formed between the upper surface US_156 and the side surface SW_156 of the hard mask layer 156 can be the interior angle formed between the tangent at a point on the side surface SW_156 and the upper surface US_156.

[0062] Furthermore, the ratio of the length W_US_156 of the upper surface US_156 of the hard mask layer 156 in the second direction D2 to the length W_BS_156 of the lower surface BS_156 of the hard mask layer 156 in the second direction D2 can be approximately 9:10 or less, for example, approximately 9:10.5 or less, approximately 9:11 or less, or approximately 9:11.5 or less, and can be approximately 9:12 or greater, for example, approximately 9:11.5 or greater, approximately 9:11 or greater, or approximately 9:10.5 or less, and can be approximately 9:10 to approximately 9:12. The length W_US_156 of the upper surface US_156 of the hard mask layer 156 in the second direction D2 can be the length measured from an upper surface US_156 that is substantially flat in the second direction D2, except for the rounded shape of the edges. In this document, flat can mean parallel to the second direction D2.

[0063] For example, in a cross-sectional view taken along the second direction D2 and the third direction D3 (e.g., Figure 3 In the hard mask layer 156, the angle θ_155 formed by the lower surface BS_155 and the side surface SW_155 of the gate electrode layer 155 can be different from the angle θ_156 formed by the upper surface US_156 and the side surface SW_156 of the hard mask layer 156. For example, the angle θ_156 formed by the upper surface US_156 and the side surface SW_156 of the hard mask layer 156 can be greater than the angle θ_155 formed by the lower surface BS_155 and the side surface SW_155 of the gate electrode layer 155.

[0064] For example, the angle θ_156U formed between the upper surface US_156 and the side surface SW_156 of the hard mask layer 156 can be greater than or equal to about 90°, for example, greater than or equal to about 90°, greater than or equal to about 95°, greater than or equal to about 100°, greater than or equal to about 105°, greater than or equal to 110°, or greater than or equal to 115°, and can be less than or equal to about 120°, for example, less than or equal to about 120°, less than or equal to about 115°, less than or equal to about 110°, less than or equal to about 105°, or less than or equal to about 100°, or less than or equal to about 95°, or less than or equal to about 90°, and can be from about 90° to about 120°.

[0065] As an example, the hard mask layer 156 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0066] The semiconductor device may further include a first protective layer 140, a second protective layer 150, and a third protective layer 160 located on the barrier layer 136, the gate electrode layer 155, and the hard mask layer 156. As an example, the semiconductor device may include a first protective layer 140, a second protective layer 150 located on the first protective layer 140, and a third protective layer 160 located on the second protective layer 150. The first protective layer 140 may cover the upper surface US_156 of the barrier layer 136, the gate electrode layer 155, and the hard mask layer 156, and may also cover the side surface SW_155 of the gate electrode layer 155, the side surface SW_152 of the gate semiconductor layer 152, and the side surface SW_156 of the hard mask layer 156. The lower surface of the first protective layer 140 may contact the barrier layer 136, the gate electrode layer 155, the gate semiconductor layer 152, and the hard mask layer 156. The upper surface of the first protective layer 140 may contact the second protective layer 150. The second protective layer 150 and the third protective layer 160 can be spaced apart from the barrier layer 136, the gate electrode layer 155, the gate semiconductor layer 152, and the hard mask layer 156 by the first protective layer 140. Therefore, the second protective layer 150 and the third protective layer 160 do not need to contact the barrier layer 136, the gate electrode layer 155, the gate semiconductor layer 152, and the hard mask layer 156.

[0067] The barrier layer 136 or gate electrode layer 155 may be protected by a first protective layer 140, a second protective layer 150, and a third protective layer 160, and may be separate from other components. The first protective layer 140, the second protective layer 150, and the third protective layer 160 may include insulating materials. For example, the first protective layer 140, the second protective layer 150, and the third protective layer 160 may include oxides such as SiO2 or Al2O3. As another example, the first protective layer 140, the second protective layer 150, and the third protective layer 160 may include nitrides such as SiN or oxide oxynitrides such as SiON. The first protective layer 140, the second protective layer 150, and the third protective layer 160 may include the same material or different materials. If the first protective layer 140, the second protective layer 150, and the third protective layer 160 are made of the same material, the boundaries between the first protective layer 140, the second protective layer 150, and the third protective layer 160 may not be visible. The first protective layer 140, the second protective layer 150, and the third protective layer 160 can each be made as a single layer or multiple layers.

[0068] Source electrode 173 and drain electrode 175 may be located on channel layer 132. Source electrode 173 and drain electrode 175 may be spaced apart from each other in the second direction D2, and hard mask layer 156, gate electrode layer 155, and gate semiconductor layer 152 may be located between source electrode 173 and drain electrode 175. Hard mask layer 156, gate electrode layer 155, and gate semiconductor layer 152 may be spaced apart from source electrode 173 and drain electrode 175 in the second direction D2. Source electrode 173 may be electrically connected to channel layer 132 on one side of gate electrode layer 155 in the second direction D2. Drain electrode 175 may be electrically connected to channel layer 132 on the other side of gate electrode layer 155 in the second direction D2. Source electrode 173 and drain electrode 175 may be located outside the drift region DTR of channel layer 132. The boundary between source electrode 173 and channel layer 132 may be an edge of the drift region DTR. Similarly, the boundary between the drain electrode 175 and the channel layer 132 can be another edge of the drift region DTR. However, this disclosure is not limited to this, and the source electrode 173 and drain electrode 175 may not be located outside the drift region DTR of the channel layer 132. In this case, the channel layer 132 may not be recessed, and the source electrode 173 and drain electrode 175 may be located on the upper surface of the channel layer 132. The lower surfaces of the source electrode 173 and the drain electrode 175 may contact the upper surface of the channel layer 132. The portion of the channel layer 132 in contact with the source electrode 173 and drain electrode 175 may be highly doped. In this case, charge carriers passing through the two-dimensional electron gas 134 can pass through the highly doped channel layer 132, that is, they can be transported to the source electrode 173 and drain electrode 175 through the upper part of the two-dimensional electron gas 134. The source electrode 173 and drain electrode 175 may not directly contact the two-dimensional electron gas 134 in the horizontal direction. The horizontal direction can refer to the direction parallel to the upper surface US_136 of the channel layer 132 or the barrier layer 136.

[0069] The source electrode 173 and the drain electrode 175 can extend in a plane along a first direction D1. That is, the source electrode 173 and the drain electrode 175 can have a rod shape extending in a plane along the first direction D1. The source electrode 173 and the drain electrode 175 can extend in a parallel direction. The source electrode 173 and the drain electrode 175 can extend in a direction parallel to the gate electrode layer 155.

[0070] The source electrode 173 and drain electrode 175 may include conductive materials. For example, the source electrode 173 and drain electrode 175 may include metals, metal alloys, conductive metal nitrides, metal silicides, doped semiconductor materials, conductive metal oxides, or conductive metal oxides. For example, the source electrode 173 and drain electrode 175 may be made of titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), or tantalum carbonitride (TaCN). The material can be made of, but is not limited to, tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or combinations thereof. The source electrode 173 and drain electrode 175 can be made of a single layer or multiple layers. The source electrode 173 and drain electrode 175 can be in ohmic contact with the channel layer 132. Compared to other regions, the region within the channel layer 132 in contact with the source electrode 173 and drain electrode 175 can be doped at a relatively high concentration.

[0071] The source electrode 173 may include a lower source electrode 173a, an intermediate source electrode 173b, and an upper source electrode 173c. The intermediate source electrode 173b may be located on the lower source electrode 173a. The upper source electrode 173c may be located on the intermediate source electrode 173b. The lower source electrode 173a may be in direct contact with the channel layer 132 and may be electrically connected to the channel layer 132. The intermediate source electrode 173b and the upper source electrode 173c may not be in direct contact with the channel layer 132, but may be electrically connected to the channel layer 132 through the lower source electrode 173a.

[0072] The drain electrode 175 may include a lower drain electrode 175a, an intermediate drain electrode 175b, and an upper drain electrode 175c. The intermediate drain electrode 175b may be located on the lower drain electrode 175a. The upper drain electrode 175c may be located on the intermediate drain electrode 175b. The lower drain electrode 175a may be in direct contact with the channel layer 132 and may be electrically connected to the channel layer 132. The intermediate drain electrode 175b and the upper drain electrode 175c may not be in direct contact with the channel layer 132, but may be electrically connected to the channel layer 132 through the lower drain electrode 175a.

[0073] The upper surfaces of the lower source electrode 173a and the lower drain electrode 175a can be located on the first protective layer 140. The upper surfaces of the lower source electrode 173a and the lower drain electrode 175a can be located between the first protective layer 140 and the second protective layer 150. The lower source electrode 173a and the lower drain electrode 175a penetrate the first protective layer 140 and the barrier layer 136, and the trenches that recess the upper surface of the channel layer 132 can be located on both sides of the gate electrode layer 155, spaced apart from each other. The lower source electrode 173a and the lower drain electrode 175a can be located in the trenches on both sides of the gate electrode layer 155, respectively. The lower source electrode 173a and the lower drain electrode 175a can be formed to fill the trenches. Within the trenches, the lower source electrode 173a and the lower drain electrode 175a can contact the channel layer 132 and the barrier layer 136. The channel layer 132 can form the bottom and sidewalls of the trench, and the barrier layer 136 can form the sidewalls of the trench. Therefore, the lower source electrode 173a and the lower drain electrode 175a can contact the upper surface and side surface of the channel layer 132. Additionally, the lower source electrode 173a and the lower drain electrode 175a can contact the side surface of the barrier layer 136. That is, the lower source electrode 173a and the lower drain electrode 175a can cover the side surfaces of the channel layer 132 and the barrier layer 136. The upper surfaces of the lower source electrode 173a and the lower drain electrode 175a can protrude from the upper surface of the first protective layer 140. Furthermore, at least one of the lower source electrode 173a and the lower drain electrode 175a can cover at least a portion of the upper surface of the first protective layer 140. A second protective layer 150 can be located on the lower source electrode 173a and the lower drain electrode 175a. At least a portion of the lower source electrode 173a and the lower drain electrode 175a may be covered by the second protective layer 150.

[0074] The semiconductor device may further include a first field dispersion layer 177a located on the first protective layer 140. The first field dispersion layer 177a may be located between the source electrode 173 and the drain electrode 175. The gate electrode layer 155 may be covered by the first field dispersion layer 177a. The first field dispersion layer 177a may be electrically connected to the source electrode 173. For example, the first field dispersion layer 177a may be connected to the lower source electrode 173a. The first field dispersion layer 177a may include the same material as the lower source electrode 173a and may be located in the same layer as the lower source electrode 173a. The first field dispersion layer 177a may be formed simultaneously with the lower source electrode 173a in the same process. The boundary between the first field dispersion layer 177a and the lower source electrode 173a is not clear, and the first field dispersion layer 177a may be integrally formed with the lower source electrode 173a. However, this disclosure is not limited thereto, and the first field dispersion layer 177a may be a separate element from the lower source electrode 173a. Furthermore, the first field dispersion layer 177a can be located in a different layer from the lower source electrode 173a, and can be formed in different processes. In some cases, the first field dispersion layer 177a can be electrically connected to the gate electrode layer 155. For example, an opening overlapping the gate electrode layer 155 can be formed in the first protective layer 140, and the first field dispersion layer 177a can be connected to the gate electrode layer 155 through the opening. In this case, the first field dispersion layer 177a may not be connected to the source electrode 173.

[0075] The first field dispersion layer 177a may overlap with the gate electrode layer 155 in the third direction D3. For example, the first field dispersion layer 177a may include an overlapping portion 177a2 that overlaps with the gate electrode layer 155 in the third direction D3, landing portions 177a1 located on both sides of the overlapping portion 177a2 in the second direction D2, and a connecting portion 177a3 connecting the overlapping portion 177a2 and the landing portion 177a1.

[0076] The landing portion 177a1 may not overlap with the gate electrode layer 155 in the third direction D3. Compared to the overlapping portion 177a2, the landing portion 177a1 may be closer to the upper surface US_136 of the barrier layer 136 in the third direction D3 (hereinafter referred to as "height in the third direction D3"). In other words, because the gate electrode layer 155 is located below the overlapping portion 177a2, and the gate electrode layer 155 is not located below the landing portion 177a1, and the thickness of the first protective layer 140 between the gate electrode layer 155 and the first field dispersion layer 177a and the thickness of the first protective layer 140 between the barrier layer 136 and the first field dispersion layer 177a are constant along the second direction D2, the height of the overlapping portion 177a2 on the gate electrode layer 155 in the third direction D3 may be higher than the height of the landing portion 177a1 in the third direction D3.

[0077] The connecting portion 177a3 is connected to the overlapping portion 177a2 and the landing portion 177a1, which have different heights in the third direction D3. Therefore, the height of the connecting portion 177a3 in the third direction D3 can increase as it moves from the landing portion 177a1 to the overlapping portion 177a2 in the second direction D2.

[0078] As described above, when etching the gate semiconductor layer 152, while partially etching the hard mask layer 156 according to the etching conditions, the hard mask layer 156 can have a rounded edge shape formed by the upper surface US_156 and the side surface SW_156. Because the edge of the hard mask layer 156 has a rounded shape, the angle θ_177a formed by the lower surface BS_177a1 of the landing portion 177a1 of the first field dispersion layer 177a and the lower surface BS_177a3 of the connecting portion 177a3 can be adjusted, thus preventing voids from being generated when forming the first field dispersion layer 177a.

[0079] For example, in a cross-sectional view taken along the second direction D2 and the third direction D3 (e.g., Figure 3 In the first field dispersion layer 177a, the angle θ_177a formed by the lower surface BS_177a1 of the landing portion 177a1 and the lower surface BS_177a3 of the connecting portion 177a3 can be greater than or equal to about 90°, for example, greater than or equal to about 90°, greater than or equal to about 100°, greater than or equal to about 110°, greater than or equal to about 120°, greater than or equal to about 130°, or greater than or equal to about 140° and less than or equal to about 150°, for example, less than or equal to about 150°, less than or equal to about 140°, less than or equal to about 130°, less than or equal to about 120°, less than or equal to about 110°, or less than or equal to about 100°, and can be from about 90° to about 150°.

[0080] The semiconductor device may further include a second field dispersion layer 177b located on the second protective layer 150. The second field dispersion layer 177b may form a field dispersion layer together with the first field dispersion layer 177a. The second field dispersion layer 177b may be located between the source electrode 173 and the drain electrode 175. The second field dispersion layer 177b may overlap with the gate electrode layer 155 on a third-direction D3. The second field dispersion layer 177b may overlap with the first field dispersion layer 177a on a third-direction D3. The gate electrode layer 155 and the first field dispersion layer 177a may be covered by the second field dispersion layer 177b. The second field dispersion layer 177b may be wider than the first field dispersion layer 177a. The second field dispersion layer 177b may completely cover the first field dispersion layer 177a. However, this disclosure is not limited thereto, and the width and positional relationship of the first field dispersion layer 177a and the second field dispersion layer 177b may be changed in various ways. The second field dispersion layer 177b may be electrically connected to the source electrode 173. For example, the second field dispersion layer 177b can be connected to the intermediate source electrode 173b. The second field dispersion layer 177b may comprise the same material as the intermediate source electrode 173b and may be located in the same layer as the intermediate source electrode 173b. The second field dispersion layer 177b may be formed simultaneously with the intermediate source electrode 173b in the same process. The boundary between the second field dispersion layer 177b and the intermediate source electrode 173b is not clearly defined, and the second field dispersion layer 177b may be integrally formed with the intermediate source electrode 173b. However, this disclosure is not limited thereto, and the second field dispersion layer 177b may be a separate component separate from the intermediate source electrode 173b. Alternatively, the second field dispersion layer 177b may be located in a different layer from the intermediate source electrode 173b and may be formed in a different process.

[0081] The semiconductor device may further include a third field dispersion layer 177c located on the third protective layer 160. The third field dispersion layer 177c may form a field dispersion layer together with the first field dispersion layer 177a and the second field dispersion layer 177b. The third field dispersion layer 177c may be located between the source electrode 173 and the drain electrode 175. The third field dispersion layer 177c may overlap with the gate electrode layer 155 on the third direction D3. The third field dispersion layer 177c may overlap with the first field dispersion layer 177a and the second field dispersion layer 177b on the third direction D3. The gate electrode layer 155, the first field dispersion layer 177a, and the second field dispersion layer 177b may be covered by the third field dispersion layer 177c. The third field dispersion layer 177c may have a wider width than the second field dispersion layer 177b. The third field dispersion layer 177c may completely cover the second field dispersion layer 177b. However, this disclosure is not limited thereto, and the width and positional relationship of the first field dispersion layer 177a, the second field dispersion layer 177b, and the third field dispersion layer 177c can be changed in various ways. The third field dispersion layer 177c can be electrically connected to the source electrode 173. For example, the third field dispersion layer 177c can be connected to the upper source electrode 173c. The third field dispersion layer 177c can comprise the same material as the upper source electrode 173c and can be located in the same layer as the upper source electrode 173c. The third field dispersion layer 177c can be formed simultaneously with the upper source electrode 173c in the same process. The boundary between the third field dispersion layer 177c and the upper source electrode 173c is not clear, and the third field dispersion layer 177c can be integrally formed with the upper source electrode 173c. However, this disclosure is not limited thereto, and the third field dispersion layer 177c can be a separate element separate from the upper source electrode 173c. In addition, the third field dispersion layer 177c can be located in a different layer from the upper source electrode 173c and can be formed in different processes.

[0082] In some embodiments, at least one of the first field dispersion layer 177a, the second field dispersion layer 177b, or the third field dispersion layer 177c may be omitted. For example, a semiconductor device may include the first field dispersion layer 177a but exclude the second field dispersion layer 177b or the third field dispersion layer 177c. Alternatively, a semiconductor device may include the second field dispersion layer 177b but exclude the first field dispersion layer 177a or the third field dispersion layer 177c. Alternatively, a semiconductor device may exclude the first field dispersion layer 177a, the second field dispersion layer 177b, and the third field dispersion layer 177c.

[0083] Figure 4 yes Figure 2 An example enlarged cross-sectional view of part P.

[0084] because Figure 4 The illustrated implementation scheme has many similarities to Figure 3 The same parts are shown in the embodiments, so their description will be omitted, and the differences will be mainly explained. Additionally, the same reference numerals are used for the same components as in the previous embodiments.

[0085] refer to Figure 4 When etching the gate semiconductor layer 152, the length W_BS_156 of the lower surface BS_156 of the hard mask layer 156 in the second direction D2 can be reduced according to the etching conditions.

[0086] Therefore, in the cross-sectional view taken along the second direction D2 and the third direction D3 (e.g., Figure 4 In the process, the length W_BS_156 of the lower surface of the hard mask layer 156 in the second direction D2 can be smaller than the length W_US_155 of the upper surface of the gate electrode layer 155 in the second direction D2.

[0087] Figure 5 yes Figure 2 An example enlarged cross-sectional view of part P.

[0088] because Figure 5 The illustrated implementation scheme has many similarities to Figure 3 The same parts are shown in the embodiments, so their description will be omitted, and the differences will be mainly explained. Additionally, the same reference numerals are used for the same components as in the previous embodiments.

[0089] refer to Figure 5 When etching the gate semiconductor layer 152, the length W_US_155 of the upper surface US_155 of the gate electrode layer 155 in the second direction D2 and the length W_BS_155 of the lower surface BS_155 of the gate electrode layer 155 in the second direction D2 can be reduced according to the etching conditions.

[0090] A cross-sectional view taken along the second direction D2 and the third direction D3 (e.g., Figure 5 In the second direction D2, the length W_US_155 of the upper surface US_155 of the gate electrode layer 155 and the length W_BS_155 of the lower surface BS_155 of the gate electrode layer 155 in the second direction D2 can be smaller than the length W_BS_156 of the lower surface BS_156 of the hard mask layer 156 in the second direction D2 and the length W_US_152 of the upper surface US_152 of the gate semiconductor layer 152 in the second direction D2.

[0091] Furthermore, the length W_BS_155 of the lower surface BS_155 of the gate electrode layer 155 in the second direction D2 can be smaller than the length W_US_155 of the upper surface US_155 of the gate electrode layer 155 in the second direction D2. Therefore, in a cross-sectional view taken along the second direction D2 and the third direction D3 (e.g., Figure 3 In the process, the gate electrode layer 155 can have an inverted trapezoidal shape.

[0092] As described above, when the gate semiconductor layer 152 is etched, the hard mask layer 156 is partially etched according to the etching conditions, and the edges formed by the upper surface US_156 and the side surface SW_156 and the edges formed by the lower surface BS_156 and the side surface SW_156 in the hard mask layer 156 can have rounded shapes.

[0093] A cross-sectional view taken along the second direction D2 and the third direction D3 (e.g., Figure 5 In the hard mask layer 156, the edge formed by the lower surface BS_156 and the side surface SW_156 can have a rounded shape. In other words, the edge formed by the lower surface BS_156 and the side surface SW_156 of the hard mask layer 156 can not have an angular shape, but can have a beveled rounded shape, for example, it can have curvature.

[0094] The angle θ_156B formed between the lower surface BS_156 and the side surface SW_156 of the hard mask layer 156 can decrease as the distance from the lower surface BS_156 of the hard mask layer 156 in the third direction (D3) increases. In this paper, the angle θ_156B formed between the lower surface BS_156 and the side surface SW_156 of the hard mask layer 156 can be an interior angle formed between the tangent at a point on the side surface SW_156 and the lower surface BS_156.

[0095] As an example, the angle θ_156B formed between the lower surface BS_156 and the side surface SW_156 of the hard mask layer 156 can be greater than or equal to about 90°, for example, greater than or equal to about 90°, greater than or equal to about 95°, greater than or equal to about 100°, greater than or equal to about 105°, greater than or equal to 110°, or greater than or equal to 115°, and can be less than or equal to about 120°, for example, less than or equal to about 120°, less than or equal to about 115°, less than or equal to about 110°, less than or equal to about 105°, or less than or equal to about 100°, or less than or equal to about 95°, or less than or equal to about 90°, and can be from about 90° to about 120°.

[0096] The rounded shape of the edge formed by the upper surface US_156 and the side surface SW_156 of the hard mask layer 156 can be gentler than the rounded shape of the edge formed by the lower surface BS_156 and the side surface SW_156 of the hard mask layer 156, and the rounded shape of the edge formed by the bottom surface BS_156 and the side surface SW_156 of the hard mask layer 156 can be steeper than the rounded shape of the edge formed by the upper surface US_156 and the side surface SW_156 of the hard mask layer 156. In other words, the curvature of the edge formed by the upper surface US_156 and the side surface SW_156 of the hard mask layer 156 can be less than the curvature of the edge formed by the lower surface BS_156 and the side surface SW_156 of the hard mask layer 156.

[0097] Figure 6 yes Figure 2 An example enlarged cross-sectional view of part P.

[0098] because Figure 6 The illustrated implementation scheme has many similarities to Figure 5 The same parts are shown in the embodiments, so their description will be omitted, and the differences will be mainly explained. Additionally, the same reference numerals are used for the same components as in the previous embodiments.

[0099] exist Figure 5 In the etching process, based on the etching conditions when etching the gate semiconductor layer 152, the length W_BS_155 of the lower surface BS_155 of the gate electrode layer 155 in the second direction D2 is reduced by a greater amount than the length W_US_155 of the upper surface US_155 of the gate electrode layer 155 in the second direction D2. The length W_BS_155 is further reduced than the length W_US_155, and this reduction is further observed in cross-sectional views taken along the second direction D2 and the third direction D3 (e.g., Figure 5 In the diagram, the gate electrode layer 155 is shown to have an inverted trapezoidal shape. In this case, the distance W_M_155 between the midpoints of the two side surfaces SW_155 of the gate electrode layer 155 in the third direction D3 can be less than the length W_US_155 of the upper surface US_155 of the gate electrode layer 155 in the second direction D2, and can be greater than the length W_BS_155 of the lower surface BS_155 in the second direction D2.

[0100] refer to Figure 6 When the gate electrode layer 155 is etched, depending on the etching conditions, the two side surfaces SW_155 of the gate electrode layer 155 have concave shapes facing the gate electrode layer 155.

[0101] Therefore, the distance W_M_155 between the midpoints of the two side surfaces SW_155 of the gate electrode layer 155 in the third direction D3 in the second direction can be less than the length W_US_155 of the upper surface US_155 of the gate electrode layer 155 in the second direction D2 and the length W_BS_155 of the lower surface BS_155 in the second direction D2 in the second direction D2.

[0102] For example, the length of the gate electrode layer 155 in the second direction (D2) can decrease approximately from the upper surface (US_155) of the gate electrode layer 155 toward the midpoint of the third direction (D3) in the third direction (D3), and then after having a minimum value near the midpoint of the third direction (D3), it can increase approximately from the midpoint of the third direction (D3) to the lower surface (BS_155).

[0103] Figure 7 yes Figure 2 An example enlarged cross-sectional view of part P.

[0104] because Figure 7 The illustrated implementation scheme has many similarities to Figure 6 The same parts are shown in the embodiments, so their description will be omitted, and the differences will be mainly explained. Additionally, the same reference numerals are used for the same components as in the previous embodiments.

[0105] exist Figure 6 In the second direction D2, the distance W_M_155 between the midpoints of the two side surfaces SW_155 of the gate electrode layer 155 in the third direction D3 can be less than the length W_US_155 of the upper surface US_155 and the length W_BS_155 of the lower surface BS_155 in the second direction D2 of the gate electrode layer 155. However, the lengths W_US_155 of the upper surface US_155 and the lower surface BS_155 in the second direction D2 of the gate electrode layer 155 are shown to be approximately the same.

[0106] refer to Figure 7 The distance W_M_155 between the midpoints of the two side surfaces SW_155 of the gate electrode layer 155 in the third direction D3, in the second direction D2, can be less than the length W_US_155 of the upper surface US_155 of the gate electrode layer 155 in the second direction D2 and the length W_BS_155 of the lower surface BS_155 of the gate electrode layer 155 in the second direction D2. The length W_US_155 of the upper surface US_155 of the gate electrode layer 155 in the second direction D2 can be less than the length W_BS_155 of the lower surface BS_155 of the gate electrode layer 155 in the second direction D2. Figure 7It is shown that the length W_BS_155 of the lower surface of the gate electrode layer 155 in the second direction D2 is greater than the lengths W_BS_156 of both the upper surface US_156 and the lower surface BS_156 of the hard mask layer 156, but this is illustrative. As another example, in the second direction D2, the length W_BS_155 of the lower surface of the gate electrode layer 155 may be less than the lengths W_US_156 of both the upper surface US_156 and the lower surface BS_156 of the hard mask layer 156.

[0107] Next, we will refer to Figures 8 to 14 A method for manufacturing a semiconductor device according to an embodiment is described. Alternatively, refer to the description above. Figures 1 to 3 .

[0108] Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 and Figure 14 This is a cross-sectional view illustrating an example of a semiconductor device manufacturing method according to the process sequence.

[0109] refer to Figure 8 A seed layer 115, a buffer layer 120, a channel layer 132, and a barrier layer 136 can be sequentially formed on the substrate 110. In addition, a gate semiconductor material layer 152_L, a gate electrode material layer 155_L, and a hard mask material layer 156_L can be sequentially formed on the barrier layer 136.

[0110] A seed layer 115, a buffer layer 120, a channel layer 132, a barrier layer 136, and a gate semiconductor material layer 152_L can be sequentially formed using epitaxial growth. The seed layer 115 can be formed first on a substrate 110, and the buffer layer 120 can be formed on the seed layer 115. The buffer layer 120 may include a superlattice layer and a high-resistivity layer. The channel layer 132 can be formed on the buffer layer 120, the barrier layer 136 can be formed on the channel layer 132, and the gate semiconductor material layer 152_L can be formed on the barrier layer 136.

[0111] Seed layer 115, buffer layer 120, channel layer 132, barrier layer 136, and gate semiconductor material layer 152_L can be made of the same semiconductor material. However, considering the function of each layer and the performance required by the semiconductor device, the material composition ratio of each layer can be different.

[0112] For example, substrate 110 comprises Si, seed layer 115 comprises AlN, and the superlattice layer of buffer layer 120 has a structure of repeated stacking of layers made of AlGaN and layers made of GaN. The high-resistivity layer of buffer layer 120 may comprise GaN, channel layer 132 may comprise GaN, and barrier layer 136 may comprise AlGaN. Channel layer 132 and barrier layer 136 may be doped with impurities or not. Gate semiconductor material layer 152_L may comprise GaN and may be doped with impurities. Gate semiconductor material layer 152_L may be doped with p-type impurities, such as magnesium (Mg).

[0113] Because Si and GaN have different crystal structures, it may not be easy to grow a channel layer 132 made of GaN directly on a substrate 110 made of Si. Therefore, by first forming a seed layer 115 or a buffer layer 120 on the substrate 110 and then forming the channel layer 132, the crystal structure of the channel layer 132 can be stably formed.

[0114] A gate electrode material layer 155_L can be formed on the gate semiconductor material layer 152_L. In other words, the gate semiconductor material layer 152_L is located between the barrier layer 136 and the gate electrode material layer 155_L.

[0115] As an example, a deposition process can be used to form the gate electrode material layer 155_L. For example, electron beam evaporation (E-beam evaporation), sputtering, physical vapor deposition (PVD), thermal chemical vapor deposition (thermal CVD), low-pressure chemical vapor deposition (LP-CVD), plasma-enhanced chemical vapor deposition (PE-CVD), or atomic layer deposition (ALD) can be used to form the gate electrode material layer 155_L, but it is not limited to these.

[0116] A hard mask material layer 156_L can be formed on the gate electrode material layer 155_L.

[0117] As an example, the hard mask material layer 156_L can be a spin-coated hard mask layer (SOH). The spin-coated hard mask material layer can be formed on the gate electrode material layer 155_L by a spin coating process.

[0118] The hard mask material layer 156_L may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0119] refer to Figure 9 A photoresist pattern PR can be formed on the hard mask material layer 156_L.

[0120] First, a photoresist composition is coated onto the hard mask material layer 156_L to form a photoresist film. As an example, the photoresist composition can be applied to the hard mask material layer 156_L by spin coating, spraying, dip coating, or knife edge coating, or by a printing method such as inkjet printing or screen printing, and then the applied photoresist composition is dried to form a photoresist film. That is, a photoresist film can be formed by coating the hard mask material layer 156_L with a photoresist composition and then curing it through a heat treatment process.

[0121] Next, a first baking process can be performed on the substrate 110 on which the photoresist film is formed. The first baking process can be performed at a temperature of about 80°C to about 180°C for about 30 seconds to about 3 minutes.

[0122] Next, the photoresist film is selectively exposed.

[0123] Examples of light that can be used in exposure processes include light with short wavelengths, such as activated i-line radiation (wavelength 365 nm), KrF excimer laser (wavelength 248 nm), and ArF excimer laser (wavelength 193 nm), as well as light with high-energy wavelengths, such as EUV (extreme ultraviolet light; wavelength 13.5 nm) or E-beam (e-book). For example, the light used for exposure can be short-wavelength light with a wavelength range of approximately 5 nm to approximately 150 nm, and can also be light with high-energy wavelengths, such as EUV or E-beam.

[0124] Because polymers are formed through cross-linking reactions such as condensation between organometallic compounds, the exposed areas of the photoresist film have different solubilities than the unexposed areas.

[0125] Subsequently, a second baking process can be performed on the substrate 110. The second baking process can be performed at a temperature of approximately 120°C to approximately 200°C for approximately 30 seconds to approximately 3 minutes. By performing the second baking process, the exposed areas of the photoresist film become less soluble in the developer.

[0126] Next, a photoresist pattern (PR) is formed by dissolving and removing the photoresist film corresponding to the unexposed areas using a developer. For example, a photoresist pattern (PR) corresponding to a negative-toned image is completed by dissolving the photoresist film corresponding to the unexposed areas using an organic solvent (such as 2-heptanone) and then removing it.

[0127] refer to Figure 10 and Figure 11The hard mask material layer 156_L and the gate electrode material layer 155_L are etched using a photoresist pattern PR to form the hard mask layer 156 and the gate electrode layer 155.

[0128] For example, the hard mask material layer 156_L and the gate electrode material layer 155_L can be etched by dry etching using a first etching gas. The first etching gas may include a fluoride gas, and the fluoride gas may include, for example, CHF3, CF4, or a mixture thereof.

[0129] At this point, the hard mask material layer 156_L and the gate electrode material layer 155_L can be etched sequentially. Alternatively, the hard mask material layer 156_L can be etched first, and then the gate electrode material layer 155_L can be etched. In this case, the same first etching gas can be used to perform the etching of the hard mask material layer 156_L and the gate electrode material layer 155_L.

[0130] In this way, since the gate electrode layer 155 is formed using a photoresist pattern PR and the gate semiconductor layer 152 is formed using a hard mask layer 156 as described later, the gate electrode layer 155 can be etched with a first etch gas and the gate semiconductor layer 152 can be etched with a second etch gas, thereby increasing the freedom to select the etch materials for the gate electrode layer 155 and the gate semiconductor layer 152.

[0131] However, when the gate electrode layer 155 is etched with the first etching gas and the gate semiconductor layer 152 is etched with the second etching gas, the byproducts generated when the gate electrode layer 155 is etched with the first etching gas may have an effect and cause defects when the gate semiconductor layer 152 is etched with the second etching gas.

[0132] refer to Figure 12 After etching the gate electrode layer 155 with the first etching gas and before etching the gate semiconductor layer 152 with the second etching gas, the byproducts generated during the etching of the gate electrode layer 155 with the first etching gas can be removed. Therefore, the defect problem caused by byproducts resulting from etching different materials of the gate electrode layer 155 and the gate semiconductor layer 152 with different etching materials can be solved.

[0133] In this process, the photoresist pattern (PR) can be removed simultaneously.

[0134] For example, the removal of byproducts or the removal of the photoresist pattern PR can be accomplished by ashing or stripping processes. In some embodiments, the ashing and stripping processes can be performed sequentially. That is, an ashing process can be performed to remove the top of the photoresist pattern PR by an oxygen (O2) plasma treatment process or an ozone (O3) treatment process, and then a stripping process can be performed.

[0135] In some implementations, the process for cleaning the substrate 110 can be performed separately from the ashing or stripping process for removing the photoresist pattern PR.

[0136] As an example, the cleaning process may include a dry cleaning process using, for example, NH3 gas, NF3 gas, or NF3 plasma, or a wet cleaning process using HF or BOE. Subsequently, a cleaning solution such as ammonia (NH4OH) may be used to clean the substrate 110.

[0137] refer to Figure 13 The gate semiconductor material layer 152_L is etched using a hard mask layer 156 to form the gate semiconductor layer 152.

[0138] As an example, a hard mask layer 156 can be used to pattern the gate semiconductor material layer 152_L. Therefore, the gate semiconductor layer 152 can have a pattern similar to that of the gate electrode layer 155. In other words, the gate semiconductor layer 152 and the gate electrode layer 155 can be self-aligned, thus making alignment between the gate electrode layer 155 and the gate semiconductor layer 152 easy and efficient. Because the hard mask layer 156 has less loss compared to the photoresist pattern PR, the pattern of the gate semiconductor layer 152 is precise.

[0139] As an example, the gate semiconductor material layer 152_L can be etched by dry etching using a second etching gas. The second etching gas is different from the first etching gas and may include a chloride gas. For example, the chloride gas may include Cl2, BCl3, or a mixture thereof.

[0140] To minimize damage to the barrier layer 136 during the etching process of the gate semiconductor material layer 152_L, selective etching process conditions may be required to create an etching rate difference between the gate semiconductor material layer 152_L and the barrier layer 136. For example, the barrier layer 136, made of AlGaN, may be difficult to etch, while the gate semiconductor material layer 152_L, made of p-GaN, may be easily etched. In this case, a surface oxidation etching method can be used by adding oxygen (O2) to the etching gas. Therefore, when the barrier layer 136 is not damaged and has a predetermined thickness, the channel layer 132 can have a high current density.

[0141] At this time, according to the etching conditions during the etching of the gate semiconductor layer 152, the hard mask layer 156 is partially etched, and the hard mask layer 156 can have a rounded shape at the corners formed by the top surface US_156 and the side surface SW_156. Because the edges of the hard mask layer 156 have a rounded shape, the angle θ_177a formed by the lower surface BS_177a1 of the landing portion 177a1 of the first field dispersion layer 177a and the lower surface BS_177a3 of the connecting portion 177a3 can be adjusted, and the generation of voids can be prevented when forming the first field dispersion layer 177a.

[0142] refer to Figure 14 A first protective layer 140 can be formed on the barrier layer 136, the gate semiconductor layer 152, and the gate electrode layer 155. The first protective layer 140 can be formed using a deposition process. The first protective layer 140 may include an insulating material. For example, the first protective layer 140 may include materials such as SiO2, SiN, SiON, or Al2O3. The first protective layer 140 is shown as a single layer, but in some cases it may consist of multiple layers. In this case, the first protective layer 140 can be formed by sequentially depositing different materials. Alternatively, by using the same material and changing the deposition conditions, the first protective layer 140 can be formed from several layers with different properties. Specifically, the portion of the first protective layer 140 adjacent to the barrier layer 136 can be made of an insulating material of higher quality than the other portions. This is to prevent electrons forming the channel from being trapped in the channel layer 132 below the barrier layer 136. The portion of the first protective layer 140 in contact with the barrier layer 136 can be made of SiO2.

[0143] Next, the first protective layer 140 is patterned to form trenches, and a source electrode 173 and a drain electrode 175 can be formed within the trenches. During the trench formation process, not only the first protective layer 140 can be patterned, but the barrier layer 136 and the channel layer 132 can also be patterned together. Furthermore, a field dispersion layer 177 can be formed together with the source electrode 173 and the drain electrode 175 during the formation process.

[0144] The source electrode 173 and drain electrode 175 can have ohmic contact with the channel layer 132. The regions within the channel layer 132 that contact the source electrode 173 and drain electrode 175 can be doped at a relatively high concentration compared to other regions. For example, the channel layer 132 can be doped using ion implantation, annealing, or other processes. However, it is not limited to these methods, and the doping process of the channel layer 132 can be performed using various other processes. The doping process of the channel layer 132 can be performed before the formation of the source electrode 173 and drain electrode 175. In some cases, the channel layer 132 may not be doped.

[0145] Within the channel layer 132, a two-dimensional electron gas 134 can be formed in the portion adjacent to the barrier layer 136. The two-dimensional electron gas 134 can be located at the interface between the channel layer 132 and the barrier layer 136. The two-dimensional electron gas 134 can be located in the drift region DTR between the source electrode 173 and the drain electrode 175. A depletion region DPR can be formed in the channel layer 132 using a gate semiconductor layer 152 with a different bandgap than the barrier layer 136. Therefore, the semiconductor device can have normally-off characteristics. That is, the semiconductor device can be a normally-off high electron mobility transistor (HEMT). In the gate-off state, the two-dimensional electron gas 134 can be located in the drift region DTR, excluding the depletion region DPR of the channel layer 132. In the gate-on state, the two-dimensional electron gas 134 continues to flow within the depletion region DPR, and the two-dimensional electron gas 134 can be completely located within the drift region DTR.

[0146] While this specification contains numerous details of specific embodiments, these should not be construed as limiting the scope of any invention or the scope that may be claimed, but rather as descriptions of features that may be characteristic of particular embodiments of a particular invention. Specific features described in the context of different embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in a single embodiment may also be implemented individually in multiple embodiments or in any suitable sub-combination. Furthermore, although features may be described above as functioning in a particular combination, in some cases, one or more features from the combination may be removed from that combination, and the combination may be for sub-combinations or variations thereof.

[0147] While this disclosure has been described in conjunction with what are now considered to be practical embodiments, it should be understood that this disclosure is not limited to the disclosed embodiments, but rather is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: Channel layer, A barrier layer, located on the channel layer, comprising a material having a band gap different from that of the channel layer. A gate electrode layer is located on the barrier layer and extends in a first direction parallel to the upper surface of the barrier layer. A gate semiconductor layer, the gate semiconductor layer being located between the barrier layer and the gate electrode layer, and A source electrode and a drain electrode are connected to the channel layer and spaced apart from the gate electrode layer in a second direction, which is parallel to the upper surface of the barrier layer and intersects the first direction. In a cross-section taken along the second direction and a third direction perpendicular to the upper surface of the barrier layer, the angle formed by the lower surface and side surface of the gate electrode layer is greater than the angle formed by the lower surface and side surface of the gate semiconductor layer.

2. The semiconductor device according to claim 1, wherein, In the cross-section taken along the second direction and the third direction, The angle formed between the lower surface and the side surface of the gate electrode layer is 60° to 90°, and The angle formed between the lower surface and the side surface of the gate semiconductor layer is 30° to 89°.

3. The semiconductor device according to claim 1, wherein, The length of the upper surface of the gate electrode layer in the second direction is less than the length of the lower surface of the gate electrode layer in the second direction.

4. The semiconductor device according to claim 1, wherein, The length of the upper surface of the gate semiconductor layer in the second direction is less than the length of the lower surface of the gate semiconductor layer in the second direction.

5. The semiconductor device according to claim 1, wherein, The length difference between the lower and upper surfaces of the gate electrode layer in the second direction is less than the length difference between the lower and upper surfaces of the gate semiconductor layer in the second direction.

6. The semiconductor device according to claim 1, wherein, The semiconductor device includes a hard mask layer located on the gate electrode layer, and In the cross-section taken along the second direction and the third direction, The edges formed by the upper and side surfaces of the hard mask layer have a rounded shape.

7. The semiconductor device according to claim 6, wherein, In the cross-section taken along the second direction and the third direction, As the distance from the upper surface of the hard mask layer in the third direction increases, the angle formed between the upper surface and the side surface of the hard mask layer decreases.

8. The semiconductor device according to claim 6, wherein, The ratio of the length of the upper surface of the hard mask layer in the second direction to the length of the lower surface of the hard mask layer in the second direction is 9:10 to 9:

12.

9. The semiconductor device according to claim 6, wherein, The length of the lower surface of the hard mask layer in the second direction is less than the length of the upper surface of the gate electrode layer in the second direction.

10. The semiconductor device according to claim 1, wherein, The semiconductor device further includes: A first protective layer, the first protective layer covering the barrier layer and the gate electrode layer, and A first field dispersion layer, located on the first protective layer, is connected to the source electrode and overlaps with the gate electrode layer in the third direction. The first field dispersion layer includes: The overlapping portion overlaps with the gate electrode layer in the third direction. The landing portion is located on both sides of the overlapping portion in the second direction, and is closer to the upper surface of the barrier layer in the third direction compared to the overlapping portion. The connecting portion connects the overlapping portion and the landing portion.

11. The semiconductor device according to claim 10, wherein, In the cross-section taken along the second direction and the third direction, The angle formed by the lower surface of the landing portion and the lower surface of the connecting portion is 90° to 150°.

12. A semiconductor device, the semiconductor device comprising: Channel layer, A barrier layer, located on the channel layer, comprising a material having a band gap different from that of the channel layer. A gate electrode layer is located on the barrier layer and extends in a first direction parallel to the upper surface of the barrier layer. A gate semiconductor layer, wherein the gate semiconductor layer is located between the barrier layer and the gate electrode layer. A hard mask layer, the hard mask layer being located on the gate electrode layer, and A source electrode and a drain electrode are connected to the channel layer and spaced apart from the gate electrode layer in a second direction, which is parallel to the upper surface of the barrier layer and intersects the first direction. Specifically, in a cross-section taken along the second direction and a third direction perpendicular to the upper surface of the barrier layer, The edges formed by the upper and side surfaces of the hard mask layer have a rounded shape, and The length of the lower surface of the gate electrode layer in the second direction is less than the length of the upper surface of the gate semiconductor layer in the second direction and the length of the lower surface of the hard mask layer in the second direction.

13. The semiconductor device according to claim 12, wherein, The edges formed by the lower surface and the side surface of the hard mask layer have a rounded shape.

14. The semiconductor device according to claim 13, wherein, In the cross-section taken along the second direction and the third direction, (i) The rounded shape of the edge formed by the upper surface and the side surface of the hard mask layer is gentler than the rounded shape of the edge formed by the lower surface and the side surface of the hard mask layer, or (ii) The rounded shape of the edge formed by the lower surface and the side surface of the hard mask layer is steeper than the rounded shape of the edge formed by the upper surface and the side surface of the hard mask layer.

15. The semiconductor device according to claim 13, wherein, The length of the upper surface of the hard mask layer in the second direction is less than the length of the lower surface of the hard mask layer in the second direction.

16. The semiconductor device according to claim 12, wherein, The length of the upper surface of the gate electrode layer in the second direction is greater than the length of the lower surface of the gate electrode layer in the second direction.

17. The semiconductor device according to claim 12, wherein, The distance between the midpoints of the two side surfaces of the gate electrode layer in the second direction is less than (i) the length of the upper surface of the gate electrode layer in the second direction and (ii) the length of the lower surface of the gate electrode layer in the second direction.

18. The semiconductor device according to claim 12, wherein, The distance between the midpoints of the two side surfaces of the gate electrode layer in the second direction is less than the length of the upper surface of the gate electrode layer in the second direction, and The length of the upper surface of the gate electrode layer in the second direction is less than the length of the lower surface of the gate electrode layer in the second direction.

19. A method for manufacturing a semiconductor device, the method comprising: A channel layer is formed on the substrate; A barrier layer is formed on the channel layer, the barrier layer comprising a material having a band gap different from that of the channel layer. A gate semiconductor material layer, a gate electrode material layer, and a hard mask material layer are sequentially formed on the barrier layer. A photoresist pattern is formed on the hard mask material layer. The hard mask material layer and the gate electrode material layer are then etched using the photoresist pattern and a first etching gas to form the hard mask layer and the gate electrode layer. Remove the photoresist pattern. The gate semiconductor layer is formed by etching the gate semiconductor material layer with a second etching gas different from the first etching gas using the hard mask layer, and A source electrode and a drain electrode are formed that are connected to the channel layer and spaced apart from the gate electrode layer.

20. The method according to claim 19, wherein, The first etching gas includes a fluoride gas, and The second etching gas includes chloride gas.

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