Semiconductor device structure and forming method thereof

Abstract

The invention particularly relates to a semiconductor device structure and a forming method thereof. According to the method, a part of a gate oxide layer is removed, and a first material epitaxial layer is exposed to serve as a cathode material of a heterojunction diode structure; a second material layer is formed, the part, formed on the exposed first material epitaxial layer, of the second material layer serves as an anode material of the heterojunction diode structure, and the part, formed on the gate oxide layer, of the second material layer serves as a gate electrode medium; and carrying out graphical processing on the second material layer to respectively form an anode electrode and a gate electrode. According to the embodiment of the invention, the heterojunction diode structure can be introduced into a part of cells in the semiconductor device structure under the condition that the cell structure and the size are not changed.

Description

Technical Field

[0001] This application relates to the field of semiconductor device design and manufacturing, and in particular to a semiconductor device structure and a method for forming the same. Background Technology

[0002] The body diode characteristic of metal-oxide-semiconductor field-effect transistors (MOSFETs) is one of the important performance parameters, significantly affecting the device's switching dynamics and reliability. In silicon carbide (SiC) MOSFETs, due to the wide bandgap of SiC material, the body diode voltage drop is much larger than that of silicon (Si) MOSFETs.

[0003] During the switching process of SiC MOSFET devices, especially in half-bridge topology applications, a short period of high freewheeling current occurs within the dead time. This means the body diode of the SiC MOSFET device experiences a large current. If the body diode characteristics are poor during this period, it will significantly impact system efficiency. Furthermore, due to the unique properties of SiC material, particularly the high density of stacking faults (SFs), the conduction of the body diode under high current in SiC MOSFET devices may also lead to reliability issues such as bipolar degradation. Therefore, improving the body diode characteristics of SiC MOSFET devices is crucial for the device's switching dynamics and reliability. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this application provides a semiconductor device structure and a method for forming the same.

[0005] In a first aspect, this application provides a method for forming a semiconductor device structure, the method comprising:

[0006] Different injection mask layers are sequentially formed on the first material epitaxial layer, and JFET region, P-well region, N+ region and P+ region are respectively formed on the first material epitaxial layer based on the different injection mask layers;

[0007] Forming a gate oxide layer;

[0008] Remove part of the gate oxide layer to expose the first material epitaxial layer as the cathode material of the heterojunction diode structure;

[0009] A second material layer is formed, wherein the second material layer formed on the exposed first material epitaxial layer serves as the anode material of the heterojunction diode structure, and the second material layer formed on the gate oxide layer serves as the gate electrode dielectric.

[0010] The second material layer is patterned to form the anode electrode and the gate electrode, respectively.

[0011] In one possible implementation of the first aspect described above, the method further includes:

[0012] Forming an insulating dielectric layer;

[0013] A source ohmic contact is formed on the surface of the first material epitaxial layer corresponding to the source region;

[0014] The insulating dielectric layer formed on the anode electrode is etched to expose the anode electrode;

[0015] A surface metal layer is formed, wherein the exposed anode electrode is connected to the source metal, the gate electrode is connected to the gate metal, and the source ohmic contact is connected to the source metal.

[0016] In one possible implementation of the first aspect described above, the first material is silicon carbide and the second material is polycrystalline silicon.

[0017] In one possible implementation of the first aspect described above, a dry etching process or a wet etching process or both are used to remove a portion of the gate oxide layer.

[0018] In one possible implementation of the first aspect described above, a thin film deposition process is used to form the second material layer.

[0019] In one possible implementation of the first aspect above, the method further includes: using an in-situ doping process or an ion diffusion process after the growth of the second material to dope the second material layer, so as to form the doped second material layer.

[0020] In one possible implementation of the first aspect above, the method further includes: annealing the interface between the second material and the first material.

[0021] In one possible implementation of the first aspect described above, a dry etching process or a wet etching process or both are used to etch the insulating dielectric layer corresponding to the source region, and a nickel secondary annealing process is used to form the source ohmic contact.

[0022] In one possible implementation of the first aspect described above, a dry etching process or a wet etching process or both are used to etch the insulating dielectric layer formed on the anode electrode.

[0023] Secondly, this application also provides a semiconductor device structure, which is formed according to the method described in the first aspect above.

[0024] This application introduces heterojunction diode (HJD) structures, such as polysilicon (Poly-Si) / SiC heterojunction diode structures, into some cells within a SiC MOSFET device, instead of integrating a metal / SiC Schottky barrier diode (SBD) in the device source. In this way, the body diode characteristics and reliability of the SiC MOSFET device can be improved without changing the cell structure or introducing additional surface-source Schottky metal processing. Attached Figure Description

[0025] Figure 1a and Figure 1b A flowchart illustrating a method for forming a semiconductor device structure according to some embodiments of this application is shown;

[0026] Figures 2a to 2h A schematic diagram of the process flow of a semiconductor device structure according to some embodiments of this application is shown;

[0027] Figure 3 A band structure diagram of a semiconductor device structure according to some embodiments of this application is shown; Detailed Implementation

[0028] Various exemplary embodiments, features, and aspects of this application will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0029] In the description of this application, it should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0030] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0031] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0032] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0033] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0034] Furthermore, to better illustrate this application, numerous specific details are provided in the following detailed description. Those skilled in the art should understand that this application can be implemented without certain specific details. In some instances, methods, means, components, and circuits well-known to those skilled in the art have not been described in detail in order to highlight the main points of this application.

[0035] The "body diode" characteristic of metal-oxide-semiconductor field-effect transistors (MOSFETs) is one of the important performance parameters, significantly impacting the device's switching dynamics and reliability. Specifically, a MOSFET device has a diode between its drain and source. Structurally, this diode is generated by the PN junction between the source (P-type body region) and drain (N-type epitaxial layer), hence the name "body diode." When the gate voltage is zero volt biased, if a positive voltage is applied between the source and drain, current will flow between them, exhibiting diode-like voltage-current characteristics. At this time, the device channel is not conductive; this diode characteristic is due to the body diode's turn-on capability. In SiC MOSFETs, due to the wide bandgap of SiC material, the body diode voltage drop is much larger than that of SiMOSFETs.

[0036] During the switching process of SiC MOSFET devices, especially in half-bridge topology applications, a short period of high freewheeling current occurs within the dead time. This means the body diode of the SiC MOSFET device experiences a large current. If the body diode characteristics are poor during this period, it will significantly impact system efficiency. Furthermore, due to the unique properties of SiC material, particularly the high density of stacking defects, the conduction of the body diode under high current in SiC MOSFET devices may also lead to reliability issues such as bipolar degradation. Therefore, improving the characteristics of the body diode in SiC MOSFET devices is crucial for the device's switching dynamics and reliability.

[0037] To improve the body diode characteristics of SiC MOSFETs, one approach is to integrate a Schottky diode within the body region of the SiC MOSFET device. This approach has two drawbacks. First, integrating the Schottky diode within the device body region increases the lateral cell pitch, affecting the device's conduction characteristics. Second, to simultaneously form both ohmic and Schottky contacts in the source region, the device fabrication process requires additional photolithography and processing steps, increasing complexity and impacting yield.

[0038] Based on this, this application introduces heterojunction diode structures, such as Poly-Si / SiC heterojunction diode structures, into some cells inside the SiC MOSFET device, instead of integrating metal / SiC Schottky diodes in the device source. In this way, the body diode characteristics and reliability of the SiC MOSFET device can be improved without changing the cell structure or introducing additional surface source Schottky metal processing.

[0039] Figure 1a A flowchart illustrating a method for forming a semiconductor device structure according to some embodiments of this application is shown.

[0040] like Figure 1a As shown, the forming method includes:

[0041] Step 101: Different implantation mask layers are sequentially formed on the first material epitaxial layer, and JFET region, P-well region, N+ region and P+ region are formed on the first material epitaxial layer based on the different implantation mask layers.

[0042] Step 102: Form the gate oxide layer;

[0043] Step 103: Remove part of the gate oxide layer to expose the first material epitaxial layer as the cathode material of the heterojunction diode structure;

[0044] Step 104: Form a second material layer, wherein the second material layer formed on the exposed first material epitaxial layer serves as the anode material of the heterojunction diode structure, and the second material layer formed on the gate oxide layer serves as the gate electrode dielectric.

[0045] Step 105: The second material layer is patterned to form the anode electrode and the gate electrode, respectively.

[0046] According to steps 101 to 105 in this embodiment, a heterojunction diode structure can be introduced into a portion of the cells inside the semiconductor device structure without changing the cell structure and size.

[0047] Figures 2a to 2h A schematic diagram of the process flow of a semiconductor device structure according to some embodiments of this application is shown.

[0048] In one example, such as Figure 2a As shown, a substrate 201 for a semiconductor device structure can be prepared first, and then a first material epitaxial layer 202 can be grown on the substrate 201. The first material epitaxial layer 202 can be a SiC epitaxial layer 202. For ease of explanation, the following description uses SiC epitaxial layer, but those skilled in the art will understand that the embodiments of this application can also be applied to epitaxial layers of other materials. Furthermore, the first material epitaxial layer 202 can be an N-type doped SiC epitaxial layer 202.

[0049] In one example, such as Figure 2a As shown, different implantation mask layers can be sequentially formed on the SiC epitaxial layer 202 according to step 101, and JFET regions, P-well regions, N+ regions, and P+ regions can be formed on the SiC epitaxial layer 202 based on different implantation mask layers. The specific type of implantation mask layer is not limited in this embodiment; for example, the implantation mask layer can be photoresist or a hard mask. The specific implementation method for forming each region is not limited in this embodiment; for example, a JFET region can be formed by JFET implantation, a P-well region can be formed by P-type ion implantation, an N+ region can be formed by high-concentration N-type ion implantation, and a P+ region can be formed by high-concentration P-type ion implantation. Subsequently, high-temperature annealing can be performed to activate the implanted ions.

[0050] In one example, such as Figure 2a As shown, the gate oxide layer 203 can be formed according to step 102. The specific implementation of forming the gate oxide layer 203 is not limited in this application embodiment. For example, processes including thermal oxidation, dielectric deposition, or both can be used to form the gate oxide layer 203.

[0051] In one example, such as Figure 2b As shown, a portion of the gate oxide layer 203 can be removed according to step 103, exposing the SiC epitaxial layer 202 as the cathode material of the heterojunction diode structure. For example, a dry etching process or a wet etching process, or both, can be used to remove a portion of the gate oxide layer 203.

[0052] In one example, such as Figure 2c As shown, a second material layer 204 can be formed according to step 104. More specifically, a thin-film deposition process can be used to form the second material layer 204. The second material layer 204 formed on the exposed SiC epitaxial layer 202 serves as the anode material of the heterojunction diode structure, and the second material layer 204 formed on the gate oxide layer 203 serves as the gate electrode dielectric. The second material layer 204 can be a Poly-Si layer 204, and when the first material epitaxial layer 202 is a SiC epitaxial layer 202, the heterojunction diode structure can be a Poly-Si / SiC heterojunction diode structure. For ease of explanation, the following description uses Poly-Si layer and Poly-Si / SiC heterojunction diode structures, but those skilled in the art will understand that embodiments of this application can also introduce heterojunction diodes of other materials into some cells inside the SiC MOSFET device.

[0053] In one example, the Poly-Si layer 204 can be doped using an in-situ doping process or an ion diffusion process after Poly-Si growth to form a doped Poly-Si layer 204. For example, an in-situ doping process can be used to dope the Poly-Si layer 204 to form a doped Poly-Si layer 204 (such as P-type or N-type doped). As another example, an ion diffusion process can be used to dope the Poly-Si layer 204 after Poly-Si growth to form a doped Poly-Si layer 204 (such as P-type or N-type doped). Specifically, using boron ion diffusion to dope the Poly-Si layer 204 can form a P-type doped Poly-Si layer 204, and using phosphorus ion diffusion to dope the Poly-Si layer 204 can form an N-type doped Poly-Si layer 204. For example, the doping process can be saturation doping. Both the P-type doped Poly-Si layer 204 and the N-type doped Poly-Si layer 204 can form a Poly-Si / SiC heterojunction diode structure with the SiC epitaxial layer 202. However, in terms of device leakage current characteristics, the P-type doped Poly-Si layer 204 has better blocking characteristics.

[0054] In one example, the Poly-Si / SiC interface can be annealed. For instance, the doped Poly-Si layer 204 can be annealed or the Poly-Si / SiC interface can be annealed using the thermal process during doping to form a well-contact Poly-Si / SiC heterojunction diode structure.

[0055] In one example, such as Figure 2d As shown, the Poly-Si layer 204 can be patterned according to step 105 to form the anode electrode 205 and the gate electrode 206, respectively. For example, a dry etching process can be used to pattern the doped Poly-Si layer 204, etching to form the patterns of the anode electrode 205 and the gate electrode 206, and the Poly-Si layers 204 of different cells can be connected in series by polycrystalline line etching and inter-elongation. As will be described below, the Poly-Si layers 204 of cell 301 are interconnected and eventually connected to the source of the device, and the Poly-Si layers 204 of cell 302 are interconnected and eventually connected to the gate of the device.

[0056] Figure 1b A flowchart illustrating a method for forming a semiconductor device structure according to some embodiments of this application is shown.

[0057] like Figure 1b As shown, the forming method further includes:

[0058] Step 106: Form an insulating dielectric layer;

[0059] Step 107: Form a source ohmic contact on the surface of the first material epitaxial layer corresponding to the source region;

[0060] Step 108: Etch the insulating dielectric layer formed on the anode electrode to expose the anode electrode;

[0061] Step 109: Form a surface metal layer, wherein the exposed anode electrode is connected to the source metal, the gate electrode is connected to the gate metal, and the source ohmic contact is connected to the source metal.

[0062] In one example, such as Figure 2e As shown, an insulating dielectric layer 207 is formed according to step 107. The specific implementation of forming the insulating dielectric layer 207 is not limited in this application embodiment. For example, an ILD process including ILD deposition and ILD patterning can be used to form the insulating dielectric layer 207.

[0063] In one example, such as Figure 2fAs shown, according to step 108, a source ohmic contact 208 is formed on the surface of the SiC epitaxial layer 202 corresponding to the source region. For example, the insulating dielectric layer 207 corresponding to the source region can be etched using a dry etching process or a wet etching process or both, and the source ohmic contact 208 can be formed using a nickel secondary annealing process.

[0064] In one example, such as Figure 2g As shown, the insulating dielectric layer 207 formed on the anode electrode 205 is etched according to step 109 to expose the anode electrode 205. For example, a dry etching process or a wet etching process or both can be used to etch the insulating dielectric layer 207 formed on the anode electrode 205.

[0065] In one example, such as Figure 2h As shown, a surface metal layer 209 is formed according to step 110, wherein the exposed anode electrode 205 is connected to the source metal, the gate electrode 206 is connected to the gate metal (not shown) through a layout, and the source ohmic contact 208 is connected to the source metal. The specific implementation of forming the surface metal layer 209 is not limited in this application embodiment; for example, surface metal deposition and etching processes can be used to form the surface metal layer 209.

[0066] This application implements, for example Figures 2a to 2h As shown, a heterojunction diode structure can be introduced into a portion of the cells 301 inside the semiconductor device structure without changing the cell structure and size, while the MOS structure of the remaining cells 302 remains unchanged.

[0067] The embodiments of this application also relate to semiconductor device structures formed according to the above-described forming method, such as planar semiconductor device structures, and more specifically, planar SiC MOSFET device structures.

[0068] Figure 3 A band structure diagram of a semiconductor device structure according to some embodiments of this application is shown.

[0069] A heterojunction is introduced in a portion of the cell 301 within the semiconductor device structure. The anode material is P-type saturated doped Poly-Si, and the cathode material is N-type doped SiC epitaxially to form a P-type heterojunction. + -Poly-Si / N - In the case of a SiC heterojunction, the band structure at the vertical dashed line of the heterojunction when no external voltage is applied is as follows: Figure 3 As shown, distance 0 refers to the boundary between Poly-Si and SiC. Moving from this boundary towards Poly-Si results in a negative distance, while moving from this boundary towards SiC results in a positive distance. Figure 3As can be seen, the heterojunction exhibits diode characteristics, which means that it can replace the body diode of a semiconductor device under certain conditions. This solves the problems of poor body diode characteristics that significantly affect system efficiency and cause bipolar degradation, and is crucial to the switching dynamic characteristics and reliability of the device.

[0070] It is understood that the various method embodiments mentioned above in this application can be combined with each other to form combined embodiments without violating the principle and logic. Due to space limitations, this application will not elaborate further. Those skilled in the art will understand that in the above methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0071] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for forming a semiconductor device structure, characterized in that, The method includes: Different injection mask layers are sequentially formed on the first material epitaxial layer, and JFET region, P-well region, N+ region and P+ region are respectively formed on the first material epitaxial layer based on the different injection mask layers; Forming a gate oxide layer; Remove part of the gate oxide layer to expose the first material epitaxial layer as the cathode material of the heterojunction diode structure; A second material layer is formed, wherein the second material layer formed on the exposed first material epitaxial layer serves as the anode material of the heterojunction diode structure, and the second material layer formed on the gate oxide layer serves as the gate electrode dielectric. The second material layer is patterned to form the anode electrode and the gate electrode, respectively.

2. The method according to claim 1, characterized in that, The method further includes: Forming an insulating dielectric layer; A source ohmic contact is formed on the surface of the first material epitaxial layer corresponding to the source region; The insulating dielectric layer formed on the anode electrode is etched to expose the anode electrode; A surface metal layer is formed, wherein the exposed anode electrode is connected to the source metal, the gate electrode is connected to the gate metal, and the source ohmic contact is connected to the source metal.

3. The method according to claim 1 or 2, characterized in that, The first material is silicon carbide, and the second material is polycrystalline silicon.

4. The method according to claim 1 or 2, characterized in that, A portion of the gate oxide layer is removed using a dry etching process, a wet etching process, or both.

5. The method according to claim 1 or 2, characterized in that, The second material layer is formed using a thin film deposition process.

6. The method according to claim 1 or 2, characterized in that, The method further includes: using an in-situ doping process or an ion diffusion process after the growth of the second material to dope the second material layer, so as to form the doped second material layer.

7. The method according to claim 1, characterized in that, The method further includes annealing the interface between the second material and the first material.

8. The method according to claim 2, characterized in that, The insulating dielectric layer corresponding to the source region is etched using a dry etching process, a wet etching process, or both, and the source ohmic contact is formed using a nickel secondary annealing process.

9. The method according to claim 2, characterized in that, The insulating dielectric layer formed on the anode electrode is etched using a dry etching process, a wet etching process, or both.

10. A semiconductor device structure, characterized in that, The semiconductor device structure is formed by the method according to any one of claims 1-9.

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