Semiconductor device

Abstract

There is provided a semiconductor device including: a substrate; a lower power line disposed below the substrate; a source / drain pattern on the substrate; a channel pattern on a side surface of the source / drain pattern, including a plurality of semiconductor patterns stacked on each other; gate electrodes between the plurality of semiconductor patterns; a backside active contact penetrating the substrate to electrically connect the lower power line and the source / drain pattern; and a backside isolation structure penetrating the substrate and the backside active contact and disposed under the gate electrode. An uppermost surface of the backside active contact is located at a higher level than an uppermost surface of the backside isolation structure.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0063409, filed on May 14, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a semiconductor device, and more specifically, to a semiconductor device including a field-effect transistor. Background Technology

[0004] Semiconductor devices can include integrated circuits composed of metal-oxide-semiconductor field-effect transistors (MOSFETs). As the size and design rules of semiconductor devices decrease, MOSFETs can be miniaturized. However, as MOSFETs shrink, the operating characteristics of semiconductor devices may deteriorate. Summary of the Invention

[0005] This disclosure provides a semiconductor device with improved electrical properties.

[0006] The technical objectives of this invention are not limited to those described herein, and other technical objectives not mentioned will be clearly understood by those skilled in the art based on the following description.

[0007] An embodiment of the present invention provides a semiconductor device comprising: a substrate; a lower power line disposed below the substrate; a source / drain pattern on the substrate; a channel pattern on a side surface of the source / drain pattern, comprising a plurality of semiconductor patterns stacked on top of each other; a gate electrode between the plurality of semiconductor patterns; a back-side active contact penetrating the substrate to electrically connect the lower power line and the source / drain pattern; and a back-side isolation structure penetrating the substrate and the back-side active contact, and disposed below the gate electrode, wherein the uppermost surface of the back-side active contact is at a level higher than the uppermost surface of the back-side isolation structure.

[0008] In an embodiment of the present invention, a semiconductor device includes: a substrate; a plurality of semiconductor patterns horizontally spaced apart from each other on the substrate; a source / drain pattern including a first pattern and a second pattern respectively disposed between the plurality of semiconductor patterns; a gate electrode between the substrate and each of the plurality of semiconductor patterns; a gate insulating film surrounding the gate electrode; a back-side active contact disposed below the substrate and including a third pattern electrically connected to the first pattern and a fourth pattern separate from the second pattern; and a back-side isolation structure penetrating the substrate and the back-side active contact, wherein the back-side isolation structure includes a first back-side isolation structure, a second back-side isolation structure, and a third back-side isolation structure horizontally spaced apart from each other, and the third pattern is disposed between the first back-side isolation structure and the second back-side isolation structure, and the fourth pattern is disposed between the second back-side isolation structure and the third back-side isolation structure.

[0009] In an embodiment of the present invention, a semiconductor device includes: a substrate including an active pattern; a device isolation film on the substrate and defining the active pattern; a channel pattern and a source / drain pattern on the active pattern, the source / drain pattern including a first source / drain pattern and a second source / drain pattern horizontally spaced apart from each other; a gate electrode on the channel pattern; a gate insulating film between the gate electrode and the channel pattern; a gate spacer on the sidewall of the gate electrode; a gate capping pattern on the upper surface of the gate electrode; an interlayer insulating film covering the source / drain pattern and the gate capping pattern; and an active contact portion penetrating the interlayer insulating film to electrically connect to a first source / drain pattern. Source / drain pattern; metal-semiconductor compound layer, between upper active contact and first source / drain pattern; gate contact, penetrating interlayer insulating film and gate capping pattern to electrically connect to gate electrode; lower power line, disposed below substrate; back-side active contact, penetrating substrate to electrically connect lower power line and second source / drain pattern; and back-side isolation structure, penetrating substrate and back-side active contact, and disposed on gate insulating film, wherein the bottom surface of back-side isolation structure is coplanar with the bottom surface of back-side active contact and the upper surface of lower power line, and the upper surface of back-side isolation structure contacts the bottom surface of gate insulating film. Attached Figure Description

[0010] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings:

[0011] Figure 1 , Figure 2 and Figure 3 This is a conceptual diagram illustrating the logic units of a semiconductor device according to an embodiment of the present invention.

[0012] Figure 4A and Figure 4BIt is a plan view used to describe a semiconductor device according to an embodiment of the concept of the present invention;

[0013] Figures 5A to 5D They are along Figure 4A Cross-sectional views taken from lines A-A', B-B', C-C', and D-D';

[0014] Figure 6 It is shown Figure 5A A magnified view of region M;

[0015] Figure 7 It is used to describe according to Figure 5A A cross-sectional view of a semiconductor device according to another embodiment; and

[0016] Figure 8A and Figure 8B , Figure 9A and Figure 9B , Figures 10A to 10C , Figures 11A to 11C , Figures 12A to 12C , Figures 13A to 13D , Figures 14A to 14D , Figures 15A to 15D , Figures 16A to 16D and Figures 17A to 17D This is a diagram illustrating a method for manufacturing a semiconductor device according to some embodiments of the concept of the present invention. Detailed Implementation

[0017] In the following description, embodiments of the invention will be presented in more detail with reference to the accompanying drawings, in order to illustrate the inventive concept more specifically. The inventive concept can be implemented with various modifications and has various forms, and specific embodiments are shown in the drawings and described in detail in the text. However, it should be understood that the inventive concept is not intended to be limited to the specific forms disclosed, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the inventive concept.

[0018] Throughout the specification, the same reference numerals may denote the same elements. In the drawings, the thickness, scale, and dimensions of elements may be exaggerated to effectively describe the technical content.

[0019] Figure 1 , Figure 2 and Figure 3 This is a conceptual diagram used to describe the logic unit of a semiconductor device according to an embodiment of the present invention.

[0020] refer to Figure 1A single-height cell (SHC) can be provided. Specifically, a first lower power line VPR1 and a second lower power line VPR2 can be disposed below the substrate 100. The first lower power line VPR1 can be a path providing the source voltage VSS (e.g., ground voltage). The second lower power line VPR2 can be a path providing the drain voltage VDD (e.g., supply voltage).

[0021] A single-height cell SHC can be defined between a first lower power line VPR1 and a second lower power line VPR2. The single-height cell SHC may include a PMOSFET region PR and an NMOSFET region NR. In other words, the single-height cell SHC can have a structure in which a CMOS can be disposed between the first lower power line VPR1 and the second lower power line VPR2.

[0022] The PMOSFET region PR and the NMOSFET region NR can each have a first width in a first horizontal direction (i.e., first direction D1). The length of the single-height cell SHC in the first direction D1 can be defined as the first height HE1. The first height HE1 can be substantially the same as the distance (e.g., the pitch) between the first lower electric line VPR1 and the second lower electric line VPR2.

[0023] A single-height unit (SHC) can constitute a logic unit. In this specification, a logic unit can be a logic device that performs a specific function (e.g., AND, OR, XOR, XNOR, or an inverter). That is, a logic unit can include transistors used to construct the logic device, and lines connecting the transistors to each other.

[0024] refer to Figure 2 A dual-height cell (DHC) can be provided. Specifically, a first lower electric field line (VPR1), a second lower electric field line (VPR2), and a third lower electric field line (VPR3) can be disposed on the substrate 100. The second lower electric field line (VPR2) can be disposed between the first lower electric field line (VPR1) and the third lower electric field line (VPR3). The third lower electric field line (VPR3) can be a path that can provide the source voltage (VSS).

[0025] The dual-height cell (DHC) can be defined between the first lower electric line VPR1 and the third lower electric line VPR3. The dual-height cell (DHC) may include a first PMOSFET region PR1, a second PMOSFET region PR2, a first NMOSFET region NR1, and a second NMOSFET region NR2.

[0026] The first NMOSFET region NR1 can be adjacent to the first lower electric field line VPR1. The second NMOSFET region NR2 can be adjacent to the third lower electric field line VPR3. The first PMOSFET region PR1 and the second PMOSFET region PR2 can be adjacent to the second lower electric field line VPR2. In the plan view, the second lower electric field line VPR2 can be located between the first PMOSFET region PR1 and the second PMOSFET region PR2.

[0027] The length of the dual-height unit DHC in the first direction D1 can be defined as the second height HE2. The second height HE2 can be... Figure 1 The first height HE1 is approximately twice that of the second height. The first PMOSFET region PR1 and the second PMOSFET region PR2 of the dual-height cell DHC can operate together as a PMOSFET region. Therefore, the channel size of the PMOS transistor in the dual-height cell DHC can be larger than... Figure 1 The channel size of the PMOS transistor in the single-height cell SHC.

[0028] For example, the channel size of the PMOS transistor in a dual-height cell DHC can be approximately twice that of the PMOS transistor in a single-height cell SHC. Therefore, a dual-height cell DHC can operate faster than a single-height cell SHC. According to embodiments of the present invention, Figure 2 The dual-height unit DHC shown can be defined as a multi-height unit. Although not shown, a multi-height unit may include a tri-height unit, the unit height of which may be approximately three times the unit height of the single-height unit SHC.

[0029] refer to Figure 3 The first single-height cell SHC1, the second single-height cell SHC2, and the double-height cell DHC can be disposed two-dimensionally on the substrate 100. The first single-height cell SHC1 can be disposed between the first lower electric field line VPR1 and the second lower electric field line VPR2. The second single-height cell SHC2 can be disposed between the second lower electric field line VPR2 and the third lower electric field line VPR3. The second single-height cell SHC2 can be adjacent to the first single-height cell SHC1 in the first direction D1.

[0030] The dual-height unit DHC can be located between the first lower power line VPR1 and the third lower power line VPR3. The dual-height unit DHC can be adjacent to the first single-height unit SHC1 and the second single-height unit SHC2 in the second horizontal direction (i.e., the second direction D2 that intersects the first direction D1).

[0031] The isolation structure DB can be set between the first single-height unit SHC1 and the dual-height unit DHC, and between the second single-height unit SHC2 and the dual-height unit DHC. The active region of the dual-height unit DHC can be electrically isolated from the active regions of each of the first single-height unit SHC1 and the second single-height unit SHC2 through the isolation structure DB.

[0032] Figure 4A and Figure 4B It is a plan view used to describe an embodiment of a semiconductor device according to the concept of the present invention. Figure 4A This is a plan view of the front surface of a semiconductor device, and Figure 4B This is a back-side plan view of a semiconductor device. Figures 5A to 5D They are along Figure 4A Cross-sectional views taken from lines A-A', B-B', C-C', and D-D'. Figure 4A and Figure 4B as well as Figures 5A to 5D The semiconductor device shown is illustrated in more detail. Figure 3 The first single-height unit SHC1 and the second single-height unit SHC2.

[0033] refer to Figure 4A as well as Figures 5A to 5D The first single-height cell SHC1 and the second single-height cell SHC2 can be disposed on the substrate 100. Logic transistors constituting the logic circuit can be disposed on each of the first single-height cell SHC1 and the second single-height cell SHC2. The substrate 100 can be a semiconductor substrate including silicon, germanium, silicon-germanium, etc., or a compound semiconductor substrate. For example, the substrate 100 can be a silicon substrate. As another example, the substrate 100 can include a silicon-based insulating layer and can include a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. The lower power lines VPR1, VPR2, and VPR3 described herein can be disposed below the substrate 100.

[0034] The substrate 100 may have a first PMOSFET region PR1, a second PMOSFET region PR2, a first NMOSFET region NR1, and a second NMOSFET region NR2. The first PMOSFET region PR1, the second PMOSFET region PR2, the first NMOSFET region NR1, and the second NMOSFET region NR2 may each extend in a second direction D2. A first single-height unit SHC1 may include the first NMOSFET region NR1 and the first PMOSFET region PR1, and a second single-height unit SHC2 may include the second PMOSFET region PR2 and the second NMOSFET region NR2.

[0035] The first active pattern AP1 and the second active pattern AP2 can be defined by a trench TR formed on the substrate 100. The first active pattern AP1 can be disposed on each of the first PMOSFET region PR1 and the second PMOSFET region PR2. The second active pattern AP2 can be disposed on each of the first NMOSFET region NR1 and the second NMOSFET region NR2. The first active pattern AP1 and the second active pattern AP2 can extend in a second direction D2. The first active pattern AP1 and the second active pattern AP2 can be vertical protrusions that are part of the substrate 100.

[0036] The device isolation film ST can fill the trench TR. The device isolation film ST can cover the sidewalls of each of the first active pattern AP1 and the second active pattern AP2. The device isolation film ST can include a silicon oxide film. The device isolation film ST may not cover the first channel pattern CH1 and the second channel pattern CH2 described herein.

[0037] A first channel pattern CH1 may be disposed on a first active pattern AP1. A second channel pattern CH2 may be disposed on a second active pattern AP2. Each of the first channel pattern CH1 and the second channel pattern CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 stacked in sequence. The first to third semiconductor patterns SP1, SP2, and SP3 may be spaced apart from each other in the vertical direction (i.e., the third direction D3).

[0038] The first to third semiconductor patterns SP1, SP2, and SP3 may each comprise silicon (Si), germanium (Ge), or silicon-germanium (SiGe). For example, the first to third semiconductor patterns SP1, SP2, and SP3 may each comprise crystalline silicon. The first to third semiconductor patterns SP1, SP2, and SP3 may each be nanosheets.

[0039] Multiple first source / drain patterns SD1 can be disposed on the first active pattern AP1. Multiple first recesses RS1 can be formed on the first active pattern AP1. The first source / drain patterns SD1 can be disposed in the first recesses RS1 respectively (see...). Figure 10A The first source / drain pattern SD1 can be an impurity region having a first conductivity type (e.g., P-type). The first channel pattern CH1 can be located between a pair of first source / drain patterns SD1. In other words, the stacked first to third semiconductor patterns SP1, SP2, and SP3 can connect a pair of first source / drain patterns SD1 to each other.

[0040] Multiple second source / drain patterns SD2 can be set on the second active pattern AP2. Multiple second recesses RS2 (see...) Figure 10BA second source / drain pattern SD2 can be formed on a second active pattern AP2. A second source / drain pattern SD2 can be disposed in a second recess RS2. The second source / drain pattern SD2 can be an impurity region having a second conductivity type (e.g., N-type). A second channel pattern CH2 can be located between a pair of second source / drain patterns SD2. In other words, the stacked first to third semiconductor patterns SP1, SP2, and SP3 can connect a pair of second source / drain patterns SD2 to each other.

[0041] The first source / drain pattern SD1 and the second source / drain pattern SD2 can be epitaxial patterns formed in a selective epitaxial growth (SEG) process. For example, the upper surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be located at substantially the same level as the upper surface of the third semiconductor pattern SP3. As another example, the upper surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be located at a higher level than the upper surface of the third semiconductor pattern SP3.

[0042] The first source / drain pattern SD1 may include a semiconductor element (e.g., SiGe) having a larger lattice parameter than the semiconductor element of the first channel pattern CH1. Therefore, a pair of first source / drain patterns SD1 can provide compressive stress to the first channel pattern CH1 between them. The second source / drain pattern SD2 may include the same semiconductor element (e.g., Si) as the second channel pattern CH2.

[0043] Each of the first source / drain patterns SD1 may include a buffer layer BFL and a main layer MAL on the buffer layer BFL. (See reference) Figure 5A A buffer layer BFL may be disposed on at least a portion of the inner sidewall of the first recess RS1. The buffer layer BFL may cover the inner sidewall of the first recess RS1. A main layer MAL may be disposed on the buffer layer BFL in the region of the first recess RS1. The main layer MAL may fill the remaining region of the first recess RS1 formed after the formation of the buffer layer BFL. The volume of the main layer MAL may be larger than the volume of the buffer layer BFL. The main layer MAL and the buffer layer BFL may each comprise silicon-germanium (SiGe). Specifically, the buffer layer BFL may contain a relatively low concentration of germanium (Ge). In another embodiment of the present invention, the buffer layer BFL may comprise silicon (Si) and may not include germanium (Ge). The buffer layer BFL may have a germanium (Ge) concentration of 0 at% to about 30 at%.

[0044] The master layer MAL can contain a relatively high concentration of germanium (Ge). For example, the master layer MAL can have a germanium (Ge) concentration of about 30 at% to about 70 at%. The germanium (Ge) concentration of the master layer MAL can increase along the third direction D3. For example, the master layer MAL adjacent to the buffer layer BFL can have a germanium (Ge) concentration of about 40 at%, but the upper part of the master layer MAL can have a germanium (Ge) concentration of about 60 at%.

[0045] Each of the buffer layer BFL and the main layer MAL can include impurities (e.g., boron, gallium, or indium), which can result in the first source / drain pattern SD1 being p-type. The buffer layer BFL and the main layer MAL can each have approximately 1E18 atoms / cm². 3 Approximately 5E22 atoms / cm 3 The impurity concentration. The impurity concentration in the main layer MAL can be greater than the impurity concentration in the buffer layer BFL.

[0046] Although the second semiconductor layer SAL described herein is replaced by the first internal electrode PO1, the second internal electrode PO2, and the third internal electrode PO3 of the gate electrode GE, the buffer layer BFL protects the main layer MAL. In other words, the buffer layer BFL prevents the etching material used to remove the second semiconductor layer SAL from penetrating into and etching the main layer MAL.

[0047] The second source / drain pattern SD2 can each comprise silicon (Si). The second source / drain pattern SD2 can also include impurities (e.g., phosphorus, arsenic, or antimony), which can cause the second source / drain pattern SD2 to be N-type. The second source / drain pattern SD2 can have approximately 1E18 atoms / cm². 3 Approximately 5E22 atoms / cm 3 The concentration of impurities.

[0048] A gate electrode GE can be provided that intersects the first channel pattern CH1 and the second channel pattern CH2 and extends in the first direction D1. The gate electrodes GE can be spaced apart from each other and arranged at a first spacing in the second direction D2. The gate electrodes GE can also vertically overlap the first channel pattern CH1 and the second channel pattern CH2 in the third direction D3, respectively.

[0049] The gate electrode GE may include a first internal electrode PO1 located between the active pattern AP1 or AP2 and the first semiconductor pattern SP1, a second internal electrode PO2 located between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third internal electrode PO3 located between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and an external electrode PO4 on the third semiconductor pattern SP3. Although the gate electrode GE is shown as having four electrodes, the embodiment is not limited thereto. For example, the gate electrode GE may include fewer or more than four electrodes.

[0050] refer to Figure 5D The gate electrode GE can be disposed on the upper surface TS, the bottom surface BS, and the two sidewalls SW of each of the first to third semiconductor patterns SP1, SP2, and SP3. In other words, the transistor according to the embodiment can be a three-dimensional field-effect transistor (e.g., MBCFET or GAAFET), wherein the gate electrode GE can surround the channel in three dimensions.

[0051] Typically, the first single-height unit SHC1 may have a first boundary BD1 and a second boundary BD2 that are opposite to each other in the second direction D2. The first boundary BD1 and the second boundary BD2 may extend along the first direction D1. The first single-height unit SHC1 may have a third boundary BD3 and a fourth boundary BD4 that are opposite to each other in the first direction D1. The third boundary BD3 and the fourth boundary BD4 may extend along the second direction D2.

[0052] A gate diced pattern CT can be disposed along a second direction D2 on the boundary of each of the first single-height cells SHC1 and the second single-height cells SHC2. For example, the gate diced pattern CT can be disposed on the third boundary BD3 and the fourth boundary BD4 of the first single-height cell SHC1. At least some gate diced patterns CT can be spaced apart from each other in the second direction D2 and arranged with a first pitch along the third boundary BD3. The pitch of the gate diced patterns CT in the second direction D2 can be the same as the pitch of the gate electrode GE. Furthermore, the gate diced patterns CT disposed on the third boundary BD3 can also be disposed on the boundary of the second single-height cell SHC2. For example, some gate diced patterns can be disposed on adjacent boundaries of the first single-height cells SHC1 and the second single-height cells SHC2. Other gate diced patterns CT can be spaced apart from each other and arranged with a first pitch along the fourth boundary BD4. In a plan view, the gate diced patterns CT on the third boundary BD3 and the fourth boundary BD4 can be arranged to overlap with the gate electrode GE, respectively. The gate diced pattern CT can include an insulating material, such as a silicon oxide film, a silicon nitride film, or a combination thereof.

[0053] The gate electrode GE on the first single-height unit SHC1 and the gate electrode GE on the second single-height unit SHC2 can be separated by a gate cutting pattern CT. The gate cutting pattern CT can be located between the gate electrode GE on the first single-height unit SHC1 and the gate electrode GE on the second single-height unit SHC2, and the gate electrode GE on the second single-height unit SHC2 is aligned with the gate electrode GE on the first single-height unit SHC1 in the first direction D1. In other words, the gate electrode GE extending in the first direction D1 can be divided into multiple gate electrodes GE by the gate cutting pattern CT.

[0054] refer to Figure 4A and Figures 5A to 5DA pair of gate spacers GS can be respectively disposed on the sidewalls of the outer electrode PO4 of the gate electrode GE. The gate spacers GS can extend along the gate electrode GE in a first direction D1. The gate spacers GS can have an upper surface that is higher than the gate electrode GE. The upper surface of the gate spacers GS can be coplanar with the upper surface of the first interlayer insulating film 110 described herein. The gate spacers GS can include at least one of SiCN, SiCON, or SiN. As another example, the gate spacers GS can include a multilayer film composed of at least two of SiCN, SiCON, or SiN.

[0055] A gate cap pattern GP may be disposed on the gate electrode GE. The gate cap pattern GP may extend along the gate electrode GE in a first direction D1. The gate cap pattern GP may include a material having etch selectivity relative to the first interlayer insulating film 110 and the second interlayer insulating film 120 described herein. Specifically, the gate cap pattern GP may include at least one of SiON, SiCN, SiCON, or SiN.

[0056] The gate insulating film GI can be located between the gate electrode GE and the first channel pattern CH1, and between the gate electrode GE and the second channel pattern CH2. The gate insulating film GI can cover the upper surface TS, the bottom surface BS, and the two sidewalls SW of each of the first to third semiconductor patterns SP1, SP2, and SP3. The gate insulating film GI can cover the upper surface of the device isolation film ST below the gate electrode GE. The gate insulating film GI can cover the upper surface of the back-side isolation structure BIST below the gate electrode GE (see...). Figure 5D The gate insulating film GI can be located between the first internal electrode PO1 and the back-side isolation structure BIST.

[0057] According to embodiments of the present invention, the gate insulating film GI may include a silicon oxide film, a silicon oxynitride film, and / or a high-dielectric film. The high-dielectric film may include a material with a higher dielectric constant than the silicon oxide film. For example, materials with a higher dielectric constant than the silicon oxide film may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0058] The gate electrode GE may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may be disposed on the gate insulating film GI to be adjacent to the first to third semiconductor patterns SP1, SP2, and SP3. The first metal pattern may include a work function metal that controls the threshold voltage of the transistor. The target threshold voltage of the transistor can be achieved by controlling the thickness and composition of the first metal pattern. For example, the first to third inner electrodes PO1, PO2, and PO3 of the gate electrode GE may be composed of the first metal pattern, which is composed of a work function metal.

[0059] The first metal pattern may include a metal nitride film. For example, the first metal pattern may include nitrogen (N) and at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), or molybdenum (Mo), or a combination thereof. Furthermore, the first metal pattern may also include carbon (C). The first metal pattern may include multiple stacked work function metal films.

[0060] The second metal pattern may include a metal with a lower resistance than the first metal pattern. For example, the second metal pattern may include at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), or tungsten (W), or a combination thereof. For example, the external electrode PO4 of the gate electrode GE may include the first metal pattern and the second metal pattern on the first metal pattern.

[0061] refer to Figure 5B The inner spacer IP can be disposed on the first NMOSFET region NR1 and the second NMOSFET region NR2. In other words, the inner spacer IP can be disposed on the second active pattern AP2. The inner spacer IP can be respectively located between the second source / drain pattern SD2 and the first to third inner electrodes PO1, PO2, and PO3 of the gate electrode GE. The inner spacer IP can be in direct contact with the second source / drain pattern SD2. Each of the first to third inner electrodes PO1, PO2, and PO3 of the gate electrode GE can be spaced apart from the second source / drain pattern SD2 by the inner spacer IP.

[0062] A first interlayer insulating film 110 may be disposed on a substrate 100. The first interlayer insulating film 110 may cover a gate spacer GS and a first source / drain pattern SD1 and a second source / drain pattern SD2. The upper surface of the first interlayer insulating film 110 may be substantially coplanar with the upper surface of the gate cap pattern GP and the upper surface of the gate spacer GS. A second interlayer insulating film 120 covering the gate cap pattern GP may be disposed on the first interlayer insulating film 110. A third interlayer insulating film 130 may be disposed on the second interlayer insulating film 120. A fourth interlayer insulating film 140 may be disposed on the third interlayer insulating film 130. For example, the first interlayer insulating film 110, the second interlayer insulating film 120, the third interlayer insulating film 130, and the fourth interlayer insulating film 140 may each comprise a silicon oxide film.

[0063] A pair of isolation structures DB, facing each other in the second direction D2, can be disposed on both sides of each of the first single-height unit SHC1 and the second single-height unit SHC2. For example, the pair of isolation structures DB can be disposed on the first boundary BD1 and the second boundary BD2 of the first single-height unit SHC1, respectively. The isolation structure DB can extend parallel to the gate electrode GE in the first direction D1. The spacing between the isolation structure DB and its adjacent gate electrode GE can be the same as the first spacing.

[0064] The isolation structure DB can penetrate the gate cap pattern GP and the gate electrode GE to extend into the interior of the first active pattern AP1 and the second active pattern AP2. The isolation structure DB can penetrate the upper part of each of the first active pattern AP1 and the second active pattern AP2. The isolation structure DB can electrically isolate the active region of each of the first single-height cell SHC1 and the second single-height cell SHC2 from the active region of the adjacent cell.

[0065] Active contacts AC can be provided that penetrate the first interlayer insulating film 110 and the second interlayer insulating film 120 to be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. Each of the active contacts AC can be positioned adjacent to a side of the gate electrode GE. In a plan view, the active contacts AC can be in the form of a strip extending along a first direction D1.

[0066] The active contact AC can be a self-aligned contact. In other words, the active contact AC can be formed in a self-aligned manner using a gate cap pattern GP and a gate spacer GS. For example, the active contact AC can at least partially cover the sidewalls of the gate spacer GS. Although not shown, the active contact AC can partially cover the upper surface of the gate cap pattern GP.

[0067] A metal-semiconductor compound layer SC (e.g., a silicide layer) may be disposed between the active contact AC and the first source / drain pattern SD1, and between the active contact AC and the second source / drain pattern SD2, respectively. The active contact AC can be electrically connected to the source / drain patterns SD1 and SD2 via the metal-semiconductor compound layer SC. For example, the metal-semiconductor compound layer SC may include at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, or cobalt silicide.

[0068] Gate contacts GC can be configured to penetrate the second interlayer insulating film 120 and the gate cap pattern GP to be electrically connected to the gate electrode GE, respectively. In the plan view, the two gate contacts GC on the first single-height cell SHC1 can be configured to overlap with the first PMOSFET region PR1. In other words, the two gate contacts GC on the first single-height cell SHC1 can be configured on the first active pattern AP1 (see...). Figure 5A In the plan view, the gate contact GC on the first single-height cell SHC1 can be configured to overlap with the first NMOSFET region NR1. In other words, the gate contact GC on the first single-height cell SHC1 can be disposed on the second active pattern AP2 (see...). Figure 5B ).

[0069] The gate contact GC can be freely disposed on the gate electrode GE without being restricted by its position. For example, the gate contact GC on the second single-height cell SHC2 can be disposed on the second PMOSFET region PR2, the second NMOSFET region NR2, and the device isolation film ST filling the trench TR (see [reference]). Figure 4A ).

[0070] According to an embodiment of the present invention, reference is made to Figure 5A and Figure 5BThe gate contact GC can directly contact the upper surface of the external electrode PO4. The gate contact GC can also directly contact the upper surface of the external electrode PO4 and a portion of the upper surface of the gate insulating film GI disposed on the surface of the external electrode PO4. For example, the gate insulating film GI can be disposed on the side surface of the external electrode PO4 and between the external electrode PO4 and the third semiconductor pattern SP3. The gate insulating film GI can expose the upper surface of the external electrode PO4. The upper portion of the active contact AC adjacent to the gate contact GC can be filled with an upper insulating pattern UIP. The upper insulating pattern UIP can have a bottom surface lower than that of the gate contact GC. In other words, due to the upper insulating pattern UIP, the upper surface of the active contact AC adjacent to the gate contact GC can become lower than the bottom surface of the gate contact GC. Therefore, short circuits that occur when the gate contact GC contacts the adjacent active contact AC can be prevented. For example, the upper insulating pattern UIP can include a silicon-based insulating material (e.g., a silicon oxide film, a silicon nitride film, or a silicon oxynitride film).

[0071] Each of the active contact AC and the gate contact GC may include a conductive pattern FM and a blocking pattern BM. The blocking pattern BM may be disposed on a side of the conductive pattern FM. For example, the blocking pattern BM may surround at least a portion of the conductive pattern FM. For example, the conductive pattern FM may include at least one metal selected from aluminum, copper, tungsten, molybdenum, or cobalt. The blocking pattern BM may cover the sidewalls and bottom surface of the conductive pattern FM. The blocking pattern BM may expose the upper surface of the conductive pattern FM. The blocking pattern BM may include a metal film / metal nitride film. The metal film may include at least one selected from titanium, tantalum, tungsten, nickel, cobalt, or platinum. The metal nitride film may include at least one selected from titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), or platinum nitride (PtN).

[0072] refer to Figure 4A and Figures 5A to 5D The first to third lower electric field lines VPR1, VPR2, and VPR3 can be disposed below the substrate 100. The first to third lower electric field lines VPR1, VPR2, and VPR3 can extend parallel to each other in the second direction D2. The first lower electric field line VPR1 can be disposed on the fourth boundary BD4 of the first single-height unit SHC1. The second lower electric field line VPR2 can be disposed on the third boundary BD3 of the first single-height unit SHC1. In other words, the first single-height unit SHC1 can be defined between the first lower electric field line VPR1 and the second lower electric field line VPR2. The second single-height unit SHC2 can be defined between the second lower electric field line VPR2 and the third lower electric field line VPR3.

[0073] According to an embodiment of the present invention, the first lower electric field line VPR1 may vertically overlap with the first NMOSFET region NR1. The second lower electric field line VPR2 may vertically overlap with the first PMOSFET region PR1 and the second PMOSFET region PR2. The third lower electric field line VPR3 may vertically overlap with the second NMOSFET region NR2.

[0074] The first to third lower power lines VPR1, VPR2 and VPR3 may include at least one or a combination thereof selected from the group consisting of copper, molybdenum, tungsten or ruthenium.

[0075] A power transport network (PDN) layer can be configured. The PDN layer can be disposed on the bottom surface of the substrate 100. The PDN layer can include multiple lower lines electrically connected to the first to third lower power lines VPR1, VPR2, and VPR3. For example, the PDN layer can include a network of lines for applying a source voltage VSS to the first lower power line VPR1 and the third lower power line VPR3. The PDN layer can also include a network of lines for applying a drain voltage VDD to the second lower power line VPR2.

[0076] refer to Figure 4A and Figure 4B as well as Figure 5A , Figure 5B and Figure 5C A first back-side active contact BAC1 can be provided. The first back-side active contact BAC1 can penetrate the substrate 100 and extend vertically from the second lower electric field line VPR2 to the first source / drain pattern SD1. A second back-side active contact BAC2 can be provided. The second back-side active contact BAC2 can penetrate the substrate 100 and extend vertically from the first lower electric field line VPR1 to the second source / drain pattern SD2.

[0077] Specifically, the first back-side active contact BAC1 and the second back-side active contact BAC2 can be disposed below the substrate 100 to have a tapered shape. For example, the lower width of each of the first back-side active contact BAC1 and the second back-side active contact BAC2 can be greater than its upper width. Each of the first back-side active contact BAC1 and the second back-side active contact BAC2 can have the shape of a strip or plate extending between a pair of isolation structures DB in a second direction D2 in a plan view.

[0078] The first back-side active contact portion BAC1 can extend vertically to the first source / drain pattern SD1, without contacting the upper active contact portion AC. The second back-side active contact portion BAC2 can extend vertically to the second source / drain pattern SD2, without contacting the upper active contact portion AC.

[0079] The first back-side active contact BAC1 may be in the form of a conductive post that vertically connects the second lower power line VPR2 and the first source / drain pattern SD1. The drain voltage VDD can be applied to the first source / drain pattern SD1 through the first back-side active contact BAC1.

[0080] The second back-side active contact BAC2 may be in the form of a conductive post that vertically connects the first lower power line VPR1 and the second source / drain pattern SD2. The source voltage VSS can be applied to the second source / drain pattern SD2 through the second back-side active contact BAC2.

[0081] A metal-semiconductor compound layer SC may be disposed between each of the first back-side active contact BAC1 and the second back-side active contact BAC2 and the source / drain patterns SD1 and SD2. For example, the metal-semiconductor compound layer SC may be a silicide layer. The first back-side active contact BAC1 and the second back-side active contact BAC2 may be electrically connected to the first source / drain pattern SD1 or the second source / drain pattern SD2 through the metal-semiconductor compound layer SC. For example, the metal-semiconductor compound layer SC may include at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, or cobalt silicide.

[0082] The first back-side active contact BAC1 and the second back-side active contact BAC2 may each include a back-side conductive pattern BFM and a back-side blocking pattern BBM. The back-side blocking pattern BBM may be disposed on the back-side conductive pattern BFM. The back-side blocking pattern BBM may surround at least a portion of the back-side conductive pattern BFM. The back-side blocking pattern BBM may cover the sidewalls and top surface of the back-side conductive pattern BFM. For example, the back-side conductive pattern BFM may include at least one metal selected from aluminum, copper, tungsten, molybdenum, or cobalt. The back-side blocking pattern BBM may cover the sidewalls and top surface of the back-side conductive pattern BFM. The back-side blocking pattern BBM may include a metal film / metal nitride film. The metal film may include at least one selected from titanium, tantalum, tungsten, nickel, cobalt, or platinum. The metal nitride film may include at least one selected from titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), or platinum nitride (PtN). The back-side conductive pattern BFM may include the same material as the conductive pattern FM described herein, and the back-side blocking pattern BBM may include the same material as the blocking pattern BM described herein.

[0083] The back-side isolation structure (BIST) can be disposed below the gate electrode GE. For example, the back-side isolation structure BIST can penetrate the substrate 100 and the first back-side active contact BAC1 at a location disposed below the corresponding gate electrode GE. Another back-side isolation structure BIST can penetrate the substrate 100 and the second back-side active contact BAC2 at another location disposed below the corresponding gate electrode GE. The back-side isolation structure BIST can extend from the upper surface of the lower electric field line VPR1 or VPR2 to the bottom surface of the gate insulating film GI surrounding the first inner electrode PO1. That is, the back-side isolation structure BIST can be in direct contact with the bottom surface of the gate insulating film GI. At least a portion of the back-side isolation structure BIST can gradually decrease in width in the second direction D2 and decrease towards the third direction D3.

[0084] refer to Figure 4B In the plan view, the back-side active contact BAC1 or BAC2 disposed between the back-side isolation structures BIST may include a back-side blocking pattern BBM disposed on its upper or lower surface. That is, the back-side blocking pattern BBM may not be disposed on the side surface of each of the back-side isolation structures BIST. In the plan view, the back-side active contact BAC1 or BAC2 disposed between the back-side isolation structure BIST and the isolation structure DB may include a back-side blocking pattern BBM disposed on its upper, lower, or side surface. That is, the back-side blocking pattern BBM may be disposed on the side surface of the isolation structure DB.

[0085] In the third direction D3, the uppermost surface of the back-side isolation structure BIST can be located at a lower level than the uppermost surface of the back-side active contact BAC1 or BAC2. That is, in the third direction D3, the uppermost surface of the back-side active contact BAC1 or BAC2 can be located at a higher level than the uppermost surface of the back-side isolation structure BIST. The bottom surface of the back-side isolation structure BIST can be substantially coplanar with the bottom surface of the back-side active contact BAC1 or BAC2.

[0086] The upper portion of the back-side isolation structure BIST can contact the substrate 100, and the lower portion of the back-side isolation structure BIST can contact the back-side active contact BAC1 or BAC2. Specifically, the first portion of the lower portion of the back-side isolation structure BIST can directly contact the back-side barrier pattern BBM of the back-side active contact BAC1 or BAC2, and the second portion of the lower portion of the back-side isolation structure BIST can directly contact the back-side conductive pattern BFM of the back-side active contact BAC1 or BAC2. In other words, the second portion of the lower portion of the back-side isolation structure BIST can directly contact the back-side conductive pattern BFM, and can be separately disposed from the back-side barrier pattern BBM of the back-side active contact BAC1 or BAC2. At least because the back-side active contact BAC1 or BAC2 can be formed before the back-side isolation structure BIST in the manufacturing method described herein, the second portion of the lower portion of the back-side isolation structure BIST can be configured not to directly contact the back-side barrier pattern BBM of the back-side active contact BAC1 or BAC2.

[0087] The back-side isolation structure (BIST) may include a silicon-based insulating material (e.g., a silicon oxide film, a silicon nitride film, or a silicon oxynitride film). The BIST can isolate the back-side active contacts BAC1 or BAC2 into units electrically connected to the source / drain patterns SD1 or SD2 of the transistor. In other words, the BIST can electrically isolate the back-side active contacts BAC1 or BAC2 into units, which allows selection of individual source / drain patterns within the source / drain patterns SD1 or SD2 to which a drain voltage VDD or a source voltage VSS can be applied. The BIST will be described below.

[0088] refer to Figure 4A and Figures 5A to 5D A first metal layer M1 can be disposed in the third interlayer insulating film 130. The first metal layer M1 may include a first line M1_I. The first lines M1_I of the first metal layer M1 may extend parallel to each other in the second direction D2.

[0089] According to an embodiment of the present invention, power lines for supplying power to the single-height cell SHC can be provided below the substrate 100. The power lines can be provided in the form of lower power lines VPR1, VPR2, and VPR3. As described herein, lower power lines VPR1, VPR2, and VPR3 can be provided below the substrate 100. As another example, lower power lines VPR1, VPR2, and VPR3 can be buried in the substrate 100. Therefore, the power lines can be omitted in the first metal layer M1. A first line M1_I for signal transmission can be provided in the first metal layer M1.

[0090] The first metal layer M1 may further include a first via VI1. The first via VI1 may be disposed below the first line M1_I of the first metal layer M1. The active contact AC and the first line M1_I of the first metal layer M1 may be electrically connected to each other through the first via VI1. The gate contact GC and the first line M1_I of the first metal layer M1 may be electrically connected to each other through the first via VI1.

[0091] The first line M1_I of the first metal layer M1 and the first via VI1 beneath it can be formed in a separate process. In other words, the first line M1_I and the first via VI1 of the first metal layer M1 can each be formed in a single damascene process. The semiconductor device according to the embodiment can be formed using a process for manufacturing semiconductor devices with design rules of less than about 20 nm.

[0092] The second metal layer M2 can be disposed in the fourth interlayer insulating film 140. The second metal layer M2 can include a plurality of second lines M2_I. Each of the second lines M2_I of the second metal layer M2 can be in the form of a line or strip extending along the first direction D1. In other words, the second lines M2_I can extend parallel to each other in the first direction D1.

[0093] The second metal layer M2 may further include a second via VI2 disposed below the second line M2_I. The first line M1_I of the first metal layer M1 and the second line M2_I of the second metal layer M2 can be electrically connected to each other through the second via VI2. For example, the second line M2_I of the second metal layer M2 and the second via VI2 below it can be formed together in a dual damascene process.

[0094] The first line M1_I of the first metal layer M1 and the second line M2_I of the second metal layer M2 may comprise the same or different materials. For example, the first line M1_I of the first metal layer M1 and the second line M2_I of the second metal layer M2 may comprise at least one metallic material selected from aluminum, copper, tungsten, molybdenum, ruthenium, or cobalt. Although not shown, metal layers (e.g., M3, M4, M5) stacked on the fourth interlayer insulating film 140 may additionally be provided. Each of the stacked metal layers may comprise lines for routing between cells.

[0095] Figure 6 It is shown Figure 5A A magnified view of region M. Referencing this in the following text... Figure 6 A semiconductor device according to an embodiment of the present invention is described. For the sake of simplicity, repeated descriptions may be omitted.

[0096] The first semiconductor patterns SP1 of the first channel pattern CH1 can be disposed horizontally spaced apart from each other on the substrate 100. The source / drain patterns SD1 connected to the first semiconductor patterns SP1 can each include a first pattern T1 and a second pattern T2 between the first semiconductor patterns SP1.

[0097] The first back-side active contact BAC1 may include a third pattern T3 electrically connected to the first pattern T1 and a fourth pattern T4 separate from the second pattern T2. ​​The back-side isolation structures may each penetrate the substrate 100 and the first back-side active contact BAC1, and may be horizontally spaced apart from each other. Each back-side isolation structure may include a first back-side isolation structure BIST1, a second back-side isolation structure BIST2, and a third back-side isolation structure BIST3. The third pattern T3 may be disposed between the first back-side isolation structure BIST1 and the second back-side isolation structure BIST2, and the fourth pattern T4 may be disposed between the second back-side isolation structure BIST2 and the third back-side isolation structure BIST3. A metal-semiconductor compound layer SC may be located between the first pattern T1 and the third pattern T3.

[0098] The first back-side isolation structure BIST1 may include a first portion P1, a second portion P2 on the first portion P1, and a third portion P3 on the second portion P2. The first to third portions P1, P2, and P3 may each include a corresponding first side surface SS1, a second side surface SS2, and a third side surface SS3. For example, since the second portion P2 is on the first portion P1 and the third portion P3 is on the second portion P2, the second side surface SS2 can extend upward from the first side surface SS1, and the third side surface SS3 can extend upward from the second side surface SS2. The first to third side surfaces SS1, SS2, and SS3 can form the linear side surfaces of the first back-side isolation structure BIST1.

[0099] The first portion P1 may have a back-side conductive pattern BFM on its side. The first portion P1 may be in direct contact with the back-side conductive pattern BFM, but may not be in direct contact with the back-side blocking pattern BBM. For example, the first portion P1 may be located horizontally below the back-side blocking pattern BBM. The back-side blocking pattern BBM may be located on the side of the second portion P2. The second portion P2 may be in direct contact with the back-side blocking pattern BBM. The substrate 100 or the first active pattern AP1 may be located on the side of the third portion P3. The third portion P3 may be in direct contact with the substrate 100 or the first active pattern AP1. That is, the first side surface SS1 may be in direct contact with the back-side conductive pattern BFM, and the second side surface SS2 may be in direct contact with the back-side blocking pattern BBM. The third side surface SS3 may be in direct contact with the substrate 100, which may be a silicon-based substrate.

[0100] The uppermost surface of the third pattern T3 of the first back-side active contact BAC1 can be located at the first level LV1. The uppermost surface of the fourth pattern T4 of the first back-side active contact BAC1 can be located at the second level LV2. The uppermost surface of each of the first to third back-side isolation structures BIST1, BIST2, and BIST3 can be located at the third level LV3. The first to third levels LV1, LV2, and LV3 can be defined as positions on the third direction D3.

[0101] The first level LV1 can be at the same level as or higher than the upper surface of the gate insulating film GI. The second level LV2 can be at the same level as the lower surface of the substrate 100. The third level LV3 can be higher than the second level LV2 and lower than the first level LV1. That is, the uppermost surface of each of the first to third back-side isolation structures BIST1, BIST2 and BIST3 can be located between the upper surface of the third pattern T3 and the upper surface of the fourth pattern T4. The third level LV3 can be at the same level as the lower surface of the gate insulating film GI.

[0102] Figure 7 It is used to describe according to Figure 5A A cross-sectional view of a semiconductor device according to another embodiment. (Refer to...) Figure 7 A first back-side active contact BAC1 can be provided, which penetrates the substrate 100 to extend vertically from the second lower electric field line VPR2 to the first source / drain pattern SD1. Specifically, the first back-side active contact BAC1 can be disposed below the substrate 100 to extend vertically from the second lower electric field line VPR2 to the first source / drain pattern SD1.

[0103] The first back-side active contact BAC1 may be in the form of a conductive post that vertically connects the second lower power line VPR2 and the first source / drain pattern SD1. The drain voltage VDD can be applied to the first source / drain pattern SD1 through the first back-side active contact BAC1.

[0104] According to the embodiment, since the first back-side active contact BAC1 is fully electrically connected to the first source / drain pattern SD1 in the unit cell, it is not necessary to form an upper active contact AC (see [link]). Figure 5A Therefore, the active contact AC can be omitted from the front surface of the semiconductor device, thereby preventing short circuits between the gate contact and the active contact. Furthermore, contacts can be formed on the front surface of the semiconductor device at a relatively low density, improving the efficiency of semiconductor device manufacturing.

[0105] Figure 8A and Figure 8B , Figure 9A and Figure 9B , Figures 10A to 10C , Figures 11A to 11C , Figures 12A to 12C , Figures 13A to 13D , Figures 14A to 14D , Figures 15A to 15D , Figures 16A to 16D and Figures 17A to 17D Each of these is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. Specifically, Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A and Figure 17A It corresponds to Figure 4A A cross-sectional view of line A-A'. Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B and Figure 17B It corresponds to Figure 4A A cross-sectional view of line B-B'. Figure 10C , Figure 11C , Figure 13C , Figure 14C , Figure 15C , Figure 16C and Figure 17C It corresponds to Figure 4A A cross-sectional view of line C-C'. Figure 8B , Figure 9B , Figure 12C , Figure 13D , Figure 14D , Figure 15D , Figure 16D and Figure 17D It corresponds to Figure 4A A cross-sectional view of line D-D'.

[0106] refer to Figure 8A and Figure 8B A substrate 100 may be provided, comprising a first PMOSFET region PR1 and a second PMOSFET region PR2, as well as a first NMOSFET region NR1 and a second NMOSFET region NR2. For example, the substrate 100 may be a silicon wafer.

[0107] Alternating stacked first semiconductor layer ACL and second semiconductor layer SAL can be formed on substrate 100. The first semiconductor layer ACL may include at least one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe), and the second semiconductor layer SAL may include another of silicon (Si), germanium (Ge), or silicon-germanium (SiGe).

[0108] Although Figure 8A and Figure 8B The diagram shows three first semiconductor layers (ACL) and three second semiconductor layers (SAL), but the number of layers can be varied. For example, the number of layers can be changed to control the number of layers in the channel pattern and / or gate electrode formed later.

[0109] The second semiconductor layer SAL may have etch selectivity relative to the first semiconductor layer ACL. For example, the first semiconductor layer ACL may include silicon (Si), and the second semiconductor layer SAL may include silicon-germanium (SiGe). The second semiconductor layer SAL may each have germanium (Ge) at a concentration of about 10 at% to about 30 at%.

[0110] The mask pattern can be formed on the first PMOSFET region PR1 and the second PMOSFET region PR2, and the first NMOSFET region NR1 and the second NMOSFET region NR2, respectively, on the substrate 100. The mask pattern can be in the form of a line or strip extending along the second direction D2.

[0111] By performing a patterning process using a mask pattern as an etching mask, a trench TR defining a first active pattern PAP1 and a second active pattern PAP2 can be formed. The first active pattern PAP1 can be formed on each of a first PMOSFET region PR1 and a second PMOSFET region PR2. The second active pattern PAP2 can be formed on each of a first NMOSFET region NR1 and a second NMOSFET region NR2. In a planar view, the first active pattern PAP1 and the second active pattern PAP2 can have the form of lines extending parallel to each other along a second direction D2.

[0112] A stacked pattern STP can be formed on each of the first active pattern PAP1 and the second active pattern PAP2. The stacked pattern STP may include an etch stop layer ESL. The stacked pattern STP may also include a first semiconductor layer ACL and a second semiconductor layer SAL alternately stacked on the etch stop layer ESL. The stacked pattern STP can be formed together with the first active pattern PAP1 and the second active pattern PAP2 during the patterning process.

[0113] A device isolation film ST that fills the trench TR can be formed. Specifically, an insulating film covering the first active pattern PAP1 and the second active pattern PAP2, as well as the stacked pattern STP, can be formed on the front surface of the substrate 100. The device isolation film ST can be formed by recessing the insulating film. For example, the device isolation film ST can be formed by recessing the insulating film until the stacked pattern STP is exposed.

[0114] The device isolation film (ST) may include an insulating material such as a silicon oxide film. A stacked pattern (STP) may be exposed on the device isolation film (ST). In other words, the stacked pattern (STP) may protrude vertically onto the device isolation film (ST).

[0115] refer to Figure 9A and Figure 9B Sacrificial patterns PP intersecting the stacked pattern STP can be formed on the substrate 100. Each sacrificial pattern PP can be formed as a line or strip extending along a first direction D1. The sacrificial patterns PP can be arranged along a second direction D2 at a first spacing.

[0116] Specifically, forming the sacrificial pattern PP may include forming a sacrificial film on the front surface of the substrate 100, forming a hard mask pattern MP on the sacrificial film, and patterning the sacrificial film using the hard mask pattern MP as an etching mask. The sacrificial film may include polysilicon.

[0117] A pair of gate spacers GS may be formed on the two sidewalls of each of the sacrificial pattern PP. Forming the gate spacers GS may include conformally forming a gate spacer film on the front surface of the substrate 100 and anisotropically etching the gate spacer film. The gate spacer film may include at least one of SiCN, SiCON, or SiN. As another example, the gate spacer film may be a multilayer film including at least two of SiCN, SiCON, or SiN.

[0118] refer to Figures 10A to 10C The first recess RS1 can be formed in the stacked pattern STP on the first active pattern PAP1. The second recess RS2 can be formed in the stacked pattern STP on the second active pattern PAP2. When forming the first recess RS1 and the second recess RS2, the device isolation film ST on both sides of each of the first active pattern PAP1 and the second active pattern PAP2 can also be recessed. (See...) Figure 10C ).

[0119] Specifically, the first recess RS1 can be formed by etching the stacked pattern STP on the first active pattern PAP1 using a hard mask pattern MP and a gate spacer GS as an etching mask. The first recess RS1 can be formed between a pair of sacrificial patterns PP. The second recess RS2 in the stacked pattern STP on the second active pattern PAP2 can be formed in the same process as the process for forming the first recess RS1.

[0120] refer to Figure 10C The fence pattern FNP can be formed on each of the first active pattern PAP1 and the second active pattern PAP2. The fence pattern FNP can be part of the remaining gate spacer GS.

[0121] refer to Figures 10A to 10C The first to third semiconductor patterns SP1, SP2, and SP3, sequentially stacked between adjacent first recesses RS1, can each be formed by a first semiconductor layer ACL. The first to third semiconductor patterns SP1, SP2, and SP3, sequentially stacked between adjacent second recesses RS2, can each be formed by a first semiconductor layer ACL. The first to third semiconductor patterns SP1, SP2, and SP3 between adjacent first recesses RS1 can constitute a first channel pattern CH1. The first to third semiconductor patterns SP1, SP2, and SP3 between adjacent second recesses RS2 can constitute a second channel pattern CH2.

[0122] refer to Figures 11A to 11C The first source / drain pattern SD1 can be formed in the first recess RS1. Specifically, the buffer layer BFL can be formed by performing a first SEG process, in which the inner sidewall of the first recess RS1 can be used as a seed layer. The buffer layer BFL can be grown using the substrate 100 and the first to third semiconductor patterns SP1, SP2, SP3 exposed by the first recess RS1 as seeds. For example, the first SEG process can include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0123] The buffer layer BFL may include a semiconductor element (e.g., SiGe) having a larger lattice parameter than the semiconductor element of the substrate 100. The buffer layer BFL may contain a relatively low concentration of germanium (Ge). In another embodiment of the invention, the buffer layer BFL may contain silicon (Si) and may not contain germanium (Ge). The buffer layer BFL may have a germanium (Ge) concentration of 0 at% to about 30 at%.

[0124] The master layer MAL can be formed by performing a second SEG process on the buffer layer BFL. The master layer MAL can be formed to completely or almost fill the first recess RS1. The master layer MAL can contain a relatively high concentration of germanium (Ge). For example, the master layer MAL can have a germanium (Ge) concentration of about 30 at% to about 70 at%.

[0125] According to embodiments of the present invention, a capping layer can be formed by performing a third SEG process on the main MAL layer. The capping layer may include silicon (Si). The capping layer may have a silicon (Si) concentration of approximately 98 at% to 100 at%.

[0126] During the formation of the buffer layer BFL and the main layer MAL, impurities (e.g., boron, gallium, or indium) that can cause the first source / drain pattern SD1 to be P-type can be implanted in situ. As another example, after the formation of the first source / drain pattern SD1, impurities can be implanted into the first source / drain pattern SD1.

[0127] A second source / drain pattern SD2 can be formed in the second recess RS2. Specifically, the second source / drain pattern SD2 can be formed by performing a selective epitaxial growth (SEG) process, in which the inner sidewalls of the second recess RS2 can be used as a seed layer. For example, the second source / drain pattern SD2 can include the same semiconductor elements as the substrate 100 (e.g., Si).

[0128] When forming the second source / drain pattern SD2, impurities that can cause the second source / drain pattern SD2 to be N-type (e.g., phosphorus, arsenic, or antimony) can be implanted in situ. As another example, after forming the second source / drain pattern SD2, impurities can be implanted into the second source / drain pattern SD2.

[0129] According to an embodiment of the present invention, before forming the second source / drain pattern SD2, the second semiconductor layer SAL exposed through the second recess RS2 can be partially replaced with an insulating material to form an inner spacer IP. For example, the inner spacer IP can be formed between the second source / drain pattern SD2 and the second semiconductor layer SAL, respectively.

[0130] refer to Figures 12A to 12C A first interlayer insulating film 110 can be formed. The first interlayer insulating film 110 can cover the first source / drain pattern SD1 and the second source / drain pattern SD2, the hard mask pattern MP, and the gate spacer GS. For example, the first interlayer insulating film 110 may include a silicon oxide film.

[0131] The first interlayer insulating film 110 can be planarized. For example, the first interlayer insulating film 110 can be planarized until the upper surface of the sacrificial pattern PP is exposed. The first interlayer insulating film 110 can be planarized using an etch-back process or a chemical mechanical polishing (CMP) process. At least a portion of the hard mask pattern MP can be removed during the planarization process. For example, the hard mask pattern MP can be completely removed during the planarization process. After the planarization process, the upper surface of the first interlayer insulating film 110 can be coplanar with the upper surface of the sacrificial pattern PP and the upper surface of the gate spacer GS.

[0132] Regions of the sacrificial pattern PP can be selectively opened using photolithography. For example, regions of the sacrificial pattern PP on the third boundary BD3 and the fourth boundary BD4 of the first single-height cell SHC1 can be selectively opened. The opened regions of the sacrificial pattern PP can be selectively removed by etching. A gate dicing pattern CT can be formed in the regions where the sacrificial pattern PP has been removed (see...). Figure 12C For example, a gate cut pattern CT can be formed by filling the area where the sacrificial pattern PP has been removed with an insulating material.

[0133] Exposed sacrificial pattern PP can be selectively removed. The outer region ORG exposing the first channel pattern CH1 and the second channel pattern CH2 can be formed by removing the sacrificial pattern PP (see [link to documentation]). Figure 12C Removing the sacrificial pattern PP can include a wet etching process that uses an etchant to selectively etch polysilicon.

[0134] The inner region IRG can be formed by selectively removing the second semiconductor layer SAL exposed through the outer region ORG (see [link]). Figure 12A and Figure 12B Specifically, the second semiconductor layer SAL can be removed while the first to third semiconductor patterns SP1, SP2, and SP3 can be preserved by performing an etching process that selectively etches the second semiconductor layer SAL. For silicon-germanium with a relatively high germanium concentration, the etching process can have a high etching rate. For example, for silicon-germanium with a germanium concentration higher than about 10 at%, the etching process can have a high etching rate.

[0135] During the etching process, the second semiconductor layer SAL on the first PMOSFET region PR1 and the second PMOSFET region PR2, as well as the first NMOSFET region NR1 and the second NMOSFET region NR2, can be removed. For example, the second semiconductor layer SAL on the first PMOSFET region PR1 and the second PMOSFET region PR2, as well as the first NMOSFET region NR1 and the second NMOSFET region NR2, can be completely removed. The etching process can be wet etching. The etching material used in the etching process can remove the second semiconductor layer SAL with a relatively high germanium concentration. Simultaneously, the first source / drain pattern SD1 on the first PMOSFET region PR1 and the second PMOSFET region PR2 can be protected during the etching process by a buffer layer BFL with a relatively low germanium concentration.

[0136] refer to Figure 12C By selectively removing the second semiconductor layer SAL, the stacked first to third semiconductor patterns SP1, SP2, and SP3 can remain on each of the first active pattern PAP1 and the second active pattern PAP2. The first to third internal regions IRG1, IRG2, and IRG3 can be formed by removing regions of the second semiconductor layer SAL. Specifically, the first internal region IRG1 can be formed between the active pattern PAP1 or PAP2 and the first semiconductor pattern SP1, the second internal region IRG2 can be formed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, and the third internal region IRG3 can be formed between the second semiconductor pattern SP2 and the third semiconductor pattern SP3.

[0137] refer to Figures 13A to 13D The gate insulating film GI can be conformally formed on the exposed first to third semiconductor patterns SP1, SP2, and SP3. The gate electrode GE can be formed on the gate insulating film GI. The gate electrode GE may include the first to third inner electrodes PO1, PO2, and PO3 formed in the first to third inner regions IRG1, IRG2, and IRG3, respectively, and the outer electrode PO4 formed in the outer region ORG.

[0138] The gate electrode GE can be recessed, and its height can be reduced. When the gate electrode GE can be recessed, the upper part of the gate cleaving pattern CT can also be recessed. For example, the upper part of the gate cleaving pattern CT can extend above the gate electrode GE. The gate capping pattern GP can be formed on the recessed gate electrode GE. The gate capping pattern GP can cover the gate electrode GE and the gate cleaving pattern CT. For example, the gate capping pattern GP can be formed on the upper surface of the gate cleaving pattern CT and the exposed side surface of the gate cleaving pattern CT.

[0139] A second interlayer insulating film 120 may be formed on a first interlayer insulating film 110. The second interlayer insulating film 120 may include a silicon oxide film. An active contact AC may be formed to penetrate a portion of the second interlayer insulating film 120 and a portion of the first interlayer insulating film 110. The active contact AC penetrating the second interlayer insulating film 120 and the first interlayer insulating film 110 may be electrically connected to at least one of a first source / drain pattern SD1 and a second source / drain pattern SD2. A gate contact GC may be formed to penetrate at least a portion of the gate cap pattern GP and the second interlayer insulating film 120. The gate contact GC penetrating the second interlayer insulating film 120 and the gate cap pattern GP may be electrically connected to the gate electrode GE.

[0140] Forming each of the active contact AC and the gate contact GC may include forming a barrier pattern BM and forming a conductive pattern FM on the barrier pattern BM. The barrier pattern BM may be formed conformally and may include a metal film / metal nitride film. The conductive pattern FM may include a metal with low resistance.

[0141] refer to Figure 4A and Figures 5A to 5D A third interlayer insulating film 130 may be formed on the active contact AC and the gate contact GC. A first metal layer M1 may be formed in the third interlayer insulating film 130. The first metal layer M1 may include a first line M1_I, which is electrically connected to at least one of the active contact AC or the gate contact GC. A fourth interlayer insulating film 140 may be formed on the third interlayer insulating film 130. A second metal layer M2 may be formed in the fourth interlayer insulating film 140.

[0142] After the BEOL process is completed, refer to Figure 8A and Figure 8B , Figure 9A and Figure 9B , Figures 10A to 10C , Figures 11A to 11C , Figures 12A to 12C , Figures 13A to 13D The substrate 100 described can be flipped. Because the substrate 100 is flipped, therefore, in the following text, in reference... Figures 14A to 14D , Figures 15A to 15D , Figures 16A to 16D and Figures 17A to 17D When making a description, refer to Figures 5A to 5D From the perspective of a completed three-dimensional semiconductor device, the terms "upper surface" and "upper part" can respectively represent "lower surface" and "lower part," and from a reference... Figures 5A to 5D From the perspective of a fully manufactured three-dimensional semiconductor device, "lower surface" and "lower part" can respectively represent "upper surface" and "upper part".

[0143] refer to Figures 14A to 14D After the BEOL process is completed, the bottom surface of the substrate 100 can be exposed by flipping the substrate 100. The exposed substrate 100 can then be partially removed.

[0144] According to embodiments of the present invention, partially removing the substrate 100 may include reducing the thickness of the substrate 100 by performing a planarization process (SAF) on the bottom surface of the substrate 100 and performing a cleaning process to selectively remove silicon (Si) on the substrate 100. The cleaning process may be performed until the upper and side surfaces of the isolation structure DB are partially exposed.

[0145] By partially removing the substrate 100, a first residual active pattern RPAP1 can be formed in the region where the first active pattern PAP1 exists. By partially removing the substrate 100, a second residual active pattern RPAP2 can be formed in the region where the second active pattern PAP2 exists (see...). Figure 14A and Figure 14B ).

[0146] By partially removing the substrate 100, a first residual active pattern RPAP1 and a second residual active pattern RPAP2 can be formed on the first source / drain pattern SD1 and the second source / drain pattern SD2. The device isolation film ST can be removed without performing a selective silicon removal cleaning process (see [link to documentation]). Figure 14C ).

[0147] refer to Figures 15A to 15D A surface-mount mask pattern (SMP) can be formed in an area where the substrate 100 is partially removed. The SMP can cover the isolation structure DB, the first remaining active pattern RPAP1, the second remaining active pattern RPAP2, and the device isolation film ST. The SMP can be formed by photolithography. A back-side contact hole (BCH) can be formed by performing an anisotropic etching process on the substrate 100 using the SMP as an etching mask. The BCH can expose the first source / drain pattern SD1 and the second source / drain pattern SD2. Specifically, the BCH can expose the source / drain pattern SD1 or SD2 that is not connected to the active contact AC. The BCH can be tapered. For example, the BCH can have a relatively narrow width at the source / drain pattern SD1 or SD2 and a relatively wide width away from the source / drain pattern SD1 or SD2.

[0148] refer to Figures 16A to 16DThe SOH mask pattern SMP can be selectively removed. After removing the SOH mask pattern SMP, a back-side blocking pattern BBM and a back-side conductive pattern BFM can be formed on the back-side contact hole BCH, substrate 100, and isolation structure DB. A metal-semiconductor compound layer SC can be formed between the source / drain pattern SD1 or SD2 and the back-side blocking pattern BBM. The back-side active contact BAC1 or BAC2 can be formed by performing a planarization process on the back-side conductive pattern BFM until the upper surface of the isolation structure DB is exposed. The planarization process can be a chemical mechanical polishing (CMP) process. In other words, the back-side blocking pattern BBM and the back-side conductive pattern BFM can constitute the back-side active contact BAC1 or BAC2. The back-side active contact BAC1 or BAC2 can be tapered. For example, the back-side active contact BAC1 or BAC2 can have a relatively narrow width at the source / drain pattern SD1 or SD2 and a relatively wide width away from the source / drain pattern SD1 or SD2.

[0149] refer to Figures 17A to 17D An anisotropic etching process can be performed on the area of ​​the gate electrode GE by forming a mask pattern on the back-side active contact BAC1 or BAC2 and using the mask pattern as an etching mask. A back-side isolation structure hole penetrating the back-side active contact BAC1 or BAC2 and the substrate 100 can be formed by performing the anisotropic etching process.

[0150] Silicon-based insulating material can be formed in the back-side isolation structure vias. The insulating material can be formed by performing a deposition process. The insulating material in the back-side isolation structure vias can constitute a back-side isolation structure (BIST). The back-side isolation structure (BIST) can separate portions of the back-side active contacts (BAC1) from each other. Similarly, the back-side isolation structure (BIST) can separate portions of the back-side active contacts (BAC2) from each other. Because the back-side isolation structure (BIST) can be formed after the back-side active contacts (BAC1) or (BAC2) are formed according to the manufacturing method described herein, the ratio of the back-side blocking pattern (BBM) in the back-side active contacts (BAC1) or (BAC2) can be reduced. That is, the ratio of the back-side blocking pattern (BBM), which has relatively high resistance, can be reduced, which can lower the resistance of the back-side active contacts (BAC1) or (BAC2) and improve the electrical characteristics of the semiconductor device.

[0151] Furthermore, the back-side active contacts BAC1 or BAC2 can be formed in a tapered shape, allowing for a relatively wide width at the top away from the source / drain patterns SD1 or SD2, and making the back-side active contacts BAC1 or BAC2 relatively easy to form. In other words, the back-side active contacts BAC1 or BAC2 with a relatively wide width at the opening can be formed before the back-side isolation structure BIST to ensure process margin, and considering the process margin, the back-side active contacts BAC1 or BAC2 can be manufactured more easily. Therefore, the cost associated with the semiconductor device manufacturing process can be reduced.

[0152] Lower power lines VPR1, VPR2, and VPR3 can be formed on the back-side active contact BAC1 or BAC2 and the back-side isolation structure BIST. Lower power lines VPR1, VPR2, and VPR3 can be connected to at least one of the back-side active contacts BAC1 or BAC2. A power transmission network layer PDN can be formed on the lower power lines VPR1, VPR2, and VPR3. The power transmission network layer PDN can be configured to apply source or drain voltages to the lower power lines VPR1, VPR2, and VPR3.

[0153] In the three-dimensional field-effect transistor according to an embodiment of the present invention, a back-side isolation structure separating the back-side active contacts can be formed after the back-side active contacts are formed, thereby reducing the resistance of the back-side active contacts. That is, since the back-side isolation structure is formed later, the proportion of back-side blocking patterns with relatively high resistance in the back-side active contacts can be reduced, thereby reducing the resistance of the back-side active contacts. Therefore, the electrical characteristics of the semiconductor device can be improved.

[0154] In the three-dimensional field-effect transistor according to an embodiment of the present invention, the back-side active contact is formed such that its upper portion has a relatively wide width when viewed from the back side of the transistor, thus the back-side active contact can be formed relatively easily. That is, since the back-side active contact with a relatively wide width can be formed before the back-side isolation structure, process margin can be ensured and the back-side active contact can be manufactured more easily. Therefore, the cost associated with the manufacturing process of the semiconductor device can be reduced.

[0155] While embodiments of the invention have been described, it should be understood that the invention should not be limited to these embodiments, but rather that various changes and modifications can be made by those skilled in the art within the spirit and scope of the invention as claimed.

Claims

1. A semiconductor device, comprising: Substrate; The lower electric field line is disposed below the substrate; Source / drain pattern on the substrate; The channel pattern comprises multiple semiconductor patterns stacked on top of each other on the side surface of the source / drain pattern; Gate electrode, located between the plurality of semiconductor patterns; A back-side active contact penetrates the substrate to electrically connect the lower power line and the source / drain pattern; as well as A back-side isolation structure penetrates the substrate and the back-side active contact portion, and is disposed below the gate electrode. The uppermost surface of the back-side active contact portion is located at a level higher than the uppermost surface of the back-side isolation structure.

2. The semiconductor device according to claim 1, wherein, The bottom surface of the back-side isolation structure is substantially coplanar with the bottom surface of the back-side active contact portion.

3. The semiconductor device according to claim 1, wherein, The back-side active contact includes a back-side conductive pattern and a back-side blocking pattern on the uppermost surface of the back-side conductive pattern.

4. The semiconductor device according to claim 3, wherein, The back-side blocking pattern covers the sidewall of the back-side conductive pattern.

5. The semiconductor device according to claim 3, wherein, The upper part of the back-side isolation structure is in contact with the substrate, and The lower part of the back-side isolation structure contacts the back-side active contact portion.

6. The semiconductor device according to claim 5, wherein, The lower first portion of the back-side isolation structure is in direct contact with the back-side blocking pattern, and The second portion of the lower part of the back-side isolation structure is in direct contact with the back-side conductive pattern.

7. The semiconductor device according to claim 1, wherein, The back-side isolation structure has a tapered shape from a narrow portion at the gate electrode to a wide portion away from the gate electrode, and The back-side active contact portion has a tapered shape extending from a narrow portion at the source / drain pattern to a wide portion away from the source / drain pattern.

8. The semiconductor device of claim 1, further comprising a gate insulating film between the gate electrode and the plurality of semiconductor patterns. in, The gate electrode includes a first inner electrode, a second inner electrode, and a third inner electrode located between adjacent semiconductor patterns among the plurality of semiconductor patterns, and an outer electrode on the uppermost semiconductor pattern. The back-side isolation structure is in direct contact with the bottom surface of the gate insulating film surrounding the first inner electrode.

9. The semiconductor device of claim 8, further comprising a gate contact electrically connected to the gate electrode. in, The gate contact portion is in contact with the external electrode.

10. A semiconductor device, comprising: Substrate; Multiple semiconductor patterns are horizontally spaced apart from each other on the substrate; The source / drain pattern includes a first pattern and a second pattern respectively located between the plurality of semiconductor patterns; A gate electrode is located between the substrate and each of the plurality of semiconductor patterns; A gate insulating film surrounds the gate electrode; A back-side active contact portion is disposed below the substrate and includes a third pattern electrically connected to the first pattern and a fourth pattern separate from the second pattern; as well as A back-side isolation structure penetrates the substrate and the back-side active contact portion. The back-side isolation structure includes a first back-side isolation structure, a second back-side isolation structure, and a third back-side isolation structure that are horizontally spaced apart from each other. The third pattern is disposed between the first back-side isolation structure and the second back-side isolation structure, and the fourth pattern is disposed between the second back-side isolation structure and the third back-side isolation structure.

11. The semiconductor device according to claim 10, wherein, The back-side active contact includes a back-side conductive pattern and a back-side blocking pattern on the back-side conductive pattern. The first back-side isolation structure includes a first part, a second part on the first part, and a third part on the second part. The first portion is in direct contact with the back-side conductive pattern. The second part is in direct contact with the back-side blocking pattern, and The third part is in direct contact with the substrate.

12. The semiconductor device according to claim 11, wherein, The back-side conductive pattern comprises a metallic material. The back-side barrier pattern includes a metal nitride film, and The metal nitride film includes at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), or platinum nitride (PtN).

13. The semiconductor device of claim 10, further comprising a metal-semiconductor compound layer between the first pattern and the third pattern.

14. The semiconductor device according to claim 10, wherein, The uppermost surface of the third pattern is located at the first horizontal level. The uppermost surface of the fourth pattern is located at the second level. The uppermost surface of each of the aforementioned back-side isolation structures is located at the third level, and The third level is higher than the second level and lower than the first level.

15. The semiconductor device according to claim 10, wherein, The uppermost surface of the third pattern is located at a level that is higher than or equal to the upper surface of the gate insulating film.

16. The semiconductor device according to claim 10, wherein, The fourth pattern is disposed on the lower surface of the substrate.

17. The semiconductor device according to claim 10, wherein, The back-side isolation structure is disposed on the bottom surface of the gate insulating film.

18. The semiconductor device according to claim 10, wherein, The width of each of the back-side isolation structures gradually decreases in the vertical direction toward the substrate.

19. A semiconductor device, comprising: Substrate, including active patterning; A device isolation film is provided on the substrate and defines the active pattern; Channel pattern and source / drain pattern, on the active pattern, the source / drain pattern includes a first source / drain pattern and a second source / drain pattern that are horizontally spaced apart from each other; Gate electrode, on the channel pattern; A gate insulating film is disposed between the gate electrode and the channel pattern; Gate spacers are located on the sidewalls of the gate electrode. A gate capping pattern is present on the upper surface of the gate electrode; An interlayer insulating film covers the source / drain pattern and the gate capping pattern; An active contact portion is provided, which penetrates the interlayer insulating film to electrically connect to the first source / drain pattern; A metal-semiconductor compound layer is situated between the active contact portion and the first source / drain pattern; A gate contact portion penetrates the interlayer insulating film and the gate capping pattern to be electrically connected to the gate electrode; The lower electric field line is disposed below the substrate; A back-side active contact penetrates the substrate to electrically connect the lower power line and the second source / drain pattern; as well as A back-side isolation structure penetrates the substrate and the back-side active contact portion, and is disposed on the gate insulating film. Wherein, the bottom surface of the back-side isolation structure is coplanar with the bottom surface of the back-side active contact and the upper surface of the lower electric field line, and The upper surface of the back-side isolation structure is in contact with the bottom surface of the gate insulating film.

20. The semiconductor device of claim 19, further comprising: A first metal layer, on the interlayer insulating film, includes a first line electrically connected to the gate contact portion; as well as A second metal layer, on top of the first metal layer, includes a second line electrically connected to the first metal layer, and The back-side isolation structure includes: The first part includes the first side surface; The second part, on the first part, includes a second side surface; and The third part, on top of the second part, includes a third side surface. The first side surface is in direct contact with the back-side conductive pattern of the back-side active contact portion. The second side surface is in direct contact with the back-side blocking pattern of the back-side active contact portion, and The third side surface is in direct contact with the substrate.

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