Semiconductor device and manufacturing method thereof
By forming a conductive interconnect structure that extends through the substrate in SOI devices, the problems of electron accumulation and poor thermal conductivity are solved, thereby improving the reliability and stability of the devices.
Patent Information
- Application Number
- CN202511111596.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-08
- Publication Date
- 2025-11-14
AI Technical Summary
Existing SOI devices suffer from electron accumulation and poor thermal conductivity due to buried oxide layers, which affects the stability and reliability of the devices.
By forming a first conductive connection structure that extends through the substrate in the dielectric layer, transistor body region, and buried oxide layer, a charge release channel and a heat conduction path are constructed, including forming vias and filling them with conductive material to achieve electrical connection and heat conduction.
It effectively avoids plasma damage caused by electron accumulation, improves the thermal conductivity of the device, and enhances the reliability and stability of the device.
Smart Images
Figure CN120957490A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device and a method for manufacturing the same. Background Technology
[0002] In existing technologies, silicon-on-insulator (SOI) devices are widely used in RF switches and low-noise amplifiers due to their excellent RF performance. Their core advantages include higher isolation, lower substrate coupling, smaller parasitic capacitance, and the absence of latch-up effects. Furthermore, they achieve functionality through a stacked structure of top silicon, a buried oxide layer (BOX), and a hand wafer. The active region of the device is formed in the top silicon, while the buried oxide layer acts as an isolation layer between the top silicon and the hand wafer, forming the basic structural framework of the SOI device.
[0003] However, existing SOI devices are limited by their structural characteristics and have at least the following drawbacks: electrons generated during transistor processing and / or operation tend to accumulate inside the device, which can lead to problems such as plasma damage and adversely affect the stability and reliability of the device. Summary of the Invention
[0004] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.
[0005] To address the existing problems, this application provides a method for manufacturing a semiconductor device, comprising:
[0006] A substrate is provided, on which a buried oxide layer is disposed, and a transistor and a dielectric layer covering the transistor are formed on the buried oxide layer;
[0007] A first conductive connection structure is formed, which extends from the side of the dielectric layer away from the substrate toward the substrate, sequentially penetrating the dielectric layer, the body region of the transistor, and the buried oxide layer, and forming an electrical connection with the substrate.
[0008] In some embodiments of this application, forming the first conductive connection structure includes:
[0009] A via is formed, the via extending from the side of the dielectric layer away from the substrate toward the substrate, sequentially penetrating the dielectric layer, the body region of the transistor, and the buried oxide layer, and exposing the substrate;
[0010] The through-hole is filled with conductive material to form the first conductive connection structure.
[0011] In some embodiments of this application, the process further includes:
[0012] An anti-reflective layer is formed on the dielectric layer, and the via extends from the side of the anti-reflective layer away from the substrate toward the substrate, sequentially penetrating the anti-reflective layer, the dielectric layer, the body region of the transistor, and the buried oxide layer, and exposing the substrate.
[0013] In some embodiments of this application, after filling the through-hole with conductive material, the method further includes: removing the anti-reflective layer and the conductive material located in the anti-reflective layer.
[0014] In some embodiments of this application, a trap-rich layer is formed in the region of the substrate near the buried oxide layer, and the end of the first conductive connection structure near the buried oxide layer is electrically connected to the trap-rich layer.
[0015] In some embodiments of this application, the semiconductor device further includes at least three second conductive connection structures, which extend from the side of the dielectric layer away from the transistor toward the dielectric layer and through the dielectric layer, and at least one of the at least three second conductive connection structures near the transistor is electrically connected to the source of the transistor, at least one is electrically connected to the drain of the transistor, and at least one is electrically connected to the gate of the transistor.
[0016] This application further provides a semiconductor device, comprising:
[0017] Substrate;
[0018] A buried oxide layer is located on the substrate;
[0019] Transistors are located on the buried oxide layer;
[0020] A dielectric layer covering the transistor;
[0021] The first conductive connection structure extends from the side of the dielectric layer away from the substrate toward the substrate, sequentially penetrating the dielectric layer, the body region of the transistor, and the buried oxide layer, and forms an electrical connection with the substrate.
[0022] In some embodiments of this application, a trap-rich layer is formed in the region of the substrate near the buried oxide layer, and the end of the first conductive connection structure near the buried oxide layer is electrically connected to the trap-rich layer.
[0023] In some embodiments of this application, at least three second conductive connection structures are further included. The at least three second conductive connection structures extend from the side of the dielectric layer away from the transistor toward the dielectric layer and penetrate the dielectric layer. At least one of the at least three second conductive connection structures near the transistor is electrically connected to the source of the transistor, at least one is electrically connected to the drain of the transistor, and at least one is electrically connected to the gate of the transistor.
[0024] In some embodiments of this application, the semiconductor device is a silicon-on-insulator device.
[0025] The semiconductor device and its manufacturing method disclosed in this application form a first conductive connection structure that penetrates the dielectric layer, the transistor body region, and the buried oxide layer and is electrically connected to the substrate. On the one hand, this constructs a direct channel for the release of excess charge generated during transistor processing and operation to the substrate, effectively avoiding plasma damage caused by electron accumulation. On the other hand, by utilizing the thermal conductivity of the first conductive structure, a thermal conduction path from the transistor to the substrate is established, significantly improving the thermal conductivity of the device. Thus, while ensuring the stability of the core electrical performance of the device, the reliability and stability of the device are improved. Attached Figure Description
[0026] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.
[0027] In the attached image:
[0028] Figure 1 A cross-sectional schematic diagram of an existing SOI device is shown;
[0029] Figure 2 A partial top cross-sectional view of an existing SOI device is shown;
[0030] Figure 3 A flowchart illustrating a method for manufacturing a semiconductor device according to a specific embodiment of this application is shown;
[0031] Figures 4A-4D A cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of this application is shown.
[0032] Figure 5 It shows Figure 4D A partial top-view cross-section. Detailed Implementation
[0033] The following description provides numerous specific details to offer a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described to avoid confusion with this application.
[0034] It should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.
[0035] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.
[0036] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0037] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0038] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.
[0039] Figure 1 and Figure 2 This illustrates a silicon-on-insulator device in the prior art. Figure 1 It is along Figure 2 A cross-sectional view from a mid-AA perspective. The silicon-on-insulator device, from bottom to top, consists of: a substrate wafer 101 (Handle Wafer); a trap-rich layer 102 grown in the substrate wafer; a buried oxide layer 103 (BOX) providing electrical isolation between the top silicon and the substrate; a top silicon layer deposited above the buried oxide layer 103, integrating core functional units, wherein a transistor 104 is constructed within the top silicon layer, comprising a gate (G), a source (S), a drain (D), and a body region (B); and a dielectric layer 105 covering the transistor, in which conductive plugs 106 are formed, respectively electrically connected to the gate (G), source (S), drain (D), and body region (B). Figure 1 Due to viewing angle limitations, the conductive plug 106, which is electrically connected to the gate G and the body region B, is not shown in the middle.
[0040] Existing SOI devices are limited by their structural characteristics and have at least the following defects: Because the buried oxide layer 103 physically isolates the top silicon and the substrate wafer 101, the thermal conductivity of the device is poor and heat is difficult to dissipate effectively through the substrate; at the same time, electrons generated during transistor processing and / or operation (such as charges caused by plasma processing) cannot be released and are prone to accumulate inside the device, which can lead to problems such as plasma damage and adversely affect the stability and reliability of the device.
[0041] Therefore, in view of the aforementioned technical problems, this application proposes a method for manufacturing a semiconductor device, such as... Figure 3 The above includes:
[0042] Step S1: Provide a substrate, on which a buried oxide layer is disposed, and on which a transistor and a dielectric layer covering the transistor are formed;
[0043] Step S2: A first conductive connection structure is formed. The first conductive connection structure extends from the side of the dielectric layer away from the substrate toward the substrate, sequentially penetrating the dielectric layer, the body region of the transistor, and the buried oxide layer, and forms an electrical connection with the substrate.
[0044] In this application, by forming a first conductive connection structure that penetrates the dielectric layer, the transistor body region, and the buried oxide layer and is electrically connected to the substrate, on the one hand, a direct channel for releasing excess charge generated during transistor processing and operation to the substrate is constructed, effectively avoiding plasma damage caused by electron accumulation; on the other hand, by utilizing the thermal conductivity characteristics of the first conductive structure, a thermal conduction path from the transistor to the substrate is established, significantly improving the thermal conductivity of the device, thereby enhancing the reliability and stability of the device while ensuring the stability of the core electrical performance of the device.
[0045] Example 1
[0046] Below, for reference Figure 3 , Figures 4A to 4D and Figure 5 The method for manufacturing the semiconductor device of this application is described in detail, wherein, Figure 3 A flowchart illustrating a method for manufacturing a semiconductor device according to a specific embodiment of this application is shown; Figures 4A to 4D A cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of this application is shown. Figure 5 It shows Figure 4D A partial top-view cross-sectional view. Among them, Figure 4D It is along Figure 5 A cross-sectional view from the perspective of the middle BB.
[0047] For example, the method for manufacturing a semiconductor device according to this application includes the following steps:
[0048] First, execute step S1, as follows: Figure 4A As shown, a substrate 201 is provided, a buried oxide layer 203 is disposed on the substrate 201, a transistor 204 is formed on the buried oxide layer 203, and a dielectric layer 205 covering the transistor 204 is formed.
[0049] For example, the substrate 201 can be any suitable semiconductor substrate, such as a silicon substrate, or it can be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including multilayer structures composed of these semiconductor materials, or it can be silicon on insulator (SOI), silicon on insulator (SSOI), silicon on insulator (S-SiGeOI), silicon on insulator (SiGeOI) and germanium on insulator (GeOI), or it can be a double-side polished wafer (DSP), or it can be a ceramic substrate such as alumina, a quartz or glass substrate, etc.
[0050] In one specific embodiment, the semiconductor device may be a silicon-on-insulator device.
[0051] In some embodiments, such as Figure 4A and Figure 5 As shown, the semiconductor device further includes at least three second conductive connection structures 206. The at least three second conductive connection structures 206 extend from the side of the dielectric layer 205 away from the transistor 204 toward the dielectric layer 205 and penetrate the dielectric layer 205. Among the at least three second conductive connection structures 206 near the end of the transistor 204, at least one is electrically connected to the source S of the transistor 204, at least one is electrically connected to the drain D of the transistor 204, and at least one is electrically connected to the gate G of the transistor 204.
[0052] For example, at least three contact holes can be formed through photolithography and etching processes. For instance, photoresist is coated onto the surface of dielectric layer 205 using photolithography, and a patterned photoresist layer is formed by exposure using a mask to define the position and size parameters of at least three contact holes. Subsequently, an etching process is used, using the patterned photoresist layer as a mask, to etch dielectric layer 205 until the source (S), drain (D), and gate (G) of transistor 204 are exposed. During etching, the uniformity of the etching rate and the accuracy of the etching depth are ensured by precisely controlling the etching gas composition, RF power, and gas pressure parameters, thereby forming at least three contact holes. After etching, residual photoresist is removed using an oxygen plasma ashing process.
[0053] Subsequently, conductive material can be deposited in each contact hole using methods commonly used in the art, such as physical vapor deposition, chemical vapor deposition, or atomic layer deposition, to form a second conductive connection structure 206 in each contact hole. The conductive material used for filling can be a metallic material such as tungsten, and there is no limitation thereto. After the conductive material has filled the contact hole cavity, the process further includes: planarization to remove excess conductive material outside the contact hole area. Exemplarily, non-limiting examples of this planarization method include mechanical planarization or chemical mechanical polishing planarization.
[0054] Next, step S2 is performed to form a first conductive connection structure 209. The first conductive connection structure 209 extends from the side of the dielectric layer 205 away from the substrate 201 toward the substrate 201, and sequentially penetrates the dielectric layer 205, the body region B of the transistor 204 and the buried oxide layer 203, and forms an electrical connection with the substrate 201.
[0055] In some embodiments, forming the first conductive connection structure 209 may include the following steps S211 to S212:
[0056] Step S211, as follows Figure 4C As shown, a via 208 is formed. The via 208 extends from the side of the dielectric layer 205 away from the substrate 201 toward the substrate 201, and sequentially penetrates the dielectric layer 205, the body region B of the transistor 204 and the buried oxide layer 203, and exposes the substrate 201.
[0057] For example, the via 208 can be formed by photolithography and etching processes. For instance, photoresist is coated onto the surface of the dielectric layer 205 using photolithography, and a patterned photoresist layer is formed by exposure using a mask to define the position and size parameters of the via 208. Subsequently, an etching process is used, using the patterned photoresist layer as a mask, to sequentially etch the dielectric layer 205, the body region B of the transistor 204, and the buried oxide layer 203 until the surface of the substrate 201 is exposed. During the etching process, the uniformity of the etching rate and the accuracy of the etching depth are ensured by precisely controlling the etching gas composition, RF power, and gas pressure parameters, thereby forming the via 208. After etching, residual photoresist is removed using an oxygen plasma ashing process.
[0058] Step S212, as follows Figure 4D As shown, conductive material is filled into the through hole 208 to form a first conductive connection structure 209.
[0059] Exemplarily, conductive material can be deposited in the via 208 using methods commonly used in the art, such as physical vapor deposition, chemical vapor deposition, or atomic layer deposition, to form a first conductive connection structure 209 in the via 208. The conductive material used can be a metallic material such as tungsten, and there is no limitation thereto. After the conductive material fills the cavity of the via 208, the process further includes: planarization to remove excess conductive material outside the region of the via 208. Exemplarily, non-limiting examples of this planarization method include mechanical planarization or chemical mechanical polishing planarization.
[0060] By forming the first conductive connection structure 209, on the one hand, a channel is provided in the substrate 201 for the release of excess charge generated during transistor processing and operation, avoiding the risk of plasma damage caused by charge accumulation inside the device, and solving the problem of difficult charge release caused by the buried oxide layer 203 isolation in existing SOI devices; on the other hand, by utilizing the thermal conductivity characteristics of the first conductive structure, a heat transfer path is opened from the transistor 204 to the substrate 201, effectively improving the thermal conductivity bottleneck caused by the insulation isolation of the buried oxide layer 203, and improving the thermal conductivity of the device. This solves the problems of charge not being able to be released and poor thermal conductivity in existing technologies, improving the reliability and stability of semiconductor devices.
[0061] In other embodiments, such as Figure 4B As shown, before forming the via 208, the method further includes: forming an anti-reflection layer 207 on the dielectric layer 205, and the via 208 extending from the side of the anti-reflection layer 207 away from the substrate 201 toward the substrate 201, sequentially penetrating the anti-reflection layer 207, the dielectric layer 205, the bulk region B of the transistor 204 and the buried oxide layer 203 and exposing the substrate 201.
[0062] For example, the anti-reflection layer 207 can be formed using deposition methods commonly used in the art, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. By providing the anti-reflection layer 207, the reflection interference of incident light on the surface of the dielectric layer 205 during photolithography can be effectively reduced, improving the photolithographic resolution and dimensional accuracy of the via 208 pattern, laying the foundation for the subsequent formation of a precisely penetrating first conductive connection structure 209, and ensuring the reliable realization of its electrical connection and thermal conduction functions.
[0063] It is worth noting that after filling the via 208 with conductive material, the process also includes removing the anti-reflective layer 207 and the conductive material within it. Specifically, selective dry etching or chemical mechanical polishing processes can be used to simultaneously remove the conductive material inside the anti-reflective layer 207, ensuring that the top of the first conductive connection structure 209 is flush with the surface of the dielectric layer 205 facing away from the substrate 201, thus avoiding excess material residue that could interfere with the device surface flatness and subsequent processes.
[0064] In some embodiments, such as Figure 4D As shown, a trap-rich layer 202 is formed in the region of substrate 201 near the buried oxide layer 203. This trap-rich layer 202 can be formed by ion implantation (using suitable dopant ions) into the region of substrate 201 near the buried oxide layer 203, combined with subsequent thermal processing, to construct a functional region with a high defect state density on the surface of substrate 201. The end of the first conductive connection structure 209 near the buried oxide layer 203 is electrically connected to the trap-rich layer 202. By setting the trap-rich layer 202, the ability to capture and temporarily store excess electrons generated during transistor processing and operation can be enhanced. Combined with the charge discharge channel of the first conductive connection structure 209, the electron release efficiency can be further improved. At the same time, by leveraging its synergistic effect with the first conductive connection structure 209, the suppression effect of plasma damage can be improved while ensuring the stability of the core electrical performance of the device, thereby improving the reliability of the device.
[0065] This concludes the description of the key steps in the semiconductor device manufacturing method of this application. The complete semiconductor device manufacturing method may also include other steps, which will not be elaborated here. It is worth mentioning that the order of the above steps can be adjusted without conflict.
[0066] In summary, the semiconductor device manufacturing method of this application, by forming a first conductive connection structure 209 that penetrates the dielectric layer 205, the bulk region B of the transistor 204, and the buried oxide layer 203 and is electrically connected to the substrate 201, on the one hand, constructs a direct channel for the release of excess charge generated during transistor processing and operation to the substrate 201, effectively avoiding plasma damage caused by electron accumulation; on the other hand, by utilizing the thermal conductivity characteristics of the first conductive structure, a thermal conduction path is established from the transistor 204 to the substrate 201, significantly improving the thermal conductivity of the device, thereby enhancing the reliability and stability of the device while ensuring the stability of the core electrical performance of the device.
[0067] Example 2
[0068] This application also provides a semiconductor device. Referring below, [further details are provided]. Figure 4D and Figure 5 This application provides a detailed description and explanation of the semiconductor device.
[0069] Specifically, such as Figure 4D and Figure 5 As shown, the semiconductor device of this application includes:
[0070] Substrate 201;
[0071] Buried oxide layer 203 is located on substrate 201;
[0072] Transistor 204 is located on buried oxide layer 203;
[0073] Dielectric layer 205 covers transistor 204;
[0074] The first conductive connection structure 209 extends from the side of the dielectric layer 205 away from the substrate 201 toward the substrate 201, and sequentially penetrates the dielectric layer 205, the body region B of the transistor 204 and the buried oxide layer 203, and forms an electrical connection with the substrate 201.
[0075] In some embodiments, continue as follows Figure 4D and Figure 5 As shown, the semiconductor device further includes at least three second conductive connection structures 206. The at least three second conductive connection structures 206 extend from the side of the dielectric layer 205 away from the transistor 204 toward the dielectric layer 205 and penetrate the dielectric layer 205. Among the at least three second conductive connection structures 206 near the end of the transistor 204, at least one is electrically connected to the source S of the transistor 204, at least one is electrically connected to the drain D of the transistor 204, and at least one is electrically connected to the gate G of the transistor 204.
[0076] In some embodiments, continue as follows Figure 4D and Figure 5 As shown, a trap-rich layer 202 is formed in the region of the substrate 201 near the buried oxide layer 203, and the end of the first conductive connection structure 209 near the buried oxide layer 203 is electrically connected to the trap-rich layer 202.
[0077] In some embodiments, the semiconductor device is a silicon-on-insulator device.
[0078] It is understood that the semiconductor device in this embodiment can be manufactured by the method in the aforementioned embodiment one. In order to avoid repetition, only a brief description is given for the same components and structures as in the aforementioned embodiment one. For specific explanations and descriptions, please refer to the description in embodiment one.
[0079] According to the semiconductor device of this application, by setting a first conductive connection structure 209 that penetrates the dielectric layer 205, the bulk region B of the transistor 204 and the buried oxide layer 203 and is electrically connected to the substrate 201, a direct channel for releasing excess charge generated during transistor processing and operation to the substrate 201 is constructed, effectively avoiding plasma damage caused by electron accumulation. On the other hand, by utilizing the thermal conductivity of the first conductive structure, a thermal conduction path from the transistor 204 to the substrate 201 is established, significantly improving the thermal conductivity of the device. Thus, while ensuring the stability of the core electrical performance of the device, the reliability and stability of the device are improved.
[0080] This application has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit this application to the scope of the described embodiments. Furthermore, those skilled in the art will understand that this application is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of this application, all of which fall within the scope of protection claimed in this application. The scope of protection of this application is defined by the appended claims and their equivalents.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, on which a buried oxide layer is disposed, and a transistor and a dielectric layer covering the transistor are formed on the buried oxide layer; A first conductive connection structure is formed, which extends from the side of the dielectric layer away from the substrate toward the substrate, sequentially penetrating the dielectric layer, the body region of the transistor, and the buried oxide layer, and forming an electrical connection with the substrate.
2. The method as described in claim 1, characterized in that, The formation of the first conductive connection structure includes: A via is formed, the via extending from the side of the dielectric layer away from the substrate toward the substrate, sequentially penetrating the dielectric layer, the body region of the transistor, and the buried oxide layer, and exposing the substrate; The through-hole is filled with conductive material to form the first conductive connection structure.
3. The method as described in claim 2, characterized in that, The process includes the following steps prior to forming the through hole: An anti-reflective layer is formed on the dielectric layer, and the via extends from the side of the anti-reflective layer away from the substrate toward the substrate, sequentially penetrating the anti-reflective layer, the dielectric layer, the body region of the transistor, and the buried oxide layer, and exposing the substrate.
4. The method as described in claim 3, characterized in that, After filling the through-hole with conductive material, the process further includes: removing the anti-reflective layer and the conductive material located in the anti-reflective layer.
5. The method as described in claim 1, characterized in that, A trap-rich layer is formed in the region of the substrate near the buried oxide layer, and the end of the first conductive connection structure near the buried oxide layer is electrically connected to the trap-rich layer.
6. The method as described in claim 1, characterized in that, The semiconductor device further includes at least three second conductive connection structures, which extend from the side of the dielectric layer away from the transistor toward the dielectric layer and through the dielectric layer. At least one of the at least three second conductive connection structures near the transistor is electrically connected to the source of the transistor, at least one is electrically connected to the drain of the transistor, and at least one is electrically connected to the gate of the transistor.
7. A semiconductor device, characterized in that, include: Substrate; A buried oxide layer is located on the substrate; Transistors are located on the buried oxide layer; A dielectric layer covering the transistor; The first conductive connection structure extends from the side of the dielectric layer away from the substrate toward the substrate, sequentially penetrating the dielectric layer, the body region of the transistor, and the buried oxide layer, and forms an electrical connection with the substrate.
8. The semiconductor device as claimed in claim 7, characterized in that, A trap-rich layer is formed in the region of the substrate near the buried oxide layer, and the end of the first conductive connection structure near the buried oxide layer is electrically connected to the trap-rich layer.
9. The semiconductor device as claimed in claim 7, characterized in that, It also includes at least three second conductive connection structures, which extend from the side of the dielectric layer away from the transistor toward the dielectric layer and through the dielectric layer, and at least one of the at least three second conductive connection structures near the transistor is electrically connected to the source of the transistor, at least one is electrically connected to the drain of the transistor, and at least one is electrically connected to the gate of the transistor.
10. The semiconductor device as claimed in claim 7, characterized in that, The semiconductor device is a silicon-on-insulator device.