Computing system and semiconductor integrated circuit module

Abstract

Provided is a computing system capable of flexibly handling various applications with a wide bandwidth and low power consumption in a stacked DRAM circuit. A DRAM circuit (400) includes a plurality of memory blocks that can be accessed independently and are logically two-dimensionally arranged so as to be recognized by an index number and a bucket number. A non-volatile memory (106) stores a reference table indicating that valid data is held in each memory block. A memory controller (111) stacked in a CPU (100) of a DRAM circuit (400) refers to a reference table in a non-volatile memory (106), and excludes a memory block that does not hold valid data from access objects even if the memory block is selected by an index number, from among memory blocks accessed simultaneously in the direction of a bucket number.

Description

Technical Field

[0001] This invention relates to computing systems and semiconductor integrated circuit modules, and particularly to the structure of computing systems and semiconductor integrated circuit modules that employ stacked dynamic random access memory as associative random access memory. Background Technology

[0002] (Stacked semiconductor integrated circuit module)

[0003] Previously, volatile memory (RAM) such as DRAM (Dynamic Random Access Memory) was known as a storage device. For DRAM, there was a demand for larger capacities to withstand the increasing performance and data volume of computing devices (hereinafter referred to as logic chips). Therefore, larger capacities were achieved through miniaturization of memory (memory cell arrays, memory chips) and planar expansion of cells. On the other hand, due to the vulnerability to noise caused by miniaturization and the increase in chip area, such capacity expansion has reached its limits.

[0004] Therefore, in recent years, technologies have been developed to stack multiple planes of memory to achieve three-dimensional (3D) storage and thus increase capacity. Furthermore, with the increasing volume of data, there is a growing demand for higher speeds of data communication between chips (logic chips and memory chips). For example, semiconductor modules with overlapping configurations of logic chips and DRAM are known (see, for example, Non-Patent Literature 1).

[0005] For example, there are known three-dimensional or 2.5-dimensional mounting techniques in which multiple IC wafers (IC chips) are mounted in a three-dimensional semiconductor integrated circuit module using a Si interposer layer employing TSV (Through Silicon Via) technology. According to such mounting techniques, high-density wiring can be formed on multiple IC wafers (IC chips), enabling miniaturization, thin-film fabrication, and broadband operation.

[0006] However, from the perspective of reducing manufacturing costs, Patent Document 1 discloses a three-dimensional or 2.5-dimensional mounting technology that uses a redistribution layer (RDL) and small Si bridging wafers to replace such a Si interposer, and then mounts multiple IC wafers (IC chips) on top of these. IC modules that use a redistribution layer to mount multiple IC wafers (chips) in this way are mostly manufactured using FOWLP (Fan Out Wafer Level Package) technology. According to this mounting technology, high-density wiring can be formed for multiple IC wafers (IC chips) at a lower cost, enabling miniaturization, thin-film construction, and wide bandwidth.

[0007] However, from the perspective of high speed and high performance, for example, Non-Patent Document 1 discloses a structure that uses so-called "Hybrid Bonding technology" to stack DRAM circuit chips and logic circuit chips.

[0008] In other words, by using a so-called flip-chip structure, interconnect electrodes are arranged in a two-dimensional array in a direction perpendicular to the silicon surface (or substrate surface), stacking silicon wafers or silicon slabs manufactured using different process technologies. This allows multiple functions to be housed in a single package. Compared to integrating multiple functions with different processes on a single silicon wafer (monochip), many functions can be mounted at a lower cost. In three-dimensional stacking, the interconnect technology during silicon stacking is crucial. To improve data transmission per unit area, different silicon chips need to be interconnected at high density. Therefore, a "hybrid bonding" technique is used, where copper (Cu) electrodes formed on the surface of silicon wafers or silicon slabs are bonded and connected to each other.

[0009] For example, Non-Patent Document 2 discloses a technique for hybrid bonding and stacking a DRAM wafer composed of 36 1Gb DRAM cores and a logic wafer having the same size as the DRAM wafer in a wafer state. The logic wafer has a memory controller corresponding to each DRAM core. The logic wafer can directly access the corresponding DRAM block through the memory controller, and can access all memory blocks through the on-chip bus.

[0010] In addition, Non-Patent Document 1 also discloses a technique for hybrid bonding and stacking a DRAM chip consisting of 12 4Gb DRAM partitions and a logic chip having the same size as the DRAM chip in a wafer state, wherein the logic chip has a cluster of processor units corresponding one-to-one with each DRAM partition.

[0011] Furthermore, searching is a widely used technical topic in computer applications. Particularly in the field of communication networks, associative memory (CAM) is widely used. While it offers fast search speeds, it typically suffers from small storage capacity, inability to hold large amounts of data, and high power consumption. For large datasets, a method is used where the data is stored as a table in SRAM (Static Random Access Memory) or DRAM, and the processor performs the search. However, this method often requires multiple memory accesses, resulting in slow search speeds.

[0012] Therefore, Non-Patent Document 3 discloses a technique for providing parallel search functionality using SRAM or DRAM and multiple matching circuits. Record keys are pre-generated based on records and stored at RAM row addresses indicated by corresponding indices. An index (row address) is generated based on the search key, the RAM row containing the target record key is accessed, multiple candidate record keys are read, and input to the matching circuits. The matching circuits determine whether the multiple record keys match the given search key; if they match, the address where the record key exists is returned. If multiple records match, the result, for example, after priority encoding, is returned. If data is stored along with the key, the stored data is returned.

[0013] Existing technical documents

[0014] Patent documents

[0015] Patent Document 1: U.S. Patent Application Publication No. 2020 / 0185367.

[0016] Non-patent literature

[0017] Non-patent literature 1: Xiping Jiang, Student Member, IEEE, Fengguo Zuo, SongWang, Xiaofeng Zhou, Yubing Wang, Qi Liu, Qiwei Ren, Senior Member, IEEE, andMing Liu, “A 1596-GB / s 48-Gb Stacked Embedded DRAM 384-Core SoC With HybridBonding Integration”, IEEE SOLID-STATE CIRCUITS LETTERS, VOL. 5, 2022, pp.110-113

[0018] Non-patent document 2: Dimin Niu1, et al., "184QPS / W 64Mb / mm2 3D Logic-to-DRAMHybrid Bonding with Process-Near-Memory Engine for Recommendation System", 2022 IEEE International Solid-State Circuits Conference (ISSCC)

[0019] Non-patent document 3: Sangyeun Cho, et al., "CA-RAM: A High-Performance MemorySubstrate for Search-Intensive Applications", 2007 IEEE InternationalSymposium on Performance Analysis of Systems & Software Summary of the Invention

[0020] The problem the invention aims to solve

[0021] However, in the technology disclosed in Non-Patent Document 2, the overall structure of 36 DRAM blocks is fixed according to the application, and no technology is disclosed to suppress the increase in power consumption caused by activating multiple blocks, which has problems in terms of flexibility and low power consumption.

[0022] Furthermore, in the technology disclosed in Non-Patent Document 1, since DRAM partitions are accessed via address multiplexing, performance cannot be improved for applications requiring random access. Additionally, for the same reasons as the technology disclosed in Non-Patent Document 2, there are issues with flexibility and low power consumption.

[0023] Furthermore, when stacked DRAM is used as associative memory as disclosed in Non-Patent Document 3, the following problem exists: as the number of records increases and the index spans multiple rows, the search speed slows down because multiple rows are accessed continuously until a match is found.

[0024] The present invention was made to solve the above-mentioned problems, and its purpose is to provide a computing system and a semiconductor integrated circuit module, which is a structure in which semiconductor chips of DRAM circuits are stacked on semiconductor chips with processor circuits, and can flexibly cope with various applications with a wide bandwidth and low power consumption.

[0025] Furthermore, the present invention aims to provide a computing system and a semiconductor integrated circuit module that can suppress power consumption and improve search speed in DRAM circuits stacked on processor circuits and operating as associative memory.

[0026] Solution for solving the problem

[0027] According to a first aspect of the present invention, a computing system is provided, comprising: a DRAM (Dynamic Random Access Memory) circuit configured with a plurality of storage cells for storing data required for computing processing; the DRAM circuit including a plurality of storage blocks configured in a logical address space that can be accessed independently; a first number and a second number associated with the plurality of storage blocks; the first number for determining storage blocks configured in a logical first direction and accessible simultaneously; and the second number for determining the plurality of storage blocks in a logically orthogonal second direction; the computing system further comprising a processor circuit stacked with the DRAM circuit; the processor circuit including: a storage circuit storing flags indicating that each storage block holds valid data in a valid block reference table composed of the first number and the second number; at least one processor core; and a controller controlling access to storage cells in the storage blocks of the DRAM circuit in the first direction according to a selection signal from the processor core; the controller selecting storage blocks in the second direction based on the selection signal; and, referring to the valid block reference table, excluding storage blocks that do not hold valid data in the storage blocks accessed simultaneously in the first direction from the access targets, even if selected by the second number.

[0028] Preferably, the DRAM circuit is an associative random access memory that reads stored data according to a search key. The first direction is the direction of the word line used to select the memory cell. The controller performs the following processing: i) receiving the search key as a selection signal, generating an index and an index number, wherein the index is used to specify the word line of multiple memory blocks that can be accessed simultaneously, and the index number is used as the second number to specify the memory block selected by the index; ii) determining the first number of the memory block to be specified for access based on the index number and the valid block reference table.

[0029] Preferably, the processor circuit includes a comparison circuit that compares key data in read data from a storage cell selected by a first number and an index number with a search key, and outputs the record data corresponding to the key data that matches the comparison result.

[0030] Preferably, the memory blocks selected in the first direction are divided into multiple groups with time differences set for access. The memory circuit stores the access order as a delay order reference table for the multiple groups. The controller refers to the delay order reference table and accesses the memory blocks in the first direction according to the access order.

[0031] Preferably, the storage circuit stores a bad block reference table as a flag representing the memory blocks containing bad bits among multiple memory blocks. The controller refers to the bad block reference table and excludes the memory block containing bad bits from the access objects, even if it is selected by the second number.

[0032] Preferably, the controller refers to the valid block reference table and only performs refresh operations on the storage blocks that have retained valid data.

[0033] Preferably, the DRAM circuit includes a memory input / output circuit that controls the reading and writing of data from multiple memory cells. The memory input / output circuit is for row address and column address, and non-multiplexed control is used to select the input of the address signal of the memory cell.

[0034] Preferably, the memory input / output circuit has multiple data input / output pads, and the memory input / output circuit continuously performs burst reads or burst writes of data from the multiple data input / output pads.

[0035] Preferably, it includes: a setting circuit that can statically set or dynamically change the operating mode of the memory input / output circuit, and the setting circuit sets the number of consecutive data accesses during burst reads or burst writes.

[0036] Preferably, within the physical configuration of the storage blocks of the DRAM circuit, the storage circuit stores the logical configuration of the storage blocks. The controller variably controls the logical configuration of the storage blocks during the reading and writing operations of the DRAM circuit according to the configuration stored in the storage circuit.

[0037] Preferably, a memory wafer including multiple DRAM circuits and a processor wafer including multiple processor circuits are stacked in wafer state and then monolithized after stacking.

[0038] According to another aspect of the present invention, a computing system is provided, comprising: a DRAM (Dynamic Random Access Memory) circuit configured with a plurality of storage cells for storing data required for computing processing; the DRAM circuit including a plurality of storage blocks that are independently accessible and logically arranged in one dimension; each of the plurality of storage blocks being associated with a first number for identifying a row selected within the plurality of storage blocks; the computing system further comprising a processor circuit stacked with the DRAM circuit; the processor circuit including: at least one processor core; and a controller that controls access to storage cells within the storage blocks of the DRAM circuit based on a selection signal from the processor core; the controller generating a first number based on the selection signal and accessing the plurality of storage blocks respectively.

[0039] Preferably, the storage blocks selected in the one-dimensional direction are divided into multiple groups with time differences set for access. The storage circuit stores the access order as a delay order reference table for the multiple groups. When the controller accesses multiple storage blocks simultaneously, it refers to the delay order reference table and accesses the storage blocks in the one-dimensional direction according to the access order.

[0040] Preferably, the storage circuit stores a bad block reference table as a flag representing the storage blocks containing bad bits among multiple storage blocks, and the controller refers to the bad block reference table to exclude storage blocks containing bad bits from the access objects.

[0041] Preferably, the DRAM circuit includes a memory input / output circuit that controls the reading and writing of data from multiple memory cells. The memory input / output circuit is for row address and column address, and non-multiplexed control is used to select the input of the address signal of the memory cell.

[0042] Preferably, the memory input / output circuit has multiple data input / output pads, and the memory input / output circuit continuously performs burst reads or burst writes of data from the multiple data input / output pads.

[0043] Preferably, it includes: a setting circuit that can statically set or dynamically change the operating mode of the memory input / output circuit, and the setting circuit sets the number of consecutive data accesses during burst reads or burst writes.

[0044] According to another aspect of the present invention, a semiconductor integrated circuit module is provided, which has multiple chips stacked on top of each other. The semiconductor integrated circuit module includes: a first integrated circuit chip, which includes DRAM (Dynamic Random Access DRAM) chips. The DRAM circuit is configured with multiple storage cells for storing data required for computational processing. The DRAM circuit includes multiple wafers, each corresponding to a plurality of independently accessible storage blocks configured in a logical address space. A first number and a second number are associated with each storage block. The first number identifies storage blocks configured in a logical first direction that can be accessed simultaneously, and the second number identifies storage blocks in a logically orthogonal second direction. The semiconductor integrated circuit module also includes a second integrated circuit chip, which includes a processor circuit for performing computational processing. The processor circuit is stacked with the DRAM circuit in a manner capable of transmitting and receiving data. The second integrated circuit chip includes: a storage circuit that stores flags indicating that each storage block holds valid data in a valid block reference table composed of the first and second numbers; at least one processor core; and a controller that controls access to storage cells in the storage blocks of the DRAM circuit in the first direction based on a selection signal from the processor core. The controller selects storage blocks in the second direction based on the selection signal. Referring to the valid block reference table, for storage blocks in the storage blocks accessed simultaneously in the first direction that do not hold valid data, even if selected by the second number, they are excluded from the access list.

[0045] Invention Effects

[0046] According to the semiconductor integrated circuit module of the present invention, power consumption can be reduced by optimizing the structure of the memory chip of the DRAM circuit and eliminating unnecessary block accesses.

[0047] Furthermore, the semiconductor integrated circuit module according to the present invention can provide a high-speed and low-power search system. Attached Figure Description

[0048] Figure 1 This is a function block diagram used to illustrate the structure of an arithmetic system 1000, which includes a CPU 100 and a DRAM circuit 400.

[0049] Figure 2 This is a schematic diagram illustrating the structure of the memory blocks in the DRAM chip that constitutes the DRAM circuit 400.

[0050] Figure 3 This is a schematic diagram showing the structure of data stored within a storage block.

[0051] Figure 4This is a function block diagram used to illustrate the structure of the memory controller 111 in the logic chip 300.

[0052] Figure 5 This is a cross-sectional view showing the structure of the CPU100 and DRAM circuit 400, which are stacked together.

[0053] Figure 6 This is a diagram showing the relationship between the CPU100 and DRAM circuit 400 stacked as a silicon wafer in the logic circuit.

[0054] Figure 7 This is a schematic diagram illustrating an example of the logical structure when accessing a storage block.

[0055] Figure 8 This is a schematic diagram illustrating an example of the structure where valid data exists in a block table.

[0056] Figure 9 This is a diagram illustrating an example of the physical structure of a DRAM memory block.

[0057] Figure 10 This is a timing diagram illustrating the patterns of memory block access.

[0058] Figure 11 This is a schematic diagram illustrating an example of how DRAM wafer dimensions are set.

[0059] Figure 12 This is a schematic diagram illustrating an example of the configuration of index numbers and bucket numbers in a variation of Embodiment 1.

[0060] Figure 13 This is a schematic diagram illustrating an example of the configuration of index numbers and bucket numbers in a variation of embodiment 1, example 2.

[0061] Figure 14 This is a schematic diagram illustrating an example of the configuration of index numbers and bucket numbers in a variation of embodiment 1, example 3.

[0062] Figure 15 This is a schematic diagram illustrating an example of the structure of a delayed access order setting table.

[0063] Figure 16 This is a timing diagram illustrating the pattern of read operations with delayed access.

[0064] Figure 17 This is a schematic diagram illustrating an example of the structure of a bad block reference table.

[0065] Figure 18 This is a schematic diagram illustrating other structures of the storage space in the DRAM circuit 400.

[0066] Figure 19This is a function block diagram used to illustrate the structure of the memory controller 111 in the logic chip relative to the DRAM circuit 400. Detailed Implementation

[0067] The structure of the semiconductor integrated circuit module according to embodiments of the present invention will be described below. Furthermore, in the following embodiments, structural elements and processing steps marked with the same reference numerals are identical or equivalent parts, and their description will not be repeated unless necessary.

[0068] The following description uses a structure where DRAM circuitry is stacked on a CPU (Central Processing Unit), which is a logic circuit (more specifically, a processor circuit), as an example of a semiconductor integrated circuit module. However, this structure is not limited to logic circuits. Furthermore, the arithmetic control circuit that functions independently to perform computational processing is called a "processor core." Therefore, it is also possible for a single processor circuit to carry multiple processor cores (multi-core).

[0069] [Implementation Method 1]

[0070] (Functional structure of semiconductor integrated circuit modules)

[0071] Figure 1 This is a function block diagram used to illustrate the structure of an arithmetic system 1000, which includes a CPU 100 and a DRAM circuit 400.

[0072] Reference Figure 1 The CPU 100 included in the logic chip 300 has a control unit 110 and an arithmetic unit 150.

[0073] Register 112 is not specifically limited, but includes: a program counter for storing the address of the memory containing the instruction to be executed next, and a base address register for storing the starting address when the program is loaded into memory. Furthermore, register 112 is a register for fetching consecutive data, used when the same instruction is repeatedly applied to consecutive data such as arrays, and includes an index register storing the relative positions from the starting address, and an instruction register for temporarily storing the fetched instruction.

[0074] The control unit 110 uses these registers to read instructions and data from the memory, or to perform data writing and other processing.

[0075] The arithmetic unit 150 performs specified bitwise operations based on the read data and instructions. Register 112 includes an accumulator for temporarily storing the operation results.

[0076] In addition, the arithmetic unit 152 is in Figure 1 It is recorded as one, but there can also be multiple cores.

[0077] The CPU 100 also has a cache memory 102. Alternatively, the cache memory 102 can be composed of multiple levels of memory. The cache memory 102 is installed as SRAM (Static Random Access Memory) located on the same chip as the arithmetic unit 152.

[0078] CPU 100 also has an external interface 104 for sending and receiving data with the outside world.

[0079] CPU 100 is connected via external interface 104 to DRAM circuitry 400, which is stacked in three dimensions on the CPU 100 chip. DRAM circuitry 400 is not particularly limited, but can function as an associative random access memory as described later.

[0080] CPU100 can also adopt a structure that transmits and receives data with main memory (not shown) via external interface 104.

[0081] The control unit 110 includes a memory controller 111. The memory controller 111 intercepts accesses from the CPU 100 to the memory and controls accesses to read data from the cache memory 102, the DRAM circuit 400, and the main memory, or to write data to these components. Furthermore, the memory controller 111 is not particularly limited, but as an integrated memory controller, it can be configured to control the refresh operation of the main memory and the DRAM circuit 400.

[0082] A non-volatile memory 102 capable of transmitting and receiving data with the CPU 100 is provided in the logic chip 300. The non-volatile memory 102 is not particularly limited, but can be, for example, flash memory. However, the non-volatile memory 102 is not limited to this structure, and other structures can be used as long as the stored data will not be lost even when the power is cut off.

[0083] DRAM circuit 400 can contain multiple DRAM chips through methods such as stacking. Furthermore, in DRAM circuit 400, independently accessible memory blocks are logically expanded in two dimensions, allowing simultaneous access to the memory blocks. Super-parallel access is achieved by assigning bucket numbers to simultaneously accessed memory blocks and appending index numbers to memory blocks in the direction of indexing, where the indexes specify the word lines to be accessed. The relationship between DRAM chips and memory blocks will be explained later.

[0084] Non-volatile memory 102 stores flags indicating that a storage block holds valid data in a two-dimensional reference table (valid data storage block table) consisting of bucket numbers and index numbers. Even if a block that does not hold valid data is selected by index, the storage controller 111 will exclude it from the access list. Additionally, the table data stored in non-volatile memory 106 can be appropriately read into register 112, a note-style memory (not shown), and used.

[0085] Figure 2 It is used to explain the composition Figure 1 This is a schematic diagram of the structure of the memory block in the DRAM chip of the DRAM circuit 400 shown.

[0086] exist Figure 2 As an example, a DRAM chip with a capacity of 570MB and memory blocks configured in a 16-row, 16-column configuration will be used for illustration. Of course, as will be discussed later, the configuration of multiple memory blocks is not limited to this structure; more generally, memory blocks can be configured in an n-row, m-column structure (n, m: natural numbers).

[0087] Furthermore, although not specifically limited, the structure of the DRAM circuit 400 is described as a circuit that operates as an associative random access memory.

[0088] Multiple storage blocks can be accessed independently and are logically configured in a two-dimensional manner within the address space.

[0089] Bucket number refers to the number used to identify each storage block that is configured along a logical first direction and can be accessed simultaneously among multiple storage blocks.

[0090] Based on the input search key, an index number and an index are generated using the method described later. These serve as numbers indicating the location of the record that is the search target in the logically second direction orthogonal to the first direction. Here, the index number refers to the number used to identify the memory block in the second direction, and the index specifies the row address used to determine the memory row (word line) within the memory block determined by the index number.

[0091] exist Figure 2 In this example, a 570MB (byte) DRAM chip consists of 16 block expansion units (capacity: 35.7MB) configured in a 4×4 shape. Furthermore, each block expansion unit consists of 16 memory blocks (capacity: 2.2MB) configured in a 4×4 shape. As explained later, the block expansion units are surrounded by scribe lines. However, the number of block expansion units constituting the DRAM chip and the number of memory blocks constituting each block expansion unit are not limited to this structure.

[0092] like Figure 2As shown, in the memory block, a control signal input pin (control signal input pad) for inputting instructions and addresses is provided on one side, and a data input / output pin (data input / output pad) for inputting and outputting data is provided on the other side orthogonal to this side.

[0093] During a single write access, multiple sets of data, consisting of record data to be searched and corresponding key data, are sequentially input from the data input / output pins and stored in the DRAM circuit 400. While not specifically limited, it can be assumed, for example, that the total record data and key data is 128 bytes, with 8 bytes of additional information bits.

[0094] like Figure 1 As explained, the non-volatile memory 102 stores a flag indicating that a memory block retains valid data in a two-dimensional reference table consisting of a bucket number and an index number. Figure 2 In this context, halftone screening is used to represent the blocks containing valid data, and diagonal lines are used to represent the blocks to which the selection index belongs and which are selected based on the search key.

[0095] Figure 3 This is a schematic diagram showing the structure of data stored within a storage block.

[0096] Reference Figure 3 Key data and record data are stored in pairs within an index corresponding to the same word line.

[0097] For example, as mentioned above, assuming the total record data and key data is 128B, and using burst write or burst read to perform 8 consecutive writes or reads, the following structure can be used: 128b × 8 = 128B of record data and key data are written into one index, and the remaining 8B is used as information data.

[0098] Here, the recorded data can be data indicating the location of the search object within the database, or it can be the search object itself.

[0099] Here, the index is any number from 1 to 16384. Since each index contains 136 bytes of data, the total storage capacity of each block is 136 bytes × 16384 = 2.2 MB. Furthermore, 16384 is equivalent to 2... 14 It can be determined using a 14-bit address.

[0100] On the other hand, the index number is 1 to 16, which can be determined using a 4-bit address.

[0101] Therefore, in Figure 3In the example, the following structure can be used: For example, an 18-bit address is generated based on the search key, the high 4 bits are used to generate the index number, and the low 14 bits are used to generate the index (equivalent to the address signal used to select the memory cell within the memory block).

[0102] Of course, the index number or index size, the size of the data input and output from the data input / output pads, and the total size of the key data and record data are not limited to these values ​​and can be changed based on the data as the storage object during the system design phase.

[0103] Figure 4 This is a function block diagram used to illustrate the structure of the memory controller 111 in the logic chip 300.

[0104] Reference Figure 4 As described above, the non-volatile memory 106 stores a flag indicating that a storage block holds valid data as a valid data existence block table 1062 consisting of a bucket number and an index number.

[0105] The storage controller 111 includes an index conversion circuit 1112 that accepts a search key input and converts it into an index number and an index. While not particularly limited, the index conversion circuit 1112 can, for example, be structured to convert the search key into an address signal equivalent to an index number and an index through an operation based on a defined hash function.

[0106] The storage controller 111 further includes: a block selection circuit 1114 that receives an index number from the index conversion circuit 1112 and generates a bucket number by referring to the valid data existence block table 1062, the bucket number being used to specify the storage block to be accessed; and a block control circuit 1116 that receives the bucket number of the accessed object from the block selection circuit 1114 and the index number and index from the index conversion circuit 1112, and outputs an enable signal to the storage block to be accessed based on the range of bucket numbers accessed simultaneously in multiple storage blocks and the index number and index to be accessed, thereby controlling the read operation.

[0107] The storage controller 111 further includes: a block R / W circuit 1120.1 configured for each storage block determined by a bucket number, for reading data from the corresponding storage block that is simultaneously selected as the access object and whose data is being read; and a comparison circuit 1120.2 that compares key data in the data from the block R / W circuit 1120.1 with a search key, and outputs the record data corresponding to the matching key as the search result.

[0108] Alternatively, the comparator circuit 1120.2 can also be configured to select a key using priority encoding when multiple keys match the search key.

[0109] Therefore, in summary, if as follows Figure 4 If the search system is configured as shown, then in the logic chip, a search key is received, an index conversion circuit 1112 is used to generate an index number and an index, and the index number and the valid data storage block table 1062 are used to determine the bucket number of the accessed object. The storage controller 111 accesses the storage cell using the index for the storage block selected according to the index number and the bucket number of the accessed object, and reads the data to the comparison circuit 1120.2.

[0110] The comparator circuit 1120.2 compares the key in the read data with the search key and outputs the record corresponding to the matching key. Alternatively, the comparator circuit 1120.2 can also output the address information of the record containing the matching key.

[0111] Furthermore, multiple comparator circuits 1120.2 can be configured in the logic chip, and each comparator circuit 1120.2 is shared by multiple memory blocks configured in the index direction.

[0112] Furthermore, the above explanation was provided under the premise that the key data and record data to be searched are pre-written into the DRAM circuit 400, and during the writing process, a valid data existence block table 1062 is also written into the non-volatile memory 106. However, for example, assuming that when writing new key data and record data pairs to the DRAM circuit 400, data is written over memory blocks that have already been written, the flag indicating that the memory block retains valid data is updated in the valid data existence block table 1062.

[0113] Figure 5 This is a cross-sectional view showing the structure of a CPU 100 and a DRAM circuit 400 stacked together.

[0114] exist Figure 5 As an example, a structure is shown that uses the flip chip structure disclosed in Non-Patent Document 1 and is implemented using "hybrid bonding technology".

[0115] In other words, the DRAM circuit and the processor circuit are hybrid-bonded using a flip-chip structure and are housed in the same package.

[0116] Here, hybrid bonding 401 refers to a technique of bonding and connecting copper (Cu) electrodes formed on the surface of a silicon wafer or silicon wafer to each other.

[0117] For example, when silicon wafers are interconnected, electrodes can be connected with an extremely short spacing of 5μm to 1μm.

[0118] In hybrid bonding, solder bumps are not used; the surface of the semiconductor chip consists of Cu electrodes and an insulating film. The surface of the Cu electrodes is formed into a recessed shape, similar to a plate. The depth of the recess is, for example, less than 20 nm. Furthermore, a very small amount, such as 0.5 nm, is removed from the surface of the insulating film.

[0119] The Cu electrode side surfaces of the silicon, which have undergone this pretreatment, are brought into contact with each other. The insulating films are then bonded together, leaving a small gap between the opposing Cu electrodes. Next, when heat treatment is performed while the silicon electrodes are pressed together, the opposing Cu electrodes expand and come into contact, forming a bond through mutual diffusion.

[0120] Based on this, through TSV (Through Silicon Via) technology, the logic circuit is connected to the resin substrate packaging substrate 700 on the back side using a connection method based on C4 (Controlled Collapse Chip Connection) bumps 600 and other solder balls. For example, a multi-layer wiring circuit is formed on the surface (upper side) of the packaging substrate 700, and it is connected to the multi-layer wiring circuit on the back side (lower side) through through-holes 702.

[0121] The back side of the package substrate 700 is connected to the motherboard (not shown) via, for example, a BGA (Ball Grid Array) 704.

[0122] In addition, although there are no specific restrictions, in order to address the heat dissipation problem, a structure that uses dummy bumps in the substrate design to improve thermal conductivity can also be adopted.

[0123] Figure 6 This is a diagram showing the relationship between the wafers when the DRAM circuit 400 is stacked as a silicon wafer on the logic wafer 300 containing the logic circuit CPU 100.

[0124] Furthermore, as described above, in this embodiment, CPU100 is used as an example of a logic circuit, but the logic circuit is not limited to this structure.

[0125] For example, as a logic chip 300 containing a logic circuit CPU 100, assuming that in Type A the chip size is 1×1 based on the chip size of the DRAM circuit 400. Assuming that in the wafer of the DRAM circuit 400, the DRAM circuit 400 is also divided into dicing slots according to the chip size of the logic chip 300. In Type A, as a silicon wafer, the wafers of the logic chip 300 and the wafers of the DRAM circuit 400 are stacked and electrically coupled in a flip-chip structure using, for example, a hybrid bonding technique.

[0126] Then, by dicing according to the chip size of logic wafer 300, it is possible to generate a stacked chip structure with a wafer size of 1×1 based on the chip size of DRAM circuit 400. Furthermore, the number of stacked wafers is not limited to two, such as... Figure 6 As shown, there can be more.

[0127] Similarly, in Figure 6 In this context, the logic chip 300, which contains the logic circuit CPU100, is assumed to have a chip size of 2×2 when the chip size of the DRAM circuit 400 is used as a reference in Type B.

[0128] In Type B, the chip is also divided into individual pieces according to the chip size of the logic chip 300 containing the CPU 100, thereby enabling the generation of a stacked chip with a chip size of 2×2 when the chip size of the DRAM circuit 400 is used as a reference.

[0129] By adopting like Figure 6 Such a structure, for example, even if type A and type B are designed and manufactured by different processor manufacturers and have different chip sizes, can be addressed by manufacturing the DRAM circuit 400 with the same design and the same process, as long as the length of each side is an integer multiple of 1, such as 1×1, 1×2, 2×2.

[0130] That is, when manufacturing stacked semiconductor integrated circuit modules, only one type of DRAM circuit 400 is needed.

[0131] Furthermore, in the case of Type B, for example, it is assumed that the logic chip 300 is the chip size equivalent to four DRAM circuits 400, and this has been described. In this case, even if the DRAM circuits 400 have four times the capacity, they can adopt, for example, a structure corresponding to the four CPUs and four DRAM circuits 400 contained in the logic chip 300.

[0132] Furthermore, in the above description, the logic chip 300 and DRAM circuit 400 were described using a structure obtained by wafer-on-wafer stacking. However, as a stacking method for semiconductor integrated circuits, this structure is not limited to. For example, chip-on-wafer stacking, die-on-wafer stacking, chip-on-chip stacking, or die-on-die stacking can also be used.

[0133] Furthermore, the electrical connection between the logic chip 300 and the DRAM circuit 400 is described using hybrid bonding, but solder bump bonding can also be used, for example.

[0134] Furthermore, the DRAM circuit 400 can also be stacked in two or more layers. In this case, it becomes a structure in which multiple layers of DRAM cells are interconnected through vias that pass through these multiple layers.

[0135] (An example of the logical structure of a storage block)

[0136] Figure 7 This is a schematic diagram illustrating an example of the logical structure when accessing a storage block.

[0137] First, for ease of explanation, we will explain the case where the burst length is 1 when writing to and reading from a 2.2MB storage block.

[0138] Reference Figure 7 With a burst length of 1, to access a 2.2MB memory block, the address is specified using a 17-bit address signal.

[0139] That is, for a 2.2MB memory block, with a burst length of 1, 136 bits are read in parallel from the bit lines. Therefore, as long as there are 2 17 The address bits are used for word line selection, which corresponds to the overall storage capacity as described below.

[0140]

[0141] At this time, corresponding to each block, the storage controller 111 generates an index signal (for block selection based on index number at time H), an instruction signal (for specifying read, write, or refresh), and an enable signal (for block selection based on bucket number at time H) for access.

[0142] Here, for example, the following structure can be adopted: the non-volatile memory 106 also stores the burst length setting information, and the block control circuit 1116 makes the burst length variable during write and read operations according to the burst length setting information.

[0143] As the burst length, it can be set to, for example, 1, 2, 4, 8, 16, 32, ... etc.

[0144] Therefore, if the burst length is 2, 136b × 2 is read in parallel from the bit lines, and the number of addresses is reduced by 1 bit to become 16 bits. If the burst length is 8, 136b × 8 is read in parallel from the bit lines, and the number of addresses is reduced by 3 bits to become 14 bits.

[0145] exist Figures 2-4 The example provided is equivalent to setting the burst length to 8.

[0146] For example, in a structure like this where the burst length is variable, then in Figure 6 In this processor, type A can set the burst length to 8, while type B can set the burst length to 32. Furthermore, it is also possible to provide different burst length settings along with the instruction during each write or read operation, dynamically changing the burst length.

[0147] Here, in addition to the "static setting method", the "dynamic setting method" can also be used to change the burst length setting by means of instructions each time it is accessed. The "static setting method" is a setting method that can retain the setting even after the power supply is cut off, such as a method of permanently setting the working mode by means of fuses in the manufacturing process, or a method of setting it as an initial setting in non-volatile memory.

[0148] Figure 8 This is a schematic diagram illustrating an example of the structure where valid data exists in a block table.

[0149] like Figure 8 As shown in (a), the valid data existence block table 1062 is a two-dimensional array consisting of bucket numbers and index numbers within the logical space that records the flags for storage blocks containing valid data. Figure 8 In (a), a halftone pattern is used to represent a storage block containing valid data.

[0150] Figure 8 (b) represents the relationship between the index number input to the block selection circuit 1114 and the bucket number whose enable signal output from the block selection circuit 1114 is at level H.

[0151] As an example, when the input index number is 10, refer to... Figure 8 In (a), the storage blocks containing valid data are bucket numbers 1 to 11, therefore the enable signal corresponding to bucket numbers 1 to 11 is level H.

[0152] like Figure 4 As explained, the index number is composed of the high-order bits of the address. For example, if it is as follows... Figure 8 In a memory block structure like (a), the high 4 bits of the address are equivalent to an index number. During read operations, the block selected by the index number and the enable signal is selected simultaneously for processing.

[0153] (An example of the physical structure of a storage block)

[0154] Figure 9 This is a diagram illustrating an example of the physical structure of a DRAM memory block.

[0155] Here, as an example, we will also use an example with a burst length of 8.

[0156] The memory block contains a memory array, a sense amplifier (not shown), and control circuitry as peripheral circuitry. Pins for inputting instructions or address signals are configured on one side, and (128+8)b data input / output pins (DQ pads) are configured on the other side.

[0157] In this configuration, the index is 14 bits. This index is decomposed into an 11-bit X address (row address: word line selection) and a 3-bit Y address (column address: bit line selection) by the C / A circuit within the peripheral circuitry. The word line and bit line selection are performed by the X decoding circuit XDEC and the Y decoding circuit Y-dec within the peripheral circuitry. Furthermore, an overdrive capacitor element VOD-cap is provided on the column side of the peripheral circuitry for sensing the operation of the amplifier, and the output of the main amplifier circuit Main_Amp is output to the input / output pad DQ-pad (data width corresponding to (128b + 8b)).

[0158] In a single read / write instruction, access to a total of (128B+8B) data from (128+8) input / output pads is performed through 8 burst actions.

[0159] The storage capacity of a storage block is: 16384 index × (128B + 8B) = 2228224B (approximately 2.2MB).

[0160] Furthermore, when a refresh command is entered, 2048 accesses are performed within a specified time using only the 11-bit X address in the index.

[0161] Alternatively, during the refresh operation, the valid data storage block table 1062 can be referenced to select only the storage blocks containing valid data as the targets of the refresh operation.

[0162] like Figure 9 As shown, the memory cell array section and the peripheral circuit section or data input / output pad section are configured very close together, thus reducing access latency. Furthermore, due to the short wiring paths, operating power can also be reduced.

[0163] like Figure 9 As shown, the DRAM circuit 400 is configured to perform data read and write access operations independently for each memory block, therefore, it can... Figure 6 The DRAM circuit 400 is configured as an extension of the CPU 100, as described in the description.

[0164] For example, when Figure 2As described above, when the wafer is constructed by cutting it according to each memory block expansion unit, the size of the DRAM circuit 400 wafer can be arbitrarily constructed on a unit basis.

[0165] Therefore, in the above structure, it is designed to be accessed independently and individually, and the bit width of each data input and output is relatively wide, which is configured to allocate multiple unit DRAM circuits to multiple memory blocks respectively.

[0166] Moreover, in this structure, as described above, the DRAM circuit 400 operates through address non-multiplexed random access. That is, the bit width of the address pins can also ensure the required number of bits, so by using address non-multiplexed address input signals, such as completing the reading or writing of 136B of data and precharging for the next access in one access, random access operation can be performed as easily as SRAM.

[0167] Figure 10 This is a timing diagram illustrating the patterns of memory block access.

[0168] Here, although there are no specific restrictions, it is assumed that the burst length is 8 and the system operates with a 250MHz clock signal.

[0169] Reference Figure 10 At clock 0, the instruction is to read, write, or refresh, and the index (address) and instruction are input simultaneously.

[0170] As described above, this embodiment employs the following structure: it does not perform the multiplexing of row and column addresses for input or page-mode access as is common in DRAM circuits.

[0171] like Figure 10 As shown, with a burst length of 8, the DRAM circuit 400 completes its read and write operations within 16 clock cycles (64 ns under the aforementioned clock signal) and becomes ready to accept the next instruction.

[0172] Furthermore, the refresh operation of the DRAM circuit 400 is completed within 8 clock cycles (32ns under the aforementioned clock signal), and it becomes ready to accept the next instruction.

[0173] In a single read access, a total of (1024+64) bits ((128+8) bytes) of data are read from the (128+8) bit DQ pad through 8 burst actions.

[0174] Similarly, in a single write access, a total of (1024+64) bits ((128+8) bytes) of data is written from the (128+8) bit DQ pad through 8 burst actions.

[0175] During the refresh process, refresh instructions are output to the 11-bit X address (row address: word line selection) within a certain time period to perform the refresh processing of the memory cell.

[0176] In the example above, the bandwidth for random access to a storage block unit is 136B × 250MHz / 16 cycles = 2215MB / s, approximately 2GB / s.

[0177] Figure 11 This is a schematic diagram illustrating an example of how DRAM wafer dimensions are set.

[0178] As an example, suppose a block extension unit consists of 4×4 storage blocks (equivalent to a capacity of 35.7MB). That is, suppose there are sharding slots (slicing areas) around the block extension unit.

[0179] By cutting the block expansion unit, for example, when cutting it into 4×4 block expansion units, a DRAM circuit with a storage capacity of 570MB can be formed.

[0180] Similarly, when divided into 4×8 block expansion units, the DRAM circuit can achieve a storage capacity of 1.14GB; when divided into 8×8 block expansion units, the DRAM circuit can achieve a storage capacity of 2.28GB; and when divided into 8×12 block expansion units, the DRAM circuit can achieve a storage capacity of 3.42GB.

[0181] [Modification 1 of Implementation Method 1]

[0182] Figure 12 This is a schematic diagram illustrating an example of the configuration of index numbers and bucket numbers in a variation of Embodiment 1.

[0183] exist Figure 12 In the example shown, the index numbers are set to 1 to 32, and the bucket numbers are set to 1 to 8.

[0184] That is, the structure is with Figure 2 The structure shown ensures a wider bandwidth for indexes than for data input / output, enabling a wider range of search keys. Alternatively, as an extreme example, a structure can be used where storage blocks are configured one-dimensionally along the index numbering direction, for example, setting the index numbers to 1–256 and the bucket number to 1.

[0185] [Modification 2 of Implementation Method 1]

[0186] Figure 13 This is a schematic diagram illustrating an example of the configuration of index numbers and bucket numbers in a variation of embodiment 1, example 2.

[0187] exist Figure 13 In the example shown, the index numbers are set to 1 to 8, and the bucket numbers are set to 1 to 32.

[0188] That is, the structure is with Figure 2 The structure shown prioritizes data input / output bandwidth over index width compared to other structures. Typically, expanding data input / output bandwidth increases power consumption; however, in the structure of Implementation 1, the increase in power consumption is suppressed by limiting the number of simultaneously accessed storage blocks using the valid data existence block table 1062. Alternatively, as an extreme example, a structure can be used that arranges storage blocks one-dimensionally along the bucket numbering direction, for example, setting the index number to 1 and the bucket number to 256.

[0189] In addition, such as Figure 12 , Figure 13 As shown, reconfiguring the index and bucket number structure does not necessarily require physically changing the cutting dimensions of the DRAM circuit 400. For example, the DRAM circuit 400 can be cut and separated into dimensions that correspond to various combinations of index and bucket numbers. In this case, the structure of the index and bucket numbers is stored in the non-volatile memory 106, and the memory controller 111 generates the index and bucket numbers by referring to this information, thereby enabling the structure of the index and bucket numbers to be variable.

[0190] [Modification 3 of Implementation Method 1]

[0191] Figure 14 This is a schematic diagram illustrating an example of the configuration of index numbers and bucket numbers in a variation of embodiment 1, example 3.

[0192] exist Figure 14 The example shown illustrates two separate memory spaces, A and B, formed on the memory chip.

[0193] Within each storage space, as an example, the index numbers are set to 1 to 8, and the bucket numbers are set to 1 to 16.

[0194] This type of storage space corresponds to a structure that has two independent memories that are not related to each other within the same logic chip.

[0195] Furthermore, the number of storage spaces, index numbers, and bucket numbers are not limited to this structure and can be changed according to the number of corresponding processors and the processing content of each processor.

[0196] [Implementation Method 2]

[0197] In Implementation 1, a structure was described that can increase the bandwidth of data input and output by simultaneously accessing storage blocks in the direction of bucket number.

[0198] However, if a large number of bit lines are activated simultaneously for data reading, there is a possibility of increased noise due to the increased peak current.

[0199] Therefore, in Embodiment 2, a structure capable of suppressing noise will be described.

[0200] In the DRAM circuit 400 of Embodiment 2, a delayed access sequence setting table is stored in the non-volatile memory 106.

[0201] In the delayed access order setting table, the bucket number is divided into multiple groups, and the groups to be activated are stored sequentially.

[0202] Figure 15 This is a schematic diagram illustrating an example of the structure of a delayed access order setting table.

[0203] like Figure 15 As shown in (a), the valid data existence block table 1062 records flags for storage blocks containing valid data in a two-dimensional array consisting of bucket numbers and index numbers within the logical space. Furthermore, in Figure 15 In (a), a halftone pattern is used to represent a storage block containing valid data.

[0204] Furthermore, such as Figure 15 As shown in (a), assume that the bucket numbers 1 to 16 are divided into four groups: bucket numbers 1 to 4 are divided into the first group, bucket numbers 5 to 8 are divided into the second group, bucket numbers 9 to 12 are divided into the third group, and bucket numbers 13 to 16 are divided into the fourth group.

[0205] Furthermore, assume that such groups are stored in the delayed access order setting table.

[0206] Moreover, such as Figure 15 As shown in (b), when the input index number of the block selection circuit 1114 is 10, refer to Figure 15 In (a), the storage blocks containing valid data are bucket numbers 1 to 11, and in the setting of the delayed access order setting table, bucket numbers 1 to 11 correspond to the first group to the third group. Therefore, the block selection circuit 1114 outputs 1 to 4 as the bucket numbers of the first group, outputs 5 to 8 as the bucket numbers of the second group, and outputs 9 to 11 as the bucket numbers of the third group.

[0207] The block control circuit 1116 outputs an enable signal to the storage block corresponding to the bucket number, based on the output from the block selection circuit 1114, while staggering the time intervals for each group.

[0208] In addition, the number of bucket numbers and the number of groups that divide the bucket numbers are not limited to these numbers.

[0209] Figure 16 It is shown as in Figure 15 The timing diagram illustrates the delayed access read operation pattern as described in the diagram.

[0210] Here, although there are no specific restrictions, it is assumed that the burst length is 8 and the system operates with a 250MHz clock signal.

[0211] Reference Figure 16 At clock 0, for instructions, the input read instruction and index (address) are used.

[0212] Correspondingly, during the period from clock 0 to clock 6, bucket numbers 1 to 4 are activated to latch the data into the sensing amplifier (not shown) until clock 6 to clock 14, when data D0 to D7 are output and pre-charged.

[0213] In addition, during the period from clock 2 to clock 8, bucket numbers 5 to 8 are activated, data is latched into the sensing amplifier (not shown), until clock 8 to clock 16, data D0 to D7 are output, and pre-charging is performed.

[0214] Furthermore, during the period from clock 4 to clock 10, bucket numbers 9 to 12 are activated (in... Figure 15 In the example, 9 to 11), the data is latched into the sensing amplifier (not shown) until clock 10 to clock 18, when the output data D0 to D7 is output and precharged.

[0215] Additionally, if valid data also exists for storage blocks numbered 13 to 16, during clock 6 to clock 12, blocks numbered 13 to 16 are activated, and the data is latched into the sense amplifier (not shown) until clock 12 to clock 20, when data D0 to D7 are output and pre-charged.

[0216] The above structure can limit all storage blocks containing valid data to working simultaneously, suppressing peak power during read operations.

[0217] [Implementation Method 3]

[0218] In Implementation 1, a structure was described that can increase the bandwidth of data input and output by simultaneously accessing storage blocks in the direction of bucket number.

[0219] However, for bad storage blocks with bad bits, even if access is performed, meaningful data may not be obtained.

[0220] Therefore, in the DRAM circuit 400 of Embodiment 3, within the non-volatile memory 106, a flag indicating a memory block containing bad bits is stored in a bad block reference table.

[0221] Figure 17 This is a schematic diagram illustrating an example of the structure of a bad block reference table.

[0222] like Figure 17 As shown in (a), the bad block reference table records flags used to identify memory blocks containing bad bits as bad blocks in a two-dimensional array of bucket numbers and index numbers within the logical space. Furthermore, in Figure 17 In (a), bad blocks are represented by slashes.

[0223] Moreover, such as Figure 17 As shown in (b), when the input index number of the block selection circuit 1114 is 6, refer to Figure 17 The bad block reference table of (a) shows that the bad block is bucket number 11. Therefore, the block selection circuit 1114 also refers to the storage data of the valid data in the block table 1062 and outputs the bucket number that excludes bucket number 11 as the storage block to be selected and accessed at the same time.

[0224] Additionally, the storage information for valid data in block table 1062 is as follows: Figure 2 In the case shown, when the input index number is 6, the storage block containing valid data does not contain bucket number 11. Therefore, based on the storage information of the valid data storage block table 1062, the block selection circuit 1114 outputs bucket numbers 1 to 6.

[0225] The block control circuit 1116 outputs an enable signal to the storage block with the corresponding bucket number based on the output from the block selection circuit 1114.

[0226] By adopting such a structure, defective memory blocks are not activated among the simultaneously selected memory blocks, thus suppressing power consumption.

[0227] [Implementation Method 4]

[0228] Figure 18 This is a schematic diagram illustrating other structures of the storage space in the DRAM circuit 400.

[0229] Reference Figure 18 In the DRAM circuit 400 of embodiment 4, an independent storage space is set on the memory chip for each memory block.

[0230] Therefore, here, the index number is 1 and the bucket number is also 1.

[0231] exist Figure 18 As an example, the example shown illustrates a configuration of 256 independent storage spaces, each the size of a storage block.

[0232] For example, in chips used for artificial intelligence or for mining processing, multiple processor elements work in parallel.

[0233] Therefore, in Figure 18 In the example, a one-to-one memory space is set up for each processor element that works independently and in parallel.

[0234] By adopting such a structure, all blocks can be accessed in parallel, resulting in the maximum expected storage bandwidth.

[0235] Figure 19 It is used to explain relative to Figure 18 Functional block diagram of the structure of the DRAM circuit 400 and the memory controller 111 in the logic chip 300.

[0236] like Figure 18 As shown, corresponding to the independent storage space set up for each storage block on the storage chip, the logic chip 300 is provided with processor elements 100.1 to 100.256, and each processor element performs the prescribed arithmetic operations in parallel. In addition, the number of processor elements does not have to be the same as the number of storage blocks; it can be less or more than the number of storage blocks.

[0237] On the other hand, for the memory controller 111 installed in the logic chip 300, individual memory controllers 111.1 to 111.256 are respectively provided corresponding to memory blocks 1 to 256. The functions of individual memory controllers 111.1 to 111.256 are the same as... Figure 4 The block control circuit 1116 and the block R / W circuit 1120.1 shown (including the comparison circuit 1120.2 when used for search purposes) are essentially the same.

[0238] Non-volatile memory 106 (including various reference tables) is also provided in the logic chip 300. The memory controller 111 includes memory controller control circuitry 112 for controlling individual memory controllers 111.1 to 111.256. The memory controller control circuitry 112 performs… Figure 4 The function of the block selection circuit 1114. However, in Figure 19 In this structure, the processing of the bucket number can be omitted. The block selection circuit 1114 generates a signal to select the corresponding memory block from memory blocks 1 to 256 based on the input address (or search key).

[0239] In addition, Figure 19 Since the processing of bucket numbering can be omitted, the block control circuit 1116 receives the enable signal for the selected memory block from the block selection circuit 1114, activates the corresponding memory block, and outputs the address signal and instruction signal for accessing the corresponding memory cell according to the index.

[0240] The storage controller 111 also includes a cross switch for outputting data read from the selected storage block to the corresponding processor element, or outputting data written from the processor element to the selected storage block, and an interface circuit with the processor.

[0241] Therefore, in this structure, the storage controller 111 specifies the storage block of the access object and generates an index based on the search key (or address signal). Furthermore, the burst length can be statically set or dynamically changed, similar to Embodiment 1, for control.

[0242] Alternatively, the selected memory blocks can be divided into multiple groups with access time differences set. The non-volatile memory 106 stores the access order as a delayed access order setting table for these multiple groups. When multiple memory blocks are selected at the same time, the controller 111 refers to the delayed access order setting table and accesses the simultaneously selected memory blocks in the prescribed access order.

[0243] Alternatively, the non-volatile memory 106 can be configured to store a bad block table representing the flags of memory blocks containing bad bits among multiple memory blocks, and the controller 111 can refer to the bad block table to exclude bad blocks containing bad bits from the access objects.

[0244] As explained above, based on the computing system and semiconductor integrated circuit module as described in Embodiments 1 to 4, power consumption can be reduced by optimizing the structure of the memory chip in the DRAM circuit and eliminating unnecessary block accesses.

[0245] Furthermore, the computing system and semiconductor integrated circuit module according to the present invention can provide a high-speed and low-power search system.

[0246] The embodiments disclosed above are examples of structures for specific implementation of the present invention and do not limit the technical scope of the present invention. The technical scope of the present invention is shown by the claims, rather than by the description of the embodiments, and is intended to include changes made within the scope of the wording of the claims and their equivalents.

[0247] Explanation of reference numerals in the attached figures

[0248] 100: CPU, 102: Cache memory, 104: External interface, 106: Non-volatile memory, 110: Control unit, 111: Memory controller, 150: Arithmetic unit, 152: Arithmetic logic unit, 300: Logic chip, 400: DRAM circuit, 1062: Valid data storage block table, 1112: Index conversion circuit, 1114: Block selection circuit, 1116: Block control circuit, 1120.1: Block R / W circuit, 1120.2: Comparison circuit.

Claims

1. A computing system having: DRAM (Dynamic Random Access Memory) circuits are configured with multiple storage cells for storing data required for computational processing. The DRAM circuit includes multiple memory blocks configured in a logical address space that can be accessed independently. These memory blocks are associated with a first number and a second number. The first number is used to determine which memory blocks are configured in a logical first direction and can be accessed simultaneously. The second number is used to determine the multiple memory blocks in a logically orthogonal second direction to the first direction. The computing system also includes a processor circuit stacked with the DRAM circuit. The processor circuit includes: The storage circuit stores flags indicating that each of the storage blocks has retained valid data in a valid block reference table composed of the first number and the second number; At least one processor core; as well as A controller, based on a selection signal from the processor core, controls access to the memory cells in the first direction within the memory block of the DRAM circuit. The controller selects the storage block in the second direction based on the selection signal. Referring to the valid block reference table, for storage blocks that do not hold valid data among the storage blocks accessed simultaneously in the first direction, even if they are selected by the second number, they are excluded from the access objects.

2. The computing system according to claim 1, wherein, The DRAM circuit is an associative random access memory that reads stored data according to a search key. The first direction is the direction used to select the word line of the memory cell. The controller performs the following processing: i) Receive the search key as the selection signal, generate an index and an index number, the index being used to specify the word line of the plurality of storage blocks that can be accessed simultaneously, and the index number being used as a second number to specify the storage block selected by the index. ii) Based on the index number and the valid block reference table, determine the first number that assigns the storage block to the accessed object.

3. The computing system according to claim 2, wherein, The processor circuit includes: A comparison circuit compares key data from read data from the storage cell selected by the first number and the index number with the search key, and outputs the record data corresponding to the key data that matches the comparison result.

4. The computing system according to claim 1 or 2, wherein, The storage blocks selected in the first direction are divided into multiple groups with time differences set for access. The storage circuit stores the access order as a delayed order reference table for the multiple groups. The controller refers to the delay order reference table and accesses the storage block in the first direction according to the access order.

5. The computing system according to claim 4, wherein, The storage circuit stores a bad block reference table containing flags representing bad blocks among the plurality of storage blocks. The controller refers to the bad block reference table and excludes a storage block containing the bad bit from the access objects, even if it is selected by the second number.

6. The computing system according to claim 1 or 2, wherein, The controller refers to the valid block reference table and only performs refresh operations on the storage blocks that hold the valid data.

7. The computing system according to claim 1 or 2, wherein, The DRAM circuit includes a memory input / output circuit that controls the reading and writing of data from the plurality of memory cells. The memory input / output circuit uses non-multiplexed control for row and column addresses to select the address signal input of the memory cell.

8. The computing system according to claim 7, wherein, The memory input / output circuit has multiple data input / output pads. The memory input / output circuit continuously performs burst reads or burst writes of data from the plurality of data input / output pads.

9. The computing system according to claim 8, comprising: The circuitry is configured to statically set or dynamically change the operating mode of the memory input / output circuitry. The setting circuit sets the number of consecutive data accesses during the burst read or burst write.

10. The computing system according to claim 1 or 2, wherein, The storage circuit stores the logical configuration settings of the storage blocks within the physical configuration of the storage blocks in the DRAM circuit. The controller can variably control the logical configuration of the memory block during the read and write operations of the DRAM circuit according to the configuration stored in the memory circuit.

11. The computing system according to claim 1 or 2, wherein, Memory wafers including multiple DRAM circuits and processor wafers including multiple processor circuits are stacked in wafer state and then monolithized after stacking.

12. A computing system having: DRAM (Dynamic Random Access Memory) circuits are configured with multiple memory cells for storing data required for computational processing. The DRAM circuitry includes multiple independently accessible, logically one-dimensionally configured memory blocks, each memory block being associated with a first number for identifying a selected row within the memory blocks. The computing system also includes a processor circuit stacked with the DRAM circuit. The processor circuit includes: At least one processor core; as well as A controller, based on a selection signal from the processor core, controls access to the memory cells within the memory block of the DRAM circuit. The controller generates the first number based on the selection signal and accesses the plurality of storage blocks respectively.

13. The computing system according to claim 12, wherein, The storage blocks selected in the one-dimensional direction are divided into multiple groups that have time differences for access. The storage circuit stores the access order as a delayed order reference table for the multiple groups. When the controller accesses multiple storage blocks simultaneously, it refers to the delay order reference table and accesses the storage blocks in the one-dimensional direction according to the access order.

14. The computing system according to claim 12, wherein, The storage circuit stores a bad block reference table containing flags representing bad blocks among the plurality of storage blocks. The controller refers to the bad block reference table and excludes the storage block containing the bad bit from the access object.

15. The computing system according to claim 12, wherein, The DRAM circuit includes a memory input / output circuit that controls the reading and writing of data from the plurality of memory cells. The memory input / output circuit uses non-multiplexing control to select the input address signal of the memory cell for row and column addresses.

16. The computing system according to claim 15, wherein, The memory input / output circuit has multiple data input / output pads. The memory input / output circuit continuously performs burst reads or burst writes of data from the plurality of data input / output pads.

17. The computing system according to claim 16, comprising: The circuitry is configured to statically set or dynamically change the operating mode of the memory input / output circuitry. The setting circuit sets the number of consecutive data accesses during the burst read or burst write.

18. A semiconductor integrated circuit module having multiple chips stacked on top of each other, the semiconductor integrated circuit module having: The first integrated circuit chip includes a DRAM (Dynamic Random Access Memory) circuit, which is configured with multiple storage cells for storing data required for computational processing. The DRAM circuit includes multiple chips, each corresponding to a plurality of independently accessible memory blocks configured in a logical address space. Each memory block is associated with a first number and a second number. The first number identifies memory blocks configured in a logical first direction that can be accessed simultaneously, while the second number identifies the memory blocks in a logically orthogonal second direction. The semiconductor integrated circuit module further includes: a second integrated circuit chip, which includes processor circuitry for performing computational processing, the processor circuitry being stacked with the DRAM circuitry in a manner capable of transmitting and receiving data. The second integrated circuit chip includes: The storage circuit stores flags indicating that each of the storage blocks has retained valid data in a valid block reference table composed of the first number and the second number; At least one processor core; as well as A controller, based on a selection signal from the processor core, controls access to the memory cells in the first direction within the memory block of the DRAM circuit. The controller selects the storage block in the second direction based on the selection signal. Referring to the valid block reference table, for storage blocks that do not hold valid data in the storage blocks accessed simultaneously in the first direction, even if they are selected by the second number, they are excluded from the access objects.

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