Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor capable of reducing stress concentration caused by an electrostrictive effect when a voltage is applied. A multilayer ceramic capacitor has a first lead-out portion (31B), a first facing portion (31A), a second lead-out portion (32B), and a second facing portion (32A), the first lead-out portion (31B) having a first external electrode-side region (31BB), a first facing portion-side region (31BC), and a first intermediate region (31BA), and the second lead-out portion (32B) having a second external electrode-side region (32BB), a second facing portion-side region (32BC), and a second intermediate region (32BA). The coverage rate of the first intermediate region (31BA) and the second intermediate region (32BA) is lower than the coverage rate of the first external electrode-side region (31BB) and the second external electrode-side region (32BB), and the coverage rate of the first intermediate region (31BA) and the second intermediate region (32BA) is lower than the coverage rate of the first facing portion (31A) and the second facing portion (32A).

Description

Technical Field

[0001] This invention relates to multilayer ceramic capacitors. Background Technology

[0002] Previously, multilayer ceramic capacitors were known. Generally, multilayer ceramic capacitors consist of a stack of alternating dielectric layers and internal electrode layers (see Patent Document 1). In such multilayer ceramic capacitors, there is a demand for further miniaturization, higher capacitance, and improved reliability. Therefore, ferroelectric materials with high dielectric constants are sometimes used as the dielectric layer material. In addition, attempts have been made to thin the dielectric layer, thin the internal electrode layer, and increase the number of these layers.

[0003] Prior art literature

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 8-306580 Summary of the Invention

[0006] The problem the invention aims to solve

[0007] Such a dielectric layer exhibits piezoelectricity and electrostriction. Therefore, if a voltage is applied to a multilayer ceramic capacitor with such a dielectric layer, the multilayer will deform accordingly due to the electrostriction effect, generating stress inside the multilayer ceramic capacitor.

[0008] The purpose of this invention is to provide a multilayer ceramic capacitor that can ensure capacitance density and maintain the connectivity between the internal electrode layer and the external electrode, while reducing stress concentration caused by the electrostriction effect when voltage is applied.

[0009] Technical solutions for solving the problem

[0010] The multilayer ceramic capacitor of the present invention comprises: a multilayer body including a plurality of stacked dielectric layers and a plurality of stacked internal electrode layers, and including a first main surface and a second main surface opposite to each other in the stacking direction, a first side surface and a second side surface opposite to each other in a width direction orthogonal to the stacking direction, and a first end surface and a second end surface opposite to each other in a length direction orthogonal to the stacking direction and the width direction; a first external electrode disposed on the first end surface side; and a second external electrode disposed on the second end surface side, wherein the plurality of internal electrode layers include a first internal electrode layer and a second internal electrode layer, the first internal electrode layer having a first lead-out portion extending to the first end surface and connected to the first external electrode, and a first opposing portion connected to the first lead-out portion and opposing the second internal electrode layer disposed adjacent to it in the stacking direction, the second internal electrode layer having a second lead-out portion extending to the second end surface and connected to the second external electrode, and so on. The first lead-out portion is connected to the second lead-out portion and is opposite to the first internal electrode layer arranged adjacent to it in the stacking direction. The first lead-out portion has a first external electrode side region near the connection portion of the first external electrode, a first opposing portion side region near the connection portion of the first opposing portion, and a first intermediate region between the first external electrode side region and the first opposing portion side region. The second lead-out portion has a second external electrode side region near the connection portion of the second external electrode, a second opposing portion side region near the connection portion of the second opposing portion, and a second intermediate region between the second external electrode side region and the second opposing portion side region. The coverage of the first intermediate region and the second intermediate region is lower than the coverage of the first external electrode side region and the second external electrode side region, and the coverage of the first intermediate region and the second intermediate region is lower than the coverage of the first opposing portion and the second opposing portion.

[0011] Invention Effects

[0012] According to the present invention, a multilayer ceramic capacitor can be provided that can ensure capacitance density and maintain the connectivity between the internal electrode layer and the external electrode, while reducing stress concentration caused by electrostriction effect when voltage is applied. Attached Figure Description

[0013] Figure 1 This is a perspective view of the stacked ceramic capacitor according to the first embodiment.

[0014] Figure 2 yes Figure 1 Sectional view II-II.

[0015] Figure 3 yes Figure 2 Sectional view III-III.

[0016] Figure 4A yes Figure 2 IVA-IVA sectional view.

[0017] Figure 4B yes Figure 2 IVB-IVB sectional view.

[0018] Figure 5A It is shown schematically. Figure 2 An enlarged sectional view of the portion shown in R1.

[0019] Figure 5B It is shown schematically. Figure 2 An enlarged sectional view of the portion shown in R2.

[0020] Figure 6A This schematically illustrates a multilayer ceramic capacitor according to the second embodiment. Figure 2 An enlarged sectional view of the portion shown in R1.

[0021] Figure 6B This schematically illustrates a multilayer ceramic capacitor according to the second embodiment. Figure 2 An enlarged sectional view of the portion shown in R2. Detailed Implementation

[0022] (First Embodiment)

[0023] Hereinafter, the first embodiment of the stacked ceramic capacitor according to the present disclosure will be described with reference to the accompanying drawings. Figure 1 This is a perspective view of the stacked ceramic capacitor 1 according to the embodiment. Figure 2 yes Figure 1 Sectional view II-II. Figure 3 yes Figure 2 Sectional view III-III. Figure 4A yes Figure 2 IVA-IVA sectional view. Figure 4B yes Figure 2 IVB-IVB sectional view.

[0024] like Figure 1 As shown, the multilayer ceramic capacitor 1 according to the embodiment has a generally rectangular parallelepiped shape. The multilayer ceramic capacitor 1 includes a multilayer body 10 having a generally rectangular parallelepiped shape and a pair of external electrodes 40 disposed separately at both ends of the multilayer body 10.

[0025] exist Figure 1 In the diagram, arrow T indicates the stacking direction of the multilayer ceramic capacitor 1 and the multilayer body 10. This stacking direction T also represents the thickness and height directions of the multilayer ceramic capacitor 1 and the multilayer body 10. Figure 1 In the diagram, arrow L indicates the length direction of the multilayer ceramic capacitor 1 and the multilayer 10, which is orthogonal to the stacking direction T. Figure 1 In the diagram, arrow W indicates the width direction of the multilayer ceramic capacitor 1 and the multilayer 10, which is orthogonal to the stacking direction T and the length direction L. A pair of external electrodes 40 are respectively disposed at one end and the other end of the multilayer 10 along the length direction L.

[0026] exist Figures 1 to 4B The diagram illustrates an XYZ orthogonal coordinate system. The length direction L of the stacked ceramic capacitor 1 and the stacked body 10 corresponds to the X-direction. The width direction W of the stacked ceramic capacitor 1 and the stacked body 10 corresponds to the Y-direction. The stacking direction T of the stacked ceramic capacitor 1 and the stacked body 10 corresponds to the Z-direction. Figure 2 The cross section shown is also known as the LT section. Figure 3 The cross-section shown is also known as the WT cross-section. Figure 4A as well as Figure 4B The cross-section shown is also called the LW cross-section.

[0027] like Figures 1 to 4B As shown, the laminate 10 includes a first main surface TS1 and a second main surface TS2 opposite to each other in the lamination direction T, a first end surface LS1 and a second end surface LS2 opposite to each other in the length direction L orthogonal to the lamination direction T, and a first side surface WS1 and a second side surface WS2 opposite to each other in the width direction W orthogonal to the lamination direction T and the length direction L.

[0028] like Figure 1 As shown, the laminate 10 has a generally rectangular parallelepiped shape. Furthermore, the length L of the laminate 10 does not necessarily have to be longer than the width W. It is preferable that the corners and edges of the laminate 10 have rounded corners. The corners are the parts where three faces of the laminate intersect, and the edges are the parts where two faces of the laminate intersect. Additionally, unevenness or recesses may be formed on part or all of the surfaces constituting the laminate 10.

[0029] The dimensions of the laminate 10 are not particularly limited, but if the length direction L of the laminate 10 is defined as dimension L, then dimension L is preferably 0.2 mm or more and 6 mm or less. Furthermore, if the lamination direction T of the laminate 10 is defined as dimension T, then dimension T is preferably 0.05 mm or more and 5 mm or less. Furthermore, if the width direction W of the laminate 10 is defined as dimension W, then dimension W is preferably 0.1 mm or more and 5 mm or less.

[0030] like Figure 2 as well as Figure 3 As shown, the laminate 10 has an inner layer 11 and a first main surface side outer layer 12 and a second main surface side outer layer 13 configured to sandwich the inner layer 11 in the lamination direction T.

[0031] The inner layer 11 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 alternately stacked in the stacking direction T. The inner layer 11 includes an internal electrode layer 30 extending from the side closest to the first main surface TS1 to the side closest to the second main surface TS2 in the stacking direction T. In the inner layer 11, the plurality of internal electrode layers 30 are arranged opposite each other, separated by dielectric layers 20. The inner layer 11 is the part that generates electrostatic capacitance and essentially functions as a capacitor.

[0032] Multiple dielectric layers 20 are composed of a dielectric material. The dielectric material may be, for example, a dielectric ceramic containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. Alternatively, the dielectric material may be a dielectric material in which secondary components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, or Ni compounds have been added to these main components. The dielectric material is particularly preferably a material containing BaTiO3 as the main component.

[0033] The thickness of the dielectric layer 20 is preferably 0.2 μm or more and 10 μm or less. The number of stacked dielectric layers 20 is preferably 15 or more and 1200 or less. In addition, the number of dielectric layers 20 is the total number of dielectric layers 20 in the inner layer portion 11 and the number of dielectric layers 20 in each of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0034] The plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged alternately in the stacking direction T, with a dielectric layer 20 sandwiched between them. The first internal electrode layers 31 extend to a first end face LS1. The second internal electrode layers 32 extend to a second end face LS2. Furthermore, hereinafter, without distinguishing between the first internal electrode layers 31 and the second internal electrode layers 32, the first internal electrode layers 31 and the second internal electrode layers 32 are sometimes collectively referred to as internal electrode layers 30.

[0035] like Figure 4A As shown, the first internal electrode layer 31 has a first opposing portion 31A and a first lead-out portion 31B. The first opposing portion 31A is the region that sandwiches the dielectric layer 20 in the middle and opposes the second internal electrode layer 32, and is located inside the laminate 10. The first lead-out portion 31B is the portion that extends from the first opposing portion 31A to the first end face LS1 and is exposed at the first end face LS1.

[0036] like Figure 4BAs shown, the second internal electrode layer 32 has a second opposing portion 32A and a second lead-out portion 32B. The second opposing portion 32A is the region that sandwiches the dielectric layer 20 in the middle and opposes the first internal electrode layer 31, and is located inside the laminate 10. The second lead-out portion 32B is the portion that extends from the second opposing portion 32A to the second end face LS2 and is exposed at the second end face LS2.

[0037] In this embodiment, the first opposing portion 31A and the second opposing portion 32A are opposed to each other through the dielectric layer 20, thereby forming a capacitor and exhibiting the characteristics of a capacitor.

[0038] The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may also have rounded corners, and the corners of the rectangular shape may also be formed at an angle. The shapes of the first lead-out portion 31B and the second lead-out portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may also have rounded corners, and the corners of the rectangular shape may also be formed at an angle.

[0039] The width W of the first opposing portion 31A and the width W of the first lead-out portion 31B can be formed with the same size, or either size can be made smaller. The width W of the second opposing portion 32A and the width W of the second lead-out portion 32B can be formed with the same size, or either size can be made narrower.

[0040] The first internal electrode layer 31 and the second internal electrode layer 32 are made of suitable conductive materials, such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals. When using an alloy, the first internal electrode layer 31 and the second internal electrode layer 32 may also be made of, for example, an Ag-Pd alloy.

[0041] The thickness of each of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably 0.2 μm or more and 2.0 μm or less. The number of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably 15 or more and 1000 or less.

[0042] like Figure 2 as well as Figure 3As shown, the first main surface side outer layer 12 is located on the first main surface TS1 side of the laminate 10. The first main surface side outer layer 12 is an assembly of multiple dielectric layers 20 located between the first main surface TS1 and the inner electrode layer 30 closest to the first main surface TS1. On the other hand, the second main surface side outer layer 13 is located on the second main surface TS2 side of the laminate 10. The second main surface side outer layer 13 is an assembly of multiple dielectric layers 20 located between the second main surface TS2 and the inner electrode layer 30 closest to the second main surface TS2. The dielectric layers 20 used in the first main surface side outer layer 12 and the second main surface side outer layer 13 can be the same as the dielectric layers 20 used in the inner layer 11.

[0043] Additionally, the laminate 10 has a counter electrode portion 11E. The counter electrode portion 11E is the portion opposite to the first counter portion 31A of the first inner electrode layer 31 and the second counter portion 32A of the second inner electrode layer 32. The counter electrode portion 11E is configured as part of the inner layer portion 11. Figure 4A as well as Figure 4B The diagram shows the width W and length L of the counter electrode portion 11E. The counter electrode portion 11E is also referred to as the effective portion of the capacitor.

[0044] Additionally, the laminate 10 has a side outer layer. The side outer layer has a first side outer layer WG1 and a second side outer layer WG2. The first side outer layer WG1 is a portion that includes a dielectric layer 20 located between the counter electrode portion 11E and the first side WS1. The second side outer layer WG2 is a portion that includes a dielectric layer 20 located between the counter electrode portion 11E and the second side WS2. Figure 3 , Figure 4A as well as Figure 4B The diagram shows the width direction W of the first side outer layer WG1 and the second side outer layer WG2. The side outer layers are also referred to as W gaps or lateral gaps.

[0045] Additionally, the laminate 10 has an end-face side outer layer. The end-face side outer layer has a first end-face side outer layer LG1 and a second end-face side outer layer LG2. The first end-face side outer layer LG1 is a portion including a dielectric layer 20 located between the counter electrode portion 11E and the first end face LS1, and a first lead-out portion 31B. That is, the first end-face side outer layer LG1 is an assembly of multiple dielectric layers 20 on the first end face LS1 side and multiple first leads-out portions 31B. The second end-face side outer layer LG2 is a portion including a dielectric layer 20 located between the counter electrode portion 11E and the second end face LS2, and a second lead-out portion 32B. That is, the second end-face side outer layer LG2 is an assembly of multiple dielectric layers 20 on the second end face LS2 side and multiple second leads-out portions 32B. Figure 2 , Figure 4A as well as Figure 4B The diagram shows the length direction L range of the first end-face side outer layer LG1 and the second end-face side outer layer LG2. Additionally, the end-face side outer layer is also referred to as the L-gap or end gap.

[0046] like Figure 1 as well as Figure 2 As shown, the external electrode 40 has a first external electrode 40A disposed on the first end face LS1 side of the laminate 10 and a second external electrode 40B disposed on the second end face LS2 side of the laminate 10.

[0047] Furthermore, the basic structures of the first external electrode 40A and the second external electrode 40B are the same. In addition, the first external electrode 40A and the second external electrode 40B have a shape that is approximately symmetrical about the cross-section WT with respect to the center of the length direction L of the multilayer ceramic capacitor 1. Therefore, in the following description, without distinguishing between the first external electrode 40A and the second external electrode 40B, the first external electrode 40A and the second external electrode 40B will sometimes be collectively referred to as external electrode 40.

[0048] A first external electrode 40A is disposed on a first end face LS1. The first external electrode 40A contacts the first lead-out portion 31B of each of the plurality of first internal electrode layers 31 exposed on the first end face LS1. Thus, the first external electrode 40A is electrically connected to the plurality of first internal electrode layers 31. The first external electrode 40A may also be disposed on a portion of a first main surface TS1 and a portion of a second main surface TS2, and a portion of a first side surface WS1 and a portion of a second side surface WS2. In this embodiment, the first external electrode 40A is formed to extend from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0049] The second external electrode 40B is disposed on the second end face LS2. The second external electrode 40B contacts the second lead-out portion 32B of each of the plurality of second internal electrode layers 32 exposed on the second end face LS2. Thus, the second external electrode 40B is electrically connected to the plurality of second internal electrode layers 32. The second external electrode 40B may also be disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the second external electrode 40B is formed to extend from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0050] As previously described, within the laminate 10, the first opposing portion 31A of the first inner electrode layer 31 and the second opposing portion 32A of the second inner electrode layer 32 are opposed to each other across the dielectric layer 20, thereby forming a capacitor. Therefore, capacitor characteristics are exhibited between the first outer electrode 40A connected to the first inner electrode layer 31 and the second outer electrode 40B connected to the second inner electrode layer 32.

[0051] like Figure 2 , Figure 4A as well as Figure 4B As shown, the first external electrode 40A has a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A. Furthermore, the second external electrode 40B has a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B.

[0052] A first base electrode layer 50A is disposed on a first end face LS1. The first base electrode layer 50A is connected to the first lead-out portion 31B of each of the plurality of first internal electrode layers 31 exposed on the first end face LS1. In this embodiment, the first base electrode layer 50A is formed to extend from the first end face LS1 to a portion of a first main face TS1 and a portion of a second main face TS2, and a portion of a first side face WS1 and a portion of a second side face WS2.

[0053] The second base electrode layer 50B is disposed on the second end face LS2. The second base electrode layer 50B contacts the second lead-out portion 32B of each of the plurality of second internal electrode layers 32 exposed on the second end face LS2. In this embodiment, the second base electrode layer 50B is formed to extend from the second end face LS2 to a portion of the first main face TS1 and a portion of the second main face TS2, and a portion of the first side face WS1 and a portion of the second side face WS2.

[0054] The first base electrode layer 50A and the second base electrode layer 50B of this embodiment are sintered layers. The sintered layers preferably contain any one of a metallic component and a glass component or a ceramic component, or both. The metallic component may contain, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloys, Au, etc. The glass component may contain, for example, at least one selected from B, Si, Ba, Mg, Al, Li, etc. The ceramic component may be the same type of ceramic material as the dielectric layer 20, or a different type of ceramic material. The ceramic component may contain, for example, at least one selected from BaTiO3, CaTiO3, (Ba,Ca)TiO3, SrTiO3, CaZrO3, etc.

[0055] The sintered layer, for example, is a conductive paste containing glass and metal applied to the laminate 10 and then sintered. The sintered layer can be formed by simultaneously firing the raw material of the laminate 10, i.e., the pre-firing laminate sheet, which has multiple internal electrodes and dielectric layers, and the conductive paste applied to the laminate sheet. Alternatively, it can be formed by firing the laminate sheet to obtain the laminate 10, then applying the conductive paste to the laminate 10 and sintering it. Furthermore, in the co-firing case described above, the sintered layer is preferably formed by sintering a conductive paste in which a ceramic material is added instead of glass. In this case, the ceramic material added is particularly preferably the same type of ceramic material as the dielectric layer 20. Additionally, the sintered layer can also consist of multiple layers.

[0056] Regarding the thickness of the first base electrode layer 50A located on the first end face LS1, corresponding to the length direction L, it is preferably 3 μm or more and 200 μm or less at the center of the stacking direction T and the width direction W of the first base electrode layer 50A.

[0057] Regarding the thickness of the second base electrode layer 50B located on the second end face LS2, corresponding to the length direction L, it is preferably 3 μm or more and 200 μm or less at the center of the stacking direction T and the width direction W of the second base electrode layer 50B.

[0058] When the first base electrode layer 50A is also provided on a portion of at least one of the first main surfaces TS1 or the second main surface TS2, the thickness of the first base electrode layer 50A provided in that portion corresponding to the stacking direction T is preferably, for example, 3 μm or more and 40 μm or less at the central portion of the first base electrode layer 50A provided in the length direction L and width direction W of that portion.

[0059] When the first base electrode layer 50A is also provided on a portion of at least one of the first side WS1 or the second side WS2, the thickness of the first base electrode layer 50A provided in that portion, corresponding to the width direction W, is preferably, for example, 3 μm or more and 40 μm or less at the central portion of the first base electrode layer 50A provided in the length direction L and the stacking direction T.

[0060] When a second base electrode layer 50B is also provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness of the second base electrode layer 50B provided on that portion, corresponding to the stacking direction T, is preferably, for example, 3 μm or more and 40 μm or less at the central portion of the second base electrode layer 50B provided on that portion in both the length direction L and the width direction W.

[0061] When a second base electrode layer 50B is also provided on a portion of at least one of the first side WS1 or the second side WS2, the thickness of the second base electrode layer 50B provided on that portion, corresponding to the width direction W, is preferably, for example, 3 μm or more and 40 μm or less at the central portion of the second base electrode layer 50B provided on that portion in the length direction L and the stacking direction T.

[0062] Furthermore, the first base electrode layer 50A and the second base electrode layer 50B are not limited to sintered layers. The first base electrode layer 50A and the second base electrode layer 50B comprise at least one selected from sintered layers, conductive resin layers, thin film layers, etc. For example, the first base electrode layer 50A and the second base electrode layer 50B may also be thin film layers. The thin film layer is formed by a thin film formation method such as sputtering or vapor deposition. The thin film layer is a layer with a thickness of 10 μm or less on which metal particles are deposited.

[0063] The first plating layer 60A is configured to cover the first substrate electrode layer 50A.

[0064] The second plating layer 60B is configured to cover the second base electrode layer 50B.

[0065] The first plating layer 60A and the second plating layer 60B may, for example, comprise at least one of the following materials: Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc. The first plating layer 60A and the second plating layer 60B may also be formed from multiple layers. Preferably, the first plating layer 60A and the second plating layer 60B have a two-layer structure in which a Sn plating layer is formed on top of a Ni plating layer.

[0066] The first plating layer 60A is configured to cover the first substrate electrode layer 50A. In this embodiment, the first plating layer 60A has a first Ni plating layer 61A and a first Sn plating layer 62A located on the first Ni plating layer 61A.

[0067] The second plating layer 60B is configured to cover the second base electrode layer 50B. In this embodiment, the second plating layer 60B has a second Ni plating layer 61B and a second Sn plating layer 62B located on the second Ni plating layer 61B.

[0068] The Ni plating layer prevents the first base electrode layer 50A and the second base electrode layer 50B from being eroded by solder during the mounting of the multilayer ceramic capacitor 1. Furthermore, the Sn plating layer improves the wettability of the solder during the mounting of the multilayer ceramic capacitor 1. This facilitates the mounting of the multilayer ceramic capacitor 1. The thicknesses of the first Ni plating layer 61A, the first Sn plating layer 62A, the second Ni plating layer 61B, and the second Sn plating layer 62B are preferably 2 μm or more and 10 μm or less.

[0069] Alternatively, the external electrode 40 of this embodiment may, for example, have a conductive resin layer comprising conductive particles and a thermosetting resin. The conductive resin layer may also be configured to cover the sintered layer. When the conductive resin layer is configured to cover the sintered layer, the conductive resin layer is disposed between the sintered layer and the plating layers (first plating layer 60A, second plating layer 60B). The conductive resin layer may completely cover the sintered layer or may cover only a portion of the sintered layer.

[0070] The conductive resin layer containing a thermosetting resin is more flexible than, for example, the conductive layer containing a sintered product such as a coated film or conductive paste. Therefore, even when the multilayer ceramic capacitor 1 is subjected to a physical impact caused by thermal cycling, the conductive resin layer functions as a buffer layer. Consequently, the conductive resin layer inhibits the formation of cracks in the multilayer ceramic capacitor 1.

[0071] The metal constituting the conductive particles can be Ag, Cu, Ni, Sn, Bi, or alloys containing them. The conductive particles preferably contain Ag. Conductive particles are, for example, Ag metal powder. Ag has the lowest resistivity among metals, making it suitable as an electrode material. Furthermore, Ag is a noble metal, therefore it is not easily oxidized and has high weather resistance. Thus, Ag metal powder is suitable as a conductive particle.

[0072] In addition, the conductive particles can also be metal powder coated with Ag. When using a material in which Ag is coated on the surface of the metal powder, the metal powder is preferably Cu, Ni, Sn, Bi, or alloys thereof. In order to make the base metal less expensive while retaining the properties of Ag, it is preferable to use Ag-coated metal powder.

[0073] Furthermore, the conductive particles can also be conductive particles that have undergone anti-oxidation treatment on Cu or Ni. Additionally, the conductive particles can also be metal powder coated with Sn, Ni, or Cu. When using a material with Sn, Ni, or Cu coated on the surface of metal powder, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy thereof.

[0074] There are no particular limitations on the shape of the conductive particles. Conductive particles with shapes such as spherical or flat can be used, but it is preferable to use a mixture of spherical and flat metal powders.

[0075] The conductive particles contained in the conductive resin layer primarily serve to ensure the layer's electrical conductivity. Specifically, multiple conductive particles come into contact with each other, thereby forming electrical pathways within the conductive resin layer.

[0076] The resin constituting the conductive resin layer may include at least one of various known thermosetting resins such as epoxy resin, phenolic resin, polyurethane resin, silicone resin, and polyimide resin. Epoxy resin, in particular, is one of the most suitable resins due to its excellent heat resistance, moisture resistance, and adhesion. Furthermore, the resin of the conductive resin layer preferably includes a curing agent along with the thermosetting resin. When using epoxy resin as the base resin, the curing agent for the epoxy resin may also be various known compounds such as phenols, amines, acid anhydrides, imidazoles, reactive esters, and amide-imides.

[0077] Alternatively, the conductive resin layer can be formed from multiple layers. The thickness of the thickest portion of the conductive resin layer is preferably 10 μm or more and 150 μm or less.

[0078] Alternatively, the structure can be such that the first base electrode layer 50A and the second base electrode layer 50B are not provided, and the first plating layer 60A and the second plating layer 60B (described later) are directly disposed on the laminate 10. That is, the laminated ceramic capacitor 1 can also have a structure including plating layers that are directly electrically connected to the first internal electrode layer 31 and the second internal electrode layer 32. In such a case, the plating layer can be formed after a catalyst is disposed on the surface of the laminate 10 as a pretreatment.

[0079] In this case, the plating layer is preferably multiple layers. The lower plating layer and the upper plating layer preferably each contain at least one metal or an alloy containing such metal, selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn. The lower plating layer is more preferably formed using Ni, which has solder resist properties. The upper plating layer is more preferably formed using Sn or Au, which has good solder wettability. Furthermore, for example, if the first inner electrode layer 31 and the second inner electrode layer 32 are formed using Ni, the lower plating layer is preferably formed using Cu, which has good adhesion to Ni. Additionally, the upper plating layer can be formed as needed, and the outer electrode 40 may also be composed solely of the lower plating layer. Furthermore, the plating layer may be the outermost layer, or other plating layers may be further formed on the surface of the upper plating layer.

[0080] The thickness of each layer of the plating layer, which is configured without a base electrode layer, is preferably 2 μm or more and 10 μm or less. Furthermore, the plating layer preferably does not contain glass. The metal content per unit volume of the plating layer is preferably 99% or more by volume.

[0081] Furthermore, by forming the plating layer directly on the laminate 10, the thickness of the base electrode layer can be reduced. Therefore, corresponding to the amount of reduction in the base electrode layer thickness, the height T dimension of the laminated ceramic capacitor 1 can be reduced, thereby achieving a lower height for the laminated ceramic capacitor 1. Alternatively, corresponding to the amount of reduction in the base electrode layer thickness, the thickness of the dielectric layer 20 sandwiched between the first inner electrode layer 31 and the second inner electrode layer 32 can be increased, thereby increasing the overall thickness. In this way, by forming the plating layer directly on the laminate 10, the design freedom of the laminated ceramic capacitor can be increased.

[0082] The above describes the basic structure of the multilayer ceramic capacitor 1 according to the embodiment. Furthermore, if the length dimension of the multilayer ceramic capacitor 1, including the laminate 10 and the external electrode 40, is defined as dimension L, then dimension L is preferably 0.2 mm or more and 6 mm or less. Furthermore, if the dimension in the lamination direction of the multilayer ceramic capacitor 1 is defined as dimension T, then dimension T is preferably 0.05 mm or more and 5 mm or less. Furthermore, if the width dimension of the multilayer ceramic capacitor 1 is defined as dimension W, then dimension W is preferably 0.1 mm or more and 5 mm or less.

[0083] Here, the inventors of this application, through repeated research, experiments, and simulations, have arrived at the following insight: to improve the overall quality of a multilayer ceramic capacitor, it is best to set the coverage of the internal electrode layer to an appropriate state. This will be explained below. In multilayer ceramic capacitors, to increase capacitance density, techniques for increasing the coverage of the internal electrode layer are being developed. Furthermore, coverage is also referred to as the ratio of the internal electrode layer to the dielectric layer. Through repeated research as described above, the inventors of this application have arrived at the following insight: increasing the coverage also helps to improve the connectivity between the internal electrode layer and the external electrode. On the other hand, it has also been observed that if the coverage of the internal electrode layer is not properly set, problems arise such as increased residual stress due to the firing process during manufacturing, and increased stress due to the electrostrictive effect when voltage is applied. If these stresses increase, the structure of the multilayer ceramic capacitor may become more susceptible to breakdown.

[0084] Figure 5A It is shown schematically. Figure 2 An enlarged sectional view of the portion shown in R1. Figure 5B It is shown schematically. Figure 2 An enlarged sectional view of the portion shown in R2. Figure 5A as well as Figure 5B It is part of the LT section. Figure 5A as well as Figure 5BThe image shows a dielectric layer 20, a first internal electrode layer 31 and a second internal electrode layer 32, and a first external electrode 40A and a second external electrode 40B in a laminate 10.

[0085] The first internal electrode layer 31 has a first lead-out portion 31B that extends to the first end face LS1 and is connected to the first external electrode 40A, and a first opposing portion 31A that is connected to the first lead-out portion 31B and is opposite to the second internal electrode layer 32 that is arranged adjacent to it in the stacking direction T.

[0086] The second internal electrode layer 32 has a second lead-out portion 32B, one end of which extends to the second end face LS2 and is connected to the second external electrode 40B, and a second opposing portion 32A, which is connected to the second lead-out portion 32B and is opposite to the first internal electrode layer 31, which is arranged adjacent to it in the stacking direction T.

[0087] The first lead-out portion 31B has a first external electrode side region 31BB near the connection portion with the first external electrode 40A, a first opposing portion side region 31BC near the connection portion with the first opposing portion 31A, and a first intermediate region 31BA located between the first external electrode side region 31BB and the first opposing portion side region 31BC.

[0088] The second lead-out portion 32B has a second external electrode side region 32BB near the connection portion with the second external electrode 40B, a second opposing portion side region 32BC near the connection portion with the second opposing portion 32A, and a second intermediate region 32BA located between the second external electrode side region 32BB and the second opposing portion side region 32BC.

[0089] The first intermediate region 31BA is located at the center of the first lead-out portion 31B along its length direction, and preferably is 60% or more and 80% or less of the length L of the first lead-out portion 31B along its length direction. The second intermediate region 32BA is located at the center of the first lead-out portion along its length direction, and preferably is 60% or more and 80% or less of the length L of the first lead-out portion along its length direction.

[0090] The coverage of the first intermediate region 31BA and the second intermediate region 32BA is lower than that of the first external electrode side region 31BB and the second external electrode side region 32BB, and the coverage of the first intermediate region 31BA and the second intermediate region 32BA is lower than that of the first opposing portion 31A and the second opposing portion 32A. This ensures capacitance density and maintains the connectivity between the internal electrode layer and the external electrode, while reducing stress concentration caused by electrostriction during voltage application.

[0091] Furthermore, the coverage of the first opposing portion side region 31BC and the second opposing portion side region 32BC is higher than the coverage of the first intermediate region 31BA and the second intermediate region 32BA. As a result, stress concentration during firing caused by the difference in the coefficients of linear expansion between the dielectric layer and the internal electrode layer can be reduced near the connection between the opposing portion and the lead-out portion of the internal electrode layer.

[0092] The coverage of the first intermediate region 31BA and the second intermediate region 32BA is preferably 55% or more. With this structure, it is less likely to cause processing difficulties in manufacturing the multilayer ceramic capacitor 1 of this embodiment.

[0093] The coverage of the first intermediate region 31BA and the second intermediate region 32BA is preferably 80% or less. This further reduces stress concentration caused by the electrostrictive effect when voltage is applied.

[0094] The coverage of the first external electrode side region 31BB and the second external electrode side region 32BB is preferably higher than that of the first intermediate region 31BA and the second intermediate region 32BA, and is at least 68%. This allows for more reliable maintenance of the connection with the external electrodes.

[0095] The coverage of the first external electrode side region 31BB and the second external electrode side region 32BB can also be higher than the coverage of the first intermediate region 31BA and the second intermediate region 32BA and is less than 88%.

[0096] The coverage of the first opposing portion side region 31BC and the second opposing portion side region 32BC is preferably higher than that of the first intermediate region 31BA and the second intermediate region 32BA, and is at least 68%. This further reduces stress concentration caused by the electrostrictive effect when voltage is applied, and further reduces stress concentration during firing due to the difference in the coefficients of linear expansion between the dielectric layer and the internal electrode layer.

[0097] The coverage of the first opposing side region 31BC and the second opposing side region 32BC can be higher than the coverage of the first intermediate region 31BA and the second intermediate region 32BA and is less than 88%.

[0098] The coverage of the first opposing portion 31A and the second opposing portion 32A is preferably higher than the coverage of the first intermediate region 31BA and the second intermediate region 32BA, and is at least 75%. Therefore, the advantages of this embodiment can be achieved while ensuring capacitance density.

[0099] The coverage of the first opposing portion 31A and the second opposing portion 32A can be higher than the coverage of the first intermediate region 31BA and the second intermediate region 32BA and is less than 88%.

[0100] The coverage of the first intermediate region 31BA and the second intermediate region 32BA is preferably 60% or more and 90% or less of the coverage of the first external electrode side region 31BB and the second external electrode side region 32BB, and more preferably 60% or more and 83% or less.

[0101] The coverage of the first intermediate region 31BA and the second intermediate region 32BA is preferably 60% or more and 90% or less of the coverage of the first opposing side region 31BC and the second opposing side region 32BC, and more preferably 60% or more and 83% or less.

[0102] The coverage of the first intermediate region 31BA and the second intermediate region 32BA is preferably 60% or more and 90% or less of the coverage of the first opposing portion 31A and the second opposing portion 32A, and more preferably 60% or more and 83% or less.

[0103] Even if the coverage of the first intermediate region 31BA and the second intermediate region 32BA is excessively reduced, the reduction effect on stress concentration caused by the electrostriction effect when voltage is applied is limited. Furthermore, if the coverage of the first intermediate region 31BA and the second intermediate region 32BA is reduced too much, the balance is disrupted, and residual stress may occur. As long as it is within the above-mentioned range, the effects of this embodiment can be appropriately obtained.

[0104] Furthermore, the coverage rates of the first external electrode side region 31BB, the first opposing portion side region 31BC, and the first opposing portion 31A are preferably approximately the same. Similarly, the coverage rates of the second external electrode side region 32BB, the second opposing portion side region 32BC, and the second opposing portion 32A are preferably approximately the same. This makes it less likely that the overall balance will be disrupted, resulting in residual stress.

[0105] The multilayer ceramic capacitor 1 according to this embodiment can ensure capacitance density and maintain the connectivity between the inner electrode layer and the outer electrode, while reducing stress concentration caused by the electrostriction effect when voltage is applied, thereby reducing stress concentration during firing due to the difference in the coefficients of linear expansion between the dielectric layer and the inner electrode layer.

[0106] (Second Implementation)

[0107] The laminated ceramic capacitor 1 according to the second embodiment will be described below. Furthermore, in the following description, the same reference numerals are used for structures identical to those in the first embodiment, and detailed descriptions are omitted. Figure 6A This schematically illustrates the multilayer ceramic capacitor 1 according to the second embodiment. Figure 2 An enlarged sectional view of the portion shown in R1. Figure 6B This schematically illustrates the multilayer ceramic capacitor 1 according to the second embodiment. Figure 2 An enlarged sectional view of the portion shown in R2. Figure 6A as well as Figure 6B It is part of the LT section. Figure 6A as well as Figure 6B The image shows a dielectric layer 20, a first internal electrode layer 31 and a second internal electrode layer 32, and a first external electrode 40A and a second external electrode 40B in a laminate 10.

[0108] In this embodiment, the coverage of the first opposing region 31BC is approximately the same as the coverage of the first intermediate region 31BA, and the coverage of the second opposing region 32BC is approximately the same as the coverage of the second intermediate region 32BA. With this structure, although slight stress may be generated compared to the first embodiment, capacitance density can be ensured and the connectivity between the internal electrode layer and the external electrode can be maintained. Simultaneously, stress concentration caused by the electrostrictive effect when voltage is applied is reduced, and stress concentration during firing due to the difference in the linear expansion coefficients of the dielectric layer and the internal electrode layer can be reduced.

[0109] Next, the method for measuring the coverage of the internal electrode layer 30 relative to the dielectric layer 20 in each embodiment will be described.

[0110] First, the internal electrode layer 30 and dielectric layer 20 located at the central portion of the laminate 10 in the lamination direction T are peeled away using an electric field, thereby exposing the internal electrode layer 30. Next, each region of the internal electrode layer 30 (regions 31A, 31BA, 31BB, 31BC, 32A, 32BA, 32BB, 32BC) is designated as the measurement target area and observed under a laser microscope. Here, the measurement target area is set, for example, to a range of 25 μm × 25 μm. Furthermore, when exposing the first internal electrode layer 31, each region of the first internal electrode layer 31 (regions 31A, 31BA, 31BB, 31BC) is first designated as the measurement target area and observed under a laser microscope. Then, the second internal electrode layer 32 is exposed by FIB (Focused Ion Beam) processing. Then, each region of the second internal electrode layer 32 (regions 32A, 32BA, 32BB, 32BC) is designated as the aforementioned measurement target area and observed under a laser microscope. Alternatively, the first internal electrode layer 31 can be observed under a laser microscope after laser microscope observation.

[0111] Then, the region of the internal electrode layer 30 within the measurement object area is identified by analyzing the laser microscope image. Then, based on the area of ​​the analysis object area and the area of ​​the region of the internal electrode layer 30, the coverage rate of the internal electrode layer 30 relative to the dielectric layer 20 is calculated as the coverage rate using the following formula (1).

[0112] Coverage (%) = (Area of ​​internal electrode layer / Area of ​​the analysis object) × 100…(1)

[0113] The coverage of the intermediate region is calculated by averaging the values ​​of the first intermediate region 31BA and the second intermediate region 32BA. The coverage of the first intermediate region 31BA and the second intermediate region 32BA is measured at the exact center of the lead-out portion in the width direction W and the length direction L.

[0114] The coverage of the external electrode side region is calculated by averaging the values ​​of the first external electrode side region 31BB and the second external electrode side region 32BB. The coverage of the first external electrode side region 31BB and the second external electrode side region 32BB is measured at a position 7% of the length of the lead-out portion in the direction from the end face of the laminate toward the center of the laminate, and at the exact center of the width direction W.

[0115] The coverage of the opposing portion side region is calculated by averaging the values ​​of the first opposing portion side region 31BC and the second opposing portion side region 32BC. The coverage of the first opposing portion side region and the second opposing portion side region is measured at a position that is 7% of the length of the lead-out portion in the length direction L of the lead-out portion, and is exactly at the center of the width direction W, in the direction toward the end face of the laminate, starting from the boundary between the opposing portion and the lead-out portion.

[0116] The coverage of the opposing portion is calculated by averaging the value of the first opposing portion 31A of the first internal electrode layer and the value of the second opposing portion 32A of the second internal electrode layer. The coverage of the first opposing portion 31A and the second opposing portion 32A is measured at the exact center of the opposing portion in the width direction W and the length direction L.

[0117] Next, the manufacturing method of the multilayer ceramic capacitor 1 according to this embodiment will be described. Regarding the multilayer ceramic capacitor 1 of this embodiment, the manufacturing method is not limited as long as the above-described requirements are met. However, a preferred manufacturing method includes the following steps. Details of each step are described below.

[0118] Prepare a dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30. Both the dielectric sheet for the dielectric layer 20 and the conductive paste for the internal electrode layer 30 contain binders and solvents. The binders and solvents can be known binders and solvents. For example, a paste containing conductive materials is a paste made by adding organic binders and organic solvents to metal powder.

[0119] On the dielectric sheet, conductive paste for the internal electrode layer 30 is printed using a printing plate patterned in the shape of the internal electrode layer 30 of this embodiment, for example, by screen printing or gravure printing. This prepares a dielectric sheet with a pattern of the first internal electrode layer 31 and a dielectric sheet with a pattern of the second internal electrode layer 32. At this time, by adjusting the thickness of the conductive paste applied to the areas where the coverage is desired, the coverage of each region of the internal electrode layer is adjusted to a desired value.

[0120] A predetermined number of dielectric sheets without the pattern of the internal electrode layer 30 are stacked to form a portion of the first main surface side outer layer 12 on the first main surface TS1 side. Dielectric sheets with the pattern of the first internal electrode layer 31 and dielectric sheets with the pattern of the second internal electrode layer 32 are sequentially and alternately stacked thereon to form a portion of the inner layer 11. A predetermined number of dielectric sheets without the pattern of the internal electrode layer 30 are stacked on top of this portion of the inner layer 11 to form a portion of the second main surface side outer layer 13 on the second main surface TS2 side. Thus, a laminated sheet is obtained.

[0121] Next, the laminated sheets are pressed in the lamination direction by means of isostatic pressing, thereby producing a laminated block.

[0122] Next, the laminated blocks are cut to a given size to become individual pieces, thus obtaining multiple laminated pieces. Then, the laminated pieces can be ground by methods such as tumbling to give the corners and edges rounded corners.

[0123] Next, the stacked pieces are fired to obtain the stack 10. The firing temperature at this time also depends on the materials of the dielectric layer 20 and the internal electrode layer 30, but is preferably 900°C or higher and 1400°C or lower.

[0124] A conductive paste, forming a base electrode layer 50, is applied to both ends of the laminate 10. In this embodiment, the base electrode layer 50 is a sintered layer. The sintered layer can be formed by applying a conductive paste containing glass components and metal to the laminate 10, for example, by impregnation, and then performing a sintering process. The sintering temperature is preferably 700°C or higher and 900°C or lower.

[0125] Alternatively, the laminated sheets before firing and the conductive paste applied to the laminated sheets can be fired simultaneously. In this case, the sintered layer is preferably formed by sintering the conductive paste, which contains ceramic material instead of glass. Here, the ceramic material added is particularly preferably the same type as the dielectric layer 20. In this case, the conductive paste is applied to the laminated sheets before firing, and the laminated sheets and the conductive paste applied to them are fired simultaneously, thereby forming a laminate 10 with a sintered layer.

[0126] Then, a plating layer is formed on the surface of the base electrode layer 50, which includes the sintered layer. In this embodiment, a first plating layer 60A is formed on the surface of the first base electrode layer 50A. Furthermore, a second plating layer 60B is formed on the surface of the second base electrode layer 50B. In this embodiment, a Ni plating layer and a Sn plating layer are formed as plating layers. During the plating process, either electrolytic plating or electroless plating can be used. However, regarding electroless plating, in order to increase the plating deposition rate, pretreatment using a catalyst or the like is required, which complicates the process. Therefore, electrolytic plating is generally preferred. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by roller plating.

[0127] Furthermore, when forming a base electrode layer using a thin film layer, a thin film layer serving as the base electrode layer is formed in the area where an external electrode is desired by masking or similar methods. The thin film layer is formed using thin film formation methods such as sputtering or vapor deposition. The thin film layer is a layer with a thickness of 10 μm or less on which metal particles are deposited.

[0128] Alternatively, when a conductive resin layer is provided, the conductive resin layer can also be configured as a sintered layer. When a conductive resin layer is provided, after applying a conductive resin paste containing a thermosetting resin and a metal component onto the sintered layer, it is heat-treated at a temperature of 250–550°C or higher. This thermosetting resin is then thermo-cured to form the conductive resin layer. The atmosphere during this heat treatment is preferably N2. Furthermore, to prevent resin scattering and oxidation of the various metal components, the oxygen concentration is preferably 100 ppm or less.

[0129] Alternatively, the plating layer can be directly disposed on the exposed portion of the internal electrode layer 30 of the laminate 10 without providing a base electrode layer. In this case, plating is performed on the first end face LS1 and the second end face LS2 of the laminate 10, forming the plating layer on the exposed portion of the internal electrode layer 30. During the plating process, either electrolytic plating or electroless plating can be used. However, regarding electroless plating, pretreatment with a catalyst or the like is required to increase the plating deposition rate, which complicates the process. Therefore, electrolytic plating is generally preferred. As the plating method, barrel plating is preferred. Furthermore, the upper plating layer formed on the surface of the lower plating layer can also be formed using the same method as the lower plating layer, as needed.

[0130] Through the above manufacturing processes, a multilayer ceramic capacitor 1 can be manufactured.

[0131] The multilayer ceramic capacitor 1 described above exhibits the following effects.

[0132] (1) The multilayer ceramic capacitor 1 according to the first embodiment includes: a multilayer body 10, comprising a plurality of stacked dielectric layers 20 and a plurality of stacked internal electrode layers 30, and including a first main surface TS1 and a second main surface TS2 opposite to each other in the stacking direction T, a first side surface WS1 and a second side surface WS2 opposite to each other in the width direction W orthogonal to the stacking direction T, and a first end surface LS1 and a second end surface LS2 opposite to each other in the length direction L orthogonal to the stacking direction T and the width direction W; a first external electrode 40A disposed on the first end surface LS1 side; and a second external electrode 40A disposed on the first end surface LS1 side. Electrode 40B is disposed on the second end face LS2 side, wherein a plurality of internal electrode layers 30 include a first internal electrode layer 31 and a second internal electrode layer 32. The first internal electrode layer 31 has a first lead-out portion 31B, one end of which extends to the first end face LS1 and is connected to the first external electrode 40A, and a first opposing portion 31A connected to the first lead-out portion 31B and opposed to the second internal electrode layer 32 disposed adjacent to it in the stacking direction. The second internal electrode layer 32 has a second lead-out portion 32, one end of which extends to the second end face LS2 and is connected to the second external electrode 40B. B. A second opposing portion 32A connected to the second lead-out portion 32B and opposite to the first internal electrode layer 31 disposed adjacent to it in the stacking direction. The first lead-out portion 31B has a first external electrode side region 31BB near the connection portion with the first external electrode 40A, a first opposing portion side region 31BC near the connection portion with the first opposing portion 31A, and a first intermediate region 31BA located between the first external electrode side region 31BB and the first opposing portion side region 31BC. The second lead-out portion 32B has a second external electrode side region near the connection portion with the second external electrode 40B. The coverage of the first intermediate region 31BA and the second intermediate region 32BA is lower than that of the first external electrode side region 31BB and the second external electrode side region 32BB, and the coverage of the first intermediate region 31BA and the second intermediate region 32BA is lower than that of the first external electrode side region 31BB and the second external electrode side region 32BB.

[0133] This ensures capacitance density and maintains the connectivity between the internal electrode layer and the external electrode, while reducing stress concentration caused by the electrostriction effect when voltage is applied.

[0134] (2) In the multilayer ceramic capacitor 1 described in (1), the coverage of the first opposing portion side region 31BC and the second opposing portion side region 32BC is higher than the coverage of the first intermediate region 31BA and the second intermediate region 32BA.

[0135] Therefore, near the connection between the opposing portion and the lead-out portion of the internal electrode layer, stress concentration during firing caused by the difference in the coefficients of linear expansion between the dielectric layer and the internal electrode layer can be reduced.

[0136] (3) In the multilayer ceramic capacitor 1 described in (1) or (2), the coverage of the first intermediate region 31BA and the second intermediate region 32BA is 55% or more.

[0137] For manufacturing the multilayer ceramic capacitor 1 of this embodiment, as long as it has such a structure, it is not easy to encounter difficulties in processing.

[0138] (4) In the multilayer ceramic capacitor 1 described in (1) to (3), the coverage of the first intermediate region 31BA and the second intermediate region 32BA is less than 80%.

[0139] This can further reduce stress concentration caused by the electrostriction effect when voltage is applied.

[0140] (5) In the multilayer ceramic capacitor 1 described in (1) to (4), the coverage of the first external electrode side region 31BB and the second external electrode side region 32BB is higher than the coverage of the first intermediate region 31BA and the second intermediate region 32BA, and is more than 68%.

[0141] This allows for a more reliable connection to the external electrodes.

[0142] (6) In the multilayer ceramic capacitor 1 described in (1) to (5), the coverage of the first opposing portion side region 31BC and the second opposing portion side region 32BC is higher than the coverage of the first intermediate region 31BA and the second intermediate region 32BA, and is more than 68%.

[0143] Therefore, it is possible to further reduce stress concentration caused by the electrostriction effect when voltage is applied, and thus further reduce stress concentration during firing caused by the difference in the coefficients of linear expansion between the dielectric layer and the internal electrode layer.

[0144] (7) In the multilayer ceramic capacitor 1 described in (1) to (6), the coverage of the first opposing portion 31A and the second opposing portion 32A is higher than the coverage of the first intermediate region 31BA and the second intermediate region 32BA, and is more than 75%.

[0145] Therefore, the effects of this embodiment can be achieved while ensuring capacitance density.

[0146] Experimental Example

[0147] <Sample Preparation>

[0148] According to the manufacturing method described in the embodiment, multiple batches of multilayer ceramic capacitors were manufactured as samples by adjusting the coverage of each region of the internal electrode layer. Then, using the manufactured samples, evaluations were performed on breakdown voltage caused by electrostriction, crack formation, and connectivity between the internal and external electrodes.

[0149] First, according to the manufacturing method described in this embodiment, a multilayer ceramic capacitor with the following specifications was manufactured as a sample of the embodiment.

[0150] • Dimensions of the multilayer ceramic capacitor: L×W×T = 3.2mm×2.5mm×2.5mm

[0151] • Capacitance: 2.2μF

[0152] Rated voltage: 100V

[0153] • Dielectric layer: BaTiO3

[0154] • Dielectric layer thickness: 1μm

[0155] • Internal electrode layer: Ni

[0156] • Substrate electrode layer: An electrode containing conductive metal (Cu) and glass components.

[0157] • Plating layer: A two-layer structure consisting of a 2μm Ni plating layer and a 2μm Sn plating layer.

[0158] • Length of the internal electrode lead-out portion (outer layer on the end face side (L-gap)) in the L direction: 220 μm

[0159] Here, each batch was manufactured under different manufacturing conditions, and the coverage of each region of the internal electrode layer was adjusted accordingly. In this experimental example, the thickness of the internal electrode layer was adjusted to a range of 0.5 μm to 1 μm, and the coverage of each region was adjusted. A necessary number of samples for each evaluation were prepared according to each embodiment and comparative example. Furthermore, five samples for coverage measurement were prepared according to each embodiment and comparative example, and the average of the measured coverage values ​​of the five samples was calculated as the coverage value for the embodiment and comparative example. However, regarding the region where the conductive paste for the internal electrode layer was applied at the reference coating thickness in this experimental example, based on the accumulation of evaluation results, the coverage was recorded as 88%.

[0160] Evaluation of breakdown voltage caused by electrostriction

[0161] The breakdown voltage of a multilayer ceramic capacitor varies depending on the degree of electrostriction. Therefore, electrostriction was evaluated using a BVD apparatus that measures the insulation breakdown voltage (BVD).

[0162] First, the external electrodes of each sample of the multilayer ceramic capacitor are placed on the electrodes of the BDV measuring device.

[0163] Next, at room temperature, with an initial voltage of 0V, a boost rate of 100V / sec, and a probe current (set to a faulty current value) of 10mA, the voltage was applied. The voltage just before exceeding the probe current was recorded and used as the voltage at which electrostriction breakdown occurred.

[0164] For each embodiment and comparative example, 20 samples were evaluated, and their average value was used as the electrostrictive breakdown voltage of the embodiment and comparative example.

[0165] <Evaluation of Crack Formation>

[0166] In the evaluation of crack formation caused by residual stress during the firing of multilayer ceramic capacitors, 100 multilayer ceramic capacitors from each batch were manufactured and tested.

[0167] The WT section passing through the center of the laminate was exposed by grinding, and the exposed section was observed using an optical microscope to confirm the presence or absence of cracks. The samples in which cracks were confirmed were counted as cracked samples (defective).

[0168] <Evaluation of the Connectivity Between Internal and External Electrodes>

[0169] In the evaluation of the connectivity between the internal and external electrodes, 100 units of each batch of multilayer ceramic capacitors were fabricated and implemented.

[0170] For 100 samples, a rapid discharge test was performed, in which the sample was short-circuited immediately after being subjected to a rated voltage of 100V. The electrostatic capacitance was then measured, and the rate of decrease from the electrostatic capacitance value before the rapid discharge test was determined. Samples with a decrease rate of 5% or more were counted as samples that showed some degree of breakage at the connection between the internal and external electrodes during the rapid discharge test, and were considered to have poor connections (defective).

[0171] Experimental Example 1

[0172] As Experimental Example 1, an experiment was conducted to evaluate the coverage rate of the intermediate regions of the leads with internal electrode layers. As shown in Table 1, the samples of Examples 1 to 5 were samples where the coverage rates of the first intermediate region 31BA and the second intermediate region 32BA were lower than the coverage rates of the first external electrode side region 31BB and the second external electrode side region 32BB, and the coverage rates of the first intermediate region 31BA and the second intermediate region 31BAB were lower than the coverage rates of the first opposing portion 31A and the second opposing portion 32A. The coverage rates of the intermediate regions of the samples of Examples 1 to 5 were set to 80%, 73%, 62%, 55%, and 41%, respectively, and the coverage rates of other regions were set to 88%. In addition, it is difficult to manufacture samples where the coverage rate of the intermediate region alone is less than 41%. As the samples of Comparative Examples 1 to 2, which were used as comparison objects, samples were prepared in which the coverage rates of the opposing portions and the leads were made equal.

[0173] [Table 1]

[0174]

[0175] As shown in Table 1, in the evaluation of the breakdown voltage caused by electrostriction, the electrostriction breakdown voltage of Examples 1 to 5, in which the coverage of the middle region was lower than that of the outer electrode side region and the coverage of the counter part, was higher than that of Comparative Example 2, in which the coverage of the counter part and the lead-out part were equal.

[0176] In the evaluation of the connectivity between the internal and external electrodes, no connection defects were observed in Examples 1-5. However, in Comparative Example 1, connection defects were observed.

[0177] In the evaluation of crack initiation, no cracks were observed in Examples 1-4. In Example 5, the crack initiation rate was also extremely low. However, in Comparative Example 2, the crack initiation rate was higher compared to the examples.

[0178] In addition, in Comparative Example 1, where the coverage of the opposing portion is lower than that of Examples 1-5, it can be considered that the capacitance density is lower than that of Examples 1-5.

[0179] Based on the above results, it was confirmed that, in the multilayer ceramic capacitors of Examples 1-5, where the coverage of the intermediate region is lower than that of the outer electrode side region and the opposing portion, capacitance density can be ensured and the connectivity between the inner electrode layer and the outer electrode can be maintained, while stress concentration caused by electrostriction during voltage application can be reduced. The coverage of the intermediate region is preferably 41% or more, more preferably 55% or more. The coverage of the intermediate region can be 41% or more and 88% or less, or 55% or more and 88% or less. Furthermore, compared to Comparative Example 2, a tendency for lower voltage to occur due to electrostriction breakdown was observed when the coverage, including the intermediate region, was high. Conversely, if the coverage of the intermediate region is too low, a tendency for residual stress during firing was observed.

[0180] Experiment Example 2

[0181] As Experimental Example 2, an experiment was conducted to evaluate the coverage of the outer electrode side region of the lead-out portion of the internal electrode layer. As shown in Table 2, the samples of Examples 1 to 3 were samples in which the coverage of the first intermediate region 31BA and the second intermediate region 32BA was lower than the coverage of the first outer electrode side region 31BB and the second outer electrode side region 32BB, and the coverage of the first intermediate region 31BA and the second intermediate region 31BAB was lower than the coverage of the first opposing portion 31A and the second opposing portion 32A. The coverage of the intermediate region of the samples of Examples 1 to 3 was set to 62%, and the coverage of the outer electrode side region was set to 88%, 74%, and 68%, respectively. The sample of Comparative Example 1 was a sample in which the coverage of the outer electrode side region was 60%, and the coverage of the first outer electrode side region 31BB and the second outer electrode side region 32BB was lower than the coverage of the first intermediate region 31BA and the second intermediate region 32BA.

[0182] [Table 2]

[0183]

[0184] As shown in Table 2, in the evaluation of breakdown voltage caused by electrostriction and the evaluation of crack formation, the results for Examples 1-3 and Comparative Example 1 were all good.

[0185] However, in the evaluation of the connectivity between the internal and external electrodes, the results for Examples 1 to 3 were good, while for Comparative Example 1, poor connectivity was observed.

[0186] Based on the above results, it was confirmed that, in the multilayer ceramic capacitors of Examples 1 to 3, where the coverage of the intermediate region is lower than that of the outer electrode side region and the opposing portion, capacitance density can be ensured and the connectivity between the inner electrode layer and the outer electrode can be maintained, while stress concentration caused by electrostriction effect when voltage is applied is reduced. Preferably, the coverage of the outer electrode side region is higher than that of the intermediate region, and is 68% or more.

[0187] Experimental Example 3

[0188] As Experimental Example 3, an experiment was conducted to evaluate the coverage of the opposing portion side region of the lead-out portion of the internal electrode layer. As shown in Table 3, the samples of Examples 1 to 4 were samples in which the coverage of the first intermediate region 31BA and the second intermediate region 32BA was lower than the coverage of the first external electrode side region 31BB and the second external electrode side region 32BB, and the coverage of the first intermediate region 31BA and the second intermediate region 31BAB was lower than the coverage of the first opposing portion 31A and the second opposing portion 32A. The coverage of the intermediate region of the samples of Examples 1 to 4 was set to 62%, and the coverage of the opposing portion side region was set to 88%, 75%, 68%, and 64%, respectively.

[0189] [Table 3]

[0190]

[0191] As shown in Table 3, in the evaluation of the breakdown voltage caused by electrostriction and the evaluation of the connectivity between the internal and external electrodes, Examples 1 to 4 all yielded good results.

[0192] In the evaluation of crack formation, no cracks were observed in Examples 1-3. The crack formation rate was also extremely low in Example 4.

[0193] Based on the above results, it was confirmed that, in the multilayer ceramic capacitors of Examples 1-4, where the coverage of the intermediate region is lower than that of the outer electrode side region and the opposing portion, capacitance density can be ensured and the connectivity between the inner electrode layer and the outer electrode can be maintained, while stress concentration caused by electrostriction during voltage application can be reduced. The coverage of the opposing portion side region is preferably higher than that of the intermediate region, at 64% or more, more preferably at 68% or more. Furthermore, if the coverage of the opposing portion side region is reduced, a tendency to generate residual stress during firing is observed.

[0194] Experiment Example 4

[0195] As Experimental Example 4, an experiment was conducted to evaluate the coverage of the opposing portions of the internal electrode layers. As shown in Table 4, the samples of Examples 1-3 were samples where the coverage of the first intermediate region 31BA and the second intermediate region 32BA was lower than the coverage of the first external electrode side region 31BB and the second external electrode side region 32BB, and the coverage of the first intermediate region 31BA and the second intermediate region 31BAB was lower than the coverage of the first opposing portion 31A and the second opposing portion 32A. The coverage of the intermediate regions of the samples of Examples 1-3 was set to 62%, and the coverage of the opposing portions was set to 88%, 75%, and 71%, respectively.

[0196] [Table 4]

[0197]

[0198] As shown in Table 4, in the evaluation of the breakdown voltage caused by electrostriction and the evaluation of the connectivity between the internal and external electrodes, Examples 1 to 3 all showed good results.

[0199] In the evaluation of crack formation, no cracks were observed in Examples 1 and 2. The crack formation rate was also extremely low in Example 3.

[0200] Based on the above results, it was confirmed that, in the multilayer ceramic capacitors of Examples 1-3, where the coverage of the intermediate region is lower than that of the outer electrode side region and the opposing portion, capacitance density can be ensured and the connectivity between the inner electrode layer and the outer electrode can be maintained, while stress concentration caused by electrostriction during voltage application can be reduced. The coverage of the opposing portion is preferably higher than that of the intermediate region, and is at least 71%, more preferably at least 75%. Furthermore, if the coverage of the opposing portion is reduced, a tendency to generate residual stress during firing is observed.

[0201] The embodiments of the present invention have been described above, but the present invention is not limited to these embodiments and can be implemented in various ways without departing from the spirit of the present invention. The present invention includes the following combinations.

[0202] <1> A multilayer ceramic capacitor includes: a multilayer body comprising multiple stacked dielectric layers and multiple stacked internal electrode layers, and including a first main surface and a second main surface opposite each other in the stacking direction, a first side surface and a second side surface opposite each other in a width direction orthogonal to the stacking direction, and a first end surface and a second end surface opposite each other in a length direction orthogonal to the stacking direction and the width direction; a first external electrode disposed on the first end surface side; and a second external electrode disposed on the second end surface side, wherein the multiple internal electrode layers include a first internal electrode layer and a second internal electrode layer, the first internal electrode layer having a first lead-out portion extending to the first end surface and connected to the first external electrode, and a first opposing portion connected to the first lead-out portion and opposing the second internal electrode layer disposed adjacent to it in the stacking direction, the second internal electrode layer having a second lead-out portion extending to the second end surface and connected to the second external electrode, and a first opposing portion opposite to the second internal electrode layer disposed adjacent to it in the stacking direction. The second lead-out portion is connected to and opposite the first inner electrode layer arranged adjacent to it in the stacking direction to a second opposing portion. The first lead-out portion has a first outer electrode side region near the connection portion with the first outer electrode, a first opposing portion side region near the connection portion with the first opposing portion, and a first intermediate region between the first outer electrode side region and the first opposing portion side region. The second lead-out portion has a second outer electrode side region near the connection portion with the second outer electrode, a second opposing portion side region near the connection portion with the second opposing portion, and a second intermediate region between the second outer electrode side region and the second opposing portion side region. The coverage of the first intermediate region and the second intermediate region is lower than the coverage of the first outer electrode side region and the second outer electrode side region, and the coverage of the first intermediate region and the second intermediate region is lower than the coverage of the first opposing portion and the second opposing portion.

[0203] <2> according to <1> The aforementioned multilayer ceramic capacitor, wherein,

[0204] The coverage of the first opposing side region and the second opposing side region is higher than the coverage of the first intermediate region and the second intermediate region.

[0205] <3> according to <1> or <2> The aforementioned multilayer ceramic capacitor, wherein,

[0206] The coverage of the first intermediate region and the second intermediate region is more than 55%.

[0207] <4> according to <1> ~ <3> The aforementioned multilayer ceramic capacitor, wherein,

[0208] The coverage of the first intermediate region and the second intermediate region is less than 80%.

[0209] <5> according to <1> ~ <4> The aforementioned multilayer ceramic capacitor, wherein,

[0210] The coverage of the first external electrode side region and the second external electrode side region is higher than that of the first intermediate region and the second intermediate region, and is above 68%.

[0211] <6> according to <1> ~ <5> The aforementioned multilayer ceramic capacitor, wherein,

[0212] The coverage of the first opposing portion side region and the second opposing portion side region is higher than the coverage of the first intermediate region and the second intermediate region, and is more than 68%.

[0213] <7> according to <1> ~ <6> The aforementioned multilayer ceramic capacitor, wherein,

[0214] The coverage of the first opposing portion and the second opposing portion is higher than the coverage of the first intermediate region and the second intermediate region, and is more than 75%.

[0215] Explanation of reference numerals in the attached figures

[0216] 1: Multilayer ceramic capacitor;

[0217] 10: Layered bodies;

[0218] 20: Dielectric layer;

[0219] 30: Internal electrode layer;

[0220] 31: First internal electrode layer;

[0221] 31A: First opposing part;

[0222] 31B: First excerpt;

[0223] 31BA: First intermediate region;

[0224] 31BB: Region on the first external electrode side;

[0225] 31BC: First opposing part side region;

[0226] 32: Second inner electrode layer;

[0227] 32A: Second opposing part;

[0228] 32B: Second lead-out section;

[0229] 32BA: Second middle area;

[0230] 32BB: Region on the second external electrode side;

[0231] 32BC: Second opposing side region;

[0232] 40: External electrode;

[0233] 40A: First external electrode;

[0234] 40B: Second external electrode;

[0235] 50: Substrate electrode layer;

[0236] 50A: First substrate electrode layer;

[0237] 50B: Second base electrode layer;

[0238] L: Length direction;

[0239] T: Stacking direction;

[0240] W: Width direction;

[0241] LS1: First end face;

[0242] LS2: Second end face;

[0243] TS1: 1st main surface;

[0244] TS2: 2nd main surface;

[0245] WS1: First side;

[0246] WS2: Second side.

Claims

1. A multilayer ceramic capacitor, comprising: A laminate includes multiple stacked dielectric layers and multiple stacked internal electrode layers, and includes a first main surface and a second main surface opposite each other in the stacking direction, a first side surface and a second side surface opposite each other in the width direction orthogonal to the stacking direction, and a first end surface and a second end surface opposite each other in the length direction orthogonal to the stacking direction and the width direction. A first external electrode is disposed on the first end face side; and The second external electrode is disposed on the second end face side. in, The plurality of internal electrode layers includes a first internal electrode layer and a second internal electrode layer. The first inner electrode layer has a first lead-out portion extending from one end to the first end face and connected to the first outer electrode, and a first opposing portion connected to the first lead-out portion and opposite to the second inner electrode layer arranged adjacent to it in the stacking direction. The second inner electrode layer has a second lead-out portion extending from one end to the second end face and connected to the second outer electrode, and a second opposing portion connected to the second lead-out portion and opposite to the first inner electrode layer arranged adjacent to it in the stacking direction. The first lead-out portion has a first external electrode side region near the connection portion with the first external electrode, a first opposing portion side region near the connection portion with the first opposing portion, and a first intermediate region between the first external electrode side region and the first opposing portion side region. The second lead-out portion has a second external electrode side region near the connection portion with the second external electrode, a second opposing portion side region near the connection portion with the second opposing portion, and a second intermediate region located between the second external electrode side region and the second opposing portion side region. The coverage of the first intermediate region and the second intermediate region is lower than the coverage of the first external electrode side region and the second external electrode side region. The coverage of the first intermediate region and the second intermediate region is lower than the coverage of the first opposing portion and the second opposing portion.

2. The multilayer ceramic capacitor according to claim 1, wherein, The coverage of the first opposing side region and the second opposing side region is higher than the coverage of the first intermediate region and the second intermediate region.

3. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein, The coverage of the first intermediate region and the second intermediate region is more than 55%.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein, The coverage of the first intermediate region and the second intermediate region is less than 80%.

5. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein, The coverage of the first external electrode side region and the second external electrode side region is higher than that of the first intermediate region and the second intermediate region, and is above 68%.

6. The multilayer ceramic capacitor according to any one of claims 1 to 5, wherein, The coverage of the first opposing portion side region and the second opposing portion side region is higher than the coverage of the first intermediate region and the second intermediate region, and is more than 68%.

7. The multilayer ceramic capacitor according to any one of claims 1 to 6, wherein, The coverage of the first opposing portion and the second opposing portion is higher than the coverage of the first intermediate region and the second intermediate region, and is more than 75%.

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