Stacked integrated circuit device including integrated capacitor device

Abstract

A stacked integrated circuit (IC) device includes a first die including active circuitry and a power distribution network (PDN). The first die has a first set of contacts on a first side of the first die. The stacked IC device also includes a second die coupled to the first side of the first die on the first side of the second die. The second die also includes a second set of contacts on a second side of the second die to electrically connect circuitry of the second die to the substrate. The stacked IC device also includes an integrated capacitor device (ICD) coupled to the first side of the first die. The ICD is electrically connected to the PDN via a first set of contacts and includes one or more through ICD conductors to electrically connect the PDN to a substrate.

Description

[0001] I. Cross-references to related applications

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 498,978, filed April 28, 2023, and U.S. Non-Provisional Patent Application No. 18 / 454,388, filed August 23, 2023, the contents of each of which are expressly incorporated herein by reference in their entirety.

[0003] II. Domain

[0004] Various features are involved in stacked integrated circuit devices.

[0005] III. Background Technology

[0006] Electrical connections exist at every level of a system hierarchy. This system hierarchy includes active devices at the lowest system level interconnecting with system-level interconnects at the highest level. For example, interconnect layers can connect different devices together on an integrated circuit. As integrated circuits become more complex, more interconnect layers are used to provide electrical connections between devices. Recently, due to the large number of devices interconnected in modern electronic devices, the number of interconnect levels in a circuit system has increased significantly. This increase in the number of interconnect levels to support the increased number of devices involves more complex processes.

[0007] State-of-the-art mobile applications demand small form factor, low cost, tight power budgets, and high electrical performance. Mobile packaging designs have evolved to meet these divergent goals for enabling multimedia-enhanced mobile applications. However, when multiple dies are arranged within a small form factor, these mobile applications are susceptible to power and signal routing issues. Specifically, due to the small footprint of stacked integrated circuits (ICs), decoupling the power distribution network (PDN) of stacked ICs to suppress power distribution noise is challenging.

[0008] IV. Overview

[0009] Various features are involved in integrated circuit devices.

[0010] One example provides a stacked integrated circuit (IC) device including a first die comprising an active circuit system and a power distribution network (PDN). The first die has a first set of contacts on a first side of the first die. The stacked IC device also includes a second die coupled to the first side of the first die on the first side of the second die. The second die also includes a second set of contacts on a second side of the second die to electrically connect the circuit system of the second die to a substrate. The stacked IC device also includes an integrated capacitor device (ICD) coupled to the first side of the first die. The ICD is electrically connected to the PDN via the first set of contacts and includes one or more through-conductors to electrically connect the PDN to the substrate.

[0011] Another example provides an apparatus including a stacked IC device. The stacked IC device includes a first die including an active circuit system and a PDN. The first die has a first set of contacts on a first side of the first die. The stacked IC device also includes a second die coupled to the first side of the first die on the first side of the second die. The second die also includes a second set of contacts on a second side of the second die to electrically connect the circuit system of the second die to a substrate. The stacked IC device also includes an ICD coupled to the first side of the first die. The ICD is electrically connected to the PDN via the first set of contacts and includes one or more through-conductors to electrically connect the PDN to the substrate.

[0012] Another example provides a method for manufacturing a stacked IC device. The method includes coupling a first side of a second die to a first side of a first die. The first die includes a first set of contacts, an active circuit system, and a power distribution network (PDN) on the first side of the first die. The second die includes a second set of contacts on a second side of the second die to electrically connect the circuit system of the second die to a substrate. The method also includes coupling an ICD to the first side of the first die via the first set of contacts, wherein the ICD includes one or more through-ICD conductors to electrically connect the PDN to the substrate.

[0013] V. Attached Figure Description

[0014] The various features, essences, and advantages will become apparent when the following detailed description is understood in conjunction with the accompanying drawings, in which similar reference numerals are used throughout to indicate them accordingly.

[0015] Figure 1A A cross-sectional view of a device including an exemplary stacked IC device is described.

[0016] Figure 1B Commentary Figure 1A A top view of an exemplary stacked IC device.

[0017] Figure 2AA cross-sectional view of a device including an exemplary stacked IC device is described.

[0018] Figure 2B Commentary Figure 2A A top view of an exemplary stacked IC device.

[0019] Figure 3A A cross-sectional view of a device including an exemplary stacked IC device is described.

[0020] Figure 3B Commentary Figure 3A A top view of an exemplary stacked IC device.

[0021] Figure 4A A cross-sectional view of a device including an exemplary stacked IC device is described.

[0022] Figure 4B Commentary Figure 4A A top view of an exemplary stacked IC device.

[0023] Figure 5 A top view of an exemplary stacked IC device is described.

[0024] Figure 6 A top view of an exemplary stacked IC device is described.

[0025] Figure 7 A top view of an exemplary stacked IC device is described.

[0026] Figure 8 A top view of an exemplary stacked IC device is described.

[0027] Figure 9 A cross-sectional view of a stacked package device, including an exemplary stacked IC device, is described.

[0028] Figure 10 (which extends across several pages) illustrates exemplary procedures for manufacturing an exemplary stacked IC device.

[0029] Figure 11 (which extends across several pages) illustrates another exemplary process for manufacturing an exemplary stacked IC device.

[0030] Figure 12 An exemplary flowchart illustrates a method for manufacturing an exemplary stacked IC device.

[0031] Figure 13 This document describes various electronic devices that can integrate the dies, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein.

[0032] VI. Detailed Description

[0033] In the following description, specific details are set forth to provide a thorough understanding of various aspects of this disclosure. However, those skilled in the art will understand that these aspects can be practiced without these specific details. For example, circuits may be shown as block diagrams to avoid obscuring these aspects in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail to avoid obscuring these aspects of this disclosure.

[0034] Specific aspects of this disclosure are described below with reference to the accompanying drawings. In the specification, common features are designated by common reference numerals. As used herein, various terms are used only for the purpose of describing a particular implementation and are not intended to limit the implementation. For example, the singular forms “a,” “some,” and “the” are intended to also include the plural forms, unless the context clearly indicates otherwise. Furthermore, some features described herein are singular in some implementations and plural in others. For ease of reference herein, such features are generally introduced as “one or more” features and are subsequently referred to in the singular or optionally plural form (as indicated by “(a few)”), unless an aspect relating to multiple features of these features is being described.

[0035] As described herein, the terms “including,” “having,” and “containing” may be used interchangeably with “comprising,” “with,” or “owning.” As used herein, “exemplary” indicates an example, an implementation, and / or aspect, and should not be construed as limiting or indicating a preference or preferred implementation. As used herein, ordinal numbers used to modify elements (such as structures, components, operations, etc.) (e.g., “first,” “second,” “third,” etc.) do not themselves indicate any priority or order of that element relative to another element, but merely distinguish that element from another element with the same name (but using an ordinal number). As used herein, the term “set” (collection) refers to one or more specific elements, while the term “multiple” refers to multiple specific elements (e.g., two or more specific elements).

[0036] Improvements in manufacturing technology and the demand for lower-cost and more powerful electronic devices have led to an increasing complexity of ICs. Typically, more complex ICs have more sophisticated interconnect schemes to enable interconnection between ICs in a device. Due to the sheer number of devices interconnected in today's state-of-the-art mobile applications, the number of interconnect levels in circuit systems has increased significantly.

[0037] These interconnects include back-end process (BEOL) interconnect layers, which can refer to conductive interconnect layers used for electrical coupling to front-end process (FEOL) active devices of the IC. Various BEOL interconnect layers are formed at corresponding BEOL interconnect levels, with lower BEOL interconnect levels typically using thinner metal layers compared to higher BEOL interconnect levels. BEOL interconnect layers can be electrically coupled to midline (MOL) interconnect layers, which interconnect to the IC's FEOL active devices.

[0038] State-of-the-art mobile applications demand small form factor, low cost, tight power budgets, and high electrical performance. Mobile packaging designs have evolved to meet these divergent goals for enabling multimedia-enhanced mobile applications. For example, fan-out (FO) wafer-level packaging (WLP), or FO-WLP process technology, is one development in packaging technology applicable to mobile applications. This chip-first FO-WLP process technology solution provides flexibility for fan-in and fan-out connections from the die to the package ball. Furthermore, this solution offers a significant reduction in the height of the first-level interconnect between the die and package ball in mobile application devices. However, when multiple dies are arranged within a small form factor, these mobile applications are susceptible to power and signal routing challenges.

[0039] Stacked die and chip architecture solutions are becoming increasingly prevalent as they demonstrate significant power performance area (PPA) gains for product lines. As used herein, “stacked die” and / or “stacked IC” refers to an arrangement in which one die (e.g., the first die) is positioned on top of (including directly above) another die (e.g., the second die). In stacked die or stacked IC devices, one or more dies may also be positioned on top of one or more other devices, such as integrated capacitor devices, as further described below. Unfortunately, stacked chip solutions can involve high power density targets, which can lead to significant power distribution inefficiencies. Various aspects of this disclosure provide a stacked IC device arranged to provide improved integration of capacitors with a power distribution network (PDN), resulting in improved PDN performance.

[0040] As used herein, the term "layer" includes films and, unless otherwise stated, is not construed as indicating vertical or horizontal thickness. As used herein, the term "chip" can refer to an integrated circuit block, a functional circuit block, or other similar circuit blocks specifically designed to work with one or more other chips to form larger, more complex chip architectures.

[0041] 3D integrated circuits (3D ICs) comprise a stacked and interconnected set of chips. Generally, 3D IC architectures offer higher performance, increased functionality, lower power consumption, and / or a smaller footprint compared to providing the same circuitry on a monolithic die or in a two-dimensional (2D) IC structure. Unfortunately, capacitive decoupling of the power distribution network (PDN) for 3D ICs to suppress power distribution noise is challenging. Specifically, the available space for landside capacitors (LSCs) in the die shadow of a 3D IC is limited due to its smaller footprint. For example, different logic blocks of a 3D IC may be placed overlapping each other in a stacked die, making decoupling the circuitry even more challenging. Furthermore, the electrical paths of conventional landside capacitor placements on the package substrate may exhibit large parasitic inductance, which can degrade the decoupling performance of the landside capacitors.

[0042] Various aspects of this disclosure relate to stacked IC devices using a 3D IC architecture, wherein integrated capacitor devices (ICDs) are stacked with dies in the 3D IC architecture to provide PDN capacitor integration. In some aspects of this disclosure, the capacitor integration method places the ICD in a space adjacent to a lower die in the die stack (e.g., between a substrate beneath an upper die and a lower die in the die stack) and electrically coupled to the PDN of the upper die, as further described below. The ICD may include, for example, one or more deep trench capacitors integrated in a semiconductor (e.g., silicon) die, one or more multilayer ceramic capacitors, one or more integrated passive device (IPD) capacitors, etc.

[0043] Exemplary stacked IC devices including integrated capacitor devices

[0044] Figure 1A A cross-sectional view of a device 100, including an exemplary stacked IC device 102, is described. Figure 1B Commentary Figure 1A A top view of an exemplary stacked IC device. Figure 1B In (and the subsequent top view), the top die of the die stack (e.g., first die 104) is illustrated with solid lines, and the components below the top die in the top view are illustrated with dashed lines.

[0045] The stacked IC device 102 includes multiple dies (e.g., a first die 104 and a second die 114). Each die may include an integrated circuit system, such as multiple transistors and / or other circuit elements arranged and interconnected to form logic cells, memory cells, etc. Components of the integrated circuit system may be formed in and / or on a semiconductor substrate. Different implementations may use different types of transistors, such as field-effect transistors (FETs), planar FETs, fin FETs, gate-all-around FETs, or a mixture of these transistor types. In some implementations, front-end processing (FEOL) processes may be used to fabricate the integrated circuit system in and / or on the semiconductor substrate.

[0046] exist Figure 1A and 1B In the stacked IC device 102, the first die 104 includes an active circuit system 106 and a power distribution network (PDN) 108. The PDN 108 includes, for example, one or more power rails, one or more ground rails, etc. The active circuit system 106 includes, for example, processing logic blocks (e.g., transistor blocks), memory blocks, etc. The first die 104 also includes a first set of contacts (including representative contacts 110) on a first side 112 of the first die 104.

[0047] exist Figure 1A and 1B In the stacked IC device 102, a second die 114 is coupled on a first side 116 of the second die to a first side 112 of the first die 104. The second die 114 includes a second set of contacts (including representative contacts 120) on a second side 118 of the second die 114 to electrically connect the circuitry of the second die 114 to a substrate 122. Due to space limitations, the circuitry of the second die 114 is not described; however, the circuitry of the second die 114 may include a PDN (e.g., one or more power rails, one or more ground rails), processing logic blocks, memory blocks, or other functional circuitry blocks configured to operate in conjunction with the active circuitry 106 of the first die 104.

[0048] The stacked IC device 102 also includes an integrated capacitor device (ICD) 124 coupled to a first side 112 of the first die 104. The ICD 124 is electrically connected to the PDN 108 via a first contact group and includes one or more through-ICD conductors 126 to electrically connect the PDN 108 to the substrate 122. Figure 1BAs explained, ICD 124 includes one or more capacitors 150 formed on or embedded in substrate 152. For example, in some implementations, capacitors 150 include one or more trench capacitors (e.g., deep trench capacitors (DTC)) in a semiconductor substrate. In this example, the semiconductor substrate may include or correspond to a third die (i.e., a die different from the first die 104 and the second die 114). In such implementations, the ICD conductors 126 include through-holes through the semiconductor substrate. As another example, capacitors 150 include or correspond to one or more multilayer ceramic capacitors.

[0049] In a particular aspect, at least one edge 130 of the first die 104 is suspended over at least one edge 132 of the second die 114 to define an overhang region 134, and the ICD 124 is disposed within the overhang region 134. Disposing the ICD 124 within the overhang region 134 positions the capacitors 150 of the ICD 124 very close to the first die 104, thereby enabling the use of a very short, low-inductance connection between the capacitors 150 and the PDN 108.

[0050] In some implementations, the stacked IC device 102 includes a molding compound 136 that at least partially encapsulates a first die 104, a second die 114, and an ICD 124 to form a packaged IC device. In some such implementations, one or more conductors 138 pass through the molding compound 136 and are electrically connected to the first die 104. In such implementations, the conductors 138 (e.g., through-hole vias (TMVs)) are configured to provide an electrical connection between the first die 104 and the substrate 122. For example, in some such implementations, the first die 104 includes an input / output (I / O) circuitry 142, and the conductors 138 are connected to the I / O circuitry 142 to provide a data path 140 between the first die 104 and another device 144 coupled to the substrate 122. As an illustrative example, the other device 144 may include a dynamic random access memory (DRAM) chip (or die). In this illustrative example, the I / O circuitry 142 of the first die 104 may include or correspond to interface circuitry (e.g., serializer / deserializer (SerDes) circuitry, double data rate (DDR) type DRAM bus interface circuitry), memory buffers, and / or other circuitry facilitating interaction between the active circuitry 106 and the DRAM. In some implementations, the I / O circuitry 142 may also be connected to other devices in addition to or in lieu of other devices 144. For example, the I / O circuitry 142 may interact with one or more other devices on a printed circuit board via connector 174.

[0051] The stacked IC device 102 may also include connectors to couple the stacked IC device 102 to other circuitry of device 100. For example, the stacked IC device 102 may include interconnects 146 (such as ball grid array (BGA), C4 bumps, or other connectors) to electrically couple the stacked IC device 102 to substrate 122. In this example, interconnect 146 may include connectors to a second set of contacts of the second die 114, through ICD conductors 126, and a plurality of conductors 138 to substrate 122.

[0052] exist Figure 1A In this stacked IC device 102, a third set of contacts (including representative contacts 160) on a first side 116 of a second die 114 is included. The third set of contacts electrically connects various circuit systems of the first and second dies 104, 114, such as connecting an active circuit system 106 of the first die 104 to the circuit system of the second die 114. The third set of contacts on the first side 116 of the second die 114 may include, for example, microbumps, conductive pillars, conductive pads (e.g., for pad-to-pad bonding), or other similar die-to-die interconnect contacts for three-dimensional (3D) die stacking. For example, in some implementations, the first die 104 is a first die, and the second die 114 is a second die designed to operate in conjunction with the first die. For the purposes of explanation, in some implementations, the active circuit system 106 of the first chip / first die 104 includes one or more first functional circuit blocks, and the circuit system of the second chip / second die 114 includes one or more second functional circuit blocks, wherein the one or more first functional circuit blocks and the one or more second functional circuit blocks are operationally dependent on each other.

[0053] Using dies arranged and interconnected as 3D stacked ICs to form the stacked IC device 102 offers various benefits compared to providing the same functional circuitry in a single monolithic chip. For example, each die is smaller than a single monolithic die comprising all the same functional circuitry blocks. Since yield losses in IC manufacturing (and the costs resulting from those losses) tend to increase with die size, using smaller dies can reduce yield losses in the IC manufacturing process (i.e., increase yield). Another benefit is that dies can be manufactured at different locations and / or by different manufacturers, and in some cases, using different manufacturing technologies (e.g., different manufacturing technology nodes). As an example, one die of a die-based integrated device (e.g., the first die 104 of the stacked IC device 102) may include components with a first minimum size (e.g., interconnects, transistors, etc.), and another die of a die-based integrated device (e.g., the second die 114 of the stacked IC device 102) may include components with a second minimum size (e.g., interconnects, transistors, etc.), wherein the second minimum size is larger than the first minimum size. In contrast, all circuit systems of a monolithic die are manufactured using the same manufacturing technologies and equipment. As a result, when manufacturing a monolithic die, the entire die may be subject to the most stringent manufacturing constraints of the most complex components. Conversely, when using dies, different dies can be manufactured using different manufacturing technologies (e.g., different manufacturing technology nodes), and only one or more dies containing the most complex components are subject to the most stringent manufacturing constraints. In this arrangement, dies manufactured using cheaper and / or higher-volume manufacturing technologies can be integrated with dies manufactured using more expensive and / or lower-volume manufacturing technologies to form ICs (e.g., stacked IC devices 102), resulting in overall savings. Furthermore, in some cases, the design of dies can be changed as technology improves. Die stacking allows such new die designs to be integrated with older die designs to form stacked IC devices, which increases manufacturing flexibility and reduces design costs.

[0054] Optionally, the second die 114 may include one or more through-silicon vias (TSVs) 162 that couple one or more contacts from the third set of contacts (e.g., contact 160) to one or more contacts from the second set of contacts (e.g., contact 120) to electrically connect the active circuitry 106 of the first die 104 to the substrate 122. In some implementations, the stacked IC device 102 includes a fourth set of contacts (including representative contact 164) on the second side 166 of the first die 104 to electrically connect the stacked IC device 102 to another device (e.g., Figure 1AOptional device 168. Optional device 168 may include another die of stacked IC device 102. Alternatively, optional device 168 may include a different IC coupled to stacked IC device 102 (e.g., a different monolithic die or stacked IC device providing different functionality than stacked IC device 102). When optional device 168 is included, first die 104 may include a TSV similar to TSV 162 of second die 114, thereby enabling interconnection from optional device 168 to second die 114 and / or from optional device 168 to substrate 122 via stacked IC device 102.

[0055] In certain aspects, capacitors 150 are coupled to PDN 108 to suppress power distribution noise of PDN 108. In conventional implementations, PDN 108 may be coupled to one or more landside capacitors (such as...). Figure 1A DTC 170 in the middle), coupled to one or more embedded capacitors (such as DTC 170 in the middle), and ... Figure 1A The DTC 172 (or both) are used to provide power distribution noise suppression. While one benefit of using stacked IC devices (such as stacked IC device 102) is the reduced footprint compared to comparable monolithic IC devices, this reduced footprint can present challenges in the placement of noise suppression capacitors. For example, noise suppression capacitors should be placed as close as possible to the PDN to provide a low-inductance electrical connection between the noise suppression capacitor and the PDN. Higher inductance leads to inefficient use of the capacitor, resulting in degraded PDN performance; therefore, lower-inductance electrical connections are generally preferred, especially in low-power devices (e.g., mobile communication devices or other battery-powered devices).

[0056] One strategy for placing noise suppression capacitors near the PDN is to place them within the die shadow of the die or IC device that includes the PDN. Stacked IC devices (such as stacked IC device 102) have small die shadows, and the area within the die shadow can often be advantageously used for other purposes, such as providing electrical connectors 174. Therefore, the technical advantage of positioning the ICD 124 in the overhang region 134 between the first die 104 and the substrate 122 is that fewer ground-side capacitors can be used to suppress noise, which frees up space on the substrate 122 for more electrical connectors 174 or allows for more advantageous positioning of such connectors 174.

[0057] Another strategy for limiting the impedance of the noise suppression capacitor to the PDN of the IC device is to embed one or more noise suppression capacitors within the substrate 122. The DTC 172 is an example of such a noise suppression capacitor. Positioning the noise suppression capacitor within the substrate 122 presents the same challenges regarding smaller die shadows, but reduces the displacement of the connector 174 on the substrate 122. However, positioning the noise suppression capacitor within the substrate 122 increases the fabrication complexity of the substrate 122 and may require the formation of discontinuities in one or more conductive surfaces 176 of the substrate 122, which could degrade the performance of the device 100. Therefore, the technical advantage of positioning the ICD 124 in the overhanging region 134 between the first die 104 and the substrate 122 is that it does not increase the fabrication complexity of the substrate 122 and avoids discontinuities in the conductive surfaces 176 of the substrate 122.

[0058] In addition to the above, the technical advantage of positioning the ICD 124 in the overhanging region 134 between the first die 104 and the substrate 122 is that this arrangement provides a much shorter (and therefore lower impedance) conductive path between the PDN 108 and the capacitor 150 compared to the capacitor or landside capacitor used to connect the PDN to the capacitor embedded in the substrate 122.

[0059] Although in some implementations Figure 1A and 1B The stacked IC device 102 is described as including two dies (e.g., a first die 104 and a second die 114), but the stacked IC device 102 may also include two or more dies stacked or interconnected to form a 3D IC stack. In such implementations, one or more additional overhang regions 134 may be formed between the dies of the stacked IC device 102, and one or more additional ICDs 124 or other devices may be disposed in such overhang regions 134 and electrically connected to the top die of the overhang region 134.

[0060] Figure 2A A cross-sectional view of device 200, including exemplary stacked IC device 202, is described, and Figure 2B Commentary Figure 2A A top view of an exemplary stacked IC device 202. Figure 2A Device 200 includes many of the same as those mentioned above. Figure 1A and 1B The same components and features are described. These components and features are physically and operationally similar to those referenced above. Figure 1A and 1B The descriptions are the same, and the same reference numerals are used in the accompanying drawings. Figure 2A and 2B The middle mark. In some implementations, device 200 includes the same as... Figure 1A and 1B Device 100 has all the same features and components as device 200; however, in order to simplify the explanation and highlight the differences between device 100 and device 200, Figure 1A and 1B Some of the components and features explained in the article have been removed from Figure 2A and 2B Omitted (or not used) Figure 2A and 2B (The figure references in the accompanying drawings shall be used to indicate these features). Omission of such features and figure references should not be construed as meaning that... Figure 2A and 2B The features and components are limited to those specifically pointed out below. For example, although Figure 2A Not shown Figure 1A Optional device 168, but device 200 may include optional device 168. Furthermore, Figure 2A It still includes, for example, a stacked IC device 202, which may include interconnects 146 (see...). Figure 1A (such as ball grid array (BGA), C4 bump or other connectors) to electrically couple the stacked IC device 102 to the substrate 122. Interconnect 146 may include connectors to a second set of contacts to a second die 114, (such as) conductors through ICD 126 and a plurality of conductors 138 to the substrate 122.

[0061] exist Figure 1A and 1B In the illustrated example, the first die 104 is larger than the second die 114, thereby allowing the edge 130 of the first die 104 to extend beyond the edge 132 of the second die 114 to form an overhanging region 134. Figure 2A and 2B In the example described herein, for the purpose of highlighting the offset positioning of dies 104 and 114, the sizes of the first die 104 and the second die 114 are described as having more similar (or identical) sizes. For illustration, in this example, the first die 104 is offset from the center relative to the second die 114 to form an overhanging region 134. For example, the second edge 206 of the second die 114 extends beyond the second edge 204 of the first die 104 to define an underhanging region 208. Figure 2A and 2B In the example described, the underhanging region 208 can be left empty or filled with molding compound 136 or spacers. Note that... Figure 2A and 2B The relative sizes of dies 104 and 114 described are merely an example. In other examples, dies 104 and 114 can have significantly different sizes and can be stacked in an offset arrangement, such as... Figure 2A and 2BAs explained herein, one or more overhanging regions (e.g., overhanging region 134) and one or more underhanging regions (e.g., underhanging region 208) are formed without departing from the scope of this disclosure.

[0062] Figure 3A A cross-sectional view of device 300, including exemplary stacked IC device 302, is described, and Figure 3B Commentary Figure 3A A top view of an exemplary stacked IC device 302. Device 300 includes a plurality of components similar to those referenced above. Figures 1A to 2B The same components and features are described. These components and features are physically and operationally identical to those described above and are designated using the same reference numerals. In some implementations, device 300 includes components similar to... Figure 1A and 1B Device 100 and / or Figure 2A and 2B Device 200 has all the same features and components; however, to simplify the explanation and highlight the differences between devices 100, 200, and 300, some components and features have been changed from those in device 200. Figure 3A and 3B Omitted (or not used) Figure 3A and 3B (The figure references in the accompanying drawings shall be used to indicate these features). Omission of such features and figure references should not be construed as meaning that... Figure 3A and 3B The features and components are limited to those specifically pointed out below. For example, although Figure 3A Not shown Figure 1A Optional device 168 may be included, but device 300 may include optional device 168. For example, stacked IC device 302 may include interconnect 146 (see, for example, see...). Figure 1A (such as ball grid array (BGA), C4 bump or other connectors) to electrically couple the stacked IC device 302 to the substrate 122. In this example, interconnect 146 may include connectors to a second set of contacts to a second die 114, (such as) conductors through ICD 126 and a plurality of conductors 138 to the substrate 122.

[0063] exist Figure 2A and 2B In the illustrated example, the second edge 206 of the second die 114 extends beyond the second edge 204 of the first die 104 to define an overhang region 208, which is either empty or filled with spacers. Figure 3A and 3BIn the example described, integrated device 304 is disposed in the underside region 208. In some implementations, integrated device 304 includes an ICD similar to ICD 124. In some such implementations, integrated device 304 includes through-ICD conductors (similar to through-ICD conductor 126 of ICD 124) to connect stacked IC devices 302 to another device disposed on top of the first die 104 (e.g., Figure 1A Optional device 168). Alternatively, if no device is disposed on the first die 104, the ICD conductors can be omitted from the integrated device 304.

[0064] In other implementations, integrated device 304 includes another die, an integrated passive device, or another component of stacked IC device 302. Regardless of whether integrated device 304 is an ICD or another device, one or more TSVs 162 of the second die 114 may be coupled to integrated device 304 to electrically connect integrated device 304 to substrate 122. Additionally or alternatively, integrated device 304 may be electrically connected to the circuitry of the second die 114.

[0065] Figure 4A A cross-sectional view of device 400, including exemplary stacked IC device 402, is described, and Figure 4B Commentary Figure 4A A top view of an exemplary stacked IC device 402. Device 400 includes a plurality of components similar to those referenced above. Figures 1A to 3B The same components and features are described. These components and features are physically and operationally identical to those described above and are labeled using the same reference numerals. In some implementations, device 400 includes components similar to... Figure 1A Device 100 has all the same features and components; however, to simplify the explanation and highlight the differences between devices 100, 200, 300, and 400, some such components and features have been changed from... Figure 4A and 4B Omitted (or not used) Figure 4A and 4B (The figure references in the accompanying drawings shall be used to indicate these features). Omission of such features and figure references should not be construed as meaning that... Figure 4A and Figure 4B The features and components are limited to those specifically pointed out below. For example, although Figure 4A Not shown Figure 1A Optional device 168 may be included, but device 400 may include optional device 168. For example, stacked IC device 402 may include interconnect 146 (see, for example, see...). Figure 1A(Such as ball grid array (BGA), C4 bump, or other connectors) to electrically couple the stacked IC device 402 to the substrate 122. In this example, interconnect 146 may include connectors to a second set of contacts of the second die 114, through ICD conductors 126, and a plurality of conductors 138 to the substrate 122. Optional devices 418 and / or 144 may also include interconnect 146 (e.g., see...). Figure 1A ) to connect optional devices 418 and / or 144 to substrate 122.

[0066] exist Figure 4A and 4B In the illustrated example, the first edge 130 of the first die 104 extends beyond the first edge 132 of the second die 114 to form an overhang region 134, and the ICD 124 is disposed within the overhang region 134, as shown in the reference. Figure 1A and 1B As described. Additionally, in Figure 4A and 4B In the illustrated example, the second edge 204 of the first die 104 extends beyond the second edge 206 of the second die 114 to form a second overhanging region 434.

[0067] exist Figure 4A and 4B In this embodiment, a second ICD 404 is disposed in a second overhanging region 434. The second ICD 404 is similar to ICD 124. For example, the second ICD 404 may include one or more capacitors 420 and one or more through-ICD conductors 406. In a particular implementation, the capacitors 420 of the ICD 404 are electrically connected to the PDN 108 of the first die 104. In some such implementations, the through-ICD conductors 406 electrically connect the PDN 108 to the substrate 122.

[0068] In some implementations, the second overhanging region 434 includes a molding compound 136, and one or more conductors 408 pass through the molding compound 136 and are electrically connected to the first die 104. For example, conductors 408 may provide an electrical connection between the first die 104 and the substrate 122. In some such implementations, conductors 408 are connected to I / O circuitry 142 (or another set of I / O circuitry for the first die 104) to provide a path 416 between the first die 104 and device 144 or another device 418 coupled to the substrate 122.

[0069] Figure 5 A top view of an exemplary stacked IC device 502 is illustrated, which may include... Figures 1A to 4BThe stacked IC device 502 includes a number of devices 100, 200, 300, and 400, or is coupled to any of these devices. (See reference above.) Figures 1A to 4B The same components and features are described. These components and features are physically and operationally identical to those described above and are labeled using the same reference numerals. In some implementations, the stacked IC device 502 includes... Figure 4A and 4B The stacked IC device 402 has all the same features and components as the stacked IC devices 102, 202, 302, 402, and 502; however, to simplify the explanation and highlight the differences between the stacked IC devices 102, 202, 302, 402, and 502, some of these components and features have been changed from those in the original IC device. Figure 5 Omitted (or not used) Figure 5 (The figure references in the accompanying drawings shall be used to indicate these features). Omission of such features and figure references should not be construed as meaning that... Figure 5 The features and components are limited to those specifically noted below.

[0070] The stacked IC device 502 is similar to the stacked IC device 402 in that the first edge 130 of the first die 104 extends beyond the first edge 132 of the second die 114 to form an overhanging region 134, and the second edge 204 of the first die 104 extends beyond the second edge 206 of the second die 114 to form a second overhanging region 434. Figure 5 In the example described, ICD 124 and conductors 138 are disposed within the first overhang region 134, and ICD 404 and conductors 408 are disposed within the second overhang region 434.

[0071] Unlike the stacked IC device 402, the stacked IC device 502 includes one or more overhanging regions. For example, in Figure 5 In this configuration, the third edge 506 of the second die 114 extends beyond the third edge 508 of the first die 104 to define a first overhang region 504. Optionally, as... Figure 5 As explained, the fourth edge 516 of the second die 114 may extend beyond the fourth edge 514 of the first die 104 to define a second overhang region 512. Although two overhang regions 504 and 512 are explained, in some implementations, the stacked IC device 502 may include a single overhang region.

[0072] exist Figure 5 In the illustrated example, one or both of the underhanging regions 504 and 512 may be filled with molding compound 136 or spacers, as shown in the reference. Figure 2A and 2BThe underhanging region 208 is described. Alternatively, in some implementations, one or more devices or components of the stacked IC device 502 may be disposed in one or both of the underhanging regions 504. For example, in Figure 5 In the middle, device 510 is disposed in the first lower hanging region 504, and device 518 is disposed in the second lower hanging region 512.

[0073] In some implementations, device 510, device 518, or both include an ICD, another die, an integrated passive device, or another component of the stacked IC device 302, as described with reference to integrated device 304 of FIG3. In some implementations, one or more TSVs 162 of the second die 114 may be coupled to device 510, one or more TSVs 162 of the second die 114 may be coupled to device 518, or both. Additionally or alternatively, one or both of devices 510, 518 may be electrically connected to the circuitry of the second die 114.

[0074] Figure 6 A top view of an exemplary stacked IC device 602 is illustrated, which may include... Figures 1A to 4B The stacked IC device 602 includes a number of devices 100, 200, 300, and 400, or is coupled to any of these devices. The stacked IC device 602 includes a number of devices referenced above. Figures 1A to 4B The same components and features are described. These components and features are physically and operationally identical to those described above and are labeled using the same reference numerals. In some implementations, the stacked IC device 602 includes... Figure 4A and 4B The stacked IC device 402 has all the same features and components as the stacked IC devices 102, 202, 302, 402, 502, and 602; however, to simplify the explanation and highlight the differences between the stacked IC devices 102, 202, 302, 402, 502, and 602, some of these components and features have been changed from... Figure 6 Omitted (or not used) Figure 6 (The figure references in the accompanying drawings shall be used to indicate these features). Omission of such features and figure references should not be construed as meaning that... Figure 6 The features and components are limited to those specifically noted below.

[0075] The stacked IC device 602 is similar to the stacked IC device 402 in that the first edge 130 of the first die 104 extends beyond the first edge 132 of the second die 114 to form an overhanging region 134, and the second edge 204 of the first die 104 extends beyond the second edge 206 of the second die 114 to form an overhanging region 434. Figure 6 In the example described, ICD 124 and conductors 138 are disposed in the first overhang region 134, and ICD 404 and conductors 408 are disposed in the second overhang region 434.

[0076] Unlike the stacked IC device 402, the stacked IC device 602 includes a third overhanging region 604. For example, in Figure 6 In the first die 104, the third edge 508 extends beyond the third edge 506 of the second die 114 to define the third overhang region 604.

[0077] exist Figure 6 In the illustrated example, device 606 may be disposed in the third overhang region 604. For example, device 606 may include one or more additional ICDs, one or more additional dies, one or more integrated passive devices, or combinations thereof. In some implementations, the third overhang region 434 includes a molding compound 136 (in addition to or replacing device 606), and one or more conductors pass through the molding compound 136 and are electrically connected to the first die 104.

[0078] Optionally, in some implementations, the fourth edge 514 of the first die 104 may also extend beyond the fourth edge 516 of the second die 114 to define a fourth overhang region. In such implementations, the fourth overhang region may include one or more additional devices similar to device 606, one or more conductors passing through the molding compound 136 and electrically connected to the first die 104, or a combination thereof.

[0079] Figure 7 A top view of an exemplary stacked IC device 702 is illustrated, which may include... Figures 1A to 4B The stacked IC device 702 includes a number of devices 100, 200, 300, and 400, or is coupled to any of these devices. The stacked IC device 702 includes a number of devices referenced above. Figures 1A to 4B The same components and features are described. These components and features are physically and operationally identical to those described above and are labeled using the same reference numerals. In some implementations, the stacked IC device 702 includes... Figure 4A and 4B The stacked IC device 402 has all the same features and components; however, to simplify the explanation and highlight the differences between stacked IC devices 102, 202, 302, 402, 502, 602, and 702, some such components and features have been changed from those in the original IC device. Figure 7 Omitted (or not used) Figure 7 (The figure references in the accompanying drawings shall be used to indicate these features). Omission of such features and figure references should not be construed as meaning that... Figure 7 The features and components are limited to those specifically noted below.

[0080] Similar to Figure 4A and 4B Stacked IC device 402, Figure 7The first die 104 and the second die 114 of the stacked IC device 702 are positioned to define two overhang regions (including a first overhang region 134 and a second overhang region 434). In the stacked IC device 402, the first overhang region 134 is located on the side of the second die 114 opposite to the second overhang region 434. Conversely, in Figure 7 In this configuration, the first overhanging region 134 is positioned on the side of the second die 114 adjacent to the second overhanging region 434. The preferred arrangement of the stacked IC devices 402 or 702 can depend on factors such as the location of the circuitry of the first die 104, the location of other devices interacting with the stacked IC devices, and other factors. As an example, in... Figure 4A In the described implementation, device 400 includes device 144 on one side of stacked IC device 402 and another device 418 on the opposite side of stacked IC device 402. In this arrangement, stacked IC device 402 may be preferred over stacked IC device 702 if the circuitry of first die 104 allows connections from the opposite side of first die 104 to PDN 108, active circuitry 106, and / or I / O circuitry 142. However, in some implementations, the circuitry of first die 104 may be arranged to facilitate connections to other devices (e.g., device 144 and / or device 418) along adjacent sides of first die 104, in which case stacked IC device 702 may be preferred. Similar considerations apply to the ease of connection to the PDN of first die 104.

[0081] Figure 8 A top view of an exemplary stacked IC device 802 is illustrated, which may include... Figures 1A to 4B The stacked IC device 802 includes a number of devices 100, 200, 300, and 400, or is coupled to any of these devices. (See reference above.) Figures 1A to 4B The same components and features are described. These components and features are physically and operationally identical to those described above and are labeled using the same reference numerals. In some implementations, the stacked IC device 802 includes... Figure 4A and 4B The stacked IC device 402 shares all the same features and components; however, to simplify the explanation and highlight the differences between stacked IC devices 102, 202, 302, 402, 502, 602, 702, and 802, some of these components and features have been changed from those in the original IC device. Figure 8 Omitted (or not used) Figure 8 (The figure references in the accompanying drawings shall be used to indicate these features). Omission of such features and figure references should not be construed as meaning that... Figure 8 The features and components are limited to those specifically noted below.

[0082] Similar to Figure 5 502 stacked IC devices Figure 8 The first die 104 and the second die 114 of the stacked IC device 802 are positioned to define two upper overhang regions (including a first upper overhang region 134 and a second upper overhang region 434) and two lower overhang regions (including a first lower overhang region 504 and a second lower overhang region 512). In the stacked IC device 502, the first upper overhang region 134 is located on the side of the second die 114 opposite to the second upper overhang region 434, and the first lower overhang region 504 is located on the side of the second die 114 opposite to the second lower overhang region 512. In contrast, in Figure 8 In this configuration, the first upper suspended region 134 is located on the side of the second die 114 adjacent to the second upper suspended region 434, and the first lower suspended region 504 is located on the side of the second die 114 adjacent to the second lower suspended region 512. (See reference...) Figure 7 The arrangement of the stacked IC device 502 or the stacked IC device 802 may depend on factors such as the location of the circuit system of the first die 104, the location of other devices that interact with the stacked IC device, and other factors.

[0083] Figure 9 A cross-sectional view of a stacked package device 900 including an exemplary stacked IC device 902 is illustrated. In various implementations, the stacked IC device 902 may include any of stacked IC devices 102, 202, 302, 402, 502, 602, 702, or 802. For example, the stacked IC device 902 includes a first die 104, which may include... Figure 9 Various circuit systems not shown include active circuit system 106, PDN 108, I / O circuit system 142, etc. Similarly, the stacked IC device 902 includes a second die 114, which may include... Figure 9 Various circuit systems, such as active circuit systems, PDN, and I / O circuit systems, are not shown in the diagram. Figure 9 In this configuration, the second die 114 also includes a TSV 162, which can be arranged to interconnect the first die 104 to the substrate 122, to connect the optional integrated device 304 to the substrate, or both. The stacked IC device 902 also includes an ICD 124 disposed in an overhang region (e.g., overhang region 134 of FIG. 1) and electrically connected to the PDN of the first die 104. Figure 9 In the stacked IC device 902, there are also (a) conductors 126 passing through the ICD to electrically connect the PDN 108 to the substrate 122, and the stacked IC device 902 further includes (a) conductors 138 passing through the molding compound 136 in the overhang region between the first die 104 and the substrate.

[0084] exist Figure 9 In this configuration, another device 910 is coupled to substrate 908, and a stacked IC device 902 is disposed between substrate 908 and substrate 122. Substrate 908 may include a redistribution network to enable device 910 to be connected to substrate 122 via conductor 906. Thus, the stacked package device 900 provides another mechanism for coupling the stacked IC device 902 to other components.

[0085] Although Figures 1A to 9 Each diagram illustrates an example of a stacked IC device comprising at least two dies; however, in other examples, the stacked IC device may include more than two dies, and any two such dies may be positioned and interconnected as described herein. Furthermore, although Figures 1A to 4B Section 9 explains stacked IC devices in the context of other devices (e.g., coupled to another device via substrate 122, such as...). Figure 1A Device 144 Figure 4A Device 418 and / or Figure 9 While the stacked IC devices disclosed herein (910) are not included in this document, they can be integrated with or contained within a wide variety of other devices. For example, devices including one or more of the stacked IC devices disclosed herein may include components such as power management integrated circuits (PMICs), application processors, modems, radio frequency (RF) devices, passive devices, filters, capacitors, inductors, transmitters, receivers, gallium arsenide (GaAs) based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon (Si) based integrated devices, silicon carbide (SiC) based integrated devices, memories, power management processors, and / or combinations thereof. In such devices, the stacked IC devices can operate as any of these components (or combinations thereof) that include active circuitry systems.

[0086] Although Figures 1A to 9Each diagram illustrates an example of a stacked IC device where the ICD coupled to the upper die (e.g., first die 104) includes through-ICD conductors, but in some implementations, one or more ICDs used in the stacked IC device may not include through-ICD conductors. For example, in an implementation including two or more ICDs (such as a stacked IC device 402 including ICD 124 and ICD 404), one or more ICDs may include through-ICD conductors, and one or more ICDs may not include through-ICD conductors. Alternatively, in some implementations, none of the ICDs include through-ICD conductors, and PDN 108 is coupled to substrate 122 via other conductors (such as one or more TSVs of second die 114 or one or more through-conductors (e.g., conductor 138)). In some implementations, the stacked IC device may include one or more overhead regions that do not include ICDs. In some such implementations, one or more other overhead regions of the stacked IC device may include ICDs. In other implementations, the stacked IC device does not include an ICD disposed in any overhang region. In this case, the PDN 108 of the first die 104 can be coupled to a capacitor (e.g., DTC 170 and / or DTC 172) on the substrate using a through-hole (e.g., conductor 138) coupled to the PDN 108 and extending through the overhang region.

[0087] Although Figures 1A to 9 Each diagram illustrates an example of a stacked IC device, including conductors (such as conductors 138 and 408) passing through portions of molded compound 136 in each overhang region. However, in some implementations, one or more of the overhang regions may not include such through-conductors. For example, in implementations including two or more overhang regions (such as overhang region 134, overhang region 434, and / or overhang region 604), fewer than all of the overhang regions may include through-conductors. For example, in Figure 6 The diagram illustrates an overhanging region 604 without a through-mold conductor (e.g., a TMV). In some implementations, the through-mold conductor is omitted entirely, and the I / O circuitry 142 of the first die 104 is coupled to the substrate 122 via other conductors, such as one or more TSVs or through-ICD conductors of the second die 114.

[0088] The various examples above illustrate other devices (e.g., devices 144, 418) coupled to a substrate 122 adjacent to a stacked IC device (e.g., one of stacked IC devices 102, 202, 302, 402, 502, 602, 702, 802, or 902). In each illustrated example, the other device is illustrated as being oriented such that the side of the other device is substantially parallel to the side of the stacked IC device. In other words, the stacked IC device and the other device are shown as being placed side-by-side. However, in some implementations, the stacked IC device or the other device may be rotated (relative to this side-by-side orientation) such that a corner of one device faces one side of the other device (e.g., a corner of the stacked IC device faces one side of the other device or a corner of the other device faces the stacked IC device). For example, this type of corner-to-edge orientation can be used in implementations where the I / O circuitry 142 and / or TMV (e.g., conductors 138, 408) of the stacked IC device are arranged along two adjacent edges of the stacked IC device, such as in... Figure 7 and 8 In the example described herein, for illustration purposes, in some such examples, the corner of a stacked IC device located between two adjacent edges may be oriented toward the side of the other device to provide a short path for the interconnection between the other device and the TMV and / or I / O circuit system 142.

[0089] Exemplary process for manufacturing a stacked IC device including integrated capacitor devices

[0090] In some implementations, manufacturing a stacked IC device (e.g., any of stacked IC devices 102, 202, 302, 402, 502, 602, 702, 802, or 902) includes several processes. Figure 10 (which spans several pages continuously) illustrates a first exemplary step for providing or manufacturing a stacked IC device including at least one ICD, as referenced. Figures 1A to 9 As described in either of these. In some implementations, the process of Figure 10 can be used to provide (e.g., during manufacturing). Figures 1A to 9 One or more of the stacked IC devices 102, 202, 302, 402, 502, 602, 702, 802 or 902.

[0091] It should be noted that the processes in Figure 10 may combine one or more stages to simplify and / or clarify the processes used to provide or manufacture integrated devices. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more processes may be substituted or replaced without departing from the scope of this disclosure. In the following description, reference is made to the various illustrative stages of the process, which are numbered (using circled numbers) in Figure 10. Each stage of the process illustrated in Figure 10 shows the concurrent formation of two stacked IC devices (e.g., on carrier 1006). In other implementations, a single stacked IC device may be formed individually, or more than two stacked IC devices may be formed concurrently together.

[0092] Phase 1 of Figure 10 illustrates the state after one or more first dies 1002 (e.g., first dies 1002A and 1002B) and one or more integrated devices 1004 (e.g., devices 1004A and 1004B) have been coupled to the carrier 1006. In a specific implementation, the first die 1002 includes or corresponds to Figures 1A to 9 An example of the first die 104 of any of the following. Integrated device 1004 corresponds to or includes an example of integrated device 304 of FIG3. Integrated device 1004 is optional. For example, in an implementation of a stacked IC device where the die is not arranged to form a hanging region (e.g., hanging region 208, hanging region 504, or hanging region 512), integrated device 1004 is omitted. In other implementations, the hanging region is formed by the die but is not used to position integrated device 1004. For example, in stacked IC device 202, hanging region 208 does not include integrated device 1004.

[0093] Phase 2 describes the state after the molding compound 1008 is disposed on the carrier 1006 and between the first die 1002 and the integrated device 1004. For example, the molding compound 1008 may include... Figures 1A to 9 A portion of the molding compound 136 (e.g., its upper layer). In a specific example, the molding compound 1008 may be applied using a deposition process, spin coating process, or similar process, and the molding compound 1008 may subsequently be cured or hardened by exposure to light, heat, and / or chemical hardeners.

[0094] Phase 3 describes the state after the formation of one or more interconnect layers 1010. The interconnect layers 1010 may include redistribution layers and / or electrical connectors (e.g., microbumps, conductive pads, or pillars) to form electrical connections to the first die 1002 and / or the integrated device 1004. The interconnect layers 1010 may include a first contact set 1012A on a first side of the first die 1002A and the integrated device 1004A, and may include a first contact set 1012B on a first side of the first die 1002B and the integrated device 1004B. The interconnect layers 1010 may be formed using one or more plating processes and one or more patterning processes.

[0095] Phase 4 describes the state after one or more second dies 1014 (e.g., second dies 1014A and 1014B) and one or more ICDs 1016 (e.g., ICDs 1016A and 1016B) have been positioned relative to die 1002 and integrated device 1004 and coupled to interconnect layers 1010. In a specific implementation, the second die 1014 includes or corresponds to Figures 1A to 9 An example of the second die 114 of any of them. The ICD corresponds to or includes... Figures 1A to 9 An instance of ICD 124 or 404 for either of them.

[0096] In the example illustrated in Figure 10, the second die 1014A may include a circuit system and a through-hole 1018 electrically connected to the contacts of the first contact set 1012A. Similarly, the ICD 1016A includes a capacitor electrically connected to the PDN of the first die 1002A via the first contact set 1012A, and may also include a through-hole conductor 1020 electrically connected to the first contact set 1012A. A similar connection is also formed at the first contact set 1012B.

[0097] Phase 5 describes the state after molding compound 1022 has been applied to the sidewalls and surfaces therebetween of the second die 1014 and ICD 1016. For example, molding compound 1022 may include... Figures 1A to 9 A portion of the molding compound 136 (e.g., its lower layer). In a specific example, the molding compound 1022 may be applied using a deposition process, spin coating process, or similar process, and the molding compound 1022 may subsequently be cured or hardened by exposure to light, heat, and / or chemical hardeners.

[0098] Phase 6 describes the state following the formation of one or more openings 1024 (including openings 1024A and 1024B) in the molding compound 1022. Opening 1024A exposes the underlying contacts 1026A of the first contact set 1012A, and opening 1024B exposes the underlying contacts 1026B of the first contact set 1012B. The openings 1024 can be formed using patterning operations, etching processes, drilling operations, laser ablation operations, other target mold removal operations, or combinations thereof.

[0099] Stage 7 describes the state after conductor deposition. For example, one or more plating processes and one or more patterning processes may be used to deposit conductor 1030 (including conductors 1030A and 1030B) and conductor 1032 (including conductors 1032A and 1032B). Conductor 1030 includes or corresponds to Figures 1A to 9 Conductors 138 of any of the following. For example, conductor 1030A provides an electrical connection through molding compound 1022 to first die 1002A, and conductor 1030B provides an electrical connection through molding compound 1022 to first die 1002B. Thus, conductor 1030 may be referred to as a through-hole. Conductor 1032 corresponds to the second set of contacts on the side of second die 1014 opposite to first die 1002.

[0100] Phase 8 describes the state after the solder bumps 1040 are formed. For example, one or more plating processes and one or more patterning processes can be used to form the solder bumps 1040. In the example illustrated in Figure 10, the solder bumps 1040 include a bump grid or array, which includes a first bump set 1042A that provides circuitry to a second die 1014A and electrical connections to an integrated device 1004A and / or a first die 1002A via one or more vias of the second die 1014A.

[0101] In this example, solder bump 1040 also includes a second bump set 1044A providing electrical connections to the circuitry of the first die 1002A via through-hole 1020A, and a third bump 1046A providing electrical connections to the circuitry of the first die 1002A via conductors 1030A. The solder bump also includes a first bump set 1042B, a second bump set 1044B, and a third bump set 1046B, which provide similar connections to the second die 1014B, integrated device 1004B, ICD 1016B, and first die 1002B. In some implementations, conductive pillars (e.g., copper pillars) may be formed instead of solder bump 1040 to reach stage 8.

[0102] Phase 9 describes the state after the stacked IC devices 1050 (including stacked IC devices 1050A and 1050B) are separated from each other (and optionally from the carrier 1006). One or more layering processes can be used to remove the stacked IC devices 1050 from the carrier 1006, and one or more dicing operations can be used to separate the stacked IC devices 1050 from each other.

[0103] The formation of the stacked IC device 1050 is completed after stage 9 of Figure 10. However, in some implementations, one or more stacked IC devices 1050 can be used to form a composite IC device. Figures 1A to 4B One of the devices 100, 200, 300 or 400 or Figure 9 Device 900 corresponds to device 1060. Stage 10 describes the state after device 1060 is formed, which may include flipping the stacked IC device 1050 to position solder bumps 1040 adjacent to substrate 1062 and heating / reflowing solder bumps 1040 to connect the stacked IC device 1050 to substrate 1062. One or more other devices 1064 may also be coupled to the substrate before, after, or simultaneously with the stacked IC device 1050 being coupled to substrate 1062.

[0104] Figure 11 (which spans several pages) illustrates a second exemplary process for providing or manufacturing a stacked IC device including at least one ICD, as referenced. Figures 1A to 9 As described in either of them. In some implementations, the process of Figure 11 can be used to provide (e.g., during manufacturing). Figures 1A to 9 One or more of the stacked IC devices 102, 202, 302, 402, 502, 602, 702, 802 or 902.

[0105] It should be noted that the processes in Figure 11 may combine one or more stages to simplify and / or clarify the processes used to provide or manufacture integrated devices. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more processes may be substituted or replaced without departing from the scope of this disclosure. In the following description, reference is made to the various illustrative stages of the process, which are numbered (using circled numbers) in Figure 11. Each stage of the process illustrated in Figure 11 shows the concurrent formation of two stacked IC devices (e.g., on carrier 1106). In other implementations, a single stacked IC device may be formed individually, or more than two stacked IC devices may be formed concurrently together.

[0106] Phase 1 of Figure 11 illustrates the state after one or more first dies 1102 (e.g., first dies 1102A and 1102B) and one or more integrated devices 1104 (e.g., devices 1104A and 1104B) have been coupled to the carrier 1106. In a specific implementation, the first die 1102 includes or corresponds to Figures 1A to 9 An example of the first die 114 of any of the following. Integrated device 1104 includes or corresponds to an example of integrated device 304 of FIG3. Integrated device 1104 is optional. For example, in an implementation where the die of a stacked IC device is not arranged to form an underhang region (e.g., underhang region 208, underhang region 504, or underhang region 512), integrated device 1104 is omitted. In other implementations, the underhang region is formed by the die but is not used to position integrated device 1104. For example, in stacked IC device 202, underhang region 208 does not include integrated device 1104.

[0107] Phase 2 describes the state after the molding compound 1108 is disposed on the carrier 1106 and between the first die 1102 and the integrated device 1104. For example, the molding compound 1108 may include... Figures 1A to 9 A portion of the molding compound 136 (e.g., its upper layer). In a specific example, the molding compound 1108 may be applied using a deposition process, spin coating process, or similar process, and the molding compound 1108 may subsequently be cured or hardened by exposure to light, heat, and / or chemical hardeners.

[0108] Phase 3 describes the state after the formation of the conductive post 1110. The conductive post 1110 is configured to form an electrical connection to the first die 1102 and / or the integrated device 1104. In a particular aspect, the conductive post 1110 includes conductors 1130 (including conductors 1130A and 1130B). The conductive post 1110 can be formed using one or more plating processes and one or more patterning processes. Conductor 1130 corresponds to... Figures 1A to 9 The conductors 138 of any one of them. For example, conductor 1130A provides an electrical connection to the first die 1102A, and conductor 1130B provides an electrical connection to the first die 1102B.

[0109] Phase 4 describes the state after one or more second dies 1114 (e.g., second dies 1114A and 1114B) and one or more ICDs 1116 (e.g., ICDs 1116A and 1116B) have been positioned relative to die 1102 and integrated device 1104 and coupled to conductive post 1110. In a specific implementation, the second die 1114 includes or corresponds to Figures 1A to 9 An example of the second die 114 of either of them. ICD 1116 includes or corresponds to Figures 1A to 9An instance of ICD 124 or 404 for either of them.

[0110] Phase 5 describes the state after molding compound 1122 has been applied to the sidewalls and surfaces therebetween of the second die 1114 and ICD 1116. For example, molding compound 1122 may include... Figures 1A to 9 A portion of the molding compound 136 (e.g., its lower layer). In a specific example, the molding compound 1122 may be applied using a deposition process, spin coating process, or similar process, and the molding compound 1122 may subsequently be cured or hardened by exposure to light, heat, and / or chemical hardeners. The molding compound 1122 at least partially includes a conductor 1130 to form through-holes.

[0111] Phase 6 describes the state after the formation of the conductive pillars 1132 (or other contacts). For example, one or more plating processes and one or more patterning processes may be used to deposit the conductive pillars 1132 (including conductive pillars 1132A and 1132B). The conductive pillars 1132 correspond to the second set of contacts on the side of the second die 1114 opposite to the first die 1102.

[0112] Phase 7 describes the state after the solder bumps 1140 are formed. For example, one or more plating processes and one or more patterning processes can be used to form the solder bumps 1140. In the example illustrated in Figure 11, the solder bumps 1140 include a bump grid or array, which includes a first bump set 1142A that provides circuitry to a second die 1114A and electrical connections to an integrated device 1104A and / or a first die 1102A via one or more vias of the second die 1114A.

[0113] In this example, solder bump 1140 also includes a second bump set 1144A providing electrical connections to the circuitry of the first die 1102A via through-hole 1120A, and a third bump 1146A providing electrical connections to the circuitry of the first die 1102A via conductor 1130A (e.g., through-hole). Solder bump 1140 also includes a first bump set 1142B, a second bump set 1144B, and a third bump set 1146B, which provide similar connections to the second die 1114B, integrated device 1104B, ICD 1116B, and the first die 1102B. In some implementations, conductive pillars (e.g., copper pillars) may be formed instead of solder bump 1040 to reach stage 7.

[0114] Phase 8 describes the state after the stacked IC devices 1150 (including stacked IC devices 1150A and 1150B) are separated from each other (and optionally from the carrier 1106). One or more layering processes can be used to remove the stacked IC devices 1150 from the carrier 1106, and one or more dicing operations can be used to separate the stacked IC devices 1150 from each other.

[0115] The formation of the stacked IC device 1150 is completed after stage 8 in Figure 11. However, in some implementations, one or more stacked IC devices 1150 can be used to form a composite IC device. Figures 1A to 4B One of the devices 100, 200, 300 or 400 or Figure 9 Device 900 corresponds to device 1160. Stage 9 describes the state after device 1160 is formed, which may include flipping stacked IC device 1150 to position solder bumps 1140 adjacent to substrate 1162 and heating / reflowing solder bumps 1140 to connect stacked IC device 1150 to substrate 1162. One or more other devices 1164 may also be coupled to substrate 1162 before, after, or simultaneously with stacked IC device 1150 being coupled to substrate 1162.

[0116] Exemplary flowchart of a method for manufacturing an integrated device including offset interconnects

[0117] In some implementations, manufacturing stacked IC devices involves several processes. Figure 12 An exemplary flowchart of a method 1200 for providing or manufacturing stacked IC devices is illustrated. In some implementations, Figure 12 Method 1200 can be used to provide or manufacture Figures 1A to 9 Any of the stacked IC devices 102, 202, 302, 402, 502, 602, 702, 802 or 902.

[0118] It should be noted that Figure 12 Method 1200 may combine one or more processes to simplify and / or clarify the methods used to provide or manufacture integrated devices. In some implementations, the order of the processes may be changed or modified.

[0119] Method 1200 includes coupling a first side of a second die to a first side of a first die at block 1202, wherein the first die includes a first set of contacts, an active circuit system, and a power distribution network (PDN) on the first side of the first die, and wherein the second die includes a second set of contacts on a second side of the second die to electrically connect the circuit system of the second die to a substrate. For example, the first die and the second die may be fabricated and / or coupled together using one or more FEOL manufacturing processes, one or more BEOL manufacturing processes, or combinations thereof. In some implementations, phase 4 of FIG10 and phase 4 of FIG11 illustrate and describe an example of coupling a first side of a second die 1014 to a first side of a first die 1002. The first die of method 1200 may include or correspond to a first die 104 of any of stacked IC devices 102, 202, 302, 402, 502, 602, 702, 802, or 902. The second die of method 1200 may include or correspond to a second die 114 of any of the stacked IC devices 102, 202, 302, 402, 502, 602, 702, 802 or 902.

[0120] Method 1200 includes coupling an integrated capacitor device (ICD) to a first side of a first die via a first set of contacts at block 1204, wherein the ICD includes one or more through-ICD conductors to electrically connect a PDN to a substrate. For example, the ICD and / or the coupling of the ICD to the first die can be fabricated using one or more FEOL manufacturing processes, one or more BEOL manufacturing processes, or a combination thereof. In some implementations, phase 4 of FIG10 and phase 4 of FIG11 illustrate and describe an example of coupling a first side of a second die 1014 to a first side of a first die 1002. The ICD of method 1200 may include or correspond to an ICD 124 of any of stacked IC devices 102, 202, 302, 402, 502, 602, 702, 802, or 902.

[0121] Exemplary electronic devices

[0122] Figure 13 The description includes various electronic devices that may include any of the stacked IC devices 102, 202, 302, 402, 502, 602, 702, 802, or 902, or integrated therewith. For example, mobile phone device 1302, laptop computer device 1304, fixed-location terminal device 1306, wearable device 1308, or vehicle 1310 (automotive or aerial equipment) may include device 1300. Device 1300 may include, for example, any of the devices 100, 200, 300, 400, or 900 described herein and / or any of the stacked IC devices 102, 202, 302, 402, 502, 602, 702, 802, or 902. Figure 13 The devices 1302, 1304, 1306, and 1308, and vehicle 1310 described herein are merely exemplary. Other electronic devices may also feature device 1300, including but not limited to the group of devices (e.g., electronic devices) comprising: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0123] One or more of the components, processes, features, and / or functions illustrated in Figures 1 to 13 may be rearranged and / or combined into a single component, process, feature, or function, or implemented in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. It should also be noted that Figures 1 to 13 and their corresponding descriptions in this disclosure are not limited to dies and / or ICs. In some implementations, Figures 1 to 13 and their corresponding descriptions may be used to manufacture, create, provide, and / or produce devices and / or integrated devices. In some implementations, devices may include dies, integrated devices, integrated passive devices (IPDs), die packages, integrated circuit (IC) devices, device packages, integrated circuit (IC) packages, wafers, semiconductor devices, package-on-package (PoP) devices, thermal devices, and / or interposers.

[0124] It should be noted that the accompanying drawings in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, not all components and / or parts are shown for clarity. In some instances, the positioning, location, size, and / or shape of the various parts and / or components in the drawings may be exemplary. In some implementations, the various components and / or parts in the drawings may be optional.

[0125] The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “coupled” is used herein to refer to direct or indirect coupling between two objects (e.g., mechanical coupling). For example, if object A is physically in contact with object B, and object B is in contact with object C, then objects A and C can still be considered coupled to each other—even if they are not in direct physical contact. Object A coupled to object B may be coupled to at least a portion of object B. The term “electrically coupled” may mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can be transferred between the two objects. Electrically coupled objects may or may not have current transferred between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or anything above fourth) is arbitrary. Any component described may be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component can be a first component, a second component, a third component, or a fourth component. The terms “enclosing,” “enclosing,” and / or any derivative meaning can refer to an object that partially or completely encloses another object. The terms “top” and “bottom” are arbitrary. A component located at the top can be situated on top of a component located at the bottom. A top component can be considered a bottom component, and vice versa. As described in this disclosure, a first component situated “above” a second component can mean that the first component is located above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, a first component can be situated above (e.g., above) a first surface of a second component, while a third component can be situated above (e.g., below) a second surface of a second component, where the second surface is opposite the first surface. It should be further noted that the term “above,” as used in this application in the context of one component being above another component, can be used to mean that a component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Thus, for example, the first component being on the second component can mean: (1) the first component is on the second component but does not directly contact the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). The first component located “in” the second component can be partially or completely located in the second component. The value of about X–XX can mean a value between X and XX (inclusive). The values(s) between X and XX can be discrete or continuous. As used in this disclosure, the terms “about 'value X'” or “approximately value X” mean within ten percent of 'value X'.For example, a value of approximately 1 or roughly 1 would mean a value in the range of 0.9–1.1. "Multiple" components can include all possible components or only some of the possible components. For example, if a device comprises ten components, then the term "multiple components" can refer to all ten components or only some of the ten components.

[0126] In some implementations, an interconnect is a element or component in a device or package that allows or facilitates an electrical connection between two points, elements, and / or assemblies. In some implementations, an interconnect may include traces, vias, pads, solder pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnects. In some implementations, an interconnect may include conductive material that can be configured to provide an electrical path for signals (e.g., data signals), ground, and / or power supplies. An interconnect may include more than one element or component. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or steps to form interconnects. In some implementations, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes may be used to form interconnects.

[0127] It should also be noted that the various disclosures contained herein can be described as processes depicted as flowcharts, flow diagrams, structure diagrams, or block diagrams. Although flowcharts can describe operations as sequential processes, many operations can be executed in parallel or concurrently. Furthermore, the order of operations can be rearranged. A process terminates when its operations are completed.

[0128] Further examples are described below to facilitate understanding of this disclosure.

[0129] According to Example 1, a stacked integrated circuit (IC) device includes: a first die including an active circuit system and a power distribution network (PDN), the first die having a first set of contacts on a first side of the first die; a second die coupled to the first side of the first die on the first side of the second die, wherein the second die includes a second set of contacts on a second side of the second die to electrically connect the circuit system of the second die to a substrate; and an integrated capacitor device (ICD) coupled to the first side of the first die, wherein the ICD is electrically connected to the PDN via the first set of contacts and includes one or more through-ICD conductors to electrically connect the PDN to the substrate.

[0130] Example 2 includes the stacked IC device of Example 1, wherein at least one edge of the first die is suspended over at least one edge of the second die to define an overhang region, and wherein the ICD is disposed within the overhang region.

[0131] Example 3 includes a stacked IC device of Example 1 or Example 2, and further includes a molding compound that at least partially encapsulates a first die, a second die, and an ICD to form a packaged IC device.

[0132] Example 4 includes the stacked IC device of Example 3, and further includes one or more conductors electrically connected to a first die and passing through a molding compound to provide an electrical connection between the first die and a substrate.

[0133] Example 5 includes the stacked IC device of Example 4, wherein the first die further includes an input / output (I / O) circuit system, and the one or more conductors are connected to the I / O circuit system to provide a data path between the first die and another device coupled to a substrate (or coupled to another device on a printed circuit board).

[0134] Example 6 includes the stacked IC device of Example 4 or Example 5, and further includes a ball grid array (BGA), wherein the BGA includes or is directly connected to a second set of contacts, one or more through-ICD conductors, and one or more conductors.

[0135] Example 7 includes a stacked IC device of any of Examples 1 to 6, wherein the ICD includes one or more trench capacitors in a semiconductor substrate.

[0136] Example 8 includes the stacked IC device of Example 7, wherein one or more through-holes in the ICD conductor include through-holes through the semiconductor substrate.

[0137] Example 9 includes a stacked IC device of any of Examples 1 to 6, wherein the ICD includes one or more multilayer ceramic capacitors.

[0138] Example 10 includes a stacked IC device of any of Examples 1 to 6, wherein the ICD includes a third die.

[0139] Example 11 includes a stacked IC device of any one of Examples 1 to 10, wherein at least two edges of a first die are suspended over at least two edges of a second die to define at least two suspended regions, and wherein an ICD is disposed in a first suspended region of the at least two suspended regions, and further includes another integrated device disposed in a second suspended region of the at least two suspended regions.

[0140] Example 12 includes the stacked IC device of Example 11, wherein another integrated device includes a second ICD.

[0141] Example 13 includes the stacked IC device of Example 12, and further includes a first conductor set disposed in a first overhanging region and different from the ICD, and a second conductor set disposed in a second overhanging region and different from the second ICD, wherein the first conductor set and the second conductor set are configured to provide an electrical connection between a first die and a substrate.

[0142] Example 14 includes a stacked IC device of any of Examples 11 to 13, wherein a second die is disposed between a first overhang region and a second overhang region.

[0143] Example 15 includes a stacked IC device of any of Examples 1 to 14, wherein at least one edge of the second die extends beyond at least one edge of the first die to define at least one underhang region, and further includes another integrated device disposed within the at least one underhang region.

[0144] Example 16 includes the stacked IC device of Example 15, wherein another integrated device includes a second ICD.

[0145] Example 17 includes a stacked IC device of any of Examples 1 to 16, and further includes a third set of contacts on a first side of the second die, wherein the third set of contacts electrically connects the active circuitry of the first die to the circuitry of the second die.

[0146] Example 18 includes the stacked IC device of Example 17, wherein the third set of contacts includes microbumps.

[0147] Example 19 includes the stacked IC device of Example 17, wherein the third set of contacts includes conductive pillars.

[0148] Example 20 includes a stacked IC device of any of Examples 17 to 19, wherein the second die includes one or more through-silicon vias (TSVs) that connect one or more contacts in a third set of contacts to one or more contacts in a second set of contacts to electrically connect the active circuitry of the first die to a substrate.

[0149] Example 21 includes a stacked IC device of any of Examples 1 to 20, and further includes a fourth set of contacts on a second side of a first die to electrically connect the stacked IC device to another device.

[0150] Example 22 includes a stacked IC device of any of Examples 1 to 21, wherein a first die is a first chip and a second die is a second chip designed to operate in conjunction with the first chip.

[0151] Example 23 includes the stacked IC device of Example 22, wherein the active circuitry of the first chip includes one or more first functional circuit blocks, and the circuitry of the second chip includes one or more second functional circuit blocks, and wherein the one or more first functional circuit blocks and the one or more second functional circuit blocks are operationally dependent on each other.

[0152] According to Example 24, a device includes: a stacked integrated circuit (IC) device comprising: a first die including an active circuit system and a power distribution network (PDN), the first die having a first set of contacts on a first side of the first die; a second die coupled to the first side of the first die on the first side of the second die, wherein the second die includes a second set of contacts on a second side of the second die to electrically connect the circuit system of the second die to a substrate; and an integrated capacitor device (ICD) coupled to the first side of the first die, wherein the ICD is electrically connected to the PDN via the first set of contacts and includes one or more through-ICD conductors to electrically connect the PDN to the substrate.

[0153] Example 25 includes the device of Example 24, and further includes a substrate and at least one second device electrically connected to the stacked IC device via one or more conductive traces on the substrate.

[0154] Example 26 includes the device of Example 24 or Example 25, wherein at least one edge of the first die is suspended over at least one edge of the second die to define an overhang region, and wherein the ICD is disposed within the overhang region.

[0155] Example 27 includes a device of any of Examples 24 to 26, and further includes a molding compound that at least partially encapsulates the first die, the second die, and the ICD to form a packaged IC device.

[0156] Example 28 includes the device of Example 27, and further includes one or more conductors electrically connected to the first die and passing through the molding compound to provide an electrical connection between the first die and the substrate.

[0157] Example 29 includes the device of Example 28, wherein the first die further includes an input / output (I / O) circuit system, and the one or more conductors are connected to the I / O circuit system to provide a data path between the first die and another device coupled to a substrate (or coupled to another device on a printed circuit board).

[0158] Example 30 includes the device of Example 28 or Example 29, and further includes a ball grid array (BGA), wherein the BGA includes or is directly connected to a second set of contacts, one or more through-ICD conductors, and one or more conductors.

[0159] Example 31 includes a device of any of Examples 24 to 30, wherein the ICD includes one or more trench capacitors in a semiconductor substrate.

[0160] Example 32 includes the device of Example 31, wherein one or more through-ICD conductors include through-holes through a semiconductor substrate.

[0161] Example 33 includes a device from any of Examples 24 to 30, wherein the ICD includes one or more multilayer ceramic capacitors.

[0162] Example 34 includes a device from any of Examples 24 to 30, wherein the ICD includes a third die.

[0163] Example 35 includes a device of any one of Examples 24 to 34, wherein at least two edges of a first die are suspended over at least two edges of a second die to define at least two suspended regions, and wherein an ICD is disposed in a first suspended region of the at least two suspended regions, and further includes another integrated device disposed in a second suspended region of the at least two suspended regions.

[0164] Example 36 includes the device of Example 35, wherein another integrated device includes a second ICD.

[0165] Example 37 includes the device of Example 36, and further includes a first conductor set disposed in a first overhanging region and different from the ICD, and a second conductor set disposed in a second overhanging region and different from the second ICD, wherein the first conductor set and the second conductor set are configured to provide an electrical connection between the first die and the substrate.

[0166] Example 38 includes a device from any of Examples 35 to 37, wherein a second die is disposed between a first overhang region and a second overhang region.

[0167] Example 39 includes a device of any one of Examples 24 to 38, wherein at least one edge of the second die extends beyond at least one edge of the first die to define at least one underhang region, and further includes another integrated device disposed within the at least one underhang region.

[0168] Example 40 includes the device of Example 39, wherein another integrated device includes a second ICD.

[0169] Example 41 includes a device of any of Examples 24 to 40, and further includes a third set of contacts on a first side of the second die, wherein the third set of contacts electrically connects the active circuitry of the first die to the circuitry of the second die.

[0170] Example 42 includes the device of Example 41, wherein the third set of contacts includes microbumps.

[0171] Example 43 includes the device of Example 41, wherein the third set of contacts includes conductive posts.

[0172] Example 44 includes a device of any of Examples 41 to 43, wherein the second die includes one or more through-silicon vias (TSVs) that connect one or more contacts in a third set of contacts to one or more contacts in a second set of contacts to electrically connect the active circuitry of the first die to a substrate.

[0173] Example 45 includes a device from any of Examples 24 to 44, and further includes a fourth set of contacts on a second side of the first die to electrically connect the stacked IC device to another device.

[0174] Example 46 includes a device of any of Examples 24 to 45, wherein the first die is a first chip and the second die is a second chip designed to operate in conjunction with the first chip.

[0175] Example 47 includes the device of Example 46, wherein the active circuit system of the first chip includes one or more first functional circuit blocks, and the circuit system of the second chip includes one or more second functional circuit blocks, and wherein the one or more first functional circuit blocks and the one or more second functional circuit blocks are operationally dependent on each other.

[0176] According to Example 48, a method of manufacturing a stacked integrated circuit (IC) device includes: coupling a first side of a second die to a first side of a first die, wherein the first die includes a first set of contacts, an active circuit system, and a power distribution network (PDN) on the first side of the first die, and wherein the second die includes a second set of contacts on a second side of the second die to electrically connect the circuit system of the second die to a substrate; and coupling an integrated capacitor device (ICD) to the first side of the first die via the first set of contacts, wherein the ICD includes one or more through-ICD conductors to electrically connect the PDN to the substrate.

[0177] Example 49 includes the method of Example 48, wherein at least one edge of the first die is suspended over at least one edge of the second die to define an overhang region, and wherein the ICD is disposed within the overhang region.

[0178] Example 50 includes the method of Example 48 or Example 49, further including at least partially encapsulating the first die, the second die, and the ICD to form a packaged IC device.

[0179] Example 51 includes the method of Example 50, further comprising providing an electrical connection between a first die and a substrate via one or more conductors passing through the molding compound.

[0180] Example 52 includes the method of Example 51, wherein the first die further includes an input / output (I / O) circuit system, and the one or more conductors are connected to the I / O circuit system to provide a data path between the first die and another device coupled to a substrate (or coupled to another device on a printed circuit board).

[0181] Example 53 includes a method of any of Examples 48 to 52, wherein the ICD includes one or more trench capacitors in a semiconductor substrate.

[0182] Example 54 includes the method of Example 53, wherein one or more ICD conductors include through-holes through a semiconductor substrate.

[0183] Example 55 includes the method of any of Examples 48 to 52, wherein the ICD includes one or more multilayer ceramic capacitors.

[0184] Example 56 includes the method of any of Examples 48 to 52, wherein the ICD includes a third die.

[0185] Example 57 includes a method of any of Examples 48 to 56, wherein at least two edges of a first die are suspended over at least two edges of a second die to define at least two suspended regions, and wherein an ICD is disposed in a first suspended region of the at least two suspended regions, and further includes another integrated device disposed in a second suspended region of the at least two suspended regions.

[0186] Example 58 includes the method of Example 57, wherein another integrated device includes a second ICD.

[0187] Example 59 includes the method of Example 58, further including providing a first conductor set disposed in a first overhanging region and different from the ICD, and providing a second conductor set disposed in a second overhanging region and different from the second ICD, wherein the first conductor set and the second conductor set are configured to provide an electrical connection between the first die and the substrate.

[0188] Example 60 includes a method of any of Examples 57 to 59, wherein a second die is disposed between a first overhang region and a second overhang region.

[0189] Example 61 includes the method of any one of Examples 48 to 60, wherein at least one edge of the second die extends beyond at least one edge of the first die to define at least one underhang region, and further includes placing another integrated device in the at least one underhang region.

[0190] Example 62 includes the method of Example 61, wherein another integrated device includes a second ICD.

[0191] Example 63 includes the method of any of Examples 48 to 62, further including providing a third set of contacts on a first side of the second die, wherein the third set of contacts electrically connects the active circuitry of the first die to the circuitry of the second die.

[0192] Example 64 includes the method of Example 63, wherein the third set of contacts includes microbumps.

[0193] Example 65 includes the method of Example 63, wherein the third set of contacts includes conductive posts.

[0194] Example 66 includes a method of any of Examples 63 to 65, wherein the second die includes one or more through-silicon vias (TSVs) that connect one or more contacts in a third set of contacts to one or more contacts in a second set of contacts to electrically connect the active circuitry of the first die to a substrate.

[0195] Example 67 includes the method of any of Examples 48 to 66, and further includes connecting a fourth set of contacts on a second side of the first die to another device.

[0196] Example 68 includes a method of any of Examples 48 to 67, wherein the first die is a first core and the second die is a second core designed to operate in conjunction with the first core.

[0197] Example 69 includes the method of Example 68, wherein the active circuit system of the first chip includes one or more first functional circuit blocks, and the circuit system of the second chip includes one or more second functional circuit blocks, and wherein the one or more first functional circuit blocks and the one or more second functional circuit blocks are operationally dependent on each other.

[0198] The various features of this disclosure described herein can be implemented in different systems without departing from this disclosure. It should be noted that the foregoing aspects of this disclosure are merely illustrative and should not be construed as limiting the scope of this disclosure. The description of aspects of this disclosure is intended to be illustrative and not to limit the scope of the appended claims. Therefore, the teachings of this disclosure can be readily applied to other types of devices, and many substitutions, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A stacked integrated circuit (IC) device, comprising: A first die, the first die including an active circuit system and a power distribution network (PDN), the first die having a first set of contacts on a first side of the first die; The second die is coupled to the first side of the first die on a first side of the second die, wherein the second die includes a second set of contacts on a second side of the second die to electrically connect the circuit system of the second die to the substrate. as well as An integrated capacitor device (ICD) is coupled to a first side of the first die, wherein the ICD is electrically connected to the PDN via the first contact set and includes one or more through-ICD conductors to electrically connect the PDN to the substrate.

2. The stacked IC device of claim 1, wherein at least one edge of the first die is suspended over at least one edge of the second die to define an overhang region, and wherein the ICD is disposed within the overhang region.

3. The stacked IC device of claim 1, further comprising a molding compound that at least partially encapsulates the first die, the second die, and the ICD to form a packaged IC device.

4. The stacked IC device of claim 3, further comprising one or more conductors electrically connected to the first die and passing through the molding compound to provide an electrical connection between the first die and the substrate.

5. The stacked IC device of claim 1, wherein at least two edges of the first die are suspended over at least two edges of the second die to define at least two suspended regions, and wherein the ICD is disposed in a first suspended region of the at least two suspended regions, and the stacked IC device further includes another integrated device disposed in a second suspended region of the at least two suspended regions.

6. The stacked IC device of claim 5, wherein the other integrated device includes a second ICD.

7. The stacked IC device of claim 6, further comprising a first conductor set disposed in the first overhanging region and different from the ICD, and a second conductor set disposed in the second overhanging region and different from the second ICD, wherein the first conductor set and the second conductor set are configured to provide an electrical connection between the first die and the substrate.

8. The stacked IC device of claim 5, wherein the second die is disposed between the first overhang region and the second overhang region.

9. The stacked IC device of claim 1, wherein at least one edge of the second die extends beyond at least one edge of the first die to define at least one underhang region, and further includes another integrated device disposed within the at least one underhang region.

10. The stacked IC device of claim 1, further comprising a third set of contacts on a first side of the second die, wherein the third set of contacts electrically connects the active circuitry of the first die to the circuitry of the second die.

11. The stacked IC device of claim 10, wherein the second die includes one or more through-silicon vias (TSVs) that connect one or more contacts in the third set of contacts to one or more contacts in the second set of contacts to electrically connect the active circuitry of the first die to the substrate.

12. The stacked IC device of claim 1, further comprising a fourth set of contacts on a second side of the first die for electrically connecting the stacked IC device to another device.

13. The stacked IC device of claim 1, wherein the first die is a first chip and the second die is a second chip designed to operate in conjunction with the first chip.

14. The stacked IC device of claim 13, wherein the active circuitry of the first chip comprises one or more first functional circuit blocks, and the circuitry of the second chip comprises one or more second functional circuit blocks, and wherein the one or more first functional circuit blocks and the one or more second functional circuit blocks are operationally dependent on each other.

15. An apparatus comprising: Stacked integrated circuit (IC) devices, including: A first die, the first die including an active circuit system and a power distribution network (PDN), the first die having a first set of contacts on a first side of the first die; A second die, the second die being coupled to a first side of the first die on a first side, wherein the second die includes a second set of contacts on a second side of the second die to electrically connect the circuitry of the second die to a substrate; and An integrated capacitor device (ICD) is coupled to a first side of the first die, wherein the ICD is electrically connected to the PDN via the first contact set and includes one or more through-ICD conductors to electrically connect the PDN to the substrate.

16. The device of claim 15, further comprising the substrate and at least one second device electrically connected to the stacked IC device via one or more conductive traces on the substrate.

17. The device of claim 15, wherein at least one edge of the first die is suspended over at least one edge of the second die to define an overhang region, and wherein the ICD is disposed within the overhang region.

18. The apparatus of claim 15, further comprising a molding compound that at least partially encapsulates the first die, the second die, and the ICD to form an encapsulated IC device.

19. The device of claim 18, further comprising one or more conductors electrically connected to the first die and passing through the molding compound to provide an electrical connection between the first die and the substrate.

20. The device of claim 19, wherein the first die further includes an input / output (I / O) circuit system, and the one or more conductors are connected to the I / O circuit system to provide a data path between the first die and another device coupled to the substrate.

21. The device of claim 15, wherein at least two edges of the first die are suspended over at least two edges of the second die to define at least two suspended regions, and wherein the ICD is disposed in a first suspended region of the at least two suspended regions, and further includes another integrated device disposed in a second suspended region of the at least two suspended regions.

22. The device of claim 21, wherein the second die is disposed between the first upper suspended region and the second upper suspended region.

23. The device of claim 15, wherein at least one edge of the second die extends beyond at least one edge of the first die to define at least one underhang region, and the device further includes another integrated device disposed within the at least one underhang region.

24. The device of claim 15, further comprising a third set of contacts on a first side of the second die, wherein the third set of contacts electrically connects the active circuitry of the first die to the circuitry of the second die.

25. The device of claim 15, further comprising a fourth set of contacts on a second side of the first die for electrically connecting the stacked IC device to another device.

26. The device of claim 15, wherein the first die is a first core, and the second die is a second core designed to operate in conjunction with the first core.

27. The device of claim 26, wherein the active circuitry system of the first chip comprises one or more first functional circuit blocks, and the circuitry system of the second chip comprises one or more second functional circuit blocks, and wherein the one or more first functional circuit blocks and the one or more second functional circuit blocks are operationally dependent on each other.

28. A method for manufacturing a stacked integrated circuit (IC) device, the method comprising: The first side of the second die is coupled to the first side of the first die, wherein the first die includes a first set of contacts, an active circuit system, and a power distribution network (PDN) on the first side of the first die, and wherein the second die includes a second set of contacts on the second side of the second die to electrically connect the circuit system of the second die to the substrate. as well as An integrated capacitor device (ICD) is coupled to a first side of the first die via the first set of contacts, wherein the ICD includes one or more through-ICD conductors to electrically connect the PDN to the substrate.

29. The method of claim 28, wherein at least one edge of the first die is suspended over at least one edge of the second die to define an overhang region, and wherein the ICD is disposed within the overhang region.

30. The method of claim 28, wherein at least one edge of the second die extends beyond at least one edge of the first die to define at least one underhang region, and the method further comprises placing another integrated device within the at least one underhang region.

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