Semiconductor device

Abstract

According to one embodiment, a semiconductor device includes: a first substrate provided with a first electrode, a second electrode, and a third electrode; a second substrate provided with a fourth electrode, a fifth electrode, and a sixth electrode, the second substrate being arranged side by side with the first substrate in the first direction; the drain electrode of the first transistor is connected with the first electrode, the grid electrode is connected with the second electrode, and the source electrode is connected with the third electrode; the drain electrode of the second transistor is connected with the fourth electrode, the grid electrode is connected with the fifth electrode, and the source electrode is connected with the sixth electrode; a first wiring connecting the second electrode and the fifth electrode in a meandering manner in the second direction; and a second wiring connecting the third electrode and the sixth electrode in a meandering manner in the second direction.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device. Background Technology

[0002] Power modules are known as semiconductor devices that achieve high output. A power module is configured as a package that integrates multiple power semiconductors.

[0003] Existing technical documents Patent documents Patent Document 1: Japanese Patent No. 4142539 Summary of the Invention

[0004] The technical problem that the invention aims to solve In one embodiment of the present invention, a semiconductor device capable of suppressing oscillations within the device is provided.

[0005] Technical solutions for solving technical problems The semiconductor device according to the embodiment includes: a first substrate on which a first electrode, a second electrode, and a third electrode are disposed separately; a second substrate on which a fourth electrode, a fifth electrode, and a sixth electrode are disposed separately and arranged in a first direction with the first substrate; a first transistor disposed on the upper surface of the first electrode, with its drain connected to the first electrode, its gate connected to the second electrode, and its source connected to the third electrode; a second transistor disposed on the upper surface of the fourth electrode, with its drain connected to the fourth electrode, its gate connected to the fifth electrode, and its source connected to the sixth electrode; a first wiring that meanders to connect the second electrode and the fifth electrode in a second direction intersecting the first direction; and a second wiring that meanders to connect the third electrode and the sixth electrode in the second direction. Attached Figure Description

[0006] Figure 1 This is a circuit diagram illustrating an example of the circuit configuration of the semiconductor device according to the first embodiment.

[0007] Figure 2 This is a top view showing the configuration of an insulating substrate in a semiconductor device according to one embodiment.

[0008] Figure 3 It is along Figure 2 A sectional view along line A1-A2.

[0009] Figure 4 This is a top view showing the configuration of the gate wiring and source sensing wiring included in a semiconductor device according to one embodiment.

[0010] Figure 5 It is along Figure 4 A sectional view along line B1-B2.

[0011] Figure 6 This is a perspective view showing the meandering portion of the upper gate wiring and the upper source sensing wiring included in a semiconductor device according to one embodiment.

[0012] Figure 7 This is a circuit diagram illustrating an example of the circuit configuration of the upper arm portion of a semiconductor device 1 according to one embodiment.

[0013] Figure 8 This is a circuit diagram illustrating an example of the circuit configuration of the upper arm portion of a semiconductor device 1 according to one embodiment. Detailed Implementation

[0014] Hereinafter, embodiments will be described with reference to the accompanying drawings. Furthermore, in the following description, constituent elements having the same function and configuration will be labeled with common reference numerals. Additionally, when multiple constituent elements sharing common reference numerals are distinguished, a suffix will be added to the common reference numerals for differentiation. Furthermore, when it is not necessary to specifically distinguish multiple constituent elements, only the common reference numerals will be used for the multiple constituent elements, without any suffix. Here, the suffix is ​​not limited to subscript characters or superscript characters, but includes, for example, lowercase English letters added to the end of the reference numerals and indexes indicating arrangement, etc.

[0015] One embodiment of the semiconductor device is a power module. Semiconductor devices, for example, are suitable for power conversion devices used in railway vehicles or industrial equipment used in renewable energy power generation systems.

[0016] 1. Circuit structure of semiconductor devices First, refer to Figure 1 An example of the circuit configuration of semiconductor device 1 will be described. Figure 1 This is a circuit diagram illustrating an example of the circuit configuration of semiconductor device 1.

[0017] like Figure 1 As shown, semiconductor device 1 includes an upper arm portion UA ​​containing a plurality of transistors connected in parallel, and a lower arm portion LA containing a plurality of transistors connected in parallel. The upper arm portion UA ​​and the lower arm portion LA are connected in series.

[0018] The upper arm portion UA ​​includes a transistor Tr10a disposed above an insulating substrate 10a and a transistor Tr10b disposed above an insulating substrate 10b. Transistors Tr10a and Tr10b are connected in parallel. Hereinafter, without limiting either insulating substrate 10a or 10b, it will be referred to as "insulating substrate 10". Furthermore, without limiting either transistor Tr10a or Tr10b, it will be referred to as "transistor Tr10".

[0019] Alternatively, multiple transistors Tr10a can be disposed above the insulating substrate 10a. In this case, the multiple transistors Tr10a are connected in parallel. Similarly, multiple transistors Tr10b can be disposed above the insulating substrate 10b. In this case, the multiple transistors Tr10b are connected in parallel. Furthermore, the upper arm portion UA ​​may also have more than three insulating substrates 10.

[0020] The lower arm portion LA includes a transistor Tr20a disposed above an insulating substrate 20a and a transistor Tr20b disposed above an insulating substrate 20b. Transistors Tr20a and Tr20b are connected in parallel. Hereinafter, without limiting either insulating substrate 20a or 20b, it will be referred to as "insulating substrate 20". Furthermore, without limiting either transistor Tr20a or Tr20b, it will be referred to as "transistor Tr20".

[0021] Alternatively, multiple transistors Tr20a can be disposed above the insulating substrate 20a. In this case, the multiple transistors Tr20a are connected in parallel. Similarly, multiple transistors Tr20b can be disposed above the insulating substrate 20b. In this case, the multiple transistors Tr20b are connected in parallel. Furthermore, the lower arm portion LA may also have more than three insulating substrates 20.

[0022] Transistors Tr10a, Tr10b, Tr20a, and Tr20b are, for example, n-channel MOS (Metal Oxide Semiconductor) transistors.

[0023] The drains of transistors Tr10a and Tr10b are connected together to the positive terminal P. A positive voltage is applied to the positive terminal P from the outside.

[0024] The gates of transistors Tr10a and Tr10b are connected to the upper gate terminal HG via upper gate wiring. A voltage is applied to the upper gate terminal HG to control the gate signals of transistors Tr10a and Tr10b. An inductor Lg10 is placed between the gates of transistors Tr10a and Tr10b. In other words, one end of inductor Lg10 is connected to the gate of transistor Tr10a, and the other end is connected to the gate of transistor Tr10b. Inductor Lg10 is a parasitic inductance in the upper gate wiring between the gates of transistors Tr10a and Tr10b.

[0025] The sources of transistors Tr10a and Tr10b are connected to the upper source sensing terminal HSS via upper source sensing wiring. The upper source sensing terminal HSS is used to sense (monitor) the source voltages of transistors Tr10a and Tr10b. An inductor Lss10 is placed between the sources of transistors Tr10a and Tr10b. In other words, one end of inductor Lss10 is connected to the source of transistor Tr10a, and the other end is connected to the source of transistor Tr10b. Inductor Lss10 is a parasitic inductance in the upper source sensing wiring between the sources of transistors Tr10a and Tr10b. For example, the coupling coefficient between inductor Lss10 and inductor Lg10 is set to k1.

[0026] In addition, the sources of transistors Tr10a and Tr10b are connected together to the output terminal AC and the drains of transistors Tr20a and Tr20b.

[0027] The gates of transistors Tr20a and Tr20b are connected to the lower gate terminal LG via a lower gate wiring. A voltage is applied to the lower gate terminal LG to control the gate signals of transistors Tr20a and Tr20b. An inductor Lg20 is placed between the gates of transistors Tr20a and Tr20b. In other words, one end of inductor Lg20 is connected to the gate of transistor Tr20a, and the other end is connected to the gate of transistor Tr20b. Inductor Lg20 is a parasitic inductance in the lower gate wiring between the gates of transistors Tr20a and Tr20b.

[0028] The sources of transistors Tr20a and Tr20b are connected to the lower source sensing terminal LSS via a lower source sensing wiring. The lower source sensing terminal LSS is used to sense (monitor) the source voltages of transistors Tr20a and Tr20b. An inductor Lss20 is placed between the sources of transistors Tr20a and Tr20b. In other words, one end of inductor Lss20 is connected to the source of transistor Tr20a, and the other end is connected to the source of transistor Tr20b. Inductor Lss20 is a parasitic inductance in the lower source sensing wiring between the sources of transistors Tr20a and Tr20b. For example, the coupling coefficient between inductor Lss20 and inductor Lg20 is set to k2.

[0029] In addition, the sources of transistors Tr20a and Tr20b are both connected to the negative terminal N. A lower voltage is applied to the negative terminal N than to the positive terminal P.

[0030] Hereinafter, without specifying either the upper gate wiring or the lower gate wiring, it will be referred to as "gate wiring". Additionally, without specifying either the upper source sensing wiring or the lower source sensing wiring, it will be referred to as "source sensing wiring".

[0031] 2. Composition of semiconductor devices 2.1 Structure on the upper surface of the insulating substrate First, refer to Figure 2 An example of the configuration of semiconductor device 1 will be described. Figure 2 This is a top view showing the structure of insulating substrates 10a, 10b, 20a, and 20b.

[0032] In the following description, the direction in which the upper arm portion UA ​​and the lower arm portion LA are arranged on the upper surface of the substrate 2 is designated as the X direction. The direction intersecting the X direction and in which the insulating substrates 10a and 10b are arranged on the upper surface of the substrate 2 is designated as the Y direction. The direction intersecting both the X and Y directions is designated as the Z direction. Furthermore, in the Z direction, the side of the insulating substrate 10 on which the semiconductor chip 100 is disposed is designated as the upper surface, and the opposite side is designated as the lower surface. The same applies to the substrate 2 and the semiconductor chip 100.

[0033] like Figure 2 As shown, the semiconductor device 1 includes a substrate 2, insulating substrates 10a, 10b, 20a and 20b, gate electrodes 11a, 11b, 21a and 21b, source electrodes 12a, 12b, 22a and 22b, drain electrodes 13a, 13b, 23a and 23b, and a plurality of semiconductor chips 100.

[0034] The substrate 2 serves as a support for the semiconductor device 1. The substrate 2 has a flat plate shape. The semiconductor device 1 can be fixed to an external device via the substrate 2. The substrate 2 may contain a conductor (e.g., copper) for electrical connection to the external device.

[0035] Insulating substrates 10a, 10b, 20a, and 20b are insulating substrates that support the semiconductor chip 100. Electrodes are provided on both sides of insulating substrates 10a, 10b, 20a, and 20b. Insulating substrates 10a, 10b, 20a, and 20b are, for example, ceramic substrates. Insulating substrates 10a, 10b, 20a, and 20b include a conductor (e.g., copper) for electrically connecting the electrodes on the upper surface to the electrodes on the lower surface. Insulating substrates 10a, 10b, 20a, and 20b are disposed on the upper surface of the substrate 2. An upper arm portion UA ​​is provided on the upper surface of insulating substrates 10a and 10b. A lower arm portion LA is provided on the upper surface of insulating substrates 20a and 20b.

[0036] First, the structure on the upper surface of the insulating substrate 10a will be described.

[0037] A gate electrode 11a, a source electrode 12a, and a drain electrode 13a are disposed on the upper surface of the insulating substrate 10a. The gate electrode 11a, the source electrode 12a, and the drain electrode 13a are disposed separately from each other on the upper surface of the insulating substrate 10a. Furthermore, the shapes of the gate electrode 11a, the source electrode 12a, and the drain electrode 13a are arbitrary.

[0038] The gate electrode 11a includes a connection portion 14a that is connected to the upper gate wiring.

[0039] The source electrode 12a includes a connection portion 15a connected to the upper source sensing wiring and a connection portion 16a connected to the output terminal AC.

[0040] The drain electrode 13a includes a connection portion 17a that is connected to the positive terminal P.

[0041] exist Figure 2 In the example shown, four semiconductor chips 100 are disposed on the drain electrode 13a. Alternatively, more than one semiconductor chip 100 may be disposed on the drain electrode 13a. The semiconductor chip 100 is an n-channel MOS transistor. The semiconductor chip 100 on the drain electrode 13a corresponds to the use of… Figure 1 The transistor Tr10a described herein has a drain terminal on its lower surface and a gate terminal and a source terminal on its upper surface. The drain terminal of the semiconductor chip 100 is electrically connected to the drain electrode 13a. The gate terminal of the semiconductor chip 100 is connected to the gate electrode 11a via a single wire WL. The source terminal of the semiconductor chip 100 is connected to the source electrode 12a via three wires WL. Furthermore, the number of wires WL connecting the gate terminal of the semiconductor chip 100 to the gate electrode 11a and the number of wires WL connecting the source terminal of the semiconductor chip 100 to the source electrode 12a are arbitrary.

[0042] Next, the configuration of the upper surface of the insulating substrate 10b will be described.

[0043] A gate electrode 11b, a source electrode 12b, and a drain electrode 13b are disposed on the upper surface of the insulating substrate 10b. The gate electrode 11b, source electrode 12b, and drain electrode 13b are disposed separately on the upper surface of the insulating substrate 10b. Furthermore, the shapes of the gate electrode 11b, source electrode 12b, and drain electrode 13b are arbitrary.

[0044] The gate electrode 11b includes a connection portion 14b that is connected to the upper gate wiring.

[0045] The source electrode 12b includes a connection portion 15b connected to the upper source sensing wiring and a connection portion 16b connected to the output terminal AC.

[0046] The drain electrode 13b includes a connection portion 17b that is connected to the positive terminal P.

[0047] exist Figure 2 In the example shown, four semiconductor chips 100 are disposed on the drain electrode 13b. Alternatively, more than one semiconductor chip 100 may be disposed on the drain electrode 13b. The semiconductor chips 100 on the drain electrode 13b correspond to the use of… Figure 1 The transistor Tr10b is described. The drain terminal of the semiconductor chip 100 is electrically connected to the drain electrode 13b. The gate terminal of the semiconductor chip 100 is connected to the gate electrode 11b via a wire WL. The source terminal of the semiconductor chip 100 is connected to the source electrode 12b via three wires WL.

[0048] Next, the structure on the upper surface of the insulating substrate 20a will be described.

[0049] A gate electrode 21a, a source electrode 22a, and a drain electrode 23a are disposed on the upper surface of the insulating substrate 20a. The gate electrode 21a, the source electrode 22a, and the drain electrode 23a are disposed separately on the upper surface of the insulating substrate 20a. Furthermore, the shapes of the gate electrode 21a, the source electrode 22a, and the drain electrode 23a are arbitrary.

[0050] The gate electrode 21a includes a connection portion 24a that is connected to the lower gate wiring.

[0051] The source electrode 22a includes a connection portion 25a connected to the lower source sensing wiring and a connection portion 26a connected to the negative terminal N.

[0052] The drain electrode 23a includes a connection portion 27a that is connected to the output terminal AC.

[0053] exist Figure 2 In the example shown, four semiconductor chips 100 are disposed on the drain electrode 23a. Alternatively, more than one semiconductor chip 100 may be disposed on the drain electrode 23a. The semiconductor chip 100 on the drain electrode 23a corresponds to the use of… Figure 1 The transistor Tr20a is described. The drain terminal of the semiconductor chip 100 is electrically connected to the drain electrode 23a. The gate terminal of the semiconductor chip 100 is connected to the gate electrode 21a via a wire WL. The source terminal of the semiconductor chip 100 is connected to the source electrode 22a via three wires WL.

[0054] Next, the configuration of the upper surface of the insulating substrate 20b will be described.

[0055] A gate electrode 21b, a source electrode 22b, and a drain electrode 23b are disposed on the upper surface of the insulating substrate 20b. The gate electrode 21b, the source electrode 22b, and the drain electrode 23b are disposed separately from each other on the upper surface of the insulating substrate 20b. Furthermore, the shapes of the gate electrode 21b, the source electrode 22b, and the drain electrode 23b are arbitrary.

[0056] The gate electrode 21b includes a connection portion 24b that is connected to the lower gate wiring.

[0057] The source electrode 22b includes a connection portion 25b connected to the lower source sensing wiring and a connection portion 26b connected to the negative terminal N.

[0058] The drain electrode 23b includes a connection portion 27b that is connected to the output terminal AC.

[0059] exist Figure 2 In the example shown, four semiconductor chips 100 are disposed on the drain electrode 23b. Alternatively, more than one semiconductor chip 100 may be disposed on the drain electrode 23b. The semiconductor chip 100 on the drain electrode 23b corresponds to the use of… Figure 1 The transistor Tr20b is described. The drain terminal of semiconductor chip 100 is electrically connected to drain electrode 23b. The gate terminal of semiconductor chip 100 is connected to gate electrode 21b via a wire WL. The source terminal of semiconductor chip 100 is connected to source electrode 22b via three wires WL.

[0060] 2.2 Cross-sectional configuration of semiconductor devices Next, refer to Figure 3 An example of the cross-sectional configuration of semiconductor device 1 will be described. Figure 3 It is along Figure 2 A sectional view along line A1-A2.

[0061] like Figure 3 As shown, a lower surface electrode 18a is provided on the lower surface of the insulating substrate 10a. The lower surface electrode 18a can be electrically connected to either the source electrode 12a or the drain electrode 13a. Solder 3 is provided between the upper surface of the substrate 2 and the lower surface electrode 18a. In other words, the lower surface electrode 18a (insulating substrate 10a) is fixed to the upper surface of the substrate 2 by the solder 3.

[0062] A gate electrode 11a, a source electrode 12a, and a drain electrode 13a are disposed on the upper surface of an insulating substrate 10a. A mounting material 200 is disposed between the upper surface of the drain electrode 13a and the semiconductor chip 100. In other words, the semiconductor chip 100 is fixed (bonded) to the upper surface of the drain electrode 13a by the mounting material 200. The mounting material 200 is made of a conductive material. For example, solder can be used as the mounting material 200. Alternatively, a non-melting sintering material (such as any one of copper, silver, lead, copper-tin compounds, silver-tin compounds, or nickel-tin compounds) can be used instead of solder. In this case, a pressure-sintering material with excellent pressure resistance can be used.

[0063] The drain terminal disposed on the lower surface of the semiconductor chip 100 is electrically connected to the drain electrode 13a via a mounting material. The gate terminal disposed on the upper surface of the semiconductor chip 100 is electrically connected to the gate electrode 11a via a wire WL. In addition, the source terminal disposed on the upper surface of the semiconductor chip 100 is electrically connected to the source electrode 12a via a wire WL.

[0064] 2.3 Configuration of gate wiring and source sensing wiring Next, refer to Figures 4 to 6 An example of the configuration of the gate wiring and the source sensing wiring will be described. Figure 4 This is a top view showing the configuration of the gate wiring and the source sensing wiring. Figure 5 It is along Figure 4 A sectional view along line B1-B2. Figure 6 This is a perspective view showing the meandering portion MP of the upper gate wiring 30 and the upper source sensing wiring 31. Furthermore, in Figure 4 In the examples shown, reference numerals for components not connected to the gate wiring or source sensing wiring have been omitted for the sake of simplicity.

[0065] like Figure 4 As shown, the semiconductor device 1 includes an upper gate wiring 30, an upper source sensing wiring 31, a lower gate wiring 40, and a lower source sensing wiring 41.

[0066] The upper gate wiring 30 is connected to the connection portion 14a of the gate electrode 11a provided on the upper surface of the insulating substrate 10a and the connection portion 14b of the gate electrode 11b provided on the upper surface of the insulating substrate 10b. One end of the upper gate wiring 30 is connected to the upper gate terminal HG. The upper gate wiring 30 has a meandering portion MP provided in the wiring portion connecting the connection portion 14a and the connection portion 14b. That is, the meandering portion MP is provided in the wiring portion connecting the insulating substrates. In other words, the upper gate wiring 30 meanders to connect the gate electrode 11a and the gate electrode 11b in the X direction. The meandering portion MP of the upper gate wiring 30 extends in the Y direction while repeatedly folding back in the X direction. In other words, the meandering portion MP includes a plurality of first portions extending in the X direction and a plurality of second portions extending in the Y direction. The plurality of first portions and the plurality of second portions are connected in series alternately one after another. In addition, the folding direction of the wiring in the meandering portion MP is arbitrary. For example, the upper gate wiring 30 can fold back in the Y direction or in the Z direction. Furthermore, the number of folds in the wiring within the meandering section MP is arbitrary. Moreover, the upper gate wiring 30 can also be sawtooth-shaped within the meandering section MP. The parasitic inductance in the meandering section MP of the upper gate wiring 30 is equivalent to using... Figure 1 The inductor is Lg10.

[0067] The upper source sensing wiring 31 is connected to the connection portion 15a of the source electrode 12a provided on the upper surface of the insulating substrate 10a and the connection portion 15b of the source electrode 12b provided on the upper surface of the insulating substrate 10b. One end of the upper source sensing wiring 31 is connected to the upper source sensing terminal HSS. The upper source sensing wiring 31 has a meandering portion MP provided in the wiring portion connecting the connection portion 15a and the connection portion 15b. In other words, the upper source sensing wiring 31 connects the source electrode 12a and the source electrode 12b in a meandering manner in the X direction. The wiring shape of the meandering portion MP of the upper source sensing wiring 31 is substantially the same as the wiring shape of the meandering portion MP of the upper gate wiring 30. Furthermore, when described as substantially the same, manufacturing deviations of the semiconductor device 1 can be included. The parasitic inductance in the meandering portion MP of the upper source sensing wiring 31 is equivalent to using Figure 1 The inductor is described as Lss10.

[0068] like Figure 5 As shown, the upper source sensing wiring 31 is positioned above the upper gate wiring 30 in the Z direction. Furthermore, as... Figure 6As shown, the meandering portion MP of the upper source sensing wiring 31 is positioned above the meandering portion MP of the upper gate wiring 30. That is, the meandering portion MP of the upper source sensing wiring 31 is arranged parallel to the meandering portion MP of the upper gate wiring 30. In other words, the upper gate wiring 30 and the upper source sensing wiring 31 meander parallel to each other in the Z direction. Specifically, when viewed from above in the Z direction, the upper gate wiring 30 and the upper source sensing wiring 31 meander overlapping in a separated state. The distance between the upper gate wiring 30 and the upper source sensing wiring 31 in the Z direction is set to H. To increase the coupling coefficient k1 (close to 1) between inductors Lg10 and Lss10, the distance H is preferably set to 2 mm or less.

[0069] Next, the lower gate wiring 40 and the lower source sensing wiring 41 will be described.

[0070] like Figure 4 As shown, the lower gate wiring 40 is connected to the connection portion 24a of the gate electrode 21a provided on the upper surface of the insulating substrate 20a and the connection portion 24b of the gate electrode 21b provided on the upper surface of the insulating substrate 20b. One end of the lower gate wiring 40 is connected to the lower gate terminal LG. Like the upper gate wiring 30, the lower gate wiring 40 has a meandering portion MP provided on the wiring portion connecting the connection portion 24a and the connection portion 24b. In other words, the lower gate wiring 40 meanders between the gate electrode 21a and the gate electrode 21b in the X direction. The meandering portion MP of the lower gate wiring 40 extends in the Y direction while repeatedly folding back in the X direction. The parasitic inductance in the meandering portion MP of the lower gate wiring 40 is equivalent to using... Figure 1 The inductor is Lg20.

[0071] The lower source sensing wiring 41 is connected to the connection portion 25a of the source electrode 22a provided on the upper surface of the insulating substrate 20a and the connection portion 25b of the source electrode 22b provided on the upper surface of the insulating substrate 20b. One end of the lower source sensing wiring 41 is connected to the lower source sensing terminal LSS. Like the upper source sensing wiring 31, the lower source sensing wiring 41 has a meandering portion MP provided on the wiring portion connecting the connection portion 25a and the connection portion 25b. In other words, the lower source sensing wiring 41 connects the source electrode 22a and the source electrode 22b in a meandering manner in the X direction. The wiring shape of the meandering portion MP of the lower source sensing wiring 41 is approximately the same as the wiring shape of the meandering portion MP of the lower gate wiring 40. The parasitic inductance in the meandering portion MP of the lower source sensing wiring 41 is equivalent to using... Figure 1 The inductor is described as Lss20.

[0072] Similar to the upper arm portion UA, the meandering portion MP of the lower source sensing wiring 41 is positioned above the meandering portion MP of the lower gate wiring 40. In other words, the lower gate wiring 40 and the lower source sensing wiring 41 meander in a parallel manner in the Z direction. That is, when viewed from above in the Z direction, the lower gate wiring 40 and the lower source sensing wiring 41 meander in an overlapping manner in a separated state. Similarly, the distance H between the lower gate wiring 40 and the lower source sensing wiring 41 in the Z direction is preferably set to 2 mm or less in order to increase the coupling coefficient k2 (close to 1) between the inductor Lg20 and the inductor Lss20, just as it is between the upper gate wiring 30 and the upper source sensing wiring 31.

[0073] 3. The impact of bends on the characteristics of semiconductor devices Next, refer to Figure 7 as well as Figure 8 The influence of the meandering portion MP of the gate wiring and the source sensing wiring on the characteristics of the semiconductor device 1 is explained. Figure 7 and Figure 8 This is a circuit diagram illustrating an example of the circuit configuration of the upper arm portion UA ​​of semiconductor device 1. Figure 7 and Figure 8 For the sake of simplicity, the circuit diagram of the lower arm portion LA is omitted in the example shown. Furthermore, the semiconductor device 1 is subject to the same influence in the circuit of the lower arm portion LA as in the circuit of the upper arm portion UA.

[0074] First, the effect of the meandering portion MP of the upper gate wiring 30 and the upper source sensing wiring 31 on the oscillation of the semiconductor device 1 (upper arm portion UA) will be explained.

[0075] like Figure 7 As shown, relative to the oscillating loop indicated by the thick solid line, inductor Lg10 becomes the impedance. Since the inductance Lg10 increases due to the meandering portion MP of the upper gate wiring 30, the oscillation is suppressed. At this time, the inductance Lss10 also increases through the meandering portion MP of the upper source sensing wiring 31. However, since no oscillating current flows through the inductance Lss10, no mutual inductance is generated.

[0076] Next, the effect on the switching speed of semiconductor device 1 will be explained.

[0077] like Figure 8As shown, inductors Lg10 and Lss10 are out of phase relative to the gate signal loop indicated by the thick solid line. Therefore, the mutual inductance of inductors Lg10 and Lss10 cancels each other out. In this embodiment, the meandering portion MP of the upper source sensing wiring 31 is arranged parallel to the meandering portion MP of the upper gate wiring 30, thus increasing the coupling coefficient k1. That is, the mutual inductance increases, and the amount of cancellation by inductor Lg10 increases. Therefore, the delay in the switching speed of the semiconductor device 1 caused by the increase in inductor Lg10 is suppressed.

[0078] According to the configuration of this embodiment, a semiconductor device 1 capable of suppressing oscillations within the device can be provided.

[0079] For example, in a module with multiple insulating substrates, the length of the source wiring connecting the insulating substrates (and the parallel-connected transistors) tends to increase. This increases the source inductance between the insulating substrates, which can easily cause oscillations during switching. Increasing the gate inductance between the insulating substrates is an effective countermeasure against oscillations. However, if the gate inductance increases, the performance of the semiconductor device degrades due to substrate misalignment during transistor switching, reduced switching speed, and other factors.

[0080] In contrast, according to the configuration of this embodiment, the semiconductor device 1 can provide a meandering portion MP in the portion connecting the insulating substrates of the gate wiring and the source sensing wiring. This increases the gate inductance between the insulating substrates, thereby suppressing oscillations.

[0081] Furthermore, according to the configuration of this embodiment, the semiconductor device 1 can arrange the meandering portion MP of the source sensing wiring and the meandering portion MP of the gate wiring parallel to each other between insulating substrates. This increases the mutual inductance between the gate inductance and the source inductance. In the gate signal loop, the source inductance and the gate inductance can be made to be in opposite phase. Therefore, in the gate signal loop, the gate inductance can be eliminated through mutual inductance. Thus, the decrease in switching speed caused by the increase in gate inductance can be suppressed.

[0082] 4. Variations, etc. Furthermore, various modifications can be applied beyond the embodiments described above.

[0083] Furthermore, the "connection" in the above embodiments also includes a state in which there is an indirect connection through the intervening of something else, such as a transistor or a resistor.

[0084] While several embodiments of the invention have been described, these embodiments are provided by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor device, characterized in that, have: A first substrate has a first electrode, a second electrode, and a third electrode disposed separately from each other; The second substrate has a fourth electrode, a fifth electrode, and a sixth electrode disposed separately from each other, and is arranged with the first substrate in a first direction; A first transistor is disposed on the upper surface of the first electrode, with its drain connected to the first electrode, its gate connected to the second electrode, and its source connected to the third electrode. The second transistor is disposed on the upper surface of the fourth electrode, with its drain connected to the fourth electrode, its gate connected to the fifth electrode, and its source connected to the sixth electrode. The first wiring connects the second electrode and the fifth electrode in a meandering manner in a second direction that intersects the first direction; as well as The second wiring connects the third electrode and the sixth electrode in a meandering manner in the second direction.

2. The semiconductor device according to claim 1, characterized in that, The first wiring and the second wiring meander in a manner that is parallel to the third direction that intersects the first direction.

3. The semiconductor device according to claim 1, characterized in that, The distance between the first wiring and the second wiring is less than 2mm.

4. The semiconductor device according to claim 1, characterized in that, The first wiring includes a plurality of first portions extending in the first direction and a plurality of second portions extending in the second direction. The plurality of first parts and the plurality of second parts are connected in series alternately one after another.

5. The semiconductor device according to claim 1, characterized in that, The semiconductor device also includes: The third substrate has a seventh electrode, an eighth electrode, and a ninth electrode disposed separately from each other; The fourth substrate has a tenth electrode, an eleventh electrode, and a twelfth electrode disposed separately from each other, and is arranged with the third substrate in the first direction; The third transistor is disposed on the upper surface of the seventh electrode, with its drain connected to the seventh electrode, its gate connected to the eighth electrode, and its source connected to the ninth electrode. The fourth transistor is disposed on the upper surface of the tenth electrode, with its drain connected to the tenth electrode, its gate connected to the eleventh electrode, and its source connected to the twelfth electrode. The third wiring connects the eighth electrode and the eleventh electrode in a meandering manner in the second direction; as well as The fourth wiring connects the ninth electrode and the twelfth electrode in a meandering manner in the second direction.

6. The semiconductor device according to claim 5, characterized in that, The third transistor and the fourth transistor are connected in series with the first transistor and the second transistor.

7. The semiconductor device according to claim 5, characterized in that, The third wiring and the fourth wiring meander in a manner parallel to each other on a third direction that intersects the first direction.

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