Phase cutting in parallel power converters

Abstract

A method and circuit enables parallel operation of power converters such that phase cutting is possible without too long start-up times. More specifically, embodiments utilize a reduced gate drive (RGD) low dropout (LDO) circuit within a single power converter to achieve a parallel power converter system that supports phase-cut simultaneous elimination of the "ping-pong" effect (synchronization problem). The RGD capability of each parallel power converter allows each power converter to be asynchronously connected without affecting the other parallel power converters. In particular, the RGD capability allows full power up of the power converter as well as significantly reduced delay of full charge balance and soft start. For example, embodiments of the invention generally have a delay of RGD charge balance measured in hundreds of microseconds, rather than a delay measured in tens of milliseconds as charge balance in conventional non-RGD power converters.

Description

Technical Field

[0001] This invention relates to electronic circuits, and more particularly to power converter circuits including DC-DC power converter circuits. Background Technology

[0002] Many electronic products, particularly mobile computing and / or communication products and components (e.g., laptops, ultrabooks, tablets, LCD and LED displays), require multiple voltage levels. For example, radio frequency (RF) transmitter power amplifiers may require relatively high voltages (e.g., 12 V or higher), while logic circuit systems may require low voltage levels (e.g., 1 V to 2 V). Other circuit systems may require intermediate voltage levels (e.g., 5 V to 10 V). Many applications may require multiple voltage levels at different current rates.

[0003] Power converters are typically used to generate lower or higher voltages from a common power source, such as a battery. One type of power converter includes converter circuitry (e.g., a charge pump based on a switched capacitor network), control circuitry, and auxiliary circuitry such as a bias voltage generator, clock generator, voltage regulator, voltage control circuitry, etc., in some implementations. As used herein, the term "charge pump" refers to a device configured to generate V... IN Increase (multiply) or decrease (divide) the pressure to V OUT Switched capacitor networks. Examples of such charge pumps include cascaded multiplier switched capacitor networks, Dickson switched capacitor networks, ladder switched capacitor networks, series-parallel switched capacitor networks, Fibonacci switched capacitor networks, and Doubler switched capacitor networks, all of which can be configured as multiphase or single-phase networks. Switched capacitor network DC-DC converters are typically integrated circuits (ICs) that can have some external components (such as capacitors) and are in most cases characterized by a fixed VC. IN With V OUT Conversion ratio (e.g., divide-by-2 or divide-by-3). An AC-DC power converter can be constructed from a DC-DC power converter by, for example, rectifying the AC input into a DC voltage; then applying the DC voltage to the DC-DC power converter.

[0004] To provide greater flexibility for system designers and to handle applications where power supply may vary (e.g., when the battery is discharging and outputting a lower voltage, or when the device's power supply switches between battery and AC-DC power line source), it is useful to utilize a DC-DC power converter with a selectable conversion ratio. For example, U.S. Patent No. 10,263,514 B1, entitled "Selectable Conversion Ratio DC-DC Converter," published April 16, 2019, assigned to the assignee of this invention and incorporated herein by reference in its entirety, describes a Dixon DC-DC power converter capable of switching between a 2-way and 3-way operating mode. As another example, U.S. Patent No. 9,203,299 B2, entitled "Controller-Driven Reconfiguration of Switched-Capacitor Power Converter," published December 1, 2015, assigned to the assignee of this invention and incorporated herein by reference in its entirety, describes other DC-DC power converter architectures with reconfigurable conversion ratios.

[0005] In some applications, it can be useful to connect multiple DC-DC power converters in parallel to increase the available current for the load. For example, if a maximum output of 100 W is required for a particular load, ten 10 W power converter integrated circuits (ICs) can be coupled in parallel. However, under lighter loads, it can be useful to turn off one or more ICs to improve light-load efficiency (also known as the "phase shedding" characteristic). For example, Figure 1A This is a block diagram illustrating four parallel-coupled prior art 2-division power converter ICs 102a to 102d (collectively referred to as "102x") connected in parallel. In the example shown, each IC 102x has a V1 coupled to a 12V voltage source (e.g., a battery). IN Terminals, and from V OUT The terminal outputs 6V to the common bus 104.

[0006] Connecting a power converter in IC form to a common output—especially for power converters with multiple power-up phases (including a capacitor charge balancing phase and a “soft” start-up (limited current) phase)—is difficult to prevent destructive inrush currents and limit power dissipation within the IC, particularly under fault conditions such as short-circuited output terminals. Conventional standalone power converter ICs often rely on a single external pull-up “power good” (also known as “PGOOD”) pin to control whether the power converter IC is connected to a common output. For example, in… Figure 1AIn this configuration, each IC 102x includes a resistor R coupled to a pull-up voltage V. DD The PGOOD terminal (pin).

[0007] The PGOOD pin is typically an open-drain output, meaning each IC can be pulled down (to logic low or 0) and pulled up (to logic high or 1) by an external resistor. A power converter IC pulls down its own PGOOD pin until it is fully ready to supply power to the common output; therefore, once a power converter IC is fully ready to supply power to the common output, it stops pulling down its PGOOD pin. However, in a configuration of parallel power converter ICs, after releasing its pull-down condition, the power converter IC also monitors the state of its PGOOD pin and typically blocks output from the IC until the PGOOD pin is logic high, indicating that all power converter ICs are ready to support the load. Therefore, a group of parallel power converter ICs using the PGOOD logic signal cannot begin operation until all ICs stop pulling down their respective PGOOD pins.

[0008] Multiple parallel operation schemes typically expect all power converters to be powered on and off simultaneously. Therefore, such parallel operation schemes do not support phase switching, because powering on a power converter that has been turned off requires pulling down its PGOOD pin, which causes the remaining power converters to reduce their respective outputs.

[0009] Furthermore, if two or more power converters are off, putting them on can cause a "ping-pong" effect if they are out of sync with their startup phases. For example, each power converter typically pulls its PGOOD pin low during the initialization phase, then through the capacitor charge balancing phase and the soft-start phase, at which point the first power converter releases its PGOOD pin. However, if the first power converter's PGOOD pin signal is still low due to the second power converter's out of sync with its release, the first power converter should assume an error and enter a cooling phase to prevent overheating, and then restart the startup process. The first power converter needs to ensure that it cools down for a longer period than it was heated to ensure there is no slow temperature rise; therefore, the cooling phase can be quite long; typically, the cooling time is longer than the soft-start time to avoid cumulative temperature rise. This reduces the "overlap" time when two power converters can be powered on simultaneously. Two power converters can "ping-pong" until they both release their respective PGOOD pins simultaneously, which can result in power-on times measured in seconds. Figure 1BThis is a state-time graph, illustrating an example of the time difference in the occurrence of PGOOD checks for the two power converters PC#1 and PC#2 due to the varying durations of the charge balance phase. The more power converters coupled in parallel, the lower the chance of successful power-up. Summary of the Invention Technical issues

[0010] Therefore, the following would be useful: enabling parallel operation of power converters, making phase switching possible, but without excessively long start-up times. Solution to the problem

[0011] This invention includes methods and circuitry that enable parallel operation of power converters, making phase switching possible without excessively long startup times. More specifically, embodiments utilize reduced gate drive (RGD) low dropout (LDO) circuitry within a single power converter to achieve a parallel power converter system that supports phase switching while simultaneously eliminating the "ping-pong" effect. The RGD capability of each parallel power converter allows each power converter to be connected asynchronously without affecting other parallel power converters. In particular, the RGD capability allows for significantly reduced latency in full power-up, full charge balance, and soft-start of the power converters. For example, embodiments of this invention typically have RGD charge balance latency measured in hundreds of microseconds, rather than the tens of milliseconds latency typically found in conventional non-RGD power converters.

[0012] One implementation enables the output of a first power converter with RGD capability to be applied to the output of at least a second power converter by: enabling the RGD capability of the first power converter to limit the current through the output of the first power converter to a first level for a sufficient time to balance the charge of at least one flying capacitor connected to the first power converter. If the output voltage of the first power converter is greater than a threshold voltage, the RGD capability of the first power converter is disabled, thereby allowing full-gate drive operation.

[0013] Another implementation provides a fast start-up of multiple power converters connected in parallel to a common output, wherein each of the multiple power converters: sets a first indication signal (CGOOD) to a first state (e.g., low) to indicate that the power converter's charge balancing is not complete; sets a second indication signal (PGOOD) to a first state to indicate that the power converter is not ready to enter full-power operation mode; balances the charge on at least one flying capacitor connected to the power converter; sets the first indication signal to a second state (e.g., high) to indicate that the power converter's charge balancing is complete; waits to receive a first indication signal in the second state from all other power converters, and then performs a soft start of the power converter; and sets the second indication signal to a second state to indicate that the soft start of the power converter is complete.

[0014] Details of one or more embodiments of the present invention are set forth in the following drawings and description. Other features, objects, and advantages of the invention should become apparent from the description, drawings, and claims. Attached Figure Description

[0015] [ Figure 1A ] Figure 1A This is a block diagram showing four parallel-coupled prior art 2-division power converter ICs. [ Figure 1B ] Figure 1B This is a state versus time graph, which shows an example of the time difference in the occurrence of PGOOD checks for the two power converters PC#1 and PC#2 due to the different durations of the charge balance phase. [ Figure 2 ] Figure 2 This is a circuit diagram of one implementation of a DC-DC selectable conversion ratio power converter. [ Figure 3 ] Figure 3 yes Figure 2 A schematic diagram of one implementation of a level shifter / driver block and an LDO block. [ Figure 4 ] Figure 4 This is a block diagram showing details of one implementation of the switch control block. [ Figure 5 ] Figure 5 This is a block diagram showing four parallel-coupled RGD ICs for a 2-to-3 divider power converter. [ Figure 6 ] Figure 6 This is a process flowchart illustrating one method that allows phase cutting within a parallel power converter system. [ Figure 7 ] Figure 7This is a block diagram showing four parallel-coupled power converter ICs with selectable conversion ratios (3-way or 2-way). [ Figure 8 ] Figure 8 This is a process flowchart illustrating one method that allows for the rapid startup of parallel power converters. [ Figure 9A ] Figure 9A This is a state versus time graph, which shows an example of the time difference in the occurrence of CGOOD and PGOOD checks for a pair of power converters PC#1 and PC#2 relative to the duration of the corresponding first charge balance phase. [ Figure 9B ] Figure 9B This is a state versus time graph, which shows an example of the time difference in the occurrence of CGOOD and PGOOD checks for a pair of power converters PC#1 and PC#2 relative to the duration of the corresponding second charge balance phase. [ Figure 10 ] Figure 10 It is a top plan view of a substrate, such as a printed circuit board or a chip module substrate (e.g., a thin film block). Detailed Implementation

[0016] Similar reference numerals and names in various figures indicate similar elements.

[0017] This invention includes methods and circuits that enable parallel operation of power converters, making phase switching possible without excessively long startup times. More specifically, embodiments utilize reduced gate drive (RGD) low dropout (LDO) circuitry within a single power converter to achieve a parallel power converter system that supports phase switching while simultaneously eliminating the "ping-pong" effect. The RGD capability of each parallel power converter allows each power converter to be connected asynchronously without affecting other parallel power converters. In particular, the RGD capability allows for significantly reduced latency in full power-up, full charge balance, and soft-start of the power converters. For example, embodiments of this invention typically have RGD charge balance latency measured in hundreds of microseconds, rather than the tens of milliseconds latency typically found in conventional non-RGD power converters.

[0018] Example power converter

[0019] For the purpose of illustrating various embodiments of the invention, it is useful to consider examples of specific DC-DC power converters. However, it should be understood that the invention is not limited to this specific power converter example, but can be used with various power converter architectures, as well as in circuits such as AC-DC converters, H-bridge polarity switches, and motor controllers and drivers.

[0020] Figure 2 This is a circuit diagram of one embodiment of a DC-DC selectable conversion ratio power converter 200. The particular power converter 200 shown can be optionally configured as a 2-divider Dickson converter or a 3-divider Dickson converter using the same basic circuitry. The same power converter 200 can be used for DC-DC boost conversion by inverting the voltage input and voltage output. However, the invention is not limited to use with selectable conversion ratio power converters, but can also be used with fixed conversion ratio power converters.

[0021] The power converter 200 shown is coupled to the voltage source V. IN Between a reference potential 202 (such as circuit ground). The power converter 200 includes three switches S1 to S3 connected in series, which are coupled in series to a first branch including two switches S4 to S5 connected in series and a second branch including two switches S6 to S7 connected in series. Each switch may include, for example, one or more FETs, said one or more FETs including one or more MOSFETs. Depending on the output ratio configuration (divide by 2 or divide by 3), the power converter 200 should be coupled to the output capacitor C. OUT node V X The output voltage is generated at that location.

[0022] A first capacitor C1a is coupled between the first upper switch pair S1, S2 and the first branch switch pair S4, S5, and a second capacitor C2a is coupled between the second upper switch pair S2, S3 and the second branch switch pair S6, S7. The first capacitor C1a, during charging, is at node V... C1a There is a voltage across its terminals, which is a function of the current conversion ratio—or V in divide-2 mode. X And in the 3-way divider mode, the voltage is 2V. X The second capacitor C2a is charged at node V. C2a A voltage V is present across its terminals. X .

[0023] At least some of the switches S1 to S7 can be selectively controlled to be in an ON (conducting) or OFF (circuiting) state via a control circuit system (not shown). At least some of the switches S1 to S7 can be selectively coupled to one of two non-overlapping complementary clock phases, namely P1 or P2. Some of the switches S1 to S7 can be permanently coupled to one of the two complementary clock phases, namely P1 or P2. Table 1 below shows the configuration of the state or associated clock phase of each of the switches S1 to S7 of the power converter 200 for both 2-way and 3-way configurations. Table 1

[0024] In either configuration, the non-overlapping complementary clock signals P1 and P2 open or close the associated power switches, causing charge to transfer from flying capacitors C1a and C2a to C. OUT In the middle, leading to C OUT Voltage V across the terminals OUT For V IN / 2 or V IN / 3. Further details of the operation of such and similar DC-DC selectable conversion rate power converters are set forth in U.S. Patent No. 10,263,514 B1.

[0025] In some implementations... Figure 2 The circuit system shown can be replicated in parallel, but operated with different P1, P2 clock signal phases (e.g., 180° apart from the P1 and P2 clock signals for the power converter 200 shown) to provide output ripple smoothing and additional current capacity. Additional parallel circuitry may be included to provide even greater current capacity.

[0026] In FET-based implementations, the on / off control signal or the P1 / P2 clock phase signal is coupled to the gate of each switch S1 through S7 at least through the driver circuit, and in many cases through both the level shifter circuit and the driver circuit. In either case, each driver circuit or level shifter / driver circuit can be powered by a regulated power supply tailored to the voltage requirements of each switch S1 through S7. The energy source for the regulated power supply can come from a variety of different sources, including V... IN Or even another phase of the power converter 200.

[0027] For example, refer to Figure 2 Power switches S1 to S7 are shown as using N-type MOSFET M CP1 To M CP7 (collectively referred to as "M") CPx This is achieved through ) . Each FET M CPxThe gate of the input signal is coupled to level shifter / driver circuit 204 (not all instances are numbered to avoid confusion). In some cases (e.g., power switches S6 and S7), level shifter / driver circuit 204 may only include the driver, as level shifting may not be necessary (note that if the power switch control path does not include a level shifter, additional circuitry such as buffers may be required to simulate the level shifter's delay and avoid timing issues). The level shifter transforms the input signal from one voltage domain (e.g., digital logic voltage) to another voltage domain (e.g., transistor control voltage). Therefore, the output of the level shifter follows the input signal, but in a different voltage range. Power to each level shifter / driver circuit 204 is provided by the corresponding low-dropout (LDO) circuit 206. The clock phase (P1 or P2 in this example) or on / off control signal can be coupled to the corresponding power FETM through the level shifter / driver circuit 204. CPx The gate.

[0028] Reduced gate drive low dropout circuit

[0029] Embodiments of the present invention (one of which will be described in detail in the next section) utilize coupling to Figure 2 Some “reduced gate drive” (RGD) configurations of the low dropout (LDO) circuit 206 of the level shifter / driver circuit 204 shown are described. Such RGD LDO configurations are described in detail in U.S. Patent Application Serial No. 17 / 331,594, entitled “Dynamic DivisionRatio Charge Pump Switching,” filed May 26, 2021, assigned to the assignee of this invention, the contents of which are incorporated herein by reference.

[0030] As background, at least FET M is implemented in U.S. Patent Application Serial No. 17 / 331,594. CP1 The driver circuit system (see this application) Figure 2 This can be adapted to limit the current through the power converter 200. In particular, it should be appreciated that when set to the ON (ON) state, the power converter FET switch M... CPx Typically, it operates under "overdrive" or "full drive" conditions. An overdriven FET gate creates a stronger conductive channel, effectively reducing the FET's on-resistance R. ON With this understanding, it should be further recognized that during potential disruptive events (e.g., during startup or when the conversion ratio of the power converter is dynamically reconfigured), some or all of the power FETs in the power converter (especially FET M) may be at risk. CP1 Increase RON This will reduce the current flowing through the FET and thus prevent excessive current spikes.

[0031] A common problem with many FET-based DC-DC power converter architectures is the need to prevent excessive current inrush during power converter startup. For example, in a selectable conversion rate DC-DC converter of the type shown in U.S. Patent No. 10,263,514 B1, there is a lack of sufficient protection circuitry when the input voltage V is first applied. IN At this time, no capacitor (sometimes called a "flying capacitor") will be initially charged, and therefore current will flow into the circuit. For example, if the on-resistance R of the FET power switch... ON It is 1 milliohm (0.001 ohm), and V IN If it is 10V, then according to Ohm's Law... The inrush current will be a spike of approximately 10,000 amperes. In integrated circuit implementations, parasitic inductance exists (e.g., due to conductor wiring on the die and printed circuit board wiring), which transforms current spikes into voltage spikes according to the following inductor principle: Such voltage spikes exert excessive electrical stress on charge pump power switches, affecting their reliability and potentially causing damage. For generating a 10 V 1 ns 100 A pulse across a charge pump power switch, the parasitic inductance is only about 100 pH. The resulting 10 V spike can exceed the breakdown voltage of many FET switches; naturally, for the same parasitic inductance, a larger current spike results in a larger voltage spike.

[0032] Problems arise when the flying capacitors of a DC-DC power converter become unbalanced, meaning there is a charge difference between the flying capacitors connected by the power switch. If this charge balance is not maintained, current spikes and potentially damaging voltage spikes may occur.

[0033] As described in U.S. Patent Application Serial No. 17 / 331,594 cited above, at least some of the LDO circuits 206 can be configured to selectively increase Ro for the associated power FET in the power converter by actively controlling the driver voltage to the gate of the power FET. ON During normal power converter operation, the power FET driver voltage can be set to overdrive the FET gate to drive R... ON Reduced to the desired level that allows for high current flow for a specific application. However, for other scenarios (e.g., during soft-start, charge balancing, or transition ratio mode changes), the power FET driver voltage can be reduced to increase RV. ON This, and therefore blocks the current flowing through the power FET to the desired level.

[0034] Figure 3 yes Figure 2 A schematic diagram of one embodiment of the level shifter / driver block 204 and LDO block 206. (See attached diagram.) Figure 2 As shown, LDO block 206 provides power to the associated power FET M. CPx The gate level shifter / driver block 204. The input to the level shifter / driver block 204. (For example, clock signal P1 or clock signal P2, or an on / off control signal) is applied to the input of level shifter 302. The output of level shifter 302 is coupled to the input of driver circuit 304, and the output of driver circuit 304 is coupled to the associated FET M. CPx The gate of the pre-driver 304. In the example shown, the driver circuit 304 includes a pre-driver 304a (in this example, a set of three series-coupled inverters) and a series-coupled final driver 304b. Internally, the final driver 304b has at least one NMOS FET n and one PMOSFET p, each having a drain-to-drain coupled conductive channel, wherein each FET n and FET p has a gate driven by the output of the pre-driver 304a. The drain of the PMOS FET p and the drain of the NMOS FET n are coupled to an associated power FET M. CPx The gate of the level shifter. Note that in some implementations, although a high drive may be required at the output of the level shifter, the level shifter 302 may be placed after the pre-driver 304a or between a pair of inverters including the pre-driver 304a.

[0035] In some implementations, the inverter can be scaled up from inverter to inverter in terms of physical size in order to provide sufficient current drive capability for FET M CPxThe gate of the inverter is charged or discharged. For example, in a driver circuit 304 with three series-coupled inverters in a pre-driver 304a, the first inverter may have a relative size of "1", the second inverter may be 3 times larger than the first inverter, and the third inverter may be 9 times larger than the first inverter. Finally, the final driver 304b may be 27 times larger than the first inverter in the pre-driver 304a. The multipliers used for each stage may differ from the 1×, 3×, 9×, and 27× ratios, but typically each stage is larger than the previous one to avoid very slow rise and fall edges. In alternative embodiments, the number of inverter stages may be fewer or more, and non-inverter stages (buffer amplifiers) may be used instead of inverter stages. Therefore, the driver circuit 304 shown is merely exemplary, and other circuits may be used to couple the output of the level shifter 302 to the associated FET M. CPx The gate.

[0036] Power to level shifter 302 and driver circuit 304 is provided by LDO block 206. In the example shown, the power source for level shifter 302 and pre-driver 304a is provided by first LDO section 310. First LDO section 310 includes source follower (common drain) amplifier circuitry, which includes a pair of FETs M LDO1 and FET M LDO2 The pair of FETs M LDO1 and FET M LDO2 The conductive channels (between the drain and source) are coupled in series, their gates are coupled together, and their sources are coupled together. FET M LDO1 FET M LDO2 The conductive channel is coupled in capacitor C O1 With supply voltage V DD-FGD Between. Capacitor C O1 It is also coupled to the floating reference potential 308. FET M LDO1 The source provides drive voltage V to level shifter 302 and pre-driver 304a. LDO_OUT1 (FET M) LDO2 It is an optional protection device.

[0037] Current source I BIAS1 Coupled in series with Zener diode D1 at the supply voltage V BIAS1 Between the reference potential 308 and the current source, which can be configured using resistors, transistors, and / or diodes in various circuits, one terminal of the Zener diode D1 is coupled to the FET M. LDO1 FET M LDO2 The gate of the FET. Resistor R1 and capacitor C1 are coupled in parallel with Zener diode D1. When FET MLDO1 FET M LDO2 When transitioning from the ON state to the OFF state, resistor R1 is used to control FET M. LDO1 FET M LDO2 Gate discharge. Due to the output drive switching circuit of LDO block 206, noise is coupled to M. LDO1 The possibility of the gate, which can modulate the output drive voltage V LOD_OUT1 Such noise is mitigated by capacitor C1, which also decouples the glitches from the power supply. An alternative implementation could be made for M... LDO1 The gate uses push-pull drive.

[0038] The current source V before Zener diode D1 BIAS1 The output terminal of FET M LDO1 FET M LDO2 The gate is provided with a substantially constant bias voltage. The bias current I... BIAS1 A current flows through the Zener diode D1, ensuring that the diode is always reverse-biased. Unlike a conventional diode that blocks any current from flowing through it when reverse-biased, the Zener diode begins to conduct once the reverse voltage reaches a predetermined value. Even with large current variations (as long as the current remains between the Zener diode's minimum breakdown current and maximum rated current), the applied reverse voltage remains almost constant. The Zener diode continues to regulate its voltage until the diode's holding current drops below the minimum current value in the reverse breakdown region.

[0039] The final driver 304b is powered by a second LDO section 312, which includes components having their coupling to the supply voltage V. DD-RGD A pair of cascaded FETs M with the conductive channel between the final driver 304b (between the drain and source). LDO3 and FET M LDO4 FET M LDO3 FET M LDO4 The gate is coupled to a FET independent of M. LDO1 and FET M LDO2 The separate gate driver circuit of the gate drive circuit system, and FET M LDO3 The source of FET M LDO4 The source electrodes are coupled together (FET M) LDO4 (This is an optional protection device). The main function of the gate driver circuit of the second LDO section 312 is to enable at least two different voltage levels at node A to be coupled to FET M. LDO3 The gate, which in turn determines the power FETM associated with the drive. CPx The final driver 304b provides the output voltage level VGATE Therefore, the associated power FET M CPx It can be placed in (1) for normal power converter operation with low R ON The overdrive or "all-gate drive" on state; or (2) the high R value selected to provide protection against possible destructive events (e.g., inrush or charge transfer currents) during events such as dynamic reconfiguration of the power converter's conversion ratio, during power converter startup, when balancing the charge in the flying capacitors within the power converter, or during fault events such as short-circuit events or thermal overloads. ON At least one current limit is reduced in the gate drive on state.

[0040] Resistor R2 and capacitor C2 are coupled in parallel with Zener diode D2 and function in essentially the same way as resistor R1 and capacitor C1. Resistor R2 is used in FET M. LDO3 FET M LDO4 When transitioning from the ON state to the OFF state, FET M... LDO3 FET M LDO4 The gate discharge. Capacitor C2 mitigates the Vo of LDO block 206. LDO_OUT2 Noise on the (drive voltage output) and decouple glitches from the power supply. Energy storage capacitor C O2 Coupled in FET M LDO4 Between the drain and the floating reference potential 308, and to FET M CPx The gate provides some initial charge, as well as isolation from the floating reference potential 308.

[0041] FET M LDO3 FET M LDO4 The gate driver circuit includes a Zener diode D2 coupled in series at the supply voltage V. BIAS2 Variable current source I between reference potential 308 and BIAS2 FET M LDO3 FET M LDO4 The gate is coupled to the current source I BIAS2 Node A between Zener diode D2 and the current source I before Zener diode D2 at node A. BIAS2 The output terminal of the FETM LDO3 FET M LDO4 The gate is provided with a substantially constant bias voltage V. GS_SF FET M LDO3 The source provides the drive voltage V to the final driver 304b. LDO_OUT2 .

[0042] Connected in parallel with Zener diode D2 is voltage control circuit 314, which includes a FET M series coupled to the first diode connection. D0 FET M connected to at least one additional diode DN The reduced gate drive P-type FET switch M SW ,in, FET switch M SW The gate is coupled to a switch control block 316, which is coupled to an enable signal EN. RGD Details of the switch control block 316 are discussed below.

[0043] The first diode is connected to the FET M. D0 FET M connected to at least one additional diode DN The conductive channels are coupled in series. As shown, the switching FET switch M... SW The conductive channel is coupled at node A to the FET M connected to the first diode. D0 Between the conductive channels. Finally, an additional diode connected in series is linked to the FET M. DN The conductive channel is coupled to the floating reference potential 308. Note that the switching FET switch M... SW It can be positioned anywhere along the voltage control circuit 314 to interrupt or enable the current flowing through the circuit. However, as Figure 3 The positioning FET switch M shown SW This can reduce the FETM due to, for example, diode connections. D0 and / or FET M DN The capacitance of FET M LDO3 and FET M LDO4 The parasitic effects.

[0044] Diode-connected FET M D0 The function is to enable FET M LDO3 Offset, because FET M D0 and FET M LDO3 The threshold voltage is effectively canceled out. An additional diode-connected FET M DN The function is: when the FET switch M SW When the voltage control circuit 314 is closed and its current mirror function is active, and FET M CPx With FET M DN The size ratio is set proportionally via FET M CPx Current I MAIN More specifically, through FET M CPx Current I MAIN With current source I BIAS2Current and FET M DN With FET M CPx The size ratio is proportional. For example, if the current source I... BIAS2 The output is 1 mA, and the FET M CPx It is FET M DN 1,000 times the size (W / LM) CPx = 1000 × W / LM DN Then through FET M CPx The maximum current will be 1,000 × 1mA = 1 A. This is achieved by ensuring that the FET M... DN Gate-to-source voltage V GS With FET M CPx Gate-to-source voltage V GS The same implementation method is used. FET M CPx The maximum gate voltage is the voltage at node A minus FET M. LDO3 Threshold voltage V TH Including FET M D0 Increase the voltage at node A by the second threshold voltage V. GS Therefore, the voltage at node A = (FET M) DN V GS )+(FET M D0 V TH ) or 2V GS If FET M LDO3 and FET M D0 Matching (proportionally), then FET M CPx V GS Maximum achievable value and FET M DN V GS They are the same, and this equivalence varies with processes, temperatures, etc.

[0045] As described, the diode-connected FET M DN Compared to FET M CPx They are proportional in size. In some implementations, FET M LDO1 FET M LDO2 FET M LDO3 FET M LDO4 FET M D0 ... FET M DN and FET M CPxSome or all of them can be segmented FETs, meaning that a device intended to be used as a large FET is fabricated as multiple (e.g., 10,000) small FETs coupled in parallel (each small FET can be referred to as a "finger," reflecting a typical aspect of their physical layout on the IC die). Diode-connected FET M D0 FET M DN The same technology can be used to manufacture it, but it can be manufactured with a much smaller number of FET fingers (e.g., as few as one finger). Due to the configuration shown, the effect of the voltage control circuit 314 on FET M... LDO3 The voltage V at the gate GS_SF Small changes in current cause the FET M CPx With FET M DN The size ratio determines the power flow of the FET M CPx A proportionally larger current I MAIN .

[0046] Add more than one diode connected to the FET M DN Allow FET M CPx With FET M DN Adjustment of the size ratio. For example, if FET M CPx With a width of 100 and 1,000 fingers, the first FET M DN It should also have a width of 100 for matching, but it can have only one finger. Therefore, FET M DN With FET M CPx The size ratio is 1,000 to 1, and it comes from current source I. BIAS2 1 mA means through FET M CPx 1 A. To change the size ratio to 2,000:1, two diodes connected to a FET M DN They can be coupled in series (source to drain). If the FET width is still 100, then the FET M is connected to two diodes. DN The effective number of fingers is half, thus giving a value relative to FET M. CPx A size ratio of 2,000 to 1.

[0047] As mentioned above, an important function of the gate driver circuit is to direct the power to the FET M. LDO3 Provides selectable adjustable gate bias voltage V GS_SF The FET M LDO3 This, in turn, controls the power supply and voltage output of the final driver 304b. Furthermore, the gate driver circuit and FET M... LDO3 Will pass through FET MCPx Current I MAIN Adjusted to be connected to FETM DN The current is directly proportional to the current. When the FET switch M... SW When disconnected, the voltage control circuit 314 is then disconnected from node A—and therefore from FET M. LDO3 The gate is disconnected—and therefore the FET M LDO3 The output is essentially unaffected; therefore, the final driver 304b can drive the FET M CPx The gate is fully overdriven to the selected level determined by the Zener diode D2.

[0048] When FET switch M SW When closed—such as during the startup of a power converter or when dynamically switching the conversion ratio or rebalancing the charge across the flying capacitor—the voltage control circuit 314 then operates as a bypass to divert the current around diode D2 and reduce the voltage at node A, thus reducing it to FET M. LDO3 The driving voltage to FET M. LDO3 The reduced gate drive voltage consequently reduces the power of the final driver 304b, and thus reduces the power of the power FET M. CPx Gate drive voltage V GATE Therefore, FET M CPx It has a reduced gate drive voltage, which results in a difference between R when it is in a fully overdriven state. ON The value is compared to the increase of R ON Value. For the power FET M through the power converter. CPx At least some of the added resistance suppresses excessive current spikes, thus protecting the power FET (and other coupled circuitry) from large voltage spikes. Selectively changing I... BIAS2 Current control is applied to power FET M CPx V GATE The value of allows for the selection of different increases in R. ON value.

[0049] In some implementations, the control circuit (not shown) can be based on measured parameters (such as V). IN value, V OUT The value of the pump capacitor voltage or the value of the load current) and / or due to a sensed event (such as a short-circuit event and / or charge imbalance on the pump capacitor) enables (triggers) the power FET M, which is in the ON state, to limit current spikes during potentially destructive events. CPxThe reduced gate drive operation. In some implementations, this can be based on a gate drive mechanism for the FET switch M that takes effect before a known impending event (such as dynamic switching of the conversion ratio). SW External enable signal EN GRD Enable (trigger) the on-state power FET M to limit current spikes during potentially destructive events. CPx Reduced gate drive operation.

[0050] The duration of the reduced gate drive operation for a power FET can be set to a fixed time suitable for a specific application, or it can be determined based on some criteria. For example, the reduced gate drive operation for a power FET can be a function of the output load, or a function of the output load and the selected maximum duration (i.e., the timeout parameter), or a function of the voltage across the flying capacitor that has reached a certain percentage (e.g., 95%) of the desired target level, or a combination of these values ​​and / or other parameters.

[0051] Using power FET M CPx The advantage of using a diode-connected FET in a voltage control circuit 314 manufactured with the same technology as (e.g., NMOSFET) is that the device should have essentially matching characteristics with respect to process / voltage / temperature (PVT) variations.

[0052] In summary, FET M LDO3 The main function of the gate driver circuit is to enable at least two different voltage levels at node A to be coupled to FET M. LDO3 The gate. More specifically, the voltage control circuit 314 can selectively make the voltage at node A such that the voltage control circuit 314 is not engaged (FET switch M). SW The first voltage level of the disconnected circuit is engaged with the voltage control circuit 314 (FET switch M). SW The voltage level shifts between at least the second voltage level (closed).

[0053] It should be understood that, Figure 3 The second LDO section 312 shown is likely easy to implement, requiring very little power and circuit area. However, in other embodiments, other devices or circuits providing the same or similar functionality can be used. For example, node A can be connected via a FET switch M. SW Coupled to an amplifier with a level-shifted reference voltage as its input; to a FETM LDO3 Gate voltage V GS_SF It may be more accurate, but at the cost of complexity, circuit area, and power (and therefore efficiency).

[0054] Notice, Figure 3The LDO block 206, including the second LDO section 312, can be used to power all the FET switches in the power converter 200 to limit the current through such switches as may be required (e.g., when the conversion ratio of the power converter 200 is dynamically changed). In some cases, for some FET switches (e.g., power switches S5 and S7 in Figure 1), the level shifter 302 circuit will not be needed. It can be applied directly to the associated pre-driver 304a. It should also be noted that the LDO block 206 can be used to provide regulated power to other types of target circuits, not just to the level shifter / driver block 204.

[0055] Figure 4 This is a block diagram showing details of one embodiment of the switch control block 316. As shown, the switch control block 316 is coupled to components of the voltage control circuit 314 and includes an NFET M having a first end of its conductive channel coupled to node A via a resistor Ra and a second end of its conductive channel coupled to a floating reference potential 308. The drain of the NFET M is coupled to a P-type FET switch M. SW The gate. Current source I BIAS The switch Sw and resistor Rb are coupled in series at voltage V as shown. BIAS Between the floating reference potential 308 and the current source I. BIAS Between resistor Rb. In an alternative implementation, a standard level shifter can be used to drive the FET switch M. SW It has a gate, but this may come at the cost of a larger IC area.

[0056] During operation, if the enable signal EN... RGD If the logic value is "1", then switch Sw closes, thereby turning on NFET M and turning on P-type FET switch M. SW The gate is pulled down to the floating reference potential of 308. The result is that the negative V... GS Applied to P-type FET switch M SW Thus, M SW Set to the ON state (i.e., the switch is closed). In contrast, if the enable signal EN... RGD If the logic value is "0", then switch Sw is open and NFET M is not conducting; therefore, the P-type FET switch M... SW V GS It is zero, thus making M SW Set to non-conducting state (i.e., disconnect the switch).

[0057] LDO block 206 can provide two or more levels of reduced gate drive. For example, in the example IC implementation, Figure 3 The LDO block 206 can be configured to provide approximately 4 A of current through the associated power FET M during the charge balance phase. CPx The RGD allows approximately 700 mA of current to flow through the associated power FET MCPx during the soft-start phase when charge balancing is not required. Full-gate drive can, for example, allow approximately 9 A or more of current to flow through the associated power FET MCPx. CPx The current values ​​listed for this example are for a specific example IC implementation, and other current values ​​can be selected for different implementations and applications. It is worth noting that the RGD capability of the LDO block 206 means that the charge pump can operate fully during both the charge balancing phase and the soft-start phase.

[0058] Reduced gate drive LDO implementation

[0059] It is worth noting that phase cutting within a group of power converters is only feasible if, once a power converter is "disconnected," other power converters can be reactivated and reconnected. The presence of an RGD LDO block within a single power converter can enable parallel power converter systems that support phase cutting while simultaneously eliminating the "ping-pong" effect, because the RGD capability allows each power converter to be asynchronously connected without affecting other power converters. In particular, the RGD capability allows for significantly reduced latency in full power-up, full charge balancing, and soft-start of the power converters. For example, the RGD charge balancing latency in embodiments of the present invention is measured in hundreds of microseconds, rather than in tens of milliseconds as in conventional non-RGD power converters. By implementing phase cutting, power consumption is saved by switching multiple FETs within the power converter for each disabled power converter.

[0060] Figure 5 This is a block diagram showing four parallel-coupled 2-to-3 divider power converters RGD ICs 502a to 502d (collectively referred to as "502x"). In the example shown, each RGD IC 502x has a Vt coupled to a 12V voltage source (e.g., a battery). IN Terminals, and from V OUT The terminals output 4V or 6V to the common bus 504. Each RGD IC 502x includes a pull-up voltage V coupled to the common bus 504 via a resistor R. DDThe PGOOD terminal (pin). In the example shown, RGD IC 502a, RGD IC 502b and RGD IC 502c each output a full gate drive current (e.g., each outputs 9 A), while RGD IC 502d outputs a reduced gate drive current (e.g., 4 A) when it transitions from the off state (due to phase cutting) to the on state.

[0061] Figure 6 This is a process flowchart 600 illustrating one method of allowing phase cutting within a parallel power converter system. The steps shown depict how one power converter in a parallel system can be powered from a shutdown (or reduced current) state and contribute power to a common output without affecting other parallel power converters.

[0062] Reference Figure 6 To bring a single power converter online, the controller (not shown) enables the signal (e.g., by setting the enable pin of the power converter to logic high) [box 602]. The single power converter can then read the programmed value (e.g., via a general-purpose input / output digital signal pin or from internal memory) and initialize internal components (e.g., programmable resistors and internal trimming parameters) [box 604].

[0063] The power converter reads the common output voltage V. OUT (or indicate V) OUT The voltage, such as the voltage across one of the terminals of a capacitor, and the measured voltage (e.g., V) OUT ) and the first threshold voltage V Th1 A comparison is made to determine whether the power converter is in a stand-alone (non-parallel) configuration or a parallel configuration [Box 606]. This can be done in several ways (e.g., V...). OUT The percentage or as below V OUT The threshold voltage V is determined by a fixed voltage representing the ideal output value. Th1 The value of V. If V OUT (Or, in the case of alternative elections,) If no other power converter is connected to the common output (or the system is in a fault condition), then the power converter starts up by pulling its PGOOD pin low [box 608] and setting the RGD current to a low value (e.g., 700 mA), thus allowing the normal independent charge balancing and soft-start phases to continue [box 610]. Setting the RGD current value low limits the voltage drop from the power converter to the Vo. IN With V OUTThe potentially large difference between (which may be zero volts) can lead to a harmful current inrush and limit power dissipation within the power converter and consequent overheating (especially in the event of a fault such as a short-circuited output terminal).

[0064] Limit the RGD current for a sufficient time to ensure all flying capacitors are balanced [box 612]. If V OUT Greater than the second threshold voltage V Th2 (In some implementations, it may be related to V) Th1 (same), and the output current I OUT Within the selected parameter values ​​(e.g., no short circuit, no overcurrent) [box 614], the power converter can release PGOOD and allow full-gate drive current [box 616]; otherwise, a problem is detected, and the power converter signals this state by keeping PGOOD low [box 618]. This can be compared with the threshold voltage V. Th1 The threshold voltage V is determined in a similar way to the value of V. Th2 The value (although not necessarily in exactly the same way, and not necessarily the same value). Note that in the configuration shown, if PGOOD is kept low by any power converter, all other power converters are typically configured to stop working, because of the assumption that the system as a whole cannot provide sufficient power to the load.

[0065] If in box 606 (Or, in the alternative options,) If at least one other power converter is connected to the common output, then the initial power converter does not pull its PGOOD pin low. Instead, power converter startup involves a sequence of parallel configurations setting its RGD current to a high value (e.g., 4 A), which quickly balances the charge on the power converter's fly-through capacitor [box 620]. Due to V IN With V OUT The voltage difference between them is smaller than that under independent configurations, so a higher RGD current can be used. For example, if V IN = 10V to a power converter configured in divide-by-two operating mode, and for the associated power FET M CPx Given a current of 4A and an initial output of 4.5V, then At 0.5 V, 4 A is equivalent to 2 W, which is low enough that the power converter should not overheat.

[0066] The RGD current is limited for a sufficient time to ensure that all flying capacitors are balanced [box 622]. It is worth noting that, due to the power FET M... CPxThe current is supplied by at least one power FET M in the power converter. CPx With its reduced gate drive limitation, this power converter can immediately supply some power to the common output while completing the charge balancing and soft-start phases—without requiring additional waiting time.

[0067] If V OUT Greater than the second threshold voltage V Th2 And the output current I OUT Within the selected parameter values ​​(e.g., no short circuit, no overcurrent) [box 624], the power converter can allow full-gate drive current [box 626], otherwise a problem will be detected, and the power converter will signal this state by pulling PGOOD low [box 628]. Furthermore, in the configuration shown, if PGOOD is kept low by any power converter, all other power converters are typically configured to stop operating, based on the assumption that the system as a whole cannot provide sufficient power to the load.

[0068] If the flying capacitor in an RGD power converter loses its charge balance, there are several options for achieving charge balance, all of which take a short time to rectify because the entire power converter balances during switching. For example, if the flying capacitor is overcharged, current may flow from V... OUT Reflux to V IN (Assume V) IN (The power supply connected at the point can be recharged), switching may be paused or reconfigured until V. OUT The descent allows excess charge to be discharged to the output of the power converter, and / or excess charge to be dumped to ground. If the flying capacitor is undercharged, it can be balanced from the output (i.e., the capacitor is charged from the output), which can increase the charge from V. IN The RGD current is used to compensate for the balance current, and / or the power FET M can be changed. CPx The RGD switch current limit helps with charge balance.

[0069] One way to summarize the implementation described above is to enable the RGD capability of the first power converter to limit the current through the output of the first power converter to a first level for a sufficient time to balance the charge of at least one flying capacitor connected to the first power converter, thereby enabling the output of the first power converter with RGD capability to be applied to the output of at least the second power converter. If the output voltage of the first power converter is greater than a threshold voltage, the RGD capability of the first power converter is disabled, thereby allowing full-gate drive operation.

[0070] Start-up of parallel power converter

[0071] A useful aid of the phase-cutting embodiments of the present invention is the circuitry and methods for accelerating the startup of parallel power converters, including those lacking RGD capability. One embodiment of the invention reuses the functionality of existing pins on the power converter to indicate parallel or non-parallel configurations and to indicate that a particular power converter has achieved charge balance. The result is a substantially shorter startup time for a group of power converters connected in parallel to a common output.

[0072] Figure 7 This is a block diagram illustrating four parallel-coupled power converter ICs 702a to 702d (collectively referred to as "702x") with selectable conversion ratios (3-way or 2-way). In the example shown, each IC 702x has a Vt coupled to a 12V voltage source (e.g., a battery). IN Terminals, and from V OUT The terminals selectively output 4V or 6V to the common bus 704. Each IC702x includes a resistor R. P Coupled to pull-up voltage (e.g., V) DD The standard open-circuit drain PGOOD terminal (pin). (Note,) Figure 7 While the discussion focuses on IC implementations of power converters, it also applies to non-IC implementations.

[0073] When any of the IC 702x units is used in an independent (non-parallel) configuration, the SyncSel pin is grounded. However, in the reused version of the IC 702x, the SyncSel pin is coupled to a pull-up voltage (e.g., V). DD The existing internal circuitry of each IC 702x (which is then reprogrammed accordingly) instructs the IC to be coupled in parallel with other similar ICs. Additionally, one IC (e.g., IC 702a) grounds its SyncSel pin to indicate that such an IC is the primary control IC in a group of ICs connected in parallel. The primary control IC provides a clock signal to the other power converter ICs (via their ClkSync pins) via its ClkSync pin, causing the other power converter ICs to switch simultaneously; without this shared clock signal, some power converter ICs may operate close but not perfectly synchronously.

[0074] In the example shown, each IC 702x includes a resistor R. C Coupled to pull-up voltage (e.g., V) DD The open-drain CGOOD pin of the IC 702x is also included. Each IC 702x also includes a resistor R. P Coupled to pull-up voltage V DD The PGOOD pin.

[0075] It should be noted that charge balancing requires a very small current, and therefore IC 702x should not heat up significantly during the charge balancing phase. On the other hand, the soft-start phase allows a considerable current to flow through IC 702x, which could lead to overheating if all ICs are not synchronized to provide power to the load. In terms of time, the charge balancing phase is typically the most variable startup phase across a group of parallel IC 702x (e.g., 0 ms to 30 ms per IC in some cases), while the soft-start phase typically has a relatively uniform and short duration (e.g., tens of microseconds) for each IC 702x. Figure 1B An example of the timing difference in PGOOD checks between two power converter ICs (PC#1 and PC#2) caused by different durations of the charge balance phase is shown.

[0076] The CGOOD pin is essentially used as a second PGOOD pin, which each IC 702x uses as an indicator that the IC has completed the fly-through capacitor charge balance. Therefore, each IC 702x delays the start of its power soft-start phase until all IC 702x have indicated via a shared CGOOD signal that they have completed their respective charge balance phases and are essentially synchronized. Once the shared CGOOD signal indicates that the charge balance phases of all IC 702x have been completed, all IC 702x can begin a relatively short and uniformly long soft-start phase. The PGOOD pin remains used to indicate that all IC 702x have successfully completed the soft-start phase and are ready to enter full-power operation mode.

[0077] Figure 8 This is a process flowchart illustrating one method for enabling rapid startup of parallel power converter ICs. (Note:) Figure 8 While the discussion focuses on the IC implementation of the power converter, it also applies to non-IC implementations. Each parallel power converter IC 702x receives an enable signal from a controller (not shown), and the internal digital circuitry is powered on [box 802]. At this time, the pull-up resistor R... C and R P Keep the CGOOD and PGOOD pins high. Then, the individual IC702x can read the programmed values ​​and initialize internal components (e.g., programmable resistors and internal tuning parameters) via general-purpose input / output digital signal pins [Box 804].

[0078] An internal check of the SyncSel pin's state determines whether IC 702x is configured for parallel or standalone operation [Box 806]. If in standalone configuration, IC 702x continues normal operation [Box 808]. If in parallel configuration, IC 702x checks the states of the CGOOD and PGOOD pins [Box 810]. If both CGOOD and PGOOD pins are high (indicating all other IC 702x pins have completed charge balancing and soft-start), IC 702x pulls its CGOOD pin low [Box 811], and the process continues at Box 814; otherwise, IC 702x pulls two of its CGOOD and PGOOD pins low to indicate that IC 702x has not completed charge balancing and is not ready for full-power operation [Box 812]. After that, IC 702x performs charge balancing on its flying capacitor and then releases the CGOOD pin of IC 702x (e.g., if CGOOD is low, it makes CGOOD high) [Box 814].

[0079] After charge balancing is complete, IC 702x checks if its CGOOD pin is high and if the timeout period (e.g., 320 ms) has expired [box 816]. If not, IC 702x essentially enters a loop to reset the timeout period to zero [box 818] and then loops back to box 812. It is worth noting that since at least one round of charge balancing has already occurred, the duration of box 814 (charge balancing of the flying capacitor) is typically significantly shortened.

[0080] If the CGOOD pin of IC 702x is high (importantly, this indicates that all other IC 702x have completed charge balancing) and the timeout period has expired, IC 702x can begin and complete its soft-start phase, at which point the PGOOD pin of IC 702x is released if it has been pulled low at block 812 [block 820]. IC 702x then checks if the PGOOD pin is high, indicating that all other IC 702x have completed the soft-start phase without problems (e.g., overcurrent or undercurrent conditions) [block 822]. If the PGOOD pin is high, IC 702x can proceed to normal full-power operation mode [block 824]. If the PGOOD pin is low, IC 702x essentially enters a loop to reset the timeout period to zero [block 818] and loops back to block 812.

[0081] The CGOOD check at box 816 allows IC 702x to avoid prematurely entering the soft-start phase until all IC 702x have completed the charge balance phase. If a cycle is required at the CGOOD check, the duration of charge balance will typically be significantly shortened because at least one round of charge balance will occur. The short duration of charge balance (potentially close to—even very close to—zero seconds) in the event of a cycle helps synchronize all IC 702x. Once no IC 702x has its CGOOD pin held low, all IC 702x can proceed to the soft-start (SS) phase. In most cases, a cooling period should not be required (if cooling is needed, the process will cycle back to the charge balance phase). Furthermore, the use of the CGOOD flag allows disengaged IC 702x to reconnect by allowing charge balance to occur without pulling PGOOD low, which could interfere with other power converters (turning them off).

[0082] Figure 9A This is a state-time graph, illustrating an example of the timing difference between the CGOOD and PGOOD checks of a pair of power converter ICs (PC#1 and PC#2) relative to the duration of the corresponding first charge balance phase. The CGOOD check periods do not overlap, therefore the two power converter ICs cycle back to... Figure 8 Box 812 in the middle.

[0083] Figure 9B This is a state-time graph, showing an example of the timing difference between the CGOOD and PGOOD checks of a pair of power converter ICs (PC#1 and PC#2) relative to the duration of the corresponding second charge balance phase. The CGOOD check periods do not overlap, as indicated by dashed line 902, therefore both power converter ICs continue into the soft-start phase (…). Figure 8 (Box 820 in the middle).

[0084] One way to summarize the CGOOD aspect of the implementation described above is to provide fast startup of multiple power converter ICs connected in parallel to a common output, wherein each of the multiple power converter ICs: sets a first indication signal (CGOOD) to a first state (e.g., low) to indicate that the charge balancing of the power converter IC has not been completed; balances the charge on at least one flying capacitor connected to the power converter IC; sets the first indication signal to a second state (e.g., high) to indicate that the charge balancing of the power converter IC has been completed; and waits to receive the first indication signal in the second state from all other power converter ICs, and then performs a soft startup of the power converter IC.

[0085] A power converter system includes a plurality of power converter integrated circuits (ICs) having reduced gate drive (RGD) capability connected in parallel to a common output terminal, wherein each of the plurality of power converters is configured to: a. Set the first indication signal to a first state to indicate that the charge balance of the power converter has not been completed; b. Balance the charge on at least one flying capacitor connected to the power converter; c. Set the first indication signal to the second state to indicate that the charge balance of the power converter has been completed; and d. Wait for the first indication signal to be in the second state to be received from all other power converters, and then perform a soft start of the power converter. By reusing the functionality of existing pins of the power converter IC and using the techniques described above to enable fast startup of the parallel power converter IC, it can be combined with the phase-cutting, reduced-gate-drive LDO implementation described above. This combination will improve efficiency and reduce power consumption by allowing both fast startup and phase cutting in the parallel power converter IC group.

[0086] Circuit Implementation

[0087] The circuits and devices according to the invention can be used alone or in combination with other components, circuits, and devices. Embodiments of the invention can be manufactured as integrated circuits (ICs), which can be encapsulated in IC packages and / or modules for ease of handling, manufacturing, and / or performance improvement. In particular, IC embodiments of the invention are typically used in modules in which one or more such ICs are combined with other circuit components or circuits (e.g., filters, amplifiers, passive components, and possible additional ICs) in a single package. Then, typically, the ICs and / or modules are often combined with other components on a printed circuit board to form part of an end product such as a cellular phone, laptop computer, or tablet computer, or to form a higher-level module that can be used in a wide variety of products such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and components, such ICs typically implement a communication mode, typically wireless communication.

[0088] As an example of further integration of the present invention with other components, Figure 10This is a top plan view of a substrate 1000, which may be, for example, a printed circuit board or a chip module substrate (e.g., a thin-film block). In the illustrated example, substrate 1000 includes a plurality of ICs 1002a to ICs 1002d having terminal pads 1004 interconnected via traces and / or conductive vias on and / or within substrate 1000 or on opposite (back) surfaces of substrate 1000 (surface conductive traces are not shown to avoid confusion, and not all terminal pads are labeled). ICs 1002a to ICs 1002d may contain, for example, signal switches, active filters, amplifiers (including one or more LNAs), and other circuitry. For example, IC 1002b may contain similar... Figure 2 , Figure 3 , Figure 5 and Figure 7 The circuit shown represents one or more instances of a power converter.

[0089] The substrate 1000 may also include one or more passive devices 1006 embedded in, formed on, and / or attached to the substrate 1000. Although shown as a general rectangle, the passive device 1006 may be, for example, a filter, capacitor, inductor, transmission line, resistor, planar antenna element, transducer (including, for example, MEMS-based transducers such as accelerometers, gyroscopes, microphones, pressure sensors, etc.), battery, etc., which are interconnected with other passive devices 1006 and / or individual ICs 1002a to IC1002d via conductive traces on or in the substrate 1000. The front or back surface of the substrate 1000 may be used as a location for forming other structures.

[0090] System aspects

[0091] The present invention improves system architecture by allowing one or more power converter ICs to be turned off to increase efficiency under light loads. The improved power converter efficiency may result in lower power consumption and longer battery life.

[0092] Note that not all power converter ICs need to have RGD capability. For example, in the case of two power converter ICs coupled in parallel, only one power converter IC may have RGD capability to allow phase switching of that unit (allowing the non-RGD power converter IC to operate in the on or off state). As another example, the primary (always on) power converter IC does not need RGD capability.

[0093] Embodiments of the present invention are useful in a variety of large radio frequency (RF) circuits and systems for performing a range of functions, including (but not limited to) impedance matching circuits, RF power amplifiers, RF low-noise amplifiers (LNAs), phase shifters, attenuators, antenna beam control systems, charge pump devices, RF switches, etc. Such functionality is useful in a variety of applications such as radar systems (including phased array and automotive radar systems), radio systems (including cellular radio systems), and test equipment.

[0094] Radio system applications include wireless RF systems (including base stations, relay stations, and handheld transceivers) using a variety of technologies and protocols, including various types of Orthogonal Frequency Division Multiplexing (“OFDM”), Orthogonal Amplitude Modulation (“QAM”), Code Division Multiple Access (“CDMA”), Time Division Multiple Access (“TDMA”), Wideband Code Division Multiple Access (“W-CDMA”), Global System for Mobile Communications (“GSM”), Long Term Evolution (“LTE”), 5G, 6G, and WiFi (e.g., 802.11a, b, g, ac, ax, be) protocols, as well as other radio communication standards and protocols.

[0095] Manufacturing technology and options

[0096] As used in this disclosure, the term "MOSFET" includes any field-effect transistor (FET) having an insulated gate with conductivity of its voltage-determining transistor, and includes an insulated gate having a metallic or metalloid, insulator, and / or semiconductor structure. The terms "metal" or "metalloid" include at least one conductive material (such as aluminum, copper, or other metals, or highly doped polycrystalline silicon, graphene, or other electrical conductors), "insulator" includes at least one insulating material (such as silicon oxide or other dielectric materials), and "semiconductor" includes at least one semiconductor material.

[0097] As used in this disclosure, the term "radio frequency" (RF) refers to an oscillation rate in the range of approximately 3 kHz to approximately 300 GHz. The term also includes frequencies used in wireless communication systems. RF frequencies can be the frequencies of electromagnetic waves or the frequencies of alternating voltage or current in a circuit.

[0098] Regarding the accompanying drawings mentioned in this disclosure, the dimensions of various elements are not drawn to scale; for clarity or emphasis, some dimensions may be significantly enlarged vertically and / or horizontally. Furthermore, references to orientation and direction (e.g., “top,” “bottom,” “above,” “below,” “lateral,” “vertical,” “horizontal,” etc.) are relative to the example drawings and are not necessarily absolute orientations or directions.

[0099] Various embodiments of the present invention can be implemented to meet a wide range of specifications. Unless otherwise stated above, the selection of suitable component values ​​is a matter of design choice. Various embodiments of the present invention can be implemented using any suitable integrated circuit (IC) technology (including, but not limited to, MOSFET structures), or in hybrid or discrete circuit form. Integrated circuit embodiments can be fabricated using any suitable substrate and process, including but not limited to standard bulk silicon, high resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise stated above, embodiments of the present invention can be implemented using other transistor technologies (such as bipolar junction transistors (BJTs), BiCMOS, LDMOS, BCD, GaAs HBTs, GaN HEMTs, GaAs pHEMTs, MESFETs, InP HBTs, InP HEMTs, FinFETs, GAAFETs, and SiC-based power device technologies) using 2D, 2.5D, and 3D structures. However, embodiments of the present invention are particularly useful when fabricated using SOI- or SOS-based processes or when fabricated using processes with similar characteristics. Fabrication using SOI or SOS processes in CMOS enables circuits to have low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high-frequency operation (i.e., up to and exceeding 300 GHz RF). Monolithic IC implementations are particularly useful because, through careful design, parasitic capacitances can typically be kept low (or at least consistent across all cells, allowing them to be compensated).

[0100] Depending on specific specifications and / or implementation technology (e.g., NMOS, PMOS, or CMOS, and enhancement-mode or depletion-mode transistor devices), voltage levels and / or voltage and / or logic signal polarities can be adjusted. The voltage, current, and power handling capabilities of components can be adjusted as needed, for example, by adjusting device size, "stacking" components (especially FETs) in series to handle higher voltages, and / or using multiple components in parallel to handle higher currents. Additional circuit components can be added to enhance the capabilities of the disclosed circuit and / or to provide additional functionality without significantly altering its function.

[0101] in conclusion

[0102] Several embodiments of the present invention have been described. It should be understood that various modifications can be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be sequentially independent and therefore may be performed in a different order than that described. Furthermore, some of the steps described above may be optional. The various activities described with respect to the methods identified above may be performed in a repetitive, serial, and / or parallel manner.

[0103] It should be understood that the foregoing description is intended to illustrate, not limit, the scope of the invention, which is defined by the scope of the appended claims, and other embodiments are within the scope of the claims. In particular, the scope of the invention includes any and all possible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the appended claims. (Note that the bracket markings of the claim elements are for the convenience of referencing such elements and do not in themselves indicate a particular desired order or enumeration of elements; furthermore, such markings may be repeated in dependent claims as references to additional elements, but are not considered as a sequence of markings that initiates conflict.)

Claims

1. A method for coupling the output of a first power converter to the output of at least a second power converter, comprising: (a) Enable the reduced gate drive (RGD) capability of the first power converter to limit the current through the output of the first power converter to one or more levels and for a sufficient time to balance the charge of at least one flying capacitor connected to the first power converter. as well as (b) Couple the output of the second power converter that is coupled to the output of the first power converter.

2. The method according to claim 1, further comprising: If the output voltage of the first power converter is greater than the threshold voltage, then the RGD capability of the first power converter is disabled.

3. The method according to claim 1, further comprising: If the voltage of the at least one flying capacitor is close to the target voltage, the RGD capability of the first power converter is disabled.

4. The method according to claim 1, further comprising: If the output voltage of the first power converter is not greater than the threshold voltage, then the power good signal line of the first power converter is set to the first state.

5. The method according to claim 1, further comprising: If a fault event occurs that affects the first power converter, the RGD capability of the first power converter is enabled.

6. The method according to claim 1, further comprising: During the dynamic reconfiguration of the conversion ratio of the power converter, the RGD capability of the first power converter is enabled.

7. The method according to claim 1, further comprising: The RGD capability of the first power converter is enabled when the charge on at least one flying capacitor connected to the first power converter is rebalanced.

8. The method according to claim 1, wherein, After the charge on the at least one flying capacitor exceeds a specified threshold, the output of the second power converter is coupled to the output of the first power converter.

9. A method of applying the output of a first power converter having reduced gate drive (RGD) capability to the output of at least a second power converter, comprising: (a) Enable and initialize the first power converter; (b) Comparing a voltage indicating the output voltage of the first power converter with a first threshold voltage to determine whether the first power converter is in an independent or parallel configuration; and (c) If the voltage indicating the output voltage of the first power converter is greater than the first threshold voltage, then: (1) Start the first power converter in parallel configuration; (2) Enable the RGD capability of the first power converter to limit the current through the output of the first power converter to a first level and for a sufficient time to balance the charge of at least one flying capacitor connected to the first power converter. as well as (3) If the output voltage of the first power converter is greater than the second threshold voltage, the RGD capability of the first power converter is disabled.

10. The method of claim 9, further comprising: If the output voltage of the first power converter is not greater than the second threshold voltage, then the power good signal line of the first power converter is set to the first state.

11. The method of claim 9, further comprising: If a fault event occurs that affects the first power converter, the RGD capability of the first power converter is reactivated.

12. The method according to claim 9, further comprising: During the dynamic reconfiguration of the conversion ratio of the power converter, the RGD capability of the first power converter is re-enabled.

13. The method of claim 9, further comprising: The RGD capability of the first power converter is reactivated when the charge on at least one flying capacitor connected to the first power converter is rebalanced.

14. A method for operating a first power converter having reduced gate drive (RGD) capability in one of an independent configuration or a parallel configuration, wherein, The output of the first power converter is applied to the output of at least the second power converter, the method comprising: (a) Enable and initialize the first power converter; (b) Compare a voltage indicating the output voltage of the first power converter with a first threshold voltage to determine whether the first power converter is in an independent configuration or a parallel configuration; (c) If the voltage indicating the output voltage of the first power converter is less than the first threshold voltage, then: (1) Set the power good signal line of the first power converter to the first state; (2) Start the first power converter in a non-parallel configuration; (3) Enable the RGD capability of the first power converter to limit the current through the output of the first power converter to a first level and for a sufficient time to balance the charge of at least one flying capacitor connected to the first power converter; (4) If the output voltage of the first power converter is greater than the second threshold voltage, then the power good signal line of the first power converter is set to the second state, and the RGD capability of the first power converter is disabled; and (5) If the output voltage of the first power converter is not greater than the second threshold voltage, then the power good signal line of the first power converter is maintained in the first state; and (d) If the output voltage of the first power converter is not less than the first threshold voltage, then: (1) Start the first power converter in parallel configuration; (2) Enable the RGD capability of the first power converter to limit the current through the output of the first power converter to a second level and for a sufficient time to balance the charge of at least one flying capacitor connected to the first power converter; (3) If the output voltage of the first power converter is greater than the second threshold voltage, then the RGD capability of the first power converter is disabled; and (4) If the output voltage of the first power converter is not greater than the second threshold voltage, then the power good signal line of the first power converter is set to the first state.

15. The method of claim 14, further comprising: If a fault event occurs that affects the first power converter, the RGD capability of the first power converter is reactivated.

16. The method of claim 14, further comprising: During the dynamic reconfiguration of the conversion ratio of the power converter, the RGD capability of the first power converter is re-enabled.

17. The method of claim 14, further comprising: The RGD capability of the first power converter is reactivated when the charge on at least one flying capacitor connected to the first power converter is rebalanced.

18. A power converter system, comprising: (a) A first power converter having reduced gate drive (RGD) capability and an output terminal; as well as (b) At least one second power converter having an output terminal coupled to the output terminal of the first power converter; During the transition from an off state to an on state, the RGD capability of the first power converter is activated to limit the current through the output of the first power converter to a first level for a sufficient time to balance the charge of at least one flying capacitor connected to the first power converter; and Specifically, if the voltage indicating the output voltage of the first power converter is greater than a threshold voltage, the RGD capability of the first power converter is disabled.

19. The invention according to claim 18, wherein, The first power converter includes a power good signal line, wherein the power good signal line is set to a first state if a voltage indicating the output voltage of the first power converter is not greater than the threshold voltage.

20. The invention according to claim 18, wherein, If a fault event occurs that affects the first power converter, the RGD capability of the first power converter is reactivated.

21. The invention according to claim 18, wherein, During the dynamic reconfiguration of the conversion ratio of the first power converter, the RGD capability of the first power converter is re-enabled.

22. The invention according to claim 18, wherein, The RGD capability of the first power converter is reactivated when the charge on at least one flying capacitor connected to the first power converter is rebalanced.

23. A power converter system, comprising: (a) A first power converter having reduced gate drive (RGD) capability and an output terminal; as well as (b) At least one second power converter having an output terminal coupled to the output terminal of the first power converter; Wherein, if the first power converter is enabled and initialized, the first power converter is configured to: compare a voltage indicating the output voltage of the first power converter with a first threshold voltage to determine whether the first power converter is in an independent configuration or a parallel configuration; Wherein, if the voltage indicating the output voltage of the first power converter is greater than the first threshold voltage, the RGD capability of the first power converter is activated to limit the current through the output terminal of the first power converter to a first level for a sufficient time to balance the charge of at least one flying capacitor connected to the first power converter; and If the output voltage of the first power converter is greater than the second threshold voltage, then the RGD capability of the first power converter is disabled.

24. The invention according to claim 23, wherein, The first power converter includes a power good signal line, and wherein the power good signal line is set to a first state if the output voltage of the first power converter is not greater than the second threshold voltage.

25. The invention according to claim 23, wherein, If a fault event occurs that affects the first power converter, the RGD capability of the first power converter is enabled.

26. The invention according to claim 23, wherein, During the dynamic reconfiguration of the conversion ratio of the first power converter, the RGD capability of the first power converter is enabled.

27. The invention according to claim 23, wherein, The RGD capability of the first power converter is enabled when the charge on at least one flying capacitor connected to the first power converter is rebalanced.

28. A method for initiating multiple power converters connected in parallel to a common output terminal, comprising: For each of the plurality of power converters (a) If both the first indication signal and the second indication signal are in the first state, then the first indication signal is set to the second state to indicate that the charge balance of the power converter has not been completed; (b) If neither the first indication signal nor the second indication signal is in the first state, the second indication signal is set to the second state to indicate that the power converter is not ready to enter full-power operation mode and that the charge balance of the power converter has not been completed; (c) Balancing the charge on at least one flying capacitor connected to the power converter; (d) Set the first indication signal to the first state to indicate that the charge balance of the power converter has been completed; (e) Wait for a first indication signal to be received from all other power converters in the first state, and then perform a soft start on the power converter; as well as (f) If the second indication signal is in the second state, then the second indication signal is set to the second state to indicate that the soft start of the power converter has been completed.

29. A method for initiating multiple power converters connected in parallel to a common output terminal, comprising: For each of the plurality of power converters (a) If both the first indication signal and the second indication signal are in the first state, then the first indication signal is set to the second state to indicate that the charge balance of the power converter has not been completed; (b) If neither the first indication signal nor the second indication signal is in the first state, the second indication signal is set to the second state to indicate that the power converter is not ready to enter full-power operation mode and that the charge balance of the power converter has not been completed; (c) Balancing the charge on at least one flying capacitor connected to the power converter; (d) Set the first indication signal to the first state to indicate that the charge balance of the power converter has been completed; (e) Determine whether the first indication signal is in the first state and whether the timeout period has expired; (f) If the first indication signal is not in the first state or if the timeout period has not expired, then the timeout period is restarted and steps (a) to (e) are repeated. (g) If the first indication signal is in the first state and if the timeout period has expired, then perform a soft start of the power converter; (h) If the second indication signal is in the second state, then the second indication signal is set to the first state to indicate that the soft start of the power converter has been completed; (i) Determine whether the second indication signal is in the first state; (j) If the second indication signal is not in the first state, then the timeout period is restarted and steps (a) through (i) are repeated; and (k) If the second indication signal is in the first state, then proceed to the full power operation mode.

30. A power converter system comprising a plurality of power converter integrated circuits (ICs) having reduced gate drive (RGD) capability connected in parallel to a common output terminal, wherein, Each of the multiple power converters is configured to: (a) Set the first indication signal to a first state to indicate that the charge balance of the power converter has not been completed; (b) Balancing the charge on at least one flying capacitor connected to the power converter; (c) Set the first indication signal to a second state to indicate that the charge balance of the power converter has been completed; as well as (d) Wait for a first indication signal to be in the second state to be received from all other power converters, and then perform a soft start of the power converter.

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