Method of forming functional substrate foil and method of forming functional substrate

Abstract

The present disclosure provides, in various illustrative embodiments, a method of forming a functional substrate foil (1), the method comprising: providing a first substrate foil (2) having a plurality of active device regions (2a); arranging a microchip (4) on the first substrate foil (2) in the active device region (2a); and bonding the second substrate foil (5) to the first substrate foil (2) in such a way that the microchip (4) is interposed between the first substrate foil (2) and the second substrate foil (5), such that a functional substrate foil (1) is formed.

Description

Technical Field

[0001] This invention relates to a method for forming a functional substrate foil, and more particularly to a functional substrate foil from which multiple flexible substrates with integrated microchips can be obtained, such as silicon-based chip-in-foil systems or custom chip-in-foil systems for manufacturing flexible smart devices and components. Furthermore, this invention relates to a method for forming a functional substrate from said functional substrate foil. Background Technology

[0002] Beyond the various medical applications that enable optimized healthcare and examinations through flexible microelectronic devices, current developments across a wide range of electronic devices are increasingly based on thin-film technologies, such as foldable smartphones, smartwatches, and OLED TVs. Typically, thin-film technologies utilize flexible circuits that can be provided in virtually any desired shape. Furthermore, the rise of thin-film technology is far from over, as the ultra-thin coating on thin-film circuit boards allows for the production of higher-density circuitry and smaller, lighter packages. This is because the technology appears to offer a method for producing flexible printed circuit boards (PCBs) with reduced thickness, while exhibiting higher performance and dynamic capabilities than known rigid or thick-film circuit counterparts.

[0003] Flexible film PCBs have similar functionality to rigid PCBs, but can be bent and folded into any desired shape, allowing designers to use flexible film PCBs in devices that need to be moved or folded during use.

[0004] In its early days, flexible PCB technology was primarily used in the aerospace and military industries. However, currently, thin-film technology is used in a wide range of fields, including computers, automobiles, and industry. Most modern communication devices, such as smartphones, tablets, and smartwatches, have incorporated thin-film technology into flexible PCBs. The flexibility of thin-film PCBs allows for dynamic movement in flip phones and wearable devices, including those commonly used in biomedical applications.

[0005] While flexible circuits offer significant reductions in space, weight, and wiring errors compared to their rigid counterparts, thin-film PCBs come with higher design and manufacturing costs. Another drawback of flexible PCBs is their difficulty in repairing or modifying, partly due to the subsequent removal and replacement of the protective film, which adds to the complexity and cost of thin-film PCBs. Furthermore, thin-film PCBs can be easily cracked or damaged if not handled or stored properly. Additionally, compared to rigid circuit boards and thick-film substrates, thin-film technology and its PCBs require higher costs due to the highly specialized design and manufacturing processes. Summary of the Invention

[0006] In one aspect of this disclosure, a method for forming a functional substrate foil at least partially solves the above and other objectives, which can provide a substrate for a functional substrate to be used in flexible thin-film applications. In particular, the functional substrate foil obtained by the method of this aspect of the disclosure can provide multiple functional substrates that can be directly used as functional substrates of the flexible thin-film printed circuit board (PCB) type.

[0007] In the illustrative embodiments described herein, the method includes providing a first substrate foil having a plurality of active device regions, disposing a microchip on the first substrate foil in the active device regions, and bonding a second substrate foil to the first substrate foil in such a manner that the microchip is inserted between the first and second substrate foils, thereby forming a functional substrate foil. Thus, a process for mass production of a functional substrate foil having a plurality of active device regions equipped with one or more microchips can be readily provided at an advantageous cost-effectiveness. A functional substrate foil with integrated microchips can be fabricated without using complex and cost-effective thin-film technologies. Herein, the functional substrate foil comprises a plurality of functional substrates corresponding to the plurality of active regions, which are obtained after separating the active regions into separate active regions.

[0008] In a first illustrative embodiment, at least one of the first substrate foil and the second substrate foil can be wound onto a dedicated spool, such that at least one of the first substrate spool and the second substrate spool is supplied. Therefore, a low-cost, high-capacity process can be provided by supplying at least one of the first substrate foil and the second substrate foil using a dedicated spool or roller.

[0009] In a second illustrative embodiment, the method may further include collecting the functional substrate foil by winding it onto a spool. Thus, a roll-to-roll process can be implemented.

[0010] In this aspect of the disclosure, roll-to-roll or R2R or roller-to-roll processes should be understood as manufacturing processes used in processing that embed, coat, print, and laminate variable applications onto a flexible roll-pressed substrate material (e.g., a first substrate foil) as material is continuously fed from one roll or roller to another. Roll-to-roll technology typically consists of several rolls or rollers, known as a web path, which wind and pass the supplied substrate material around these rolls or rollers during multiple operations. As the first substrate foil moves along the web path, the technology applies additive or subtractive materials and / or devices to the first substrate foil to produce or manufacture products or parts with functional substrate foils, such as those described in this aspect. Roll-to-roll processing, or R2R, is also known as web processing or roll-to-roll processing. In particular, the first substrate foil and the second substrate foil can represent webs unwound from a dedicated reel or roll and conveyed along a web path to one or more processing stations, wherein the first substrate foil and the second substrate foil undergo, individually or together, one or more processes described in more detail below with respect to this aspect of the disclosure. Therefore, R2R processing allows for continuous production at high speeds without the start-stop issues associated with sheet processing, which is the opposite of R2R. Furthermore, the R2R process allows for the efficient and cost-effective mass production of rolls or reels of functional substrate foils with high productivity.

[0011] In a third illustrative embodiment, the method may further include separating a functional substrate foil into a plurality of functional substrates, such that each of the plurality of functional substrates includes one or more microchips inserted between a first substrate provided after separating the first substrate foil and a second substrate provided after separating the second substrate foil. For example, each functional substrate may have an active region equipped with one or more microchips disposed on the first substrate within the active region of the functional substrate. Thus, a large number of functional substrates can be obtained at low cost and in high yield.

[0012] In a fourth illustrative embodiment, when the second substrate foil is bonded to the first substrate foil, the second substrate foil may have a repeating second substrate wiring pattern formed on the microchip-facing surface of the second substrate foil. In this case, bonding the second substrate foil to the first substrate foil may include aligning the second substrate foil relative to the microchip, such that one or more microchips are aligned relative to the second substrate wiring pattern. Therefore, chip contact via the repeating second substrate wiring can be achieved easily and cost-effectively, and the second substrate foil provides a desired wiring pattern corresponding to the desired function of the active region of the functional substrate foil.

[0013] In a fifth illustrative embodiment, the first substrate foil may have a repeating first substrate wiring pattern formed on the surface of the first substrate foil, and each of the plurality of active device regions may have a dedicated first substrate wiring pattern formed therein. Therefore, chip contact via the repeating first substrate wiring pattern can be achieved easily and cost-effectively, with the first substrate foil providing a desired wiring pattern corresponding to the desired function of the active regions of the functional substrate foil.

[0014] In some illustrative examples of the fifth illustrative embodiment, the microchip may be disposed on a first substrate foil aligned with a first substrate wiring pattern in each active device region. Hereinafter, the microchip has contact pads formed on a surface of the microchip opposite to the first substrate foil. For example, a repeating first substrate wiring pattern may be formed on a first surface of the first substrate foil, opposite to a second surface of the first substrate foil on which the microchip is disposed. Thus, the repeating wiring pattern can provide communication with the microchip.

[0015] In some illustrative combinations of the fourth and fifth illustrative embodiments, the method may further include supplying a second substrate foil such that a repeating second substrate wiring pattern is aligned relative to the contact pads of the microchip, such that when the second substrate foil is bonded to the first substrate foil, at least a subset of the contact pads makes electrical contact with the second substrate wiring pattern. Thus, reliable contact between the microchip and the first substrate can be achieved.

[0016] In some other illustrative combinations of the fourth and fifth illustrative embodiments, the method may further include supplying a second substrate foil such that a repeating second substrate wiring pattern is aligned with the contact pads of the microchip. When the second substrate foil is bonded to the first substrate foil, the repeating second substrate wiring pattern may be formed on a first surface of the second substrate foil opposite to the second surface of the second substrate foil facing the microchip.

[0017] In some illustrative examples of these other illustrative combinations, the method may further include forming a second substrate pass-through that extends only fully through the second substrate foil, aligned with the contact pads and the repeating second substrate wiring pattern, such that at least a subset of the contact pads are electrically contacted with the second substrate wiring pattern through the second substrate pass-through. Thus, the repeating second substrate wiring pattern can provide communication with the microchip.

[0018] In some illustrative examples of the above-described illustrative combinations, the method may further include forming at least one conductive portion that extends completely through at least one of the first and second substrate foils. Each conductive portion can electrically connect a repeating second substrate wiring pattern to a repeating first substrate wiring pattern. Thus, the repeating wiring pattern can provide communication with the microchip.

[0019] In some illustrative embodiments representing alternatives to the fifth illustrative embodiment, the microchip may have contact pads formed thereon, and the microchip may be bonded to a first substrate foil according to a flip-chip process. Hereinafter, a flip-chip process is used to mount the microchip to the first substrate foil, aligning it with a first substrate wiring pattern providing circuitry (relative to external circuitry of the microprocessor), on which the microchip with contact pads formed (i.e., the contact pads are disposed on an initial first side of the microchip) is flipped such that the contact pads face the first substrate foil (and the microchip is configured such that their downward-facing initial first side on the first substrate foil now represents a second side opposite to the initial first side). When the microchip is disposed on the first substrate foil in this manner, the contact pads (now facing the first substrate foil) are aligned such that the contact pads are aligned with matching pads of the first substrate wiring pattern.

[0020] In some illustrative examples of the above alternatives, a repeating first substrate wiring pattern may be formed on a first surface of a first substrate foil on which a microchip is disposed, and the microchip may have contact pads formed on a surface of the microchip facing the first surface of the first substrate foil. Furthermore, disposing of the microchip on the first substrate foil may include aligning the microchip relative to the repeating first substrate wiring pattern such that at least a subset of the contact pads are in electrical contact with the repeating first substrate wiring pattern.

[0021] In some illustrative examples of the fifth embodiment, the method may further include forming a conductive adhesive on at least a subset of the contact pads of the microchip prior to bonding. Thus, easy bonding of the microchip to a dedicated wiring pattern is achieved.

[0022] In a sixth illustrative embodiment, bonding the second substrate foil to the first substrate foil may include depositing an adhesive layer on the first substrate foil after the microchip is disposed on the first substrate foil. Therefore, lamination of the first and second substrate foils can be readily achieved.

[0023] In the seventh illustrative embodiment, at least one microchip may be an ASIC chip. Therefore, a fully functional substrate foil is provided, wherein each functional substrate with an ASIC (application-specific integrated circuit) chip provided by the functional substrate foil is highly functional to provide local data processing at each functional substrate with the ASIC chip. Hereinafter, an ASIC chip (also referred to as a CSP (customer-specific product) chip) is a chip with an integrated custom IC designed, planned, developed, and used for a specific purpose, its task being optimized, efficient, and possessing all the necessary functions and features to be used in a particular application. For example, when using an ASIC chip configured to process sensor signals output by a sensor device coupled to the ASIC chip, the sensor device may also be integrated into the functional substrate in addition to the ASIC chip (i.e., another chip integrated into the functional substrate in addition to the ASIC chip implements the electronic or electromechanical sensor device). Thus, direct processing of these sensor signals is achieved at the functional substrate where these sensor signals are generated, and the complexity of the system employing such a sensor device is reduced, for example, by reducing the number of physical interconnections required in the system employing such a sensor device.

[0024] In the eighth illustrative embodiment, the microchip may have a thickness of less than 50 μm. For example, the thickness of the microchip may be less than 40 μm or less than 30 μm, for example, it may be in the range from about 20 μm to about 30 μm. In some illustrative examples herein, the microchip may be thinned to have the thickness described according to the eighth illustrative embodiment, for example, by grinding a pre-provided microchip to the desired thickness. Thus, a thin and flexible functional substrate foil is provided.

[0025] In the ninth illustrative embodiment, at least one of the first substrate foil and the second substrate foil is made of a thermoplastic material. In some illustrative examples herein, the thermoplastic material may be a material prepared from at least one of polyimide (PI), polyethylene terephthalate (PET), polyvinyl chloride (PVC), and FR-4, wherein FR-4 is a composite material composed of woven fiberglass cloth and an epoxy resin binder, and has flame retardancy (self-extinguishing) properties. Thus, easy and cost-effective manufacturing of the functional substrate foil is achieved.

[0026] In some of the illustrative embodiments described above, repeating wiring patterns can be provided on the first substrate foil and / or the second substrate foil. For example, the first substrate foil and / or the second substrate foil can be provided with repeating wiring patterns by felting conductive material onto at least one surface of the substrate foil (first substrate foil and / or second substrate foil), and then patterning the deposited conductive material, for example, by etching, laser patterning, etc., to produce the desired wiring pattern. In laser patterning, for example, segments of the conductive layer are removed to produce a wiring pattern for circuitry on the substrate foil. Compared to photolithography, laser patterning allows for greater flexibility in customization for specific applications and reduces the need for consumable materials during circuit board manufacturing processes. Preventing damage to the substrate is a challenge in laser patterning, but the risk can be mitigated by using methods such as front and back side processing.

[0027] Alternatively, the conductive material can be printed onto at least one surface of the substrate foil (first substrate foil and / or second substrate foil) in the form of a desired wiring pattern. For example, the conductive material can be at least one of aluminum, silver, gold, copper, indium tin oxide, and carbon, while the substrate material used to provide the substrate foil (first substrate foil and / or second substrate foil) can include at least one of quartz, glass, ceramic, organic materials, PI, PET, PEEK, and FR-4. In an illustrative example where the substrate foil (first substrate foil and / or second substrate foil) is provided as a web of rolls or rollers, the material of the first substrate foil can include a thermoplastic material, such as, but not limited to, at least one of PI, PET, PEEK, and FR-4.

[0028] In some illustrative examples, wiring patterns formed on a first substrate made of PI and / or FR-4 may be formed of copper and / or gold, while wiring patterns formed on a first substrate made of PET and / or PVC may be formed of aluminum and / or copper.

[0029] In some illustrative examples, such as the functional substrate foil used in flexible printed circuit boards (PCBs), a functional substrate foil may contain at least a single layer of copper, where it should be understood that additional layers can be used to enhance functionality. For example, multilayer PCBs may use through-holes to have connections between the various layers, thereby allowing multiple available coatings.

[0030] In some illustrative embodiments of this disclosure, a functional substrate foil can be used as a substrate in the process of realizing a PCB type known as a “rigid-flexible” PCB, combining flexible and non-flexible circuitry to create hybrid design solutions.

[0031] In some of the illustrative embodiments described above, the alignment of the microchip relative to the substrate foil can be achieved by optical and / or mechanical alignment devices. For example, the first and second substrate foils can be equipped with adjustment holes formed in the first and second substrate foils with a predetermined geometric relationship relative to the occupied areas of one or more microchips to be configured in a dedicated active region. Furthermore, optical devices such as cameras can be provided for optical control and / or evaluation of the microchip's configuration relative to the first and second substrate foils. Additionally or alternatively, an adjustment device including one or more adjustment pins can be provided, which engage with the adjustment holes to ensure the correct position and orientation of the first and second substrate foils.

[0032] For example, when the first substrate foil and / or the second substrate foil are unwound or rewound from a dedicated spool, the adjustment device can move along the unwound or rewound direction of the dedicated spool and parallel to the unwound or rewound substrate foil until the microchip is properly aligned with the first substrate foil or the second substrate foil is properly aligned with the first substrate foil and bonded to the first substrate foil.

[0033] In another aspect of this disclosure, a method for forming a functional substrate is provided. In an illustrative embodiment herein, the method includes providing a functional substrate foil formed according to the method of an aspect of this disclosure as described above, and separating at least one functional substrate from the functional substrate foil. Therefore, electronic devices based on such flexible substrates can be readily provided with high yield, high production capacity, and low manufacturing costs. For example, in addition to a variety of medical applications in which flexible microelectronic devices support optimized medical care and examinations, electronic devices formed based on at least one functional substrate obtained in this aspect can be, but are not limited to, foldable smartphones, smartwatches, and OLED TVs. In the field of medical applications, the functional substrate can be used for smart patches and catheter applications.

[0034] In some non-limiting but illustrative examples of these applications, flexible electronic devices with integrated sensors can be provided based on at least one functional substrate having at least one microchip and including at least one sensor device integrated into or coupled to the functional substrate in subsequent processing. In this document, such flexible electronic devices can be configured to detect minute physiological signals and can be used to monitor human health. For example, a patch sensor integrated into or coupled to at least one functional substrate can be used to detect blood glucose concentration, wherein such a patch sensor can be embodied in two ways: as a flexible paper battery patch and a biosensor patch. The paper battery patch can disrupt the balance of tissue fluid in the body through electrochemical dual channels, promoting the recollection of arterial glucose and the permeation of glucose into the skin surface. Such a biosensor patch can be used to detect blood glucose concentration induced by the paper battery patch, and this design can use dual electrodes to ensure the accuracy of detecting low blood glucose concentrations. For example, additionally or alternatively, a temperature sensor element can be integrated into or coupled to the functional substrate, enabling immediate acquisition and evaluation of local temperature measurements. As an example of flexible electronic devices with functional substrates and temperature sensing capabilities, inflammation caused by prolonged exercise or physical activity can be detected to prevent potential damage to joints such as the wrists and knees. For instance, wearable flexible temperature sensors can determine the presence of inflammation by monitoring changes in body temperature at the joints in real time. Temperature sensors integrated onto programmable functional substrates can provide stable measurements of body temperature at desired body parts, such as joints. Temperature changes measured by the sensor in a static state can be expected to be small (0.01°C to 0.07°C), and even during cyclical movement, the measured temperature changes can still be less than 0.1°C. However, temperature changes greater than 1°C may indicate joint damage or inflammation.

[0035] In other applications, monitoring the electrical potential on the surface of the human heart may be important in the treatment of diseases. Signal acquisition on the human heart may depend on the tight connections between the sensor and tissue cells, making it impossible for conventional rigid detectors to detect potentials within the heart. However, a multifunctional balloon catheter system with a serpentine interconnect structure can be provided based on functional substrates, where contact sensors and multiple electrodes can be integrated into one or more functional substrates. Therefore, high electrode density can be achieved on such a balloon catheter system, ensuring complete signal acquisition from the entire heart, enabling monitoring of cardiac activity with minimal harm to the person being monitored.

[0036] In some illustrative embodiments herein, at least one functional substrate can be removed from a functional substrate foil by at least one of cutting and stamping a portion of a functional substrate foil including an active region having at least one microchip.

[0037] In some specific illustrative but non-limiting examples of the various embodiments described above, a first substrate foil may be provided by a base substrate foil, and a second substrate foil may be provided by a top substrate foil, wherein the top substrate foil is supplied during the method of forming the functional substrate foil such that the top substrate foil is positioned above the base substrate foil when the microchip is inserted between the base substrate foil and the top substrate foil. Therefore, the base substrate foil can be considered to represent a foil for providing a base substrate in an active region on which the microchip is mounted before being inserted between the base substrate foil and the top substrate foil. In this document, the first substrate reel can be considered to be a base substrate reel, and the second substrate reel can be considered to be a top substrate reel, and after the functional substrate foil is separated into functional substrates, each functional substrate includes a base substrate and a top substrate.

[0038] Furthermore, a repeating first substrate wiring pattern can be considered to represent a repeating base substrate wiring pattern, and a repeating second substrate wiring pattern can be considered to represent a repeating top substrate wiring pattern. In some examples herein, a repeating base substrate wiring pattern formed on a first surface of a first substrate foil opposite to a second surface on which a microchip is disposed can represent a repeating base substrate wiring pattern formed on a lower surface of a base substrate foil opposite to an upper surface on which a microchip is disposed.

[0039] In some illustrative combinations of the fourth and fifth illustrative embodiments described above, the top substrate foil may be supplied such that a repeating top substrate wiring pattern is aligned relative to the contact pads of the microchip, and when the top substrate foil is bonded to the base substrate foil, the repeating top substrate wiring pattern is formed on the upper surface of the top substrate foil (representing the first surface of the second substrate foil as described above), which is opposite to the lower surface of the top substrate foil facing the microchip (representing the second surface of the second substrate foil as described above).

[0040] According to some illustrative examples herein, the first substrate pass-through as described above represents a top substrate pass-through that extends fully through the top substrate foil in alignment with only the contact pads and the repeating top substrate wiring pattern, so that at least a subset of the contact pads are electrically contacted with the top substrate wiring pattern through the top substrate pass-through.

[0041] In the case of flip-chip technology, a microchip can have contact pads formed thereon, and the microchip can be bonded to a base substrate foil. In this paper, the flip-chip process is used to mount a microchip onto a base substrate foil aligned with a base substrate wiring pattern providing circuitry (representing circuitry external to a microprocessor), on which contact pads are formed (i.e., the contact pads are located on the top side of the microchip). The microchip is flipped such that the contact pads face the base substrate foil (and the microchip is configured such that its top side faces downwards on the base substrate foil). When the microchip is positioned on the base substrate foil in this manner, the contact pads (now facing the base substrate foil) are aligned such that the contact pads are aligned with matching pads of the base substrate wiring pattern.

[0042] In some of the illustrative examples described above, a repeating base substrate wiring pattern may be formed on the upper surface of a base substrate foil on which a microchip is disposed (described above by way of a first surface of a first substrate foil), and the microchip may have contact pads formed on a surface of the microchip facing the upper surface of the base substrate foil (described above by way of a second surface facing the first surface of the first substrate foil), wherein disposing the microchip on the base substrate foil may include aligning the microchip relative to the repeating base substrate wiring pattern such that at least a subset of the contact pads are in electrical contact with the repeating base substrate wiring pattern.

[0043] In some other specific illustrative but non-limiting examples of the various embodiments described above, the first substrate foil may be provided by a base substrate foil, and the second substrate foil may be provided by a bottom substrate foil, wherein the bottom substrate foil is supplied during the method of forming the functional substrate foil such that the bottom substrate foil is disposed below the base substrate foil when the microchip is inserted between the base substrate foil and the bottom substrate foil. Therefore, the base substrate foil can be considered to represent a foil for providing a base substrate in an active region on which the microchip is mounted before being inserted between the base substrate foil and the bottom substrate foil. In this document, the first substrate reel can be considered to be a base substrate reel, and the second substrate reel can be considered to be a bottom substrate reel, and after the functional substrate foil is separated into functional substrates, each functional substrate includes a base substrate and a bottom substrate.

[0044] Furthermore, a repeating first substrate wiring pattern can be considered to represent a repeating base substrate wiring pattern, and a repeating second substrate wiring pattern can be considered to represent a repeating bottom substrate wiring pattern. In some examples herein, a repeating base substrate wiring pattern formed on a first surface of a first substrate foil opposite to a second surface on which a microchip is disposed can represent a repeating base substrate wiring pattern formed on an upper surface of a base substrate foil opposite to a lower surface on which a microchip is disposed.

[0045] In some illustrative combinations of the fourth and fifth illustrative embodiments described above, the bottom substrate foil may be supplied such that a repeating bottom substrate wiring pattern is aligned relative to the contact pads of the microchip, and when the bottom substrate foil is bonded to the base substrate foil, the repeating bottom substrate wiring pattern is formed on the lower surface of the bottom substrate foil (representing the first surface of the second substrate foil as described above), which is opposite to the upper surface of the bottom substrate foil facing the microchip (representing the second surface of the second substrate foil as described above).

[0046] According to some illustrative examples herein, the first substrate pass-through as described above represents a bottom substrate pass-through that extends fully through the bottom substrate foil in alignment with only the contact pads and the repeating bottom substrate wiring pattern, so that at least a subset of the contact pads are electrically contacted with the bottom substrate wiring pattern through the bottom substrate pass-through.

[0047] In the case of flip-chip technology, a microchip can have contact pads formed thereon, and the microchip can be bonded to a base substrate foil. In this paper, the flip-chip process is used to mount a microchip onto a base substrate foil aligned with a base substrate wiring pattern providing circuitry (representing circuitry external to a microprocessor), on which contact pads are formed (i.e., the contact pads are located on the bottom side of the microchip). The microchip is flipped such that the contact pads face the base substrate foil (and the microchip is configured such that its bottom side faces downwards on the base substrate foil). When the microchip is positioned on the base substrate foil in this manner, the contact pads (now facing the base substrate foil) are aligned such that the contact pads are aligned with matching pads of the base substrate wiring pattern.

[0048] In some of the illustrative examples described above, a repeating base substrate wiring pattern may be formed on the lower surface of a base substrate foil on which a microchip is disposed (described above as a first surface of the first substrate foil), and the microchip may have contact pads formed on a surface of the microchip facing the lower surface of the base substrate foil (described above as a second surface facing the first surface of the first substrate foil), wherein disposing the microchip on the base substrate foil may include aligning the microchip relative to the repeating base substrate wiring pattern such that at least a subset of the contact pads are in electrical contact with the repeating base substrate wiring pattern. Attached Figure Description

[0049] Various illustrative embodiments and other advantages of the aspects of this disclosure will become apparent from the detailed description of the accompanying drawings presented below.

[0050] Figures 1 to 4 A schematic side view illustrates the process for manufacturing a functional substrate foil according to some illustrative embodiments of the present disclosure.

[0051] Figures 5 to 7 A schematic side view illustrates the process for manufacturing a functional substrate foil according to some other illustrative embodiments of this disclosure.

[0052] Figure 8 A roll-to-roll process for manufacturing functional substrate foils according to some illustrative embodiments of the present disclosure is schematically shown in a schematic side view.

[0053] Figure 9 An active region on a base substrate foil according to some illustrative embodiments of the present disclosure is schematically shown in an enlarged top view.

[0054] Figure 10 This schematically illustrates a subsequent stage in the fabrication of a functional substrate foil when the top base foil is aligned relative to the base substrate foil, according to some illustrative embodiments of the present disclosure. Figure 9 The active region.

[0055] The accompanying drawings are provided only to illustrate some concepts and aspects of this disclosure and do not show all possible details of certain embodiments, and are not necessarily drawn to scale. Detailed Implementation

[0056] about Figures 1 to 4 The following describes a process for manufacturing functional substrate foils according to some illustrative embodiments of the present disclosure.

[0057] Figure 1 The illustration schematically depicts an early stage in the fabrication of a functional substrate foil according to some illustrative embodiments of the present disclosure. A base substrate foil 2 having multiple active device regions is provided. Figure 1 The active region 2a is schematically indicated by dashed lines as an illustrative representation of a plurality of active regions adjacent to the active region 2a. The base substrate foil 2 may be formed of a substrate material, such as a material suitable for providing a thin substrate of a flexible circuit board. In some illustrative but non-limiting examples, the material may include at least one of quartz, glass, ceramic, organic materials, PI, PET, PEEK, and FR-4. In illustrative examples where the base substrate foil is provided as a web or roll, the material of the base substrate foil may include a thermoplastic material, such as, but not limited to, at least one of PI, PET, PEEK, and FR-4.

[0058] For example, the active region 2a may have a repeating base substrate wiring pattern 3, where "repeated" indicates... Figure 1The base substrate wiring pattern 3 formed in the active region 2a of the base substrate foil 3 shown can be repeated in at least one adjacent active region (not shown). For example, all active regions (not shown) of the entire base substrate foil 2 can have a base substrate wiring pattern (not shown) formed therein, which has the same characteristics as... Figure 1 The active region 2a in the figure has the same shape and form as the base substrate wiring pattern 3.

[0059] In some illustrative embodiments of this disclosure, the repeating base substrate wiring pattern 3 includes conductive lines and pads, by... Figure 1 The base substrate wiring pattern elements 3a and 3b are schematically illustrated for circuit structures used to achieve desired electrical functions. For example, the base substrate wiring pattern 3 can be formed as contact and interconnect structures and / or used to achieve desired electrical functions, such as an antenna wiring loop pattern including a loop antenna as an inductor element and one or more optional capacitor elements.

[0060] refer to Figure 1 The base substrate foil 2 has a repeating base substrate wiring pattern 3 formed on its surface, that is, formed on the lower surface or lower side surface 2d of the base substrate foil 2 relative to the supply or supply direction of the process for forming the functional substrate foil. In particular, at least in Figure 1 In the initial stage illustrated in the diagram, the repeating base substrate wiring pattern 3 can be formed only on the lower surface or lower side surface 2d of the base substrate foil 2, and by... Figure 1 The opposite surface indicated by the upper surface 2u remains free of any wiring pattern. For example, a base substrate foil 2 may be provided on which no base substrate wiring pattern 3 is formed, and at the beginning regarding Figures 1 to 4 In the illustrated process, a base substrate foil 2 without any wiring pattern formed thereon is prepared and provided. Subsequently, the base substrate foil 2 can undergo a wiring pattern forming process, and after the base substrate foil 2 is supplied to a manufacturing process for forming a functional foil substrate, a repeating base substrate wiring pattern 3 can be formed on at least one of the surfaces 2u and 2d of the base substrate foil 2.

[0061] In some illustrative but non-limiting examples, the substrate wiring pattern 3 may include one or more wires formed on at least one surface and / or at least one contact pad of the substrate foil 2. Figures 1 to 4 The schematic diagram is illustrated using substrate wiring pattern elements 3a and 3b. For example, the substrate wiring pattern 3 may be formed from at least one of aluminum, silver, gold, copper, indium tin oxide, and carbon.

[0062] In some illustrative embodiments herein, the base substrate foil 2 may have a repeating wiring pattern 3 formed thereon, provided that the base substrate foil 2 is not initially provided with such a repeating wiring pattern. In some illustrative examples herein, the base substrate foil 2 may undergo the following process: on at least one surface of the substrate foil (e.g., as...) Figure 1 A conductive material is deposited in a felt-like manner on the lower surface 2d shown, and then the deposited conductive material is patterned, for example, by etching, laser patterning, etc., to produce a desired wiring pattern. For example, when subjected to laser patterning, segments of the deposited conductive material are removed to produce a repeating base substrate wiring pattern on the base substrate foil 2. Compared to photolithography, laser patterning allows for greater flexibility in the customization of specific applications and reduces the need for consumable materials during the circuit board manufacturing process. Preventing damage to the substrate is a challenge in laser patterning, but the risk can be mitigated by using methods such as front and back processing. In some alternative examples described herein, the conductive material can be printed onto at least surface 2d of the base substrate foil 2 to form a repeating base substrate wiring pattern 3 as the desired wiring pattern.

[0063] In some illustrative but non-limiting examples, repeating substrate wiring patterns 3 may be formed on substrate foil 2 made of PI and / or FR-4, and the conductive material may be copper and / or gold, while wiring patterns formed on substrate foil 2 made of substrate material made of PET and / or PVC may be formed of aluminum and / or copper.

[0064] refer to Figure 2 This illustrates a later stage in the manufacturing process, particularly the stage where the active region is equipped with one or more microchips. For example, a single microchip 4 may be configured on the base substrate foil 2 in the active region 2a. However, this does not impose any limitations, and two or more microchips (not shown) may be configured on the base substrate foil 2 in the active region 2a.

[0065] Microchip 4 may include a chip substrate 4b on which a bare chip 4a having an integrated circuit (not shown) is mounted. The bare chip 4a may be a bare chip or a packaged bare chip. In some specific illustrative examples and as shown... Figure 2 As illustrated in the diagram, the bare chip 4a may include at least one contact pad, such as contact pads 4c and 4d formed on the upper surface side of the bare chip 4a, which is the side surface of the bare chip 4a opposite to the side surface through which the bare chip 4a is mounted to the chip substrate 4b. Therefore, after the microchip 4 is disposed on the base substrate foil 2, the contact pads 4c and 4d are exposed to further processing.

[0066] In some illustrative embodiments of this disclosure, the microchip 4 can be mounted to the upper surface 2u of the base substrate foil 2 by mounting the chip substrate 4b to the upper surface 2u. For example, the microchip 4 can be fixed to the upper surface 2u in the active region 2a by adhering the microchip 4 to the upper surface 2u.

[0067] Continue to refer to Figure 2 Microchip 4 can be implemented as an application-specific integrated circuit (ASIC) chip, that is, the integrated circuit (not shown) of bare chip 4 includes an ASIC, so as to realize the desired function using microchip 4. Therefore, the active region 2a of the base substrate foil 2 can realize the desired function, and based on Figure 2 Any substrate foil fabricated using the intermediate structure shown can achieve the desired functionality provided by the ASIC.

[0068] In some illustrative embodiments herein, the microchip 4 in the active region 2a (and similarly any microchip disposed in any other active region) may have a thickness of less than 50 μm. For example, the thickness of the microchip 4 may be less than 40 μm or may be less than 30 μm, for example, it may be in the range from about 20 μm to about 30 μm. In some illustrative examples herein, the microchip 4 (and any other microchip disposed on the base substrate foil 2) may be thinned to have the thickness described according to the eighth illustrative embodiment, for example, by grinding the pre-provided microchip 4 to the desired thickness.

[0069] refer to Figure 3 This illustrates a later stage in the manufacturing process, specifically the supply of the top substrate foil 5 with a repeating base substrate wiring pattern 8 to... Figure 2 The diagram shows the intermediate structure obtained at the end of the process. The top substrate foil 5 is in... Figure 3 The process stage shown in the diagram is bonded to the base substrate foil 2.

[0070] In some illustrative embodiments of this disclosure, the repeating top substrate wiring pattern 8 includes conductive lines and pads, schematically illustrated by top substrate wiring pattern elements 8a, 8b, and 8c formed on the upper surface 5u of the top substrate foil 5, as shown below. Figure 3 As shown in the diagram, the top substrate wiring pattern 8 can be formed into a circuit structure for realizing desired electrical functions on the top substrate foil 5. For example, the top substrate wiring pattern 8 can be formed into a contact and interconnect structure and / or an antenna wiring loop pattern for realizing desired electrical functions, such as including a loop antenna as an inductor element and one or more optional capacitor elements.

[0071] Continue to refer to Figure 3The top substrate foil 5 has a repeating top substrate wiring pattern 8 formed on its upper surface 5u, which is the upper surface 5u of the top substrate foil 5 that remains exposed after the top substrate foil 5 is bonded to the base substrate foil 2. Figure 3 As shown, the repeating top substrate wiring pattern 5 can be formed only on the upper surface 5u of the top substrate foil 5, and is composed of... Figure 3 The opposite surface indicated by the lower or lower side surface 5d remains without any wiring pattern. For example, the top substrate foil 5 may be provided with a repeating top substrate wiring pattern 8 pre-formed on the top substrate foil 5. In this case, supplying the top substrate foil 5 to the process for bonding the top substrate foil 5 to the base substrate foil 3 requires the top substrate foil 5 to be aligned with the base substrate foil 2. For example, the top substrate foil 5 is aligned with the base substrate foil 3 by aligning the repeating top substrate wiring pattern 8 relative to at least one of the repeating base substrate wiring pattern 3, the active region 2a, the microchip 4, and some alignment marks (not shown). Alternatively, the top substrate foil 5 may be supplied to the bonding process, and subsequently, the repeating top substrate wiring pattern 8 may be formed on the exposed upper surface 5u of the top substrate foil 5 by a patterned deposition and etching process sequence or a laser patterning process or a printing process.

[0072] In some illustrative embodiments herein, the bonding process may include depositing an adhesive 6 on the upper surface 2u of the base substrate foil 2. For example, the adhesive 6 may be deposited with a thickness substantially corresponding to the thickness of the microchip 4.

[0073] After bonding the top substrate foil 5 to the base substrate foil 2 (with the microchip 4 inserted between the bonded top substrate foil 5 and the base substrate foil 2), a vertical electrical connection or conductive portion 7 can be formed to connect the base substrate wiring pattern 3 to the top substrate wiring pattern 8. For example, the conductive portion 7 electrically connects the base substrate wiring pattern element 3a to the top substrate wiring pattern element 8a on the surface 5u of the top substrate foil 5. The conductive portion 7 extends completely through each of the top substrate foil 5 and the base substrate foil 2 for electrically interconnecting the repeating base substrate wiring pattern 2 on the lower surface 2d of the base substrate foil 2 with the repeating top substrate wiring pattern 5 on the upper surface 5u of the top substrate foil 5.

[0074] exist Figure 3 At the end of the process stage illustrated in the diagram, an intermediate substrate foil is obtained, wherein, with the microchip 4 inserted between the top substrate foils 5, the top substrate foil 5 is bonded to the base substrate foil 2. (See diagram for reference.) Figure 3 As shown, the repeating top substrate wiring pattern 8 is aligned with the microchip 4 in the active region 2a, such that the top substrate wiring pattern elements 8b and 8c are aligned with the conductive pads 4c and 4d of the microchip 4.

[0075] refer to Figure 4 This illustrates a later stage in the manufacturing process, particularly the formation of the functional substrate foil 1. In the functional substrate foil 1, vertical interconnect structures or conductive portions 9a and 9b are formed in the top substrate foil 5, aligned with the top substrate wiring pattern elements 8b and 8c and the conductive pads 4c and 4d of the microchip 4, to electrically connect the top substrate wiring pattern 8 to the microchip 4. Each of the conductive portions 9a and 9b extends completely through the top substrate foil 5 to establish an electrical connection between the top substrate wiring pattern 8 and the microchip 4.

[0076] although Figures 1 to 4 The illustration shows a base substrate foil 2 having a repeating base substrate wiring pattern 3 formed on the surface of the base substrate foil 2 (i.e., on the lower surface or lower side surface 2d of the base substrate foil 2). However, this does not impose any limitation on this disclosure, and the repeating base substrate wiring pattern 3 may be formed on two opposite surfaces 2u and 2d of the base substrate foil 2. In some embodiments not shown, the base substrate foil 2 may not have any wiring pattern, i.e., the repeating base substrate wiring pattern 3 may be omitted.

[0077] although Figures 1 to 4 The illustration shows a microchip 4 disposed on the upper surface 2u of a base substrate 2, while a repeating base substrate wiring pattern 3 is formed on the lower surface 2d of the base substrate foil 2; however, this does not impose any limitation on this disclosure. Conversely, the repeating base substrate wiring pattern 3 could be formed on the upper surface 2u of the base substrate foil 2 (although...). Figure 1 (not shown in the figure), and the microchip 4 can be mounted on the upper surface 2u of the base substrate foil 2 according to the flip chip technology, so that the contact pads 4c and 4d of the microchip are brought into the mechanical and electrical contact pads provided by the repeating base substrate wiring pattern 3 on the surface 2u of the base substrate foil 2.

[0078] although Figure 3 and Figure 4 The conductive portion 7 is illustrated as extending completely through both the top substrate foil 5 and the base substrate foil 2, but this does not impose any restrictions because Figure 4The extent to which the conductive portion 7 extends through the functional substrate foil 1 depends on the repeating substrate wiring pattern to be interconnected. In the first case, where the repeating base substrate wiring pattern 3 is formed on the lower surface 2d of the base substrate foil 2 and the repeating top substrate wiring pattern 8 is formed on the lower surface 5d of the top base substrate (instead of the illustrated embodiment), the conductive portion 7 extends completely through the base substrate foil 2 without passing through the top substrate foil 5. In this first case, the microchip 4 can only be contacted from the outside of the functional substrate foil 1 on one side, particularly by forming the repeating base substrate wiring pattern 3 on the lower surface 2d of the base substrate foil 2. In the second case, where the repeating base substrate wiring pattern 3 is formed on the upper surface 2u of the base substrate foil 2 (instead of the illustrated embodiment) and the repeating top substrate wiring pattern 8 is formed on the upper surface 5u of the top base substrate, the conductive portion 7 extends completely through the top substrate foil 5 without passing through the base substrate foil 2. In the second case, the microchip 4 can only be contacted from the outside of the functional substrate foil 1 on one side, specifically by forming a repeating top substrate wiring pattern 8 on the upper surface 5u of the top substrate foil 2. This second case can be implemented in some illustrative examples where the microchip 4 is mounted to the base substrate foil 2 in the active region 2a via flip-chip technology, so as to contact the contact pads 4c, 4d of the microchip 4 by forming a repeating base substrate wiring pattern 3 on the upper surface 2u of the base substrate foil 2.

[0079] In short, Figures 1 to 4 It shows the manufacturing process. Figure 4 The process of the functional substrate foil 1 is described above. According to various illustrative embodiments of the present disclosure as described above, the process includes: providing a base substrate foil 2 having a plurality of active device regions (illustrated by active region 2a for illustrative purposes); configuring a microchip illustrated by microchip 4 for illustrative purposes, but more than one microchip may be configured in each active region, and one or more additional microchips (not shown) other than microchip 4 may be present in the active region 2a on the base substrate foil 2 of the active device regions (see active region 2a); and bonding the top substrate foil 5 to the base substrate foil 2 in such a way that the microchip (see microchip 4) is inserted between the base substrate foil 2 and the top substrate foil 5, thereby forming the functional substrate foil 1.

[0080] Despite Figure 1 The image is not shown in the image, but it is based on the following combination. Figure 8 As presented, at least one of the base substrate foil 2 and the top substrate foil 5 can be wound onto a dedicated spool or roller, such that at least one of the base substrate spool or roller and the top substrate spool or roller is provided (corresponding to the following description). Figure 8The top substrate foil 5 and / or the base substrate foil 2 can therefore be considered as webs rather than sheet-type foils. Additionally or alternatively, the process may also include winding the foil onto a reel or roller (corresponding to the following description). Figure 8 The functional substrate foil 1 is collected by a reel or roller (R3), which enables the implementation of the R2R process.

[0081] The above about Figures 1 to 4 In some illustrative embodiments of the described process, the process may further include separating the functional substrate foil 1 into a plurality of functional substrates. Figure 4 Not illustrated, but the individual functional substrate is thought to be derived from... Figure 4 The active region 2a is cut from the functional substrate foil 1 in the middle, such that each of the multiple functional substrates includes one or more microchips (at least...). Figures 1 to 4 Microchip 4), one or more of which are inserted into the base substrate (when from Figure 4 (obtained when the active region is cut from the base substrate foil 2) and the top substrate ... Figure 4 (obtained when the active region is cut out from the top substrate foil 5 in the middle).

[0082] As mentioned above Figure 3 As described herein, when the top substrate foil 5 is bonded to the base substrate foil 2, the top substrate foil 5 may have a repeating top substrate wiring pattern 8 formed on an upper surface 5u, which corresponds to the surface of the top substrate foil 5 opposite to the lower surface 5d facing the microchip 4. As an alternative to the embodiment illustrated in this specific illustration, in which the repeating top substrate wiring pattern 8 is formed on the upper surface 5u (corresponding to the exposed surface of the top substrate foil 5 after bonding to the base substrate foil 2), when the top substrate foil 5 is bonded to the base substrate foil 2, the top substrate foil 5 may have a repeating top substrate wiring pattern 8 formed on a lower surface 5d, which corresponds to the surface of the top substrate foil 5 facing the microchip 4. In this document, bonding the top substrate foil 5 to the base substrate foil 2 may include aligning the top substrate foil 5 relative to the microchip 4 such that at least the microchip 4 is aligned relative to the top substrate wiring pattern 8 in the active region 2a.

[0083] In some of the above embodiments, the base substrate foil 2 has a repeating base substrate wiring pattern 3 formed on the surface of the base substrate foil 2 (i.e., at least on one of surfaces 2u and 2d). Hereinafter, each of the plurality of active device regions (i.e., active region 2a) has a dedicated base substrate wiring pattern, such as the base substrate wiring pattern 3, formed therein. A microchip (i.e., microchip 4) may be disposed on the base substrate foil 2 aligned with the base substrate wiring pattern 3 in each active device region (such as active region 2a), and the microchip (including microchip 4) has contact pads (such as contact pads 4c and 4d of microchip 4) formed on a surface opposite to the base substrate foil 2. The repeating base substrate wiring pattern 3 may be formed on a lower surface 2d of the base substrate foil 2 opposite to the upper surface 2u of the base substrate foil 2 (on which microchips such as microchip 4 in active region 2a are disposed).

[0084] In some illustrative embodiments as described above, the process may further include supplying a top substrate foil 5 such that a repeating top substrate wiring pattern 8 is aligned with contact pads of the microchip (such as contact pads 4c, 4d of the microchip 4 in the active region 2a) such that when the top substrate foil 5 is bonded to the base substrate foil 2, at least a subset of the contact pads (at least one of the contact pads 4c, 4d of the microchip 4 in the active region 2a) is in electrical contact with the top substrate wiring pattern 8.

[0085] In some alternative illustrative embodiments, the process may further include supplying a top substrate foil 5 such that a repeating top substrate wiring pattern 8 is aligned with contact pads of the microchip (such as contact pads 4c, 4d of the microchip 4 in active region 2a). When the top substrate foil 5 is bonded to the base substrate foil 2, the repeating top substrate wiring pattern 8 may be formed on the upper surface 5u of the top substrate foil 5, which is opposite to the lower surface 5d of the top substrate foil 5 facing the microchip (i.e., microchip 4). The process may also include forming top substrate conductive portions (such as conductive portions 9a, 9b in active region 2a) that extend only fully through the top substrate foil 5 and are aligned with the contact pads 4c, 4d of the microchip 4 in active region 2a and the repeating top substrate wiring pattern 8, such that at least one subset of the contact pads (at least one of the contact pads 4c, 4d of the microchip 4 in active region 2a) is electrically contacted with the top substrate wiring pattern 8 through the top substrate conductive portions (such as conductive portions 9a, 9b in active region 2a).

[0086] In some illustrative embodiments, the process may further include forming at least one conductive portion (corresponding to conductive portion 7 in active region 2a) that extends completely through at least one of the base substrate foil 2 and the top substrate foil 5, wherein each conductive portion electrically connects the repeating top substrate wiring pattern 8 to the repeating base substrate wiring pattern 3.

[0087] As mentioned above Figure 2 As an alternative to the described and illustrated embodiments, a microchip, such as a microchip 4 in an active region, may be bonded to a base substrate foil 2 using flip-chip technology.

[0088] In some of the illustrative embodiments described above, the process may further include forming a conductive adhesive on at least a subset of the contact pads of the microchip prior to bonding (e.g., forming a conductive adhesive on contacts 4c, 4d of the microchip 4 in the active region 4).

[0089] In some of the illustrative embodiments described above, after the top substrate foil 5 is bonded to the base substrate foil 2 including a microchip, such as a microchip 4, which is disposed on the base substrate foil, an adhesive layer, such as adhesive 6, is deposited on the base substrate foil 2.

[0090] about Figures 5 to 7 The following describes a process for manufacturing a functional substrate foil according to some other illustrative embodiments of the present disclosure.

[0091] Figure 5 The illustration schematically depicts an early stage in the fabrication of a functional substrate foil according to some illustrative embodiments of the present disclosure. A base substrate foil 12 having multiple active device regions is provided. Figure 5 The active region 12a is schematically indicated by dashed lines as an illustrative representation of a plurality of active regions adjacent to the active region 12a. The base substrate foil 12 may be formed of a substrate material, such as a material suitable for providing a thin substrate of a flexible circuit board. In some illustrative but non-limiting examples, the material may include at least one of quartz, glass, ceramic, organic materials, PI, PET, PEEK, and FR-4. In illustrative examples where the base substrate foil is provided as a web or roll, the material of the base substrate foil may include a thermoplastic material, such as, but not limited to, at least one of PI, PET, PEEK, and FR-4.

[0092] For example, the active region 12a may have a repeating base substrate wiring pattern 13, where "repeated" indicates... Figure 5The base substrate wiring pattern 13 formed in the active region 12a of the base substrate foil 13 shown can be repeated in at least one adjacent active region (not shown). For example, all active regions (not shown) of the entire base substrate foil 12 can have a base substrate wiring pattern (not shown) formed therein, which has a similar shape to... Figure 5 The active region 12a in the figure has the same shape and form as the base substrate wiring pattern 13.

[0093] In some illustrative embodiments of this disclosure, the repeating base substrate wiring pattern 13 includes conductive lines and pads (made by...). Figure 5 The base substrate wiring pattern elements 13a and 13b are schematically illustrated in the diagram, representing a circuit structure for realizing a desired electrical function. For example, the base substrate wiring pattern 13 can be formed as a contact and interconnect structure and / or for realizing a desired electrical function, such as an antenna wiring loop pattern including a loop antenna as an inductor element and one or more optional capacitor elements.

[0094] refer to Figure 5 The base substrate foil 12 has a repeating base substrate wiring pattern 13 formed on its surface, that is, formed on the lower surface or lower side surface 12d of the base substrate foil 12 relative to the supply or supply direction of the process for forming the functional substrate foil. In particular, at least in Figure 5 In the initial stage illustrated, the repeating base substrate wiring pattern 13 may be formed only on the lower surface or lower side surface 12d of the base substrate foil 12, and by Figure 5 The opposite surface indicated by the upper surface 12u remains without any wiring pattern. For example, a base substrate foil 12 on which no base substrate wiring pattern 13 is formed can be provided, and at the beginning regarding Figures 5 to 7 In the illustrated process, a base substrate foil 12 without any wiring pattern formed thereon is prepared and provided. Subsequently, the base substrate foil 12 may undergo a wiring pattern forming process, and after the base substrate foil 12 is supplied to a manufacturing process for forming a functional foil substrate, a repeating base substrate wiring pattern 13 may be formed on at least one of the surfaces 12u and 12d of the base substrate foil 12.

[0095] In some illustrative but non-limiting examples, the substrate wiring pattern 13 may include one or more wires formed on at least one surface and / or at least one contact pad of the substrate foil 12. Figures 5 to 7 The schematic diagram is illustrated using base substrate wiring pattern elements 13a and 13b. For example, the base substrate wiring pattern 13 may be formed from at least one of aluminum, silver, gold, copper, indium tin oxide, and carbon.

[0096] In some illustrative embodiments herein, the base substrate foil 12 may have a repeating wiring pattern 13 formed thereon, even when the base substrate foil 12 is not initially provided with such a repeating base substrate wiring pattern 13. In some illustrative examples herein, the base substrate foil 12 may undergo the following process: on at least one surface of the substrate foil (e.g., as...) Figure 5 A conductive material is deposited in a felt-like manner on the lower surface 12d shown, and then the deposited conductive material is patterned, for example, by etching, laser patterning, etc., to produce a desired wiring pattern. For example, when subjected to laser patterning, segments of the deposited conductive material are removed to produce a repeating base substrate wiring pattern on the base substrate foil 12. Compared to photolithography, laser patterning allows for greater flexibility in the customization of specific applications and reduces the need for consumable materials during the circuit board manufacturing process. Preventing damage to the substrate is a challenge in laser patterning, but the risk can be mitigated by using methods such as front and back side processing. In some alternative examples herein, the conductive material can be printed onto at least surface 12d of the base substrate foil 12 to form a repeating base substrate wiring pattern 13 as the desired wiring pattern.

[0097] In some illustrative but non-limiting examples, repeating substrate wiring patterns 13 may be formed on substrate foil 12 made of PI and / or FR-4, and the conductive material may be copper and / or gold, while wiring patterns formed on substrate foil 12 made of substrate material made of PET and / or PVC may be formed of aluminum and / or copper.

[0098] refer to Figure 6 This illustrates a later stage in the manufacturing process, particularly the stage where the active region is equipped with one or more microchips. For example, a single microchip 14 may be configured on the base substrate foil 12 in the active region 12a. However, this does not impose any limitations, and two or more microchips (not shown) may be configured on the base substrate foil 12 in the active region 12a.

[0099] Microchip 14 may include a chip substrate 14b on which a bare chip 14a having an integrated circuit (not shown) is mounted. The bare chip 14a may be a bare chip or a packaged bare chip. In some specific illustrative examples and as... Figure 6 As illustrated, the bare die 14a may include at least one contact pad, such as contact pads 14c and 14d formed on the upper surface side of the bare die 14a, that is, the side surface of the bare die 14a opposite to the side surface through which the bare die 14a is mounted to the chip substrate 14b. Therefore, after the microchip 14 is disposed on the base substrate foil 12, the contact pads 14c and 14d are exposed to further processing.

[0100] In some illustrative embodiments of this disclosure, the microchip 14 can be mounted to the upper surface 12u of the base substrate foil 12 by mounting the chip substrate 14b to the upper surface 12u. For example, the microchip 14 can be fixed to the upper surface 12u in the active region 12a by adhering the microchip 14 to the upper surface 12u.

[0101] Continue to refer to Figure 6 Microchip 14 can be implemented as an application-specific integrated circuit (ASIC) chip; that is, the integrated circuit (not shown) of bare chip 14 includes an ASIC, so that the desired function can be achieved using microchip 14. Therefore, the active region 12a of the base substrate foil 12 can achieve the desired function, and based on... Figure 6 Any substrate foil fabricated using the intermediate structure shown can achieve the desired functionality provided by the ASIC.

[0102] In some illustrative embodiments herein, the microchip 14 in active region 12a (and similarly any microchip disposed in any other active region) may have a thickness of less than 50 μm. For example, the thickness of microchip 14 may be less than 40 μm or may be less than 30 μm, for example, it may be in the range from about 20 μm to about 30 μm. In some illustrative examples herein, for example, microchip 14 (and any other microchip disposed on base substrate foil 12) may be thinned to have the thickness described according to the eighth illustrative embodiment by grinding a pre-provided microchip 14 to the desired thickness.

[0103] refer to Figure 7 This illustrates a later stage in the manufacturing process, specifically the supply of a top substrate foil 15 with a repeating base substrate wiring pattern 18 to... Figure 6 The diagram shows the intermediate structure obtained at the end of the process. The top substrate foil 15 is in... Figure 7 The process stage shown in the diagram is bonded to the base substrate foil 12.

[0104] In some illustrative embodiments of this disclosure, the repeating top substrate wiring pattern 18 includes conductive lines and pads, schematically illustrated by top substrate wiring pattern elements 18a, 18b, and 18c formed on the lower surface 15d of the top substrate foil 15, as shown below. Figure 3 As shown. The top substrate wiring pattern 18 can be formed into a circuit structure for implementing desired electrical functions on the top substrate foil 15. For example, the top substrate wiring pattern 18 can be formed into a contact and interconnect structure and / or for implementing desired electrical functions, such as an antenna wiring loop pattern including a loop antenna as an inductor element and one or more optional capacitor elements.

[0105] Continue to refer to Figure 7The top substrate foil 15 has a repeating top substrate wiring pattern 18 formed on its lower surface 15d, which is the surface of the top substrate foil 15 opposite to its upper surface 15u, which remains exposed after the top substrate foil 15 is bonded to the base substrate foil 12. Figure 7 As shown, the repeating top substrate wiring pattern 15 can be formed only on the lower surface 5d of the top substrate foil 15, and is formed by... Figure 7 The surface opposite to the upper or upper side surface 15u in the upper substrate foil 15 has no wiring pattern. For example, the top substrate foil 15 may be provided with a repeating top substrate wiring pattern 18 pre-formed on the top substrate foil 15. In this case, supplying the top substrate foil 15 to the process for bonding the top substrate foil 15 to the base substrate foil 13 requires alignment of the top substrate foil 15 with the base substrate foil 12. For example, the top substrate foil 15 is aligned with the base substrate foil 13 by aligning the repeating top substrate wiring pattern 18 relative to at least one of the repeating base substrate wiring pattern 13, the active region 12a, the microchip 14, and some alignment marks (not shown).

[0106] In some illustrative embodiments herein, the top substrate foil 15 can be supplied to the bonding process after a repeating top substrate wiring pattern 18 is formed on the lower surface 15d of the top substrate foil 15 facing the microchip 14 by a patterned deposition and etching process sequence or a laser patterning process or a printing process.

[0107] In some illustrative embodiments herein, the bonding process may include depositing an adhesive 16 on the upper surface 12u of the base substrate foil 12. For example, the adhesive 16 may be deposited as an adhesive fluid having a thickness substantially corresponding to the thickness of the microchip 14, and after the top substrate foil 15 is positioned over the base substrate foil 12, a roller R may roll over the stack of the top substrate foil 15 above the base substrate foil 12, wherein the microchip 14 is positioned between the active regions 12a. The roller may smooth the stack and remove air bubbles that may form during the bonding process.

[0108] exist Figure 7 At the end of the process stage illustrated in the diagram, a functional substrate foil 10 is obtained, wherein, with the microchip 14 inserted between the top substrate foils 15 in the active region 12a, the top substrate foil 15 is bonded to the base substrate foil 12. (As shown) Figure 7 As shown, the repeating top substrate wiring pattern 18 is aligned with the microchip 14 in the active region 12a, such that the top substrate wiring pattern elements 18b and 18c are aligned with the conductive pads 14c and 14d of the microchip 14, and are in electrical and mechanical contact when the top substrate foil 15 is bonded to the base substrate foil 12.

[0109] although Figures 5 to 7 The illustration shows a base substrate foil 12 having a repeating base substrate wiring pattern 13 formed on the surface of the base substrate foil 12 (i.e., on the lower surface or lower side surface 12d of the base substrate foil 12). However, this does not impose any limitation on this disclosure, and the repeating base substrate wiring pattern 13 may not be formed on either of the two opposite surfaces 12u and 12d of the base substrate foil 12. In these embodiments not illustrated, the base substrate foil 12 does not have any wiring pattern; that is, the repeating base substrate wiring pattern 13 is omitted.

[0110] although Figures 5 to 7 The diagram shows a microchip 14 disposed on the lower surface 12u of a base substrate 2, while a repeating base substrate wiring pattern 13 is formed on the lower surface 12d of the base substrate foil 12; however, this does not impose any limitation on this disclosure. Conversely, the repeating base substrate wiring pattern 13 may be formed on the upper surface 12u of the base substrate foil 12 (although...). Figure 5 (Not shown in the figure), and the microchip 14 can be mounted to the upper surface 12u of the base substrate foil 12 according to flip-chip technology, such that the contact pads 14c, 14d of the microchip form mechanical and electrical contacts with the pads provided by the repeating base substrate wiring pattern 13 on the surface 12u of the base substrate foil 12. Furthermore, the top substrate foil 15 can be configured without any top substrate wiring pattern, such that the microchip only contacts the repeating base substrate wiring pattern 13.

[0111] although Figures 5 to 7 Any vertical interconnects or conductive portions formed in the top substrate foil 15 are not shown, but this does not impose any limitations, and the top substrate wiring pattern elements 18a and 18b may be contacted by vertical interconnects extending through the top substrate foil 15 and aligned with the top substrate wiring pattern elements 18a and 18b to provide external contact on the upper surface 15u of the top substrate foil 15. Furthermore, the upper side 15u of the top substrate foil 15 may have wiring patterns formed thereon for possible contact with the vertical interconnects (not shown) on the upper surface 15u of the top substrate foil 15.

[0112] although Figures 5 to 7 No vertical interconnects or conductions formed in the functional substrate foil 10 for vertically interconnecting the top substrate foil 15 and the base substrate foil 12 are shown, but this does not impose any limitations, and the top substrate wiring pattern 18 may be contacted by one or more vertical interconnects extending through the top substrate foil 15 and aligned with both the top substrate wiring pattern 18 and the base substrate wiring pattern 13, for providing electrical connection toward contact elements provided by the base substrate wiring pattern 13 on the lower surface 12d of the base substrate foil 12.

[0113] In short, Figures 5 to 7It shows the manufacturing process. Figure 7 The process of the functional substrate foil 10 is described above. According to various illustrative embodiments of the present disclosure as described above, the process includes: providing a base substrate foil 12 having a plurality of active device regions (illustrated by active region 12a for illustrative purposes); configuring a microchip illustrated by microchip 14 for illustrative purposes, but more than one microchip may be configured in each active region, and one or more additional microchips (not shown) may be present on the base substrate foil 12 in the active device regions (see active region 12a) in addition to microchip 14; and bonding the top substrate foil 15 to the base substrate foil 12 in such a way that the microchip (see microchip 14) is inserted between the base substrate foil 12 and the top substrate foil 15, thereby forming the functional substrate foil 10.

[0114] Despite Figure 5 The image is not shown in the image, but it is based on the following combination. Figure 8 As presented, at least one of the base substrate foil 12 and the top substrate foil 15 can be wound onto a dedicated spool or roller, such that at least one of the base substrate spool or roller and the top substrate spool or roller is provided (corresponding to the following description). Figure 8 The top substrate foil 15 and / or the base substrate foil 12 can therefore be considered as webs rather than sheet-type foils. Additionally or alternatively, the process may also include winding the foil onto a reel or roller (corresponding to the following description). Figure 8 The functional substrate foil 1 is collected by a reel or roller (R3), which enables the implementation of the R2R process.

[0115] The above about Figures 5 to 7 In some illustrative embodiments of the described process, the process may further include separating the functional substrate foil 10 into a plurality of functional substrates. Figure 7 Not illustrated, but the individual functional substrate is thought to be derived from... Figure 7 The active region 12a is cut out from the functional substrate foil 10 in the middle, such that each of the plurality of functional substrates includes one or more microchips (at least Figures 5 to 7 Microchip 14), one or more of which are inserted into the base substrate (when from...) Figure 7 (obtained when the active region is cut from the base substrate foil 12) and the top substrate (when from Figure 7 (obtained when the active region is cut out from the top substrate foil 15 in the middle).

[0116] As mentioned above Figure 7As described, the top substrate foil 15 may have a repeating top substrate wiring pattern 18 formed on a lower surface 15d, which corresponds to the surface of the top substrate foil 15 facing the microchip 14 when the top substrate foil 15 is bonded to the base substrate foil 12. However, as an alternative to this explicitly illustrated embodiment, the repeating top substrate wiring pattern 18 may be formed on an upper surface 15u, which corresponds to the surface of the top substrate foil 15 exposed after the top substrate foil 15 is bonded to the base substrate foil 12. Hereinafter, bonding the top substrate foil 15 to the base substrate foil 2 may include aligning the top substrate foil 15 relative to the microchip 14 such that at least the microchip 14 is aligned relative to the top substrate wiring pattern 18 in the active region 12a. Subsequently, vertical interconnects ( Figure 7 Not shown in the diagram, but corresponding to Figure 4 The conductive portions 9a and 9b) are formed in the top substrate foil 15 to vertically interconnect the top substrate wiring pattern 18 in the active region 12a with the microchip 14.

[0117] In some of the above embodiments, the base substrate foil 12 has a repeating base substrate wiring pattern 13 formed on the surface of the base substrate foil 12 (i.e., at least on one of surfaces 12u and 12d). Hereinafter, each of the plurality of active device regions (i.e., active region 12a) has a dedicated base substrate wiring pattern, such as base substrate wiring pattern 13, formed therein. A microchip (i.e., microchip 14) may be disposed on the base substrate foil 12 in alignment with the base substrate wiring pattern 13 in each active device region (such as active region 12a), the microchip (including microchip 14) having contact pads (such as contact pads 14c and 14d of microchip 14) formed on a surface of the microchip opposite to the base substrate foil 12. Repeating base substrate wiring pattern 13 can be formed on the lower surface 12d of the base substrate foil 12 opposite to the upper surface 12u of the base substrate foil 12, on which microchips such as microchips 14 in active regions 12a are disposed.

[0118] In some illustrative embodiments as described above, the process may further include supplying a top substrate foil 15 such that a repeating top substrate wiring pattern 18 is aligned with contact pads of a microchip (such as contact pads 14c, 14d of the microchip 14 in the active region 12a) such that when the top substrate foil 15 is bonded to the base substrate foil 12, at least a subset of the contact pads (at least one of the contact pads 14c, 14d of the microchip 14 in the active region 12a) is in electrical contact with the top substrate wiring pattern 18.

[0119] In some alternative illustrative embodiments (not shown), the process may further include supplying a top substrate foil 15 such that a repeating top substrate wiring pattern 18 is aligned with contact pads of the microchip (such as contact pads 14c, 14d of the microchip 14 in active region 12a). When the top substrate foil 15 is bonded to the base substrate foil 12, the repeating top substrate wiring pattern 18 may be formed on an upper surface 15u of the top substrate foil 15, which is opposite to the lower surface 15d of the top substrate foil 15 facing the microchip (i.e., microchip 14). The process may also include forming top substrate conductive portions (such as conductive portions 19a, 19b in active region 12a) that extend only fully through top substrate foil 15 and are aligned with contact pads 14c, 14d of microchip 14 in active region 12a and repeating top substrate wiring pattern 18, such that at least one subset of contact pads (at least one of contact pads 14c, 14d of microchip 14 in active region 12a) is electrically contacted with top substrate wiring pattern 18 through top substrate conductive portions (such as conductive portions 19a, 19b in active region 12a).

[0120] In some illustrative embodiments, the process may further include forming at least one conductive portion (not shown, corresponding to) in the active region 12a. Figure 3 The conductive portion 7 extends completely through at least one of the base substrate foil 12 and the top substrate foil 15, wherein each conductive portion electrically connects the repeating top substrate wiring pattern 18 to the repeating base substrate wiring pattern 13.

[0121] As mentioned above Figure 6 As an alternative to the described and illustrated embodiments, a microchip, such as microchip 14 in an active region, may be bonded to a base substrate foil 12 according to flip-chip technology.

[0122] In some of the illustrative embodiments described above, the process may also include forming a conductive adhesive on at least a subset of the contact pads of the microchip prior to bonding (e.g., forming a conductive adhesive on contacts 14c, 14d of the microchip 14 in the active region 14).

[0123] In some of the illustrative embodiments described above, after the top substrate foil 15 is bonded to the base substrate foil 12, including a microchip, such as a microchip 14, disposed on the base substrate foil in the active region 12a, an adhesive layer, such as adhesive 16, is deposited on the base substrate foil 12.

[0124] refer to Figure 8 The image schematically illustrates a roll-to-roll or roller-to-roll process (R2R) in a side view. Figure 8 The R2R process shown can be related to the above regarding Figures 1 to 7Any combination of processes described.

[0125] The spool or roller R1 of process R2R provides the base substrate foil 22. The base substrate foil 22 can be any of the base substrate foils 2 and 12 described above, the corresponding disclosure of which is incorporated herein by reference in its entirety.

[0126] The reel or roller R2 of process R2R provides a top substrate foil 25. The top substrate foil 25 can be either of the top substrate foils 5 and 15 described above, the corresponding disclosure of which is incorporated herein by reference in its entirety.

[0127] Continue to refer to Figure 8 A reel or roller R1 is configured to supply a base substrate foil 22 having multiple active device regions (one active region 20 is schematically indicated by a dashed box B for illustrative purposes only). Active region 20 can be understood to correspond to any of the active regions 2a and 12 as described above, the corresponding disclosure of which is incorporated herein by reference in its entirety.

[0128] The base substrate foil 22 and the top substrate foil 25 are supplied as a continuous web to one or more processing chambers P, which, for illustrative purposes only, are... Figure 8 The diagram is schematically indicated by a single box. One or more processing chambers P are configured to perform the operations described above. Figures 1 to 7 Any process described herein, and the corresponding public information thereof, shall be incorporated herein by reference in its entirety.

[0129] At the output of one or more processing chambers P, the functional substrate foil 20' is output and collected on a reel or roller R3. The functional substrate foil 20' can be understood to correspond to any of the functional substrate foils 1 and 10 as described above, the corresponding disclosure of which is incorporated herein by reference in its entirety.

[0130] refer to Figure 9 and 10 The following section will describe the alignment process in this disclosure. The alignment described below can be compared with the alignment described above. Figures 1 to 7 Any combination of processes described. Furthermore, alignment as described below can be achieved as above regarding... Figure 8 Executed in one or more processing rooms P as described.

[0131] Figure 9 An enlarged portion of the base substrate foil 32 according to some illustrative embodiments of the present disclosure is shown schematically. In some illustrative examples, the illustrative enlarged portion of the base substrate foil 32 may be an active region of the base substrate foil 32. The base substrate foil 32 may correspond to any of the base substrate foils 2, 12, 22 as described above, the corresponding disclosure of which is incorporated herein by reference in its entirety.

[0132] The base substrate foil 32 may have a base substrate wiring pattern formed by base substrate wiring pattern elements 33a, 33b, 33c, and 33d formed on the surface of the base substrate foil 32. The base substrate wiring pattern elements 33a, 33b, 33c, and 33d may be electrically connected to the microchip 34. The microchip 34 may be one of a plurality of microchips (not shown) and / or one or more sensor elements (not shown).

[0133] exist Figure 9 In the schematic diagram, the substrate wiring pattern elements 33a, 33b, 33c, and 33d are illustrated as L-shaped wires. However, this does not impose any limitations, and other shapes and forms of the substrate wiring pattern elements can be used alternatively. For example, the substrate wiring pattern can realize an antenna wiring loop for a UHF antenna device, and at least one of the substrate wiring pattern elements 33a, 33b, 33c, and 33d can be implemented as a loop antenna and / or one or more capacitor elements.

[0134] Continue to refer to Figure 9 At least one adjustment or alignment hole 37a, 37b, 37c can be formed as an example of an alignment mark. The alignment holes 37a, 37b, 37c can be formed adjacent to, for example, around, the microchip 34 in the active region of the base substrate foil 32. The alignment holes 37a to 37c can be positioned at the vertices of a specific geometry having a given geometric dimension, such that the microchip 34 and / or the base substrate wiring pattern elements 33a, 33b, 33c, 33d have a clearly defined geometric relationship with each of the alignment holes 37a, 37b, 37c. In particular, each of the microchip 34 and / or the base substrate wiring pattern elements 33a, 33b, 33c, 33d can be uniquely located on the surface of the base substrate foil 32.

[0135] In some illustrative embodiments herein, alignment holes 37a, 37b, and 37c may be formed as openings in the base substrate foil 32 that extend at least partially through the base substrate foil 32. When alignment holes 37a, 37b, and 37c are formed as through-holes in the base substrate foil 32, the alignment of the base substrate foil 32 can be observed from two opposite surfaces of the base substrate foil 32.

[0136] In some illustrative embodiments, the alignment of the base substrate foil 32 can be monitored during the manufacturing process of the functional substrate foil (e.g., any of the functional substrate foils 1, 10, 20' as described above) by an optical device (such as an imaging device including a camera and optionally a display for displaying images acquired by the camera). With the aid of additional image rendering software, the images acquired by the camera can be evaluated during the automated process, and the desired alignment of the base substrate foil 32 can be achieved.

[0137] refer to Figure 10 The alignment of the base substrate foil 32 and the top substrate foil 35 relative to each other will be described. The top substrate foil 35 may correspond to any of the top substrate foils 5, 15, and 25 as described above, the corresponding disclosure of which is incorporated herein by reference in its entirety.

[0138] As an example of alignment marks, the top substrate foil 35 has at least one adjustment hole or alignment hole 37'a, 37'b', 37'c formed therein. The alignment holes 37'a, 37'b', 37'c are formed in the top substrate foil 35 and match the alignment holes 37a, 37b, 37c in the base substrate foil 32. The alignment holes 37'a, 37'b', 37'c are formed in the top substrate foil 35 such that when the alignment holes 37'a, 37'b', 37'c are directly vertically aligned with the alignment holes 37a, 37b, 37c in the base substrate foil 32, the desired alignment of the base substrate foil 32 and the top substrate foil 35 relative to each other is achieved.

[0139] In some illustrative and non-limiting examples, adjustment tools T1 and T2 with adjustment pins may be provided, which engage alignment holes 37'a, 37'b', and 37'c only when the top substrate foil 35 and the base substrate foil 32 are properly aligned with each other. When entering... Figure 8 When processing at least one of the processing chambers P, adjustment tools T1 and T2 can be engaged with the base substrate foil 32 / 22 in the initial stage, and subsequently, when the top substrate foil 35 / 25 is supplied to bond the top substrate foil 35 / 25 to the base substrate foil 32 / 22, the top substrate foil 35 / 25 is aligned by engaging alignment holes 37'a, 37'b', and 37'c in the top substrate foil 35 / 25 through adjustment tools T1 and T2. After alignment is established, the tools can be removed and the bonding process (as described above) can be performed. Figure 3 The described combination or as mentioned above Figure 7 (The described bonding process).

[0140] although Figures 1 to 7 An illustrative embodiment in which a microchip is configured on a base substrate foil and a top substrate foil is supplied thereon is described, but this does not impose any limitations on the above description, and Figures 1 to 7In an alternative embodiment not illustrated, the base substrate foil may be provided together with a bottom substrate foil instead of a top substrate foil, wherein the bottom substrate foil is supplied during the method of forming the functional substrate foil such that the bottom substrate foil is positioned below the base substrate foil when the microchip is inserted between the base substrate foil and the bottom substrate foil. Therefore, the base substrate foil is still considered to represent a foil for providing a base substrate in an active region on which the microchip is mounted before being inserted between the base substrate foil and the bottom substrate foil. In this document, the bottom substrate foil may be provided by a bottom substrate roll, and each functional substrate may be considered to include both the base substrate and the bottom substrate after the functional substrate foil has been separated into functional substrates.

[0141] In addition, a repeating bottom substrate wiring pattern can be provided instead of the aforementioned repeating top substrate wiring pattern, wherein the repeating base substrate wiring pattern can be formed on the upper surface of the base substrate foil, which is opposite to the lower surface of the base substrate foil on which the microchip is disposed.

[0142] Instead of the above, regarding Figures 1 to 7 In some illustrative embodiments described in the detailed description, the bottom substrate foil can be supplied such that a repeating bottom substrate wiring pattern is aligned relative to the contact pads of the microchip, and the repeating bottom substrate wiring pattern is formed on a lower surface of the bottom substrate foil opposite to the upper surface of the bottom substrate foil (instead of as described above in the section on...). Figures 1 to 7 (as described in the detailed description, a repeating top substrate wiring pattern formed on the upper surface of the top substrate foil) (instead of as described above in the section on...) Figures 1 to 7 The lower surface of the top substrate foil described in the detailed description faces the microchip when the bottom substrate foil is bonded to the base substrate foil.

[0143] Instead of the above about Figures 1 to 7 Some illustrative embodiments described in the detailed description may provide a bottom substrate conduction that extends only fully through the bottom substrate foil aligned with the contact pads and the repeating bottom substrate wiring pattern, so that at least a subset of the contact pads are electrically contacted with the bottom substrate wiring pattern through the bottom substrate conduction (instead of the top substrate conduction described above in the detailed description).

[0144] Instead of the above, regarding Figures 1 to 7The flip-chip process described in the detailed description provides a flip-chip process applicable to a base substrate foil in the presence of a bottom substrate foil, allowing a microchip to have contact pads formed thereon and for the microchip to be bonded to the base substrate foil. In this document, these flip-chip processes are used to mount a microchip onto a base substrate foil aligned with a base substrate wiring pattern providing circuitry (representing circuitry external to a microprocessor), on which contact pads are formed (i.e., the contact pads are located on the bottom side of the microchip). The microchip is flipped such that the contact pads face the base substrate foil (and the microchip is configured such that its bottom side is facing down on the base substrate foil). When the microchip is positioned on the base substrate foil in this manner, the contact pads (now facing the base substrate foil) are aligned such that the contact pads are aligned with matching pads of the base substrate wiring pattern.

[0145] Instead of the above, regarding Figures 1 to 7 Some illustrative embodiments described in the detailed description may involve forming repeating base substrate wiring patterns on the lower surface of the base substrate foil on which a microchip is disposed (instead of as described above in the section on...). Figures 1 to 7 The repeating base substrate wiring pattern formed on the upper surface of the base substrate foil as described in the detailed description, and the microchip may have contact pads formed on the upper surface of the microchip facing the lower surface of the base substrate foil (instead of the contact pads formed on the upper surface of the microchip as described above in the description of the base substrate foil). Figures 1 to 7 The microchip described in the detailed description (the lower surface of the upper surface of the base substrate foil) is facing the base substrate foil, wherein positioning the microchip on the base substrate foil may include aligning the microchip relative to a repeating base substrate wiring pattern such that at least a subset of contact pads are in electrical contact with the repeating base substrate wiring pattern.

Claims

1. A method for forming a functional substrate foil, the method comprising: A first substrate foil having multiple active device regions is provided; A microchip is disposed on the first substrate foil in the active device region; as well as The second substrate foil is bonded to the first substrate foil in such a manner that the microchip is inserted between the first substrate foil and the second substrate foil, thereby forming the functional substrate foil.

2. The method of claim 1, wherein at least one of the first substrate foil and the second substrate foil is wound on a dedicated spool, such that at least one of the first substrate spool and the second substrate spool is provided.

3. The method of claim 1 or 2, further comprising collecting the functional substrate foil by winding it onto a spool.

4. The method according to any one of claims 1 to 3, further comprising separating the functional substrate foil into a plurality of functional substrates, such that each of the plurality of functional substrates includes one or more microchips inserted between the first substrate and the second substrate.

5. The method according to any one of claims 1 to 4, wherein the second substrate foil has a repeating second substrate wiring pattern formed on the surface of the second substrate foil facing the microchip when the second substrate foil is bonded to the first substrate foil, and wherein bonding the second substrate foil to the first substrate foil includes aligning the second substrate foil relative to the microchip such that one or more microchips are aligned relative to the second substrate wiring pattern.

6. The method according to any one of claims 1 to 5, wherein the first substrate foil has a repeating first substrate wiring pattern formed on the surface of the first substrate foil, and each of the plurality of active device regions has a dedicated first substrate wiring pattern formed therein.

7. The method of claim 6, wherein the microchip is disposed on the first substrate foil in alignment with the first substrate wiring pattern in each active device region, the microchip having contact pads formed on the microchip on a surface opposite to the first substrate foil.

8. The method of claim 7, wherein the repeating first substrate wiring pattern is formed on a first surface of the first substrate foil, the first surface being opposite to a second surface of the first substrate foil on which the microchip is disposed.

9. The method of claim 7 or 8 in conjunction with claim 5, further comprising supplying the second substrate foil such that the repeating second substrate wiring pattern is aligned with the contact pads of the microchip such that when the second substrate foil is bonded to the first substrate foil, at least a subset of the contact pads are in electrical contact with the second substrate wiring pattern.

10. The method of claim 7 or 8 in conjunction with claim 5, further comprising supplying the second substrate foil in such a manner that the repeating second substrate wiring pattern is aligned with the contact pads of the microchip, wherein when the second substrate foil is bonded to the first substrate foil, the repeating second substrate wiring pattern is formed on a first surface of the second substrate foil opposite to a second surface of the second substrate foil facing the microchip, and wherein the method further comprises forming a second substrate conduction that extends fully through the second substrate foil in alignment with the contact pads and the repeating second substrate wiring pattern, such that at least a subset of the contact pads is electrically contacted with the second substrate wiring pattern through the second substrate conduction.

11. The method of claim 9 or 10, further comprising forming at least one conductive portion extending completely through at least one of the first substrate foil and the second substrate foil, wherein each conductive portion electrically connects the repeating second substrate wiring pattern to the repeating first substrate wiring pattern.

12. The method of claim 6, wherein the microchip has contact pads formed thereon, and the microchip is bonded to the first substrate foil according to flip-chip technology.

13. The method according to any one of claims 7 to 12, further comprising forming a conductive adhesive on at least a subset of the contact pads of the microchip prior to the bonding.

14. The method of any one of claims 1 to 13, wherein bonding the second substrate foil to the first substrate foil comprises depositing an adhesive layer on the first substrate foil after the microchip is disposed on the first substrate foil.

15. The method according to any one of claims 1 to 14, wherein at least one microchip is an ASIC chip.

16. The method according to any one of claims 1 to 15, wherein the microchip has a thickness of less than 50 μm.

17. The method according to any one of claims 1 to 16, wherein at least one of the first substrate foil and the second substrate foil is made of a thermoplastic material.

18. A method for forming a functional substrate, the method comprising: A functional substrate foil is provided, the functional substrate foil being formed by the method according to any one of claims 1 to 17; as well as At least one functional substrate is separated from the functional substrate foil.

19. The method of claim 18, wherein the at least one functional substrate is removed from the functional substrate foil by at least one of cutting and stamping a portion of the functional substrate foil comprising an active region having at least one microchip.

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