Semiconductor device and method for manufacturing semiconductor device

Abstract

There is provided a semiconductor device including: a chip having a main surface; a gate electrode formed on the main surface; an interlayer film covering the gate electrode; an opening which is formed in the interlayer film so as to be separated from an electrode-side portion of the gate electrode in a lateral direction along the main surface, and which exposes a part of the main surface as a contact surface; and a surface electrode formed on the interlayer film and mechanically and electrically connected to the contact surface within the opening, the interlayer film including: an insulating upper portion in contact with an electrode upper portion of the gate electrode; an insulating side portion in contact with the electrode side portion; and an insulating corner portion in contact with an electrode corner portion of the gate electrode, the corner portion thickness of the interlayer film at the insulating corner portion being thicker than at least one of an upper portion thickness of the interlayer film at the insulating upper portion and a side portion thickness of the interlayer film at the insulating side portion.

Description

[0001] This application corresponds to Japanese Patent Application No. 2023-044003, filed with the Japan Patent Office on March 20, 2023, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a semiconductor device and a method for manufacturing the same. Background Technology

[0003] Patent document 1 discloses a SiC semiconductor device comprising: a p-type body region, which in n - Multiple n-type source regions are formed on the surface of the p-type SiC semiconductor layer, each constituting a unit cell; an n-type source region is formed inside the p-type main region; a gate electrode is positioned opposite the p-type main region across a gate insulating film; n + Type drain region and p + A p-type collector region is formed adjacent to the back side of the SiC semiconductor layer; and a p-type body region is formed adjacent to the front n-type collector region. + n between the drain regions - Type-shifting drift region. + The collector region is formed as a region comprising at least two unit cells that covers the surface of the SiC semiconductor layer along the X-axis.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2015-207588 Summary of the Invention

[0007] The problem that the invention aims to solve

[0008] One embodiment of this disclosure provides a semiconductor device and a method for manufacturing the same, which can improve the withstand voltage reliability between the gate electrode and the surface electrode.

[0009] Solution for solving the problem

[0010] One embodiment of this disclosure provides a semiconductor device comprising: a chip having a main surface; a gate electrode formed on the main surface, having: an electrode upper portion along the main surface; an electrode side portion rising from the main surface; and an electrode corner portion formed by a portion of the gate electrode material missing, connecting the electrode upper portion and the electrode side portion; an interlayer film covering the gate electrode; an opening formed in the interlayer film laterally along the main surface, separated from the electrode side portion, exposing a portion of the main surface as a contact surface; and a surface electrode formed on the interlayer film, mechanically and electrically connected to the contact surface within the opening, the interlayer film comprising: an insulating upper portion contacting the electrode upper portion; an insulating side portion contacting the electrode side portion; and an insulating corner portion contacting the electrode corner portion, the corner thickness of the interlayer film at the insulating corner portion being thicker than at least one of the upper thickness of the interlayer film at the insulating upper portion and the side thickness of the interlayer film at the insulating side portion.

[0011] One embodiment of this disclosure provides a method for manufacturing a semiconductor device, comprising the following steps: forming a base electrode on a main surface of a wafer; selectively isotropically etching the base electrode in the thickness direction, followed by anisotropic etching, thereby forming a gate electrode having an upper electrode portion along the main surface, an electrode side portion rising from the main surface, and an electrode corner portion including an arcuate recess connecting the upper electrode portion and the electrode side portion and curving inward toward the base electrode; forming an interlayer film on the main surface such that it covers the gate electrode; forming an opening on the interlayer film such that it is separated from the electrode side portion in the lateral direction along the main surface, exposing a portion of the main surface as a contact surface; and forming a surface electrode on the interlayer film such that it is mechanically and electrically connected to the contact surface within the opening.

[0012] One embodiment of this disclosure provides a method for manufacturing a semiconductor device, comprising the following steps: forming a base electrode on a main surface of a wafer; selectively performing anisotropic tapered etching on the base electrode in the thickness direction, followed by anisotropic vertical etching, thereby forming a gate electrode having an upper electrode portion along the main surface, an electrode side portion rising from the main surface, and an electrode corner portion including a flat inclined wall connecting the upper electrode portion and the electrode side portion and sloping downward from the upper electrode portion to the electrode side portion; forming an interlayer film on the main surface such that it covers the gate electrode; forming an opening on the interlayer film such that it is separated from the electrode side portion in the lateral direction along the main surface, exposing a portion of the main surface as a contact surface; and forming a surface electrode on the interlayer film such that it is mechanically and electrically connected to the contact surface within the opening.

[0013] One embodiment of this disclosure provides a method for manufacturing a semiconductor device, comprising the following steps: forming a base electrode comprising polysilicon on a main surface of a wafer; selectively anisotropically etching the base electrode in the thickness direction to form a gate electrode having an upper electrode portion along the main surface, an electrode side portion rising from the main surface, and an electrode corner portion connecting the upper electrode portion and the electrode side portion; thermally oxidizing the gate electrode to form an arcuate portion of the electrode corner portion that curves obliquely upward toward the gate electrode; forming an interlayer film on the main surface such that it covers the gate electrode; forming an opening on the interlayer film such that it is separated from the electrode side portion in the lateral direction along the main surface, exposing a portion of the main surface as a contact surface; and forming a surface electrode on the interlayer film such that it is mechanically and electrically connected to the contact surface within the opening.

[0014] Invention Effects

[0015] According to one embodiment of the present disclosure, a semiconductor device and a method thereof that can improve the withstand voltage reliability between the gate electrode and the surface electrode can be provided. Attached Figure Description

[0016] Figure 1 This is a top view of a semiconductor device illustrating an implementation method.

[0017] Figure 2 It is along Figure 1 The cross-sectional view along line II-II shown.

[0018] Figure 3 This is a top view showing an example layout of the first main face.

[0019] Figure 4 It is an enlarged top view showing the main part of the first main surface.

[0020] Figure 5 This is an enlarged top view showing another major part of the first main surface.

[0021] Figure 6 It is along Figure 5 The sectional view along line VI-VI is shown.

[0022] Figure 7 It means Figure 6 Enlarged sectional view of the main part.

[0023] Figure 8 It is along Figure 5 The cross-sectional view of line VIII-VIII shown.

[0024] Figure 9 It means Figure 8Enlarged sectional view of the main part.

[0025] Figure 10 It means Figure 7 Enlarged sectional view of the main part.

[0026] Figure 11 It is a schematic diagram representing a wafer.

[0027] Figure 12A It is a cross-sectional view showing the manufacturing process of a semiconductor device.

[0028] Figure 12B It means Figure 12A A cross-sectional view of the subsequent processes.

[0029] Figure 12C It means Figure 12B A cross-sectional view of the subsequent processes.

[0030] Figure 12D It means Figure 12C A cross-sectional view of the subsequent processes.

[0031] Figure 12E It means Figure 12D A cross-sectional view of the subsequent processes.

[0032] Figure 12F It means Figure 12E A cross-sectional view of the subsequent processes.

[0033] Figure 12G It means Figure 12F A cross-sectional view of the subsequent processes.

[0034] Figure 12H It means Figure 12G A cross-sectional view of the subsequent processes.

[0035] Figure 12I It means Figure 12H A cross-sectional view of the subsequent processes.

[0036] Figure 12J It means Figure 12I A cross-sectional view of the subsequent processes.

[0037] Figure 12K It means Figure 12J A cross-sectional view of the subsequent processes.

[0038] Figure 12L It means Figure 12K A cross-sectional view of the subsequent processes.

[0039] Figure 12M It means Figure 12L A cross-sectional view of the subsequent processes.

[0040] Figure 13 This is a cross-sectional view showing a first modified example of the gate electrode.

[0041] Figure 14A It means and Figure 13 A diagram showing the process involved in forming the gate electrode.

[0042] Figure 14B It means Figure 14A A cross-sectional view of the subsequent processes.

[0043] Figure 15 This is a cross-sectional view showing a second modified example of the gate electrode.

[0044] Figure 16A It means and Figure 15 A diagram showing the process involved in forming the gate electrode.

[0045] Figure 16B It means Figure 16A A cross-sectional view of the subsequent processes. Detailed Implementation

[0046] The embodiments will now be described in detail with reference to the accompanying drawings. The drawings are schematic diagrams and not strictly illustrative; relative positions, scales, ratios, angles, etc., may not be consistent. Corresponding structures in the drawings are labeled with the same reference numerals, and repeated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the description preceding the omission or simplification applies.

[0047] When the term "substantially" is used in this specification, it includes not only the numerical value (shape) that is equal to the numerical value (shape) of the comparison object, but also a numerical error (shape error) within ±10% of the numerical value (shape) of the comparison object. In the following description, terms such as "first," "second," and "third" are used, but these are notations assigned to the names of each structure to clarify the order of description, and are not intended to define the essence of the names of each structure.

[0048] In the following description, "p-type" or "n-type" is used to refer to the conductivity type of the semiconductor (impurity), but "p-type" can also be called the "first conductivity type" and "n-type" the "second conductivity type." Conversely, "n-type" can also be called the "first conductivity type" and "p-type" the "second conductivity type." "P-type" is the conductivity type originating from trivalent elements, and "n-type" is the conductivity type originating from pentavalent elements. The trivalent element is at least one of boron, aluminum, gallium, and indium. The pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0049] Figure 1 This is a top view showing the semiconductor device 1 of the embodiment. Figure 2It is along Figure 1 The cross-sectional view along line II-II shown. Figure 3 This is a top view showing a layout example of the first main face 3. Figure 4 This is an enlarged top view showing the main part of the first main surface 3. Figure 5 This is an enlarged top view showing another major part of the first main surface 3.

[0050] Figure 6 It is along Figure 5 The sectional view along line VI-VI is shown. Figure 7 It means Figure 6 Enlarged sectional view of the main part. Figure 8 It is along Figure 5 The cross-sectional view of line VIII-VIII shown. Figure 9 It means Figure 8 Enlarged sectional view of the main part.

[0051] Reference Figures 1-9 Semiconductor device 1 is a semiconductor switching device having an insulated-gate transistor structure Tr as an example of a device structure. The transistor structure Tr has a vertical structure. Semiconductor device 1 is a SiC semiconductor device having a chip 2 including a SiC single crystal. Chip 2 can also be called a "SiC chip" or a "semiconductor chip".

[0052] In this embodiment, chip 2 is composed of hexagonal SiC single crystals, forming a cuboid shape. Hexagonal SiC single crystals have various polymorphs, including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, and 6H-SiC single crystals. This embodiment shows an example where chip 2 is composed of 4H-SiC single crystals, but chip 2 can also be composed of other polymorphs.

[0053] Chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are quadrilaterals when viewed from the vertical direction Z (hereinafter referred to as "top view"). The vertical direction Z is also the thickness direction of chip 2 and the normal direction of the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 can also be squares or rectangles when viewed from the top.

[0054] The first main surface 3 and the second main surface 4 are preferably formed from the c-plane of a SiC single crystal. In this case, the first main surface 3 is preferably formed from the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed from the carbon surface ((000-1) surface) of the SiC single crystal.

[0055] The first side surface 5A and the second side surface 5B extend along the first main surface 3 in a first direction X and are opposite each other along the first main surface 3 in a second direction Y that intersects the first direction X. Specifically, the second direction Y is orthogonal to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and are opposite each other in the first direction X.

[0056] In the following description, one side of the first direction X refers to the third side 5C, and the other side of the first direction X refers to the fourth side 5D. Similarly, one side of the second direction Y refers to the first side 5A, and the other side of the second direction Y refers to the second side 5B. In this configuration, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X can be the a-axis direction of the SiC single crystal, and the second direction Y can be the m-axis direction of the SiC single crystal.

[0057] Chip 2 (first main surface 3 and second main surface 4) has a deviation angle that is tilted at a predetermined angle in a predetermined deviation direction relative to the c-plane of the SiC single crystal. That is, the amount of the deviation angle by which the c-axis ((0001) axis) of the SiC single crystal is tilted from the vertical axis toward the deviation direction. In addition, the amount of the deviation angle by which the c-plane of the SiC single crystal is tilted relative to the horizontal plane.

[0058] The deviation direction is preferably the a-axis direction (i.e., the second direction Y) of the SiC single crystal. The deviation angle can be greater than 0° and less than 10°. The deviation angle can have a value belonging to at least one of the following ranges: greater than 0° and less than 1°, greater than 1° and less than 2.5°, greater than 2.5° and less than 5°, greater than 5° and less than 7.5°, and greater than 7.5° and less than 10°.

[0059] The deviation angle is preferably 5° or less. Particularly preferred is a deviation angle of 2° or more but less than 4.5°. The deviation angle is typically set in the range of 4° ± 0.1°. This specification does not exclude a deviation angle of 0° (i.e., the first main surface 3 is facing the front relative to surface c).

[0060] Semiconductor device 1 includes an n-type first semiconductor region 6 formed within chip 2 in a region (surface layer) on the side of a first main surface 3. The first semiconductor region 6 may also be referred to as a "drift region," "drain drift region," or "drain region," etc. A drain potential, which is a high potential (first potential), is applied to the first semiconductor region 6. The first semiconductor region 6 is formed in a layered manner extending along the first main surface 3, exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. In this configuration, the first semiconductor region 6 is composed of an epitaxial layer (specifically, a SiC epitaxial layer).

[0061] The semiconductor device 1 includes an n-type second semiconductor region 7 formed in a region (surface layer) on the side of the second main surface 4 within the chip 2. A drain potential is applied to the second semiconductor region 7. The second semiconductor region 7 may also be referred to as a "drain region" or the like. The second semiconductor region 7 has a higher n-type impurity concentration than the first semiconductor region 6 and is electrically connected to the first semiconductor region 6 within the chip 2.

[0062] The second semiconductor region 7 is formed as a layer extending along the second main surface 4, exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this configuration, the second semiconductor region 7 is constituted by a semiconductor substrate (specifically a SiC substrate). That is, the chip 2 has a stacked structure including a semiconductor substrate and an epitaxial layer. The second semiconductor region 7 has a thickness greater than that of the first semiconductor region 6.

[0063] Semiconductor device 1 includes an active region 8 disposed on chip 2. The active region 8 is a region that includes a device structure (transistor structure Tr) and generates an output current (drain current). The active region 8 is disposed within chip 2 at intervals from the periphery (first to fourth sides 5A to 5D) of chip 2 when viewed from above. The active region 8 is configured to have a polygonal shape (in this case, a quadrilateral shape) with four sides parallel to the periphery of chip 2 when viewed from above. The planar area of ​​the active region 8 is preferably 50% or more and 90% or less of the planar area of ​​the first main surface 3.

[0064] Semiconductor device 1 includes an outer peripheral region 9 disposed in chip 2 outside an active region 8. Viewed from above, the outer peripheral region 9 is disposed in the area between the periphery of chip 2 and the active region 8. Viewed from above, the outer peripheral region 9 extends in a strip along the active region 8 and is configured as a polygonal ring (in this case, a quadrilateral ring) surrounding the active region 8.

[0065] The semiconductor device 1 includes a plurality of p-type main regions 20 formed in the surface portion of the first main surface 3 in the active region 8. The plurality of main regions 20 are assigned a source potential that is a low potential (second potential) different from a high potential (first potential). The plurality of main regions 20 are arranged at intervals in a first direction X, and are each formed as a strip extending in a second direction Y. That is, the plurality of main regions 20 are arranged as stripes extending along the second direction Y.

[0066] Multiple main regions 20 are formed spaced apart from the bottom of the first semiconductor region 6 toward the first main surface 3, and are opposite to the second semiconductor region 7 across a portion of the first semiconductor region 6. Preferably, the multiple main regions 20 are formed spaced apart from the middle portion of the first semiconductor region 6 toward the first main surface 3. The multiple main regions 20 are exposed from the first main surface 3.

[0067] The semiconductor device 1 includes a p-type outer body region 21 formed in the outer peripheral region 9 on the surface layer of the first main surface 3. The outer body region 21 preferably has a p-type impurity concentration approximately equal to that of the main body region 20. However, the p-type impurity concentration of the outer body region 21 can be either less than or higher than that of the main body region 20.

[0068] The outer main body region 21 is formed at intervals from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D) toward the active region 8, and extends in a strip along the active region 8. The outer main body region 21 has a portion that extends in a strip along the first direction X and a portion that extends in a strip along the second direction Y when viewed from above, thus dividing the active region 8 from multiple directions.

[0069] In this configuration, the outer main body region 21 surrounds the active region 8 when viewed from above and is divided into a polygonal ring with four sides parallel to the periphery of the first main surface 3 (in this configuration, it is a quadrilateral ring). That is, the outer main body region 21 forms the boundary between the active region 8 and the outer peripheral region 9. The outer main body region 21 may also have an edge portion that connects the portion extending along the first direction X and the portion extending along the second direction Y when viewed from above in an arc shape (preferably a quarter arc shape) (see reference). Figure 4 ).

[0070] The outer body region 21 has an inner edge portion on the side of the active region 8 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the outer body region 21 is connected to the plurality of body regions 20 in the portion extending along the first direction X. Thus, the outer body region 21 is fixed to the same potential as the plurality of body regions 20.

[0071] The outer main body region 21 preferably has a width greater than that of the main body region 20. The width of the main body region 20 is the width in a direction orthogonal to the extension direction (i.e., the first direction X). The width of the outer main body region 21 is the width in a direction orthogonal to the extension direction. Of course, the width of the outer main body region 21 can be approximately equal to the width of the main body region 20, or it can be less than the thickness of the main body region 20.

[0072] The ratio of the width of the outer main body region 21 to the width of the main body region 20 can be 10 or more and 50 or less. Preferably, the width ratio is 20 or more and 40 or less.

[0073] The outer body region 21 is formed at intervals from the bottom of the first semiconductor region 6 toward the first main surface 3, and is opposite to the second semiconductor region 7 across a portion of the first semiconductor region 6. Preferably, the outer body region 21 is formed at intervals from the middle portion of the first semiconductor region 6 toward the first main surface 3. The outer body region 21 is exposed from the first main surface 3.

[0074] The outer main body region 21 preferably has a thickness (depth) that is approximately equal to that of the main body region 20. Of course, the thickness of the outer main body region 21 can be less than or greater than the thickness of the main body region 20.

[0075] The semiconductor device 1 includes a plurality of n-type surface drift regions 22 formed on the surface portion of the first main surface 3. In this configuration, each of the plurality of surface drift regions 22 is constituted by a portion of the first semiconductor region 6. Of course, the plurality of surface drift regions 22 may have an n-type impurity concentration that is higher than that of the first semiconductor region 6, or they may have an n-type impurity concentration that is lower than that of the first semiconductor region 6.

[0076] Multiple surface drift regions 22 are each divided into regions between multiple adjacent main body regions 20 in the first direction X. Specifically, the surface portion of the first main surface 3 is divided by multiple main body regions 20 and outer main body regions 21. The multiple surface drift regions 22 are arranged at intervals in the first direction X, forming stripes extending in the second direction Y. That is, the multiple surface drift regions 22 are formed as stripes extending in the second direction Y.

[0077] Semiconductor device 1 includes multiple n-type source regions 23 and 24 respectively formed on the surface portion of multiple main regions 20. The multiple source regions 23 and 24 have an n-type impurity concentration higher than that of the first semiconductor region 6. Source potentials are assigned to the multiple source regions 23 and 24.

[0078] Multiple source regions 23 and 24 on the surface of each main body region 20 include a first source region 23 located on one side of the first direction X and a second source region 24 located on the other side of the first direction X. In this configuration, in the first direction X, a first source region 23 is formed at one end of the main body region 20, and a second source region 24 is formed at the other end of the main body region 20.

[0079] The first source region 23 is formed spaced apart from one end of the main body region 20 to the other end, extending in a strip shape along the extension direction of the main body region 20. The first source region 23 is formed spaced apart from the outer main body region 21 in the second direction Y. That is, the first source region 23 is not formed in the outer main body region 21. The first source region 23 is formed spaced apart from the bottom of the main body region 20 towards the first main surface 3, and is opposed to the first semiconductor region 6 across a portion of the main body region 20.

[0080] The second source region 24 is formed spaced apart from the first source region 23 toward the other end of the main body region 20. The second source region 24 is also formed spaced apart from the other end of the main body region 20 toward one end, extending in a strip shape along the extension direction of the main body region 20. The second source region 24 is formed spaced apart from the outer main body region 21 in the second direction Y. That is, the second source region 24 is not formed in the outer main body region 21. The second source region 24 is formed spaced apart from the bottom of the main body region 20 toward the first main surface 3, and is opposed to the first semiconductor region 6 across a portion of the main body region 20.

[0081] When multiple first source regions 23 are formed in a main body region 20, the multiple first source regions 23 may also be formed at intervals along the extension direction of the main body region 20. In this case, each first source region 23 may also be formed as a strip extending in the second direction Y. Similarly, when multiple second source regions 24 are formed in a main body region 20, the multiple second source regions 24 may also be formed at intervals along the extension direction of the main body region 20. In this case, each second source region 24 may also be formed as a strip extending in the second direction Y.

[0082] Semiconductor device 1 includes multiple p-type contact regions 25 formed in the surface portion of multiple body regions 20 within an active region 8. The contact regions 25 may also be referred to as "back gate regions". A source potential is assigned to the multiple contact regions 25. The contact regions 25 have a higher p-type impurity concentration compared to the p-type impurity concentration of the body regions 20.

[0083] In this configuration, a contact region 25 is located on the surface of the corresponding main body region 20, between the first source region 23 and the second source region 24. The contact region 25 extends in a strip shape along the extension direction of the main body region 20 (source regions 23, 24). The contact region 25 is formed at a distance from the outer main body region 21 in the second direction Y. That is, the contact region 25 is not formed on the outer main body region 21. The contact region 25 is formed at a distance from the bottom of the main body region 20 toward the first main surface 3, and is opposite to the first semiconductor region 6 across a portion of the main body region 20.

[0084] When multiple contact areas 25 are formed in a single main body region 20, the multiple contact areas 25 may also be formed at intervals along the extending direction of the main body region 20. In this case, each contact area 25 may also be formed as a strip extending along the second direction Y.

[0085] Semiconductor device 1 includes a plurality of p-type channel regions 26, 27 formed on the surface portion of a first main surface 3. The plurality of channel regions 26, 27 are respectively divided on the surface portion of a plurality of main body regions 20 into regions between the ends of the plurality of main body regions 20 (a plurality of surface drift regions 22) and the peripheries of a plurality of source regions 23, 24. In this configuration, the plurality of channel regions 26, 27 are arranged at intervals in a first direction X, and are respectively formed as stripes extending in a second direction Y. That is, the plurality of channel regions 26, 27 are arranged as stripes extending along the second direction Y.

[0086] The multiple channel regions 26 and 27 include multiple first channel regions 26 and multiple second channel regions 27. The multiple first channel regions 26 are respectively divided into regions between one end of multiple main regions 20 (surface drift regions 22) and multiple first source regions 23, forming a current path extending horizontally. The multiple second channel regions 27 are respectively divided into regions between the other end of multiple main regions 20 (surface drift regions 22) and multiple second source regions 24, forming a current path extending horizontally.

[0087] The semiconductor device 1 includes a plurality of planar electrode-type gate structures 30 disposed on a first main surface 3 in an active region 8. The plurality of gate structures 30 are arranged at intervals in a first direction X, and are respectively formed as stripes extending in a second direction Y. That is, the plurality of gate structures 30 are arranged in a stripe-like pattern extending along the second direction Y. The extension direction of the plurality of gate structures 30 is consistent with the offset direction of the SiC single crystal.

[0088] Each gate structure 30 is disposed over at least one channel region 26, 27. In this configuration, each gate structure 30 is configured to traverse a surface drift region 22 and span two adjacent main regions 20, covering multiple channel regions 26, 27. Specifically, each gate structure 30 is configured to span a first source region 23 on one side of a main region 20 and a second source region 24 on the other side of a main region 20, covering the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26, and the second channel region 27.

[0089] The structure of a gate structure 30 is described below. The gate structure 30 has a stacked structure including an insulating film 31 and a gate electrode 32. The gate structure 30 does not have insulating sidewall structures (spacers) on the side of the gate electrode 32. The insulating film 31 may also include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the insulating film 31 has a single-layer structure made of a silicon oxide film. The insulating film 31 is particularly preferably made of a silicon oxide film composed of the oxide of the chip 2.

[0090] An insulating film 31 covers the first main surface 3 in a film-like manner and is disposed on at least one channel region 26, 27. In this manner, the insulating film 31 is disposed in a way that traverses a surface drift region 22 and spans two adjacent main body regions 20, covering multiple channel regions 26, 27.

[0091] Specifically, the insulating film 31 is configured to span a first source region 23 on one side of the main body region 20 and a second source region 24 on the other side of the main body region 20, covering the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26, and the second channel region 27.

[0092] The insulating film 31 partially covers the first source region 23 at intervals from the contact region 25, such that a portion of the first source region 23 and the contact region 25 are exposed from the first main surface 3. The insulating film 31 partially covers the second source region 24 at intervals from the contact region 25, such that a portion of the second source region 24 and the contact region 25 are exposed from the first main surface 3.

[0093] The thickness of the insulating film 31 can also be 10 nm or more and 150 nm or less. The thickness of the insulating film 31 can be within at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less. Preferably, the thickness of the insulating film 31 is 25 nm or more and 75 nm or less.

[0094] A gate electrode 32 is disposed on an insulating film 31 and faces at least one channel region 26, 27 across the insulating film 31. A gate potential, serving as a control potential, is applied to the gate electrode 32. The gate electrode 32 controls the inversion and non-inversion of at least one channel region 26, 27 in response to the gate potential.

[0095] The gate electrode 32 comprises a conductive semiconductor polysilicon. The gate electrode 32 may also comprise either or both of p-type and n-type conductive polysilicon. The conductivity type of the gate electrode 32 is adjusted according to the gate threshold voltage to be achieved. The gate electrode 32 may also be referred to as a "polysilicon gate," "polycrystalline gate," etc.

[0096] The gate electrode 32 is formed as a strip extending in the second direction Y. That is, the extension direction of the gate electrode 32 is consistent with the deviation direction of the SiC single crystal. In this manner, the gate electrode 32 is formed in the first direction X at intervals from both ends of the insulating film 31 inward, so that both ends of the insulating film 31 are exposed. The gate electrode 32 is disposed on the insulating film 31 in such a way that it traverses a surface drift region 22 and spans two adjacent main regions 20, and is opposed to a plurality of channel regions 26, 27 through the insulating film 31.

[0097] Specifically, the gate electrode 32 is configured to span the first source region 23 on one side of the main body region 20 and the second source region 24 on the other side of the main body region 20, and is positioned opposite the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26 and the second channel region 27 through the insulating film 31.

[0098] The gate electrode 32 has an upper electrode portion 33, a first electrode side portion 34 on one side in the first direction X, and a second electrode side portion 35 on the other side in the first direction X. The upper electrode portion 33 extends along the insulating film 31 (first main surface 3). The upper electrode portion 33 may also extend substantially parallel to the insulating film 31 (first main surface 3). The upper electrode portion 33 may also be referred to as the upper electrode wall.

[0099] The first electrode side portion 34 is formed at intervals from one end of the insulating film 31 to the other end in the first direction X, and extends in the vertical direction Z. The second electrode side portion 35 is formed at intervals from the other end of the insulating film 31 to one end in the first direction X, and extends in the vertical direction Z.

[0100] The first electrode side portion 34 and the second electrode side portion 35 may also extend perpendicularly to the insulating film 31. That is, the gate electrode 32 may also be formed into a quadrilateral shape (a flat rectangular shape) in cross-section. The first electrode side portion 34 and the second electrode side portion 35 may also be inclined toward the upper electrode portion 33. In other words, the gate electrode 32 may also be formed into a conical shape (preferably an isosceles trapezoidal shape) in cross-section. The first electrode side portion 34 and the second electrode side portion 35 may also be referred to as the first electrode sidewall and the second electrode sidewall, respectively.

[0101] The width of the gate structure 30 can be 1 μm or more and 10 μm or less. The width of the gate structure 30 is the width in the direction orthogonal to the extension direction (i.e., the first direction X). Preferably, the width of the gate structure 30 is 1 μm or more and 5 μm or less.

[0102] The thickness of the gate structure 30 can be 0.1 μm or more and 2.0 μm or less. Preferably, the thickness of the gate structure 30 is 0.2 μm or more and 1.0 μm or less.

[0103] Reference Figure 6 and Figure 7 The gate electrode 32 includes an upper electrode portion 33 and an electrode corner portion 41 connecting the first electrode side portion 34 and the second electrode side portion 35. The electrode corner portion 41 is formed by a portion of the material of the gate electrode 32 being missing. In this manner, the electrode corner portion 41 is formed by a recess that bends inward toward the gate electrode 32. Thus, the upper electrode portion 33 is partially formed on the surface portion of each gate electrode 32 when viewed from above.

[0104] When viewed from above, the upper electrode portion 33 is formed spaced inward from at least one of the first electrode side portion 34 and the second electrode side portion 35 of the gate electrode 32, exposing at least one of the peripheral portions on the first electrode side portion 34 and the second electrode side portion 35. In this configuration, the upper electrode portion 33 is formed spaced inward from both the first electrode side portion 34 and the second electrode side portion 35, exposing both the peripheral portions on the first electrode side portion 34 and the peripheral portions on the second electrode side portion 35 when viewed from above.

[0105] The upper electrode portion 33, when viewed from above, is formed as a strip extending along the gate electrode 32. That is, the extension direction of the upper electrode portion 33 is consistent with the deviation direction of the SiC single crystal. The upper electrode portion 33 is opposite to a surface drift region 22 in the stacking direction. Alternatively, the upper electrode portion 33 can be formed by spacing from two adjacent main regions 20 toward the surface drift region 22 when viewed from above, and is opposite only to a surface drift region 22 in the stacking direction.

[0106] The upper electrode portion 33 can also traverse a surface drift region 22 and span two adjacent main body regions 20 when viewed from above. In this case, the upper electrode portion 33 can also be formed at intervals from the first source region 23 on one side of the main body region 20 and the second source region 24 on the other side of the main body region 20 toward the surface drift region 22, and is opposite to the surface drift region 22, the first channel region 26 and the second channel region 27 in the stacking direction.

[0107] In this configuration, the upper electrode 33 is formed in a manner that spans the first source region 23 on one side of the main body region 20 and the second source region 24 on the other side of the main body region 20, and is opposite to the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26 and the second channel region 27 in the stacking direction.

[0108] Given the responsiveness of the switching speed, the upper portion 33 of the electrode is preferably opposite to either or both (preferably both) of the first channel region 26 and the second channel region 27. The upper portion 33 of the electrode is preferably opposite to the entire area of ​​the first channel region 26 in the stacking direction when viewed in cross-section. The upper portion 33 of the electrode is preferably opposite to the entire area of ​​the second channel region 27 in the stacking direction when viewed in cross-section.

[0109] The electrode corner portion 41 can be arranged in various ways depending on the arrangement of the upper electrode portion 33. When viewed from above, the upper electrode portion 33 is formed at intervals from at least one direction inward of the first electrode side portion 34 and the second electrode side portion 35 of the gate electrode 32, the electrode corner portion 41 is formed in the region of at least one side of the first electrode side portion 34 and the second electrode side portion 35.

[0110] In this configuration, the upper electrode portion 33 is formed spaced inwardly from both the first electrode side portion 34 and the second electrode side portion 35 of the gate electrode 32. Therefore, the electrode corner portion 41 has an electrode corner portion 41A that is located relative to the region of the upper electrode portion 33 on the first electrode side portion 34, and an electrode corner portion 41B that is located relative to the region of the upper electrode portion 33 on the second electrode side portion 35 (see reference). Figure 5 as well as Figure 7 ).

[0111] One electrode corner portion 41A is connected to the first electrode side portion 34 from one peripheral edge of the upper electrode portion 33. The electrode corner portion 41A extends in a strip shape along the upper electrode portion 33 in the second direction Y. Another electrode corner portion 41B is connected to the second electrode side portion 35 from the other peripheral edge of the upper electrode portion 33. The other electrode corner portion 41B is opposite to one electrode corner portion 41A in the first direction X, across the upper electrode portion 33, and extends in a strip shape along the upper electrode portion 33 in the second direction Y.

[0112] An electrode corner portion 41A is opposite to the first source region 23 in the stacking direction. An electrode corner portion 41A may also be opposite only to the first source region 23 in the stacking direction. An electrode corner portion 41A may also be opposite to both the first source region 23 and the first channel region 26 in the stacking direction. An electrode corner portion 41A may also be opposite to the surface drift region 22, the first source region 23, and the first channel region 26 in the stacking direction.

[0113] In view of the responsiveness of the switching speed, preferably one of the electrode corner portions 41A is formed at intervals from the first channel region 26 toward the first electrode side portion 34 when viewed from above. That is, preferably one electrode corner portion 41A is not opposite to the first channel region 26 in the stacking direction when viewed in cross section.

[0114] Another electrode corner 41B is opposite to the second source region 24 in the stacking direction. Alternatively, the other electrode corner 41B may be opposite only to the second source region 24 in the stacking direction. Another electrode corner 41B may also be opposite to both the second source region 24 and the second channel region 27 in the stacking direction. Another electrode corner 41B may also be opposite to the surface drift region 22, the second source region 24, and the second channel region 27 in the stacking direction.

[0115] In view of the responsiveness of the switching speed, the other electrode corner 41B is preferably formed at intervals from the second channel region 27 toward the second electrode side 35 when viewed from above. That is, the other electrode corner 41B is preferably not opposite to the second channel region 27 in the stacking direction when viewed in cross section.

[0116] Reference Figure 4 , Figure 5 as well as Figure 8 The semiconductor device 1 includes a p-type terminal region 45 formed on a first main surface 3 in an outer peripheral region 9. The terminal region 45 may also be referred to as a "well region," "terminal well region," etc., and may have a p-type impurity concentration approximately equal to that of the outer body region 21. The p-type impurity concentration of the terminal region 45 may be higher or lower than that of the outer body region 21.

[0117] Terminal region 45 is formed inwardly from the periphery of the first main surface 3 in the area between the periphery of the first main surface 3 and the outer main body region 21. Terminal region 45 extends in a strip-like shape along the outer main body region 21 when viewed from above. Terminal region 45 has a portion extending in a strip-like shape along a first direction X and a portion extending in a strip-like shape along a second direction Y when viewed from above, thus dividing the active region 8 in multiple directions.

[0118] In this configuration, the terminal region 45, when viewed from above, surrounds the outer main body region 21 and is divided into a polygonal ring with four sides parallel to the periphery of the first main surface 3 (in this configuration, a quadrilateral ring). The terminal region 45 may also have an edge portion that, when viewed from above, connects the portion extending along the first direction X and the portion extending along the second direction Y in an arc shape (preferably a quarter arc shape) (see reference). Figure 4 ).

[0119] The terminal region 45 is formed spaced apart from the bottom of the first semiconductor region 6 toward the first main surface 3, and faces the second semiconductor region 7 across a portion of the first semiconductor region 6. Preferably, the terminal region 45 is formed spaced apart from the middle portion of the first semiconductor region 6 toward the first main surface 3. The terminal region 45 may also have a thickness (depth) approximately equal to the thickness (depth) of the outer body region 21. The thickness of the terminal region 45 may be greater than or less than the thickness of the outer body region 21.

[0120] The terminal region 45 has an inner edge on the side of the active region 8 and an outer edge on the peripheral side of the first main surface 3. The inner edge of the terminal region 45 is connected to the outer edge of the outer main body region 21. Thus, the terminal region 45 is fixed to the same potential as the outer main body region 21 and is electrically connected to the plurality of main body regions 20 via the outer main body region 21. In this manner, the inner edge of the terminal region 45 is connected to the outer edge of the outer main body region 21 around its entire circumference.

[0121] The terminal region 45 (inner edge) has an overlapping region 46 that overlaps with the outer edge of the outer body region 21. The overlapping region 46 is a high-concentration region including both the outer edge of the outer body region 21 and the inner edge of the terminal region 45. That is, the overlapping region 46 includes both the p-type impurities of the outer body region 21 and the p-type impurities of the terminal region 45, and has a higher p-type impurity concentration than both the p-type impurity concentrations of the outer body region 21 and the terminal region 45.

[0122] The overlapping region 46 extends in a strip shape along the outer main body region 21 when viewed from above. The overlapping region 46, when viewed from above, has a portion extending in a strip shape in a first direction X and a portion extending in a strip shape in a second direction Y, dividing the active region 8 from multiple directions. In this configuration, the overlapping region 46 is divided into a polygonal ring shape (in this configuration, a quadrilateral ring shape) with four sides parallel to the periphery of the first main surface 3. The width of the overlapping region 46 is preferably greater than the width of the main body region 20. Of course, the width of the overlapping region 46 can also be less than the width of the main body region 20.

[0123] Semiconductor device 1 may also have a well region (46) with a relatively high concentration of p-type impurities instead of overlapping region 46. In this case, the well region (46) has a higher p-type impurity concentration than both the p-type impurity concentration of the outer body region 21 and the p-type impurity concentration of the terminal region 45. The well region (46) may also be formed in either or both of the surface portion of the outer body region 21 and the surface portion of the terminal region 45.

[0124] Semiconductor device 1 includes at least one (preferably two or more and less than 20) p-type field regions 47 formed in the outer peripheral region 9 on the surface portion of the first main surface 3. The number of field regions 47 is typically three or more and less than eight. In this configuration, semiconductor device 1 includes three field regions 47. The field regions 47 are formed in an electrically floating state to mitigate the electric field within the chip 2 at the periphery of the first main surface 3. The number, spacing, width, depth, p-type impurity concentration, etc., of the field regions 47 are arbitrary and can be varied depending on the electric field to be mitigated.

[0125] Field region 47 may also have a p-type impurity concentration that is approximately equal to that of the main region 20 (terminal region 45). The p-type impurity concentration of field region 47 may be higher or lower than that of the main region 20 (terminal region 45).

[0126] Multiple field regions 47 are spaced apart from the periphery of the first main surface 3 and formed in the region between the periphery of the first main surface 3 and the active region 8. Specifically, the multiple field regions 47 are formed in the region between the periphery of the first main surface 3 and the outer main body region 21. More specifically, the multiple field regions 47 are arranged in a spaced-apart manner from the terminal region 45 toward the periphery of the first main surface 3 in the region between the periphery of the first main surface 3 and the terminal region 45.

[0127] Multiple field regions 47 are formed in a strip shape extending along the active region 8 (terminal region 45) when viewed from above. Each of the multiple field regions 47 has a portion extending in a strip shape in a first direction X and a portion extending in a strip shape in a second direction Y. In this configuration, the multiple field regions 47 are formed in a polygonal ring shape (in this configuration, a quadrilateral ring shape) surrounding the active region 8 (terminal region 45) when viewed from above. The multiple field regions 47 may also have an edge portion (see reference) connecting the portions extending in the first direction X and the portions extending in the second direction Y in an arc shape (preferably a quarter arc shape). Figure 4 ).

[0128] Multiple field regions 47 are formed at intervals from the bottom of the first semiconductor region 6 toward the first main surface 3, and are opposite to the second semiconductor region 7 across a portion of the first semiconductor region 6. Preferably, the multiple field regions 47 are formed at intervals from the middle portion of the first semiconductor region 6 toward the first main surface 3.

[0129] Reference Figure 8The semiconductor device 1 includes a peripheral insulating film 51 covering the first main surface 3 in the peripheral region 9. The peripheral insulating film 51 may also include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this configuration, the peripheral insulating film 51 has a single-layer structure composed of a silicon oxide film. Particularly preferably, the peripheral insulating film 51 comprises a silicon oxide film composed of an oxide of the chip 2. The peripheral insulating film 51 is preferably composed of an insulating material of the same type as the insulating material of the insulating film 31. The peripheral insulating film 51 preferably has a thickness substantially equal to that of the insulating film 31.

[0130] The peripheral insulating film 51 covers the first main surface 3 in a film-like manner in the peripheral region 9. The peripheral insulating film 51 covers the outer main body region 21, the terminal region 45, and the multiple field regions 47. The peripheral insulating film 51 is connected to the multiple insulating films 31 on the active region 8 side. Specifically, the peripheral insulating film 51 is integrally formed with the multiple insulating films 31, forming a single insulating film with the multiple insulating films 31.

[0131] Reference Figure 4 , Figure 5 as well as Figure 8 The semiconductor device 1 includes a gate wiring 52 disposed on a first main surface 3 in an outer peripheral region 9. The semiconductor device 1 does not have insulating sidewall structures (spacers) on the sides of the gate wiring 52. The gate wiring 52 is selectively wound on the first main surface 3 and has portions extending in directions different from those of a plurality of gate electrodes 32. The gate wiring 52 is connected to the plurality of gate electrodes 32, imparting gate signals to the plurality of gate electrodes 32. The gate wiring 52 may also be referred to as a "polysilicon gate wiring," "polycrystalline gate wiring," "second gate electrode," etc.

[0132] Gate wiring 52 comprises conductive semiconductor polysilicon. Gate wiring 52 may also comprise either or both of p-type and n-type conductive polysilicon. Gate wiring 52 preferably has the same conductivity type as gate electrode 32. The conductivity type of gate wiring 52 is adjusted according to the conductivity type of gate electrode 32.

[0133] Gate wiring 52 is disposed on the outer peripheral insulating film 51 in the outer peripheral region 9. Specifically, gate wiring 52 is disposed on a portion of the outer peripheral insulating film 51 that covers the outer main body region 21, and is opposed to the outer main body region 21 through the outer peripheral insulating film 51. Gate wiring 52 is formed at intervals from the periphery of the first main surface 3 toward the active region 8, and extends in a strip shape along the active region 8. When viewed from above, gate wiring 52 has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y, dividing the active region 8 from multiple directions.

[0134] In this configuration, the gate wiring 52, when viewed from above, surrounds the active region 8 and is divided into a polygonal ring with four sides parallel to the periphery of the first main surface 3 (in this configuration, a quadrilateral ring). The gate wiring 52 can also be terminal or ring-shaped. In this configuration, the gate wiring 52 extends in a strip shape (in this configuration, a ring) along the outer body region 21 when viewed from above, and is opposed to the outer body region 21 across the entire region in the stacking direction by the outer peripheral insulating film 51. The gate wiring 52 may also have an edge portion (see reference) where the portion extending along the first direction X and the portion extending along the second direction Y when viewed from above are connected in an arc shape (preferably a quarter arc shape). Figure 4 ).

[0135] The gate wiring 52 is formed to be narrower than the outer body region 21 when viewed from above, and is disposed on the outer body region 21 at intervals from the inner edge and the outer edge of the outer body region 21. That is, in this manner, a plurality of gate electrodes 32 are led out onto the outer body region 21, and the gate wiring 52 is connected to the plurality of gate electrodes 32 on the outer body region 21.

[0136] The width of the gate wiring 52 is preferably greater than the width of the gate electrode 32. The width of the gate wiring 52 is the width in a direction orthogonal to the extension direction. Of course, the width of the gate wiring 52 can also be less than the width of the gate electrode 32. The width of the gate wiring 52 can also be greater than the width of the outer body region 21. The thickness of the gate wiring 52 is preferably approximately equal to the thickness of the gate electrode 32.

[0137] The gate wiring 52 has a wiring upper portion 53, a first wiring side portion 54 on the inner edge side, and a second wiring side portion 55 on the outer edge side. The wiring upper portion 53 extends along the outer peripheral insulating film 51 (first main surface 3). The wiring upper portion 53 may also extend substantially parallel to the outer peripheral insulating film 51 (first main surface 3). The wiring upper portion 53 may also be referred to as the wiring upper wall. The first wiring side portion 54 extends vertically in the Z direction above the outer peripheral insulating film 51, and the second wiring side portion 55 extends vertically in the Z direction above the outer peripheral insulating film 51.

[0138] The first wiring side 54 is connected to a plurality of gate electrodes 32 (first electrode side 34 and second electrode side 35) at a portion extending along the first direction X. That is, the gate wiring 52 has a plurality of portions connected in a T-shape relative to the plurality of gate electrodes 32. Thus, the gate wiring 52 is fixed to the same potential as the plurality of gate electrodes 32.

[0139] The first wiring side 54 and the second wiring side 55 may also extend perpendicularly to the outer peripheral insulating film 51. That is, the gate wiring 52 may also be formed into a quadrilateral shape (a flat rectangular shape) in cross-section. The first wiring side 54 and the second wiring side 55 may also be inclined toward the wiring upper portion 53. In other words, the gate wiring 52 may also be formed into a conical shape (preferably an isosceles trapezoidal shape) in cross-section. The first wiring side 54 and the second wiring side 55 may also be referred to as the first wiring sidewall and the second wiring sidewall, respectively.

[0140] Reference Figure 8 and Figure 9 The gate wiring 52 includes a wiring corner 61 that connects the upper wiring portion 53 to the first wiring side portion 54 and the second wiring side portion 55. The wiring corner 61 is formed by a portion of the material of the gate wiring 52 being missing. In this manner, the wiring corner 61 is formed by a recess that bends inward toward the gate wiring 52. Thus, the upper wiring portion 53 is partially formed on the surface portion of each gate wiring 52 when viewed from above.

[0141] When viewed from above, the upper portion 53 of the wiring is formed spaced inward from at least one of the first wiring side portion 54 and the second wiring side portion 55 of the gate wiring 52, exposing at least one of the peripheral portions of the first wiring side portion 54 and the second wiring side portion 55. In this configuration, the upper portion 53 of the wiring is formed spaced inward from both the first wiring side portion 54 and the second wiring side portion 55, exposing both the peripheral portions of the first wiring side portion 54 and the peripheral portions of the second wiring side portion 55.

[0142] The upper wiring portion 53 extends in a strip shape along the gate wiring 52 when viewed from above, and is opposite to the outer body region 21 in the stacking direction. The upper wiring portion 53 has a portion that extends in a strip shape along a first direction X and a portion that extends in a strip shape along a second direction Y when viewed from above. In this configuration, the upper wiring portion 53 surrounds the active region 8 when viewed from above and is divided into a polygonal ring shape (in this configuration, a quadrilateral ring shape) with four sides parallel to the periphery of the first main surface 3.

[0143] The upper portion 53 of the wiring can also be end-shaped or loop-shaped. The upper portion 53 of the wiring can also have an edge portion that connects the portion extending along the first direction X and the portion extending along the second direction Y into an arc shape (preferably a quarter arc shape) when viewed from above.

[0144] The upper portion 53 of the wiring is connected to the upper portions 33 of the multiple gate electrodes 32 and the gate wiring 52. That is, the upper portion 53 of the wiring is integrally formed with the upper portions 33 of the multiple electrodes and has multiple portions that are connected in a T-shape relative to the upper portions 33 of the multiple electrodes (see reference). Figure 5 ).

[0145] The wiring corner 61 adopts various layouts depending on the layout of the wiring upper portion 53. When the wiring upper portion 53 is formed at intervals from at least one of the first wiring side portion 54 and the second wiring side portion 55 of the gate wiring 52, the wiring corner 61 is formed in the wiring upper portion 53 in the region of at least one of the first wiring side portion 54 and the second wiring side portion 55.

[0146] In this configuration, the upper wiring portion 53 is formed spaced inwardly from both the first wiring side portion 54 and the second wiring side portion 55 of the gate wiring 52. Therefore, the wiring corner portion 61 has a wiring corner portion 61A on one side of the region of the upper wiring portion 53 that is divided on the first wiring side portion 54, and a wiring corner portion 61B on the other side of the region of the upper wiring portion 53 that is divided on the second wiring side portion 55 (see reference). Figure 5 as well as Figure 9 ).

[0147] One wiring corner 61A is connected to the first wiring side 54 of the gate wiring 52 from one peripheral edge of the wiring upper portion 53. One wiring corner 61A extends in a strip along the wiring upper portion 53. Another wiring corner 61B is connected to the second wiring side 55 of the gate wiring 52 from the other side of the wiring upper portion 53. Another wiring corner 61B is opposite to the wiring corner 61B on one side across the wiring upper portion 53 and extends in a strip along the wiring upper portion 53.

[0148] Wiring corner 61 (one wiring corner 61A) is connected to multiple electrode corners 41 at the connection points of the multiple gate electrodes 32 and the gate wiring 52. That is, wiring corner 61 and multiple electrode corners 41 are integrally formed. Wiring corner 61 has multiple portions that are L-shapedly connected to the connection points of the multiple gate electrodes 32 and the gate wiring 52 relative to the multiple electrode corners 41 (see reference). Figure 5 ).

[0149] Semiconductor device 1 includes an insulating interlayer film 70 covering a first main surface 3. The interlayer film 70 may also be referred to as an "interlayer insulating film," "intermediate insulating film," etc. The interlayer film 70 covers both the active region 8 and the peripheral region 9 on the first main surface 3.

[0150] Interlayer film 70 covers multiple gate structures 30 in the active region 8. For each gate structure 30, interlayer film 70 directly covers both the insulating film 31 and the gate electrode 32. That is, interlayer film 70 has portions that directly cover the upper electrode portion 33, the first electrode side portion 34, the second electrode side portion 35, and the electrode corner portion 41 of the gate electrode 32.

[0151] Interlayer film 70 sandwiches peripheral insulating film 51 within peripheral region 9, simultaneously covering outer main body region 21, terminal region 45, and multiple field regions 47. Interlayer film 70 directly covers both peripheral insulating film 51 and gate wiring 52. That is, interlayer film 70 has portions that directly cover the upper wiring portion 53, first wiring side portion 54, second wiring side portion 55, and wiring corner portion 61 of gate wiring 52. In this configuration, interlayer film 70 is connected to the first to fourth side surfaces 5A to 5D. Interlayer film 70 may also be formed with gaps between the first to fourth side surfaces 5A to 5D, exposing the peripheral portion (first semiconductor region 6) of the first main surface 3.

[0152] In this configuration, the interlayer film 70 has a laminated structure comprising a first oxide film 72 (first insulating film) and a second oxide film 73 (second insulating film) sequentially stacked from the first main surface 3. The first oxide film 72 has a monolayer structure composed of an unadulterated silicon oxide film. The first oxide film 72 may also be referred to as an NSG film (Nondoped Silicate Glass film).

[0153] The first oxide film 72 covers both the active region 8 and the peripheral region 9. The first oxide film 72 covers multiple gate structures 30 in the active region 8. The first oxide film 72 covers both sides of the insulating film 31 and the gate electrode 32 with respect to each gate structure 30 in a film-like manner.

[0154] The first oxide film 72 has a first covering portion 74, a second covering portion 75, and a third covering portion 76. The first covering portion 74 extends horizontally in a film-like manner along the insulating film 31 (first main surface 3) and has a portion that contacts the first electrode side portion 34 (second electrode side portion 35) of the gate electrode 32. In this configuration, the first covering portion 74 (first oxide film 72) has a thickness less than that of the gate electrode 32 and covers the insulating film 31 at intervals from the height position of the upper electrode portion 33 of the gate electrode 32 toward the insulating film 31.

[0155] The second cover portion 75 extends from the first cover portion 74 toward the stacking direction to the upper electrode portion 33 side, and directly covers the first electrode side portion 34 (second electrode side portion 35) and the electrode corner portion 41 in a film-like manner.

[0156] The third cover 76 extends from the second cover 75 toward the upper electrode 33 and extends in a film-like manner along the upper electrode 33 in the horizontal direction. The third cover 76 directly covers the entire area of ​​the upper electrode 33 between one electrode corner 41A and the other electrode corner 41B.

[0157] The first oxide film 72 sandwiches the outer peripheral insulating film 51 in the outer peripheral region 9 and covers the outer body region 21, the terminal region 45, and multiple field regions 47. The first oxide film 72 covers the gate wiring 52 in the outer peripheral region 9.

[0158] The first oxide film 72 has a first wiring cover 77, a second wiring cover 78, and a third wiring cover 79. The first wiring cover 77 extends horizontally along the outer peripheral insulating film 51 (first main surface 3) in a film-like manner and has a portion that connects to the first wiring side 54 (second wiring side 55) of the gate wiring 52. In this configuration, the first wiring cover 77 (first oxide film 72) has a thickness less than that of the gate wiring 52 and covers the outer peripheral insulating film 51 at intervals from the height position of the upper wiring portion 53 of the gate wiring 52 toward the outer peripheral insulating film 51.

[0159] The second wiring cover 78 extends from the first wiring cover 77 toward the wiring upper part 53 in the stacking direction, and directly covers the first electrode side 34 (second electrode side 35) and the wiring corner 61 in a film-like manner.

[0160] The third wiring cover 79 extends from the second wiring cover 78 toward the upper wiring portion 53 and extends horizontally in a membrane-like manner along the upper wiring portion 53. The third wiring cover 79 directly covers the entire area of ​​the upper wiring portion 53 between one wiring corner portion 61A and the other wiring corner portion 61B.

[0161] The second oxide film 73 can have a single-layer structure composed of a phosphorus-containing silicon oxide film, or a multilayer structure including a phosphorus-containing silicon oxide film. The phosphorus-containing silicon oxide film may contain boron. The phosphorus-containing silicon oxide film can also be called a PSG film (Phosphorus Silicon Glass film). A silicon oxide film containing both phosphorus and boron can also be called a BPSG film (Boron Phosphorus Silicon Glass film).

[0162] The second oxide film 73 may also have a monolayer structure consisting of a PSG film or a BPSG film stacked on the first oxide film 72. Alternatively, the second oxide film 73 may have a laminated structure including a PSG film stacked on the first oxide film 72 and a BPSG film stacked on top of the PSG film. In this embodiment, as an example, the second oxide film 73 has a monolayer structure consisting of a PSG film.

[0163] The second oxide film 73 covers the first oxide film 72 in a film-like manner, and together with the first oxide film 72, covers the active region 8 and the outer peripheral region 9. The second oxide film 73 sandwiches the first oxide film 72 in the active region 8 and together covers multiple gate structures 30. Specifically, the second oxide film 73 covers both the insulating film 31 and the gate electrode 32 in a film-like manner, with the first oxide film 72 in a film-like manner.

[0164] The second oxide film 73 includes a first upper cover portion 80 and a second upper cover portion 81. The first upper cover portion 80 covers the first cover portion 74 and the second cover portion 75 of the first oxide film 72. The portion of the first upper cover portion 80 above the first cover portion 74 sandwiches the insulating film 31 covered by the first cover portion 74.

[0165] The first upper cover portion 80 extends in a film-like manner from the first cover portion 74 along the second cover portion 75 in the stacking direction, covering the first electrode side portion 34 (second electrode side portion 35) and the electrode corner portion 41 of the gate structure 30 through the second cover portion 75. That is, the first upper cover portion 80 has a portion that covers the first electrode side portion 34 (second electrode side portion 35) and the electrode corner portion 41 through the second cover portion 75.

[0166] The second upper cover portion 81 covers the third cover portion 76 of the first oxide film 72. The second upper cover portion 81 extends horizontally in a film-like manner from the first upper cover portion 80 along the third cover portion 76, covering the upper electrode portion 33 of the gate structure 30 across the third cover portion 76. The second upper cover portion 81 sandwiches the third cover portion 76 between one electrode corner portion 41A and the other electrode corner portion 41B, thus covering the entire area of ​​the upper electrode portion 33.

[0167] The second upper cover portion 81 has a portion that covers the upper part 33 of the electrode through the first oxide film 72 (third cover portion 76) and a portion that covers the corner portion 41 of the electrode through the first oxide film 72 (second cover portion 75).

[0168] The second oxide film 73 sandwiches the outer peripheral insulating film 51 and the first oxide film 72 in the outer peripheral region 9, and together covers the outer body region 21, the terminal region 45, and multiple field regions 47. The second oxide film 73 covers the gate wiring 52 in the outer peripheral region 9 through the first oxide film 72.

[0169] The second oxide film 73 includes a first upper wiring cover portion 82 and a second upper wiring cover portion 83. The first upper wiring cover portion 82 covers the first wiring cover portion 77 and the second wiring cover portion 78 of the first oxide film 72. The portion of the first upper wiring cover portion 82 above the first wiring cover portion 77 covers the outer peripheral insulating film 51 across the first wiring cover portion 77.

[0170] The first upper wiring cover portion 82 extends in a film-like manner from the first wiring cover portion 77 along the second wiring cover portion 78 in the stacking direction, covering the first wiring side portion 54 (second wiring side portion 55) and the wiring corner portion 61 through the second wiring cover portion 78. That is, the first upper wiring cover portion 82 has a portion that covers the first wiring side portion 54 (second wiring side portion 55) and the wiring corner portion 61 through the second wiring cover portion 78.

[0171] The second upper wiring cover 83 covers the third wiring cover 79 of the first oxide film 72. The second upper wiring cover 83 extends horizontally in a film-like manner from the first upper wiring cover 82 along the third wiring cover 79, covering the upper portion 53 of the wiring through the third wiring cover 79. The second upper wiring cover 83 sandwiches the third wiring cover 79 between one wiring corner 61A and the other wiring corner 61B, thus covering the entire area of ​​the upper portion 53 of the wiring.

[0172] The second upper wiring cover 83 has a portion that covers the upper part 53 of the wiring through the first oxide film 72 (third wiring cover 79) and a portion that covers the corner 61 of the wiring through the first oxide film 72 (second wiring cover 78).

[0173] The semiconductor device 1 includes a plurality of source openings 90 formed in an interlayer film 70 in an active region 8. The plurality of source openings 90 are formed at intervals to the sides of the plurality of gate electrodes 32, exposing a first main surface 3 (chip 2). Specifically, the plurality of source openings 90 are formed in the region between the plurality of gate electrodes 32, penetrating the insulating film 31 and the interlayer film 70.

[0174] Multiple source openings 90 penetrate both the first oxide film 72 and the second oxide film 73, and have walls defined by the first oxide film 72 and the second oxide film 73. The multiple source openings 90 expose the corresponding multiple source regions 23, 24 and the contact region 25 respectively.

[0175] In this configuration, a plurality of source openings 90 are formed at intervals in the first direction X, and are respectively formed as stripes extending in the second direction Y. That is, the plurality of source openings 90 are formed as stripes extending in the second direction Y. The plurality of source openings 90 are formed at intervals from the gate wiring 52 in the second direction Y. That is, the plurality of source openings 90 are formed in the region surrounded by the plurality of gate electrodes 32 and the gate wiring 52.

[0176] Multiple source openings 90 may also be formed in the region between two adjacent gate structures 30 along the first direction X. In this case, the multiple source openings 90 may also be arranged in a row with intervals in the second direction Y. Moreover, in this case, each source opening 90 may be formed in a quadrilateral shape (square), a rectangular shape extending along the first direction X, a rectangular shape extending along the second direction Y, a hexagonal shape, a circular shape, etc. when viewed from above.

[0177] The source opening 90 may have a width W of 0.2 μm or more and 3 μm or less. The width W of the source opening 90 is preferably 0.3 μm or more and 1 μm or less. The source opening 90 may have a depth D of 0.2 μm or more and 2 μm or less. The depth D of the source opening 90 is preferably 0.5 μm or more and 1 μm or less.

[0178] The source opening 90 preferably has an aspect ratio D / W of 0.3 or more and 3 or less. The aspect ratio D / W is defined by the ratio of the depth D of the source opening 90 to the width W of the source opening 90. The aspect ratio D / W is preferably 0.5 or more and 2 or less. Particularly preferred is an aspect ratio D / W greater than 1. According to this structure, a plurality of gate structures 30 are arranged with a narrow pitch.

[0179] The semiconductor device 1 includes a plurality of source recesses 91 formed in portions of the first main surface 3 that are exposed from a plurality of source openings 90. The semiconductor device 1 is not required to have source recesses 91. Therefore, a structure without source recesses 91 may also be used.

[0180] Multiple source recesses 91 each have a planar shape matching the planar shape of a corresponding source opening 90, and are recessed from the first main surface 3 toward the second main surface 4. The multiple source recesses 91 are formed at intervals from the bottom of the corresponding main body region 20 toward the first main surface 3, exposing the corresponding multiple source regions 23, 24 and contact regions 25. Specifically, the multiple source recesses 91 are formed at intervals from the bottom of the corresponding multiple source regions 23, 24 (contact regions 25) toward the first main surface 3.

[0181] The semiconductor device 1 includes at least one (or multiple) external openings 92 formed in an interlayer film 70 in a peripheral region 9. The multiple external openings 92 are formed in the interlayer film 70 in portions covering a terminal region 45. The multiple external openings 92 penetrate the interlayer film 70, exposing the terminal region 45. In this embodiment, the multiple external openings 92 are formed in the interlayer film 70 in portions covering an overlapping region 46 of the terminal region 45, exposing the overlapping region 46.

[0182] Multiple external openings 92 may also replace the terminal region 45 (overlapping region 46) or, based thereon, expose the outer main body region 21. The multiple external openings 92 penetrate both the first oxide film 72 and the second oxide film 73, and have a wall surface defined by both the first oxide film 72 and the second oxide film 73.

[0183] Multiple external openings 92 are formed at intervals along the terminal region 45 (overlapping region 46) (see reference). Figure 4 and Figure 5 The multiple external openings 92 can also be formed in a quadrilateral (square), rectangular, hexagonal, circular, or other shapes when viewed from above. The multiple external openings 92 can also be formed in a strip shape that extends along the terminal region 45 (overlapping region 46) when viewed from above. Like the source opening 90, the external openings 92 can also have an aspect ratio D / W (preferably greater than 1).

[0184] The semiconductor device 1 may also have a single external opening 92. The single external opening 92 may also be formed as a strip extending along the terminal region 45 (overlapping region 46). The single external opening 92 may also have a portion extending in a strip shape along a first direction X and a portion extending in a strip shape along a second direction Y when viewed from above.

[0185] The single outer opening 92 can also be formed as a polygonal ring with four sides parallel to the periphery of the first main surface 3, either end-shaped or ring-shaped (in this case, a quadrilateral ring). The single outer opening 92 can also have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y, which, when viewed from above, mimic the terminal region 45 (overlapping region 46), into an arc shape (preferably a quarter arc shape).

[0186] The semiconductor device 1 includes a plurality of recesses 93 formed in portions of the first main surface 3 that are exposed from a plurality of external openings 92. The semiconductor device 1 does not necessarily need to have the recesses 93. Therefore, a structure without the recesses 93 may also be used.

[0187] Multiple recesses 93 each have a planar shape that matches the planar shape of the corresponding external opening 92, and are recessed from the first main surface 3 toward the second main surface 4. The multiple recesses 93 are formed at intervals from the bottom of the terminal region 45 (overlapping region 46) toward the first main surface 3, thus exposing the terminal region 45 (overlapping region 46) respectively. In the case of a single external opening 92, a single external recess 93 is formed that matches the planar shape of the single external opening 92.

[0188] The semiconductor device 1 includes at least one (in this case, multiple) gate openings 94 formed in an interlayer film 70 in an outer peripheral region 9. The multiple gate openings 94 are formed in the interlayer film 70 covering portions of the gate wiring 52. The multiple gate openings 94 penetrate the interlayer film 70, exposing the upper portion 53 of the gate wiring 52.

[0189] Specifically, multiple gate openings 94 expose the upper portion 53 of the gate wiring 52. More specifically, multiple gate openings 94 expose the upper portion 53 of the wiring at intervals from the corner 61 inward. Multiple gate openings 94 expose only the upper portion 53 of the wiring, without exposing the corner 61. Of course, one or more gate openings 94 may be formed that expose the corner 61 of the wiring.

[0190] Multiple gate openings 94 penetrate both the first oxide film 72 and the second oxide film 73, and have walls divided by the first oxide film 72 and the second oxide film 73.

[0191] Multiple gate openings 94 are formed at intervals along gate wiring 52 (upper wiring 53) (see reference). Figure 4 as well as Figure 5 The multiple gate openings 94 can also be formed in a quadrilateral (square), rectangular, hexagonal, circular, or other shapes when viewed from above. The multiple gate openings 94 can also be formed as a strip extending along the gate wiring 52 when viewed from above. The gate openings 94 can have the same aspect ratio D / W (preferably greater than 1) as the source openings 90.

[0192] Semiconductor device 1 may also have a single gate opening 94. The single gate opening 94 may also be formed as a strip extending along the gate wiring 52. The single gate opening 94 may also have a portion extending in a strip shape along a first direction X and a portion extending in a strip shape along a second direction Y when viewed from above.

[0193] The single gate opening 94 can also be formed as a polygonal ring with four sides parallel to the periphery of the first main surface 3, either end-shaped or ring-shaped (in this case, a quadrilateral ring). The single gate opening 94 can also have an edge portion that connects the portion extending in the first direction X, which mimics the gate wiring 52 (wiring upper portion 53) when viewed from above, and the portion extending in the second direction Y, into an arc shape (preferably a quarter arc shape).

[0194] Reference Figure 1 The semiconductor device 1 includes a source pad electrode 95 disposed on an interlayer film 70. The source pad electrode 95 is a terminal electrode on which a source potential is applied from the outside. The source pad electrode 95 may also be referred to as a "first pad electrode", "first main surface electrode", "first terminal electrode", etc.

[0195] The source pad electrode 95 is disposed on the portion of the interlayer film 70 covering the active region 8. The source pad electrode 95 covers multiple gate electrodes 32 through the interlayer film 70 and is electrically isolated from the multiple gate electrodes 32 by the interlayer film 70. The source pad electrode 95 is electrically connected to multiple body regions 20, outer body region 21, multiple source regions 23, 24, contact region 25, etc., through multiple source openings 90.

[0196] In this configuration, the source pad electrode 95 has a first pad portion 96, a second pad portion 97, and a third pad portion 98. The first pad portion 96 has a relatively large planar area, forming the main body of the source pad electrode 95. In this configuration, the first pad portion 96 is formed into a polygonal shape (quadrilateral shape in this configuration) with four sides parallel to the periphery of the chip 2 when viewed from above, and is offset towards the fourth side 5D side relative to the center of the active region 8. The first pad portion 96 covers multiple gate electrodes 32 through the interlayer film 70 and is electrically connected to multiple main body regions 20 via multiple source openings 90.

[0197] The second pad portion 97 has a planar area smaller than that of the first pad portion 96, and extends in a strip shape (quadrilateral shape) from one end of the first pad portion 96 in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C side. The second pad portion 97 covers a plurality of gate electrodes 32 through the interlayer film 70, and is electrically connected to a plurality of body regions 20 via a plurality of source openings 90.

[0198] The third pad portion 98 has a planar area smaller than that of the first pad portion 96, and extends in a strip shape (quadrilateral shape) from the other end of the first pad portion 96 in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C side, and is opposite to the second pad portion 97 in the second direction Y. The third pad portion 98 covers a plurality of gate electrodes 32 through the interlayer film 70, and is electrically connected to a plurality of body regions 20 via a plurality of source openings 90.

[0199] The planar area of ​​the third pad portion 98 can also be approximately equal to the planar area of ​​the second pad portion 97. Of course, the planar area of ​​the third pad portion 98 can be larger or smaller than the planar area of ​​the second pad portion 97. Either or both of the second pad portion 97 and the third pad portion 98 can be used as a terminal portion for current monitoring.

[0200] The source pad electrode 95 does not necessarily have both a second pad portion 97 and a third pad portion 98. The source pad electrode 95 may also have only one of the second pad portion 97 and the third pad portion 98. Of course, the source pad electrode 95 may also be composed only of the first pad portion 96, without the second pad portion 97 and the third pad portion 98.

[0201] Reference Figure 6 and Figure 7 The source pad electrode 95 includes a first base electrode film 100 and a first main electrode film 102. The first base electrode film 100 can also be referred to as the "source base electrode film", and the first main electrode film 102 can be referred to as the "source main electrode film".

[0202] The first base electrode film 100 forms the lower layer of the source pad electrodes 95 (first pad portion 96, second pad portion 97, and third pad portion 98), and covers the active region 8 with an interlayer film 70. The first base electrode film 100 covers the region of the interlayer film 70 where multiple source openings 90 are formed as a film. That is, the first base electrode film 100 extends from the interlayer film 70 into the multiple source openings 90.

[0203] The first base electrode film 100 has a portion that covers the upper surface of the interlayer film 70 in a film-like manner and a portion that covers the walls of the plurality of source openings 90 in a film-like manner. The first base electrode film 100 has recesses defined in each of the plurality of source openings 90. The first base electrode film 100 may also have a portion that partially covers the gate wiring 52 through the interlayer film 70. The first base electrode film 100 may also be formed at intervals from the gate wiring 52 inward when viewed from above.

[0204] Reference Figure 7 In this configuration, the first substrate electrode film 100 has a laminated structure comprising a first electrode film 103 laminated on an interlayer film 70 and a second electrode film 104 laminated on the first electrode film 103. In this configuration, the first electrode film 103 comprises a Ti film, and the second electrode film 104 comprises a TiN film.

[0205] The first substrate electrode film 100 does not necessarily need to have a laminated structure; it can also have a single-layer structure composed of either the first electrode film 103 (Ti film) or the second electrode film 104 (TiN film). The thickness of the first electrode film 103 can also be 10 nm or more and 100 nm or less. The thickness of the second electrode film 104 can also be 50 nm or more and 200 nm or less.

[0206] The first electrode film 103 covers the region of the interlayer film 70 where multiple source openings 90 are formed in a film-like manner, and extends from the interlayer film 70 into the multiple source openings 90. The first electrode film 103 has a portion that covers the upper surface of the interlayer film 70 in a film-like manner, and a portion that covers the wall surfaces of the multiple source openings 90 in a film-like manner. The first electrode film 103 directly covers the interlayer film 70.

[0207] That is, the first electrode film 103 directly covers the second oxide film 73. The first electrode film 103 is opposed to the plurality of gate electrodes 32 through the interlayer film 70.

[0208] The first electrode film 103 extends along the wall of the source opening 90, covering the insulating film 31, the first oxide film 72, and the second oxide film 73. The first electrode film 103 is positioned opposite the first electrode side 34 (second electrode side 35) of the gate electrode 32 across the interlayer film 70.

[0209] The first electrode film 103 covers the first main surface 3 in a film-like manner at the bottom of each source opening 90 and is electrically connected to the first main surface 3. Specifically, the first electrode film 103 has a portion at the bottom of each source opening 90 that covers the source recess 91 in a film-like manner and is electrically connected to multiple source regions 23, 24 and contact region 25.

[0210] The first electrode film 103 may also cover the source recess 91 in a film-like manner from the height position of the first main surface 3 toward the bottom side of the source recess 91 at intervals. The first electrode film 103 may also have a portion located on the bottom side of the source recess 91 relative to the height position of the first main surface 3, and a portion located on the insulating film 31 side relative to the height position of the first main surface 3.

[0211] The second electrode film 104 covers the region in the interlayer film 70 where multiple source openings 90 are formed on the first electrode film 103 in a film-like manner. The second electrode film 104 has a portion that covers the upper surface of the interlayer film 70 in a film-like manner, sandwiching the first electrode film 103, and a portion that covers the wall surface of the first electrode film 103 in a film-like manner, sandwiching the wall surface of the multiple source openings 90. The second electrode film 104 is positioned opposite to the multiple gate electrodes 32 through the first electrode film 103 and the interlayer film 70.

[0212] The second electrode film 104 extends along the wall of the source opening 90 and covers the insulating film 31, the first oxide film 72, and the second oxide film 73 through the first electrode film 103. The second electrode film 104 is opposite to the first electrode side 34 (second electrode side 35) of the gate electrode 32 through the first electrode film 103 and the interlayer film 70.

[0213] The second electrode film 104 has a portion that sandwiches the first electrode film 103 at the bottom of each source opening 90, covering the source recess 91 in a film-like form. It is electrically connected to the plurality of source regions 23, 24 and the contact region 25 via the first electrode film 103. When the first electrode film 103 is located on the bottom side of the source recess 91 relative to the first main surface 3, the second electrode film 104 may also have a portion located within the source recess 91. When the first electrode film 103 has a portion located above the first main surface 3, the entire second electrode film 104 is located above the source recess 91.

[0214] The first main electrode film 102 forms the upper portion of the source pad electrode 95 (first pad portion 96, second pad portion 97, and third pad portion 98) and covers the first base electrode film 100 in a film-like manner. The first main electrode film 102 includes a conductive material that is different from the conductive material of the first base electrode film 100.

[0215] The first main electrode film 102 may also include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may also include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The first main electrode film 102 has a thickness greater than the thickness (total thickness) of the first substrate electrode film 100.

[0216] The thickness of the first main electrode film 102 may also be 0.5 μm or more and 5 μm or less. The thickness of the first main electrode film 102 may also have a value belonging to at least one of the following ranges: 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0217] The first main electrode film 102 extends from the interlayer film 70 into the plurality of source openings 90, and is mechanically and electrically connected to the plurality of source regions 23, 24 and contact region 25. Thus, the first main electrode film 102 is positioned opposite the plurality of gate electrodes 32 across the first base electrode film 100 and the interlayer film 70. Specifically, the first main electrode film 102 is positioned opposite the upper electrode portion 33 and the electrode corner portion 41 of each gate electrode 32 across the first base electrode film 100 and the interlayer film 70.

[0218] Semiconductor device 1 includes a source finger electrode 110 extending from a source pad electrode 95 to an outer peripheral region 9. The source finger electrode 110 transfers the source potential imparted to the source pad electrode 95 to the outer peripheral region 9. In this manner, the source finger electrode 110 is wound from a portion of the source pad electrode 95 (first pad portion 96) on the fourth side 5D side to a portion of the interlayer film 70 covering the outer peripheral region 9.

[0219] The source finger electrode 110 is led out onto the terminal region 45 and electrically connected to the terminal region 45 via a plurality of external openings 92. Specifically, the source finger electrode 110 is electrically connected to the overlapping region 46 of the terminal region 45 via a plurality of external openings 92.

[0220] The source finger electrode 110 extends in a strip shape along the terminal region 45 (overlapping region 46). When viewed from above, the source finger electrode 110 has a portion extending in a strip shape in a first direction X and a portion extending in a strip shape in a second direction Y. In this configuration, the source finger electrode 110 is formed as a polygonal ring (in this configuration, a quadrilateral ring) with four sides parallel to the periphery of the first main surface 3, surrounding the source pad electrode 95. The source finger electrode 110 may also have an edge portion (see reference) where the portion extending in the first direction X and the portion extending in the second direction Y when viewed from above are connected in an arc shape (preferably a quarter arc shape). Figure 4 ).

[0221] The source finger electrode 110, like the source pad electrode 95, includes a first base electrode film 100 and a first main electrode film 102. The first base electrode film 100 forms the lower layer of the source finger electrode 110 and covers the outer peripheral region 9 with an interlayer film 70.

[0222] The first base electrode film 100 covers the region of the interlayer film 70 where multiple external openings 92 are formed in a film-like manner. That is, the first base electrode film 100 extends from the interlayer film 70 into the multiple external openings 92. The first base electrode film 100 has a portion that covers the upper surface of the interlayer film 70 in a film-like manner and a portion that covers the wall surfaces of the multiple external openings 92 in a film-like manner. The first base electrode film 100 divides recesses into the multiple external openings 92.

[0223] The first base electrode film 100, like the source pad electrode 95, has a stacked structure including a first electrode film 103 and a second electrode film 104. The first electrode film 103 covers the region of the interlayer film 70 where multiple external openings 92 are formed in a film-like manner, and extends from the interlayer film 70 into the multiple external openings 92. That is, the first electrode film 103 has a portion that covers the upper surface of the interlayer film 70 in a film-like manner, and a portion that covers the wall surface of the multiple external openings 92 in a film-like manner.

[0224] The first electrode film 103 covers the first main surface 3 in a film-like manner at the bottom of each external opening 92 and is electrically connected to the first main surface 3 (chip 2). Specifically, the first electrode film 103 has a portion at the bottom of each external opening 92 that covers the external recess 93 in a film-like manner, and is electrically connected to the terminal region 45 (overlapping region 46) within the external recess 93.

[0225] The first electrode film 103 may also be spaced apart from the height position of the first main surface 3 toward the bottom side of the outer recess 93 to cover the outer recess 93 in a film-like manner. The first electrode film 103 may have a portion located at the bottom side of the outer recess 93 relative to the height position of the first main surface 3, and a portion located on the side of the outer peripheral insulating film 51 relative to the height position of the first main surface 3.

[0226] The second electrode film 104 covers the region of the interlayer film 70 in which a plurality of external openings 92 are formed on the first electrode film 103 in a film-like manner. That is, the second electrode film 104 has a portion that sandwiches the first electrode film 103 and covers the upper surface of the interlayer film 70 in a film-like manner, and a portion that sandwiches the first electrode film 103 and covers the wall surface of the plurality of external openings 92 in a film-like manner.

[0227] The second electrode film 104 has a portion at the bottom of each external opening 92 that covers the outer recess 93 in a film-like manner through the first electrode film 103, and is electrically connected to the terminal region 45 (overlapping region 46) via the first electrode film 103. When the first electrode film 103 is located on the bottom side of the outer recess 93 relative to the first main surface 3, the second electrode film 104 may also have a portion located inside the outer recess 93. When the first electrode film 103 has a portion located above the first main surface 3, the entire second electrode film 104 is located above the outer recess 93.

[0228] The first main electrode film 102 forms the upper part of the source finger electrode 110 and covers the first base electrode film 100 in a film-like manner. The first main electrode film 102 extends from the interlayer film 70 into a plurality of external openings 92 and is mechanically and electrically connected to the terminal region 45 (overlapping region 46).

[0229] Semiconductor device 1 includes gate fingers 115 selectively wound on an interlayer film 70. Gate fingers 115 deliver gate potential to gate wiring 52. Gate fingers 115 are wound over a portion of the interlayer film 70 covering the gate wiring 52 (i.e., over the outer peripheral region 9) and electrically connected to the gate wiring 52 via a plurality of gate openings 94.

[0230] The gate finger electrode 115 is disposed spaced apart from the source pad electrode 95 and the source finger electrode 110 in the region between the source pad electrode 95 and the source finger electrode 110. The gate finger electrode 115 is disposed on the gate wiring 52 and extends in a strip shape along the gate wiring 52. When viewed from above, the gate finger electrode 115 has a portion extending in a strip shape in a first direction X and a portion extending in a strip shape in a second direction Y.

[0231] In this configuration, the gate finger electrode 115 is formed as an ended strip with four sides parallel to the periphery of the first main surface 3, surrounding the source pad electrode 95. The gate finger electrode 115 may also have an edge portion (see reference) where the portion extending in the first direction X and the portion extending in the second direction Y, when viewed from above, are connected in an arc shape (preferably a quarter arc shape). Figure 4 The gate finger electrode 115 has a pair of open terminals on the fourth side surface 5D side through which the source finger electrode 110 passes.

[0232] Reference Figure 9The gate finger electrode 115 includes a second base electrode film 120 and a second main electrode film 122. The second base electrode film 120 may also be referred to as the "gate base electrode film" and the second main electrode film 122 as the "gate main electrode film".

[0233] The second base electrode film 120 forms the lower layer of the gate finger electrode 115 and covers the interlayer film 70 in the outer peripheral region 9. The second base electrode film 120 covers the region in the interlayer film 70 where a plurality of gate openings 94 are formed as a film. That is, the second base electrode film 120 extends from the interlayer film 70 into the plurality of gate openings 94. The second base electrode film 120 has a portion that covers the upper surface of the interlayer film 70 in a film-like manner, and a portion that includes the wall surface of the plurality of gate openings 94 in a film-like manner. The second base electrode film 120 divides a plurality of recesses in the plurality of gate openings 94.

[0234] The second substrate electrode film 120 has a laminated structure including a first electrode film 123 laminated on the interlayer film 70 and a second electrode film 124 laminated on the first electrode film 123. Preferably, the first electrode film 123 comprises the same conductive material as the first electrode film 103 on the source side, and the second electrode film 124 comprises the same conductive material as the second electrode film 104 on the source side. In this embodiment, the first electrode film 123 comprises a Ti film, and the second electrode film 124 comprises a TiN film.

[0235] The second substrate electrode film 120 does not necessarily need to have a laminated structure; it can also have a single-layer structure composed of either the first electrode film 123 (Ti film) or the second electrode film 124 (TiN film). The first electrode film 123 can also have a thickness approximately equal to the thickness of the first electrode film 103 on the source side. The second electrode film 124 can also have a thickness approximately equal to the thickness of the second electrode film 104 on the source side.

[0236] The first electrode film 123 covers the region in the interlayer film 70 where the plurality of gate openings 94 are formed in a film-like manner, and extends from the interlayer film 70 into the plurality of gate openings 94. That is, the first electrode film 123 has a portion that covers the upper surface of the interlayer film 70 in a film-like manner, and a portion that covers the wall surface of the plurality of gate openings 94 in a film-like manner.

[0237] The first electrode film 123 covers the gate wiring 52 in a film-like manner at the bottom of each gate opening 94 and is electrically connected to the gate wiring 52. Specifically, the first electrode film 123 has a portion of the upper part 53 of the wiring that covers the gate wiring 52 in a film-like manner at the bottom of each gate opening 94 and is mechanically and electrically connected to the upper part 53 of the wiring.

[0238] The first electrode film 123 is mechanically connected to the upper portion 53 of the wiring at intervals from the corner 61 inwards. That is, the first electrode film 123 is only mechanically connected to the upper portion 53 of the wiring, and not to the corner 61 of the wiring. The first electrode film 123 is electrically connected to the corner 61 of the wiring via the upper portion 53 of the wiring. Of course, the first electrode film 123 (the second base electrode film 120) may also have a portion connected to the corner 61 of the wiring.

[0239] The second electrode film 124 covers the region in the interlayer film 70 where a plurality of gate openings 94 are formed on the first electrode film 123 in a film-like manner. That is, the second electrode film 124 has a portion that sandwiches the first electrode film 123 and covers the upper surface of the interlayer film 70 in a film-like manner, and a portion that sandwiches the wall surface of the first electrode film 123 and covers the plurality of gate openings 94 in a film-like manner.

[0240] The second electrode film 124 has a portion at the bottom of each gate opening 94 where the first electrode film 123 is sandwiched to cover the gate wiring 52 in a film-like manner, and is electrically connected to the gate wiring 52 via the first electrode film 123. Specifically, the second electrode film 124 has a portion that covers the upper part 53 of the gate wiring 52 in a film-like manner through the first electrode film 123, and is electrically connected to the upper part 53 of the wiring via the first electrode film 123.

[0241] The second electrode film 124 is positioned above the upper portion 53 of the wiring, spaced inwards from the corner portion 61. That is, the second electrode film 124 is positioned opposite the upper portion 53 of the wiring only, and not opposite the corner portion 61, via the first electrode film 123. The second electrode film 124 is electrically connected to the corner portion 61 of the wiring via the first electrode film 123 and the upper portion 53. Alternatively, the second electrode film 124 may also have a portion that is opposite the corner portion 61 via the first electrode film 123.

[0242] The second main electrode film 122 forms the upper portion of the gate finger electrode 115, covering the second base electrode film 120 in a film-like manner. The second main electrode film 122 includes a conductive material different from the conductive material of the second base electrode film 120.

[0243] The second main electrode film 122 may also include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may also include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. Preferably, the second main electrode film 122 includes the same conductive material as the conductive material of the first main electrode film 102. The second main electrode film 122 may also have a thickness approximately equal to that of the first main electrode film 102.

[0244] The second main electrode film 122 extends from the interlayer film 70 into multiple gate openings 94 and is mechanically and electrically connected to the upper wiring portion 53.

[0245] Semiconductor device 1 includes a gate pad electrode 130 disposed on an interlayer film 70. The gate pad electrode 130 is a terminal electrode to which a gate potential is imparted from the outside. The gate pad electrode 130 may also be referred to as a "second pad electrode," "second main surface electrode," "second terminal electrode," etc. The gate pad electrode 130 is disposed in the region between the source pad electrode 95 and the source finger electrode 110, spaced apart from the source pad electrode 95 and the source finger electrode 110.

[0246] In this configuration, the gate pad electrode 130 is positioned relative to the first pad portion 96 on the third side surface 5C and is held by the second pad portion 97 and the third pad portion 98. That is, the gate pad electrode 130 is opposite to the first pad portion 96 in the first direction X, and opposite to the second pad portion 97 and the third pad portion 98 in the second direction Y.

[0247] The gate pad electrode 130, when viewed from above, is formed as a polygon with four sides parallel to the periphery of the chip 2 (in this case, a quadrilateral shape). The gate pad electrode 130 has an area smaller than the planar area of ​​the source pad electrode 95 (first pad portion 96). The gate pad electrode 130 may also have a planar area smaller than the planar area of ​​the second pad portion 97 (third pad portion 98).

[0248] The gate pad electrode 130 is disposed over the portion covering the active region 8 and the outer peripheral region 9 and is connected to the gate finger electrode 115. The gate pad electrode 130 may cover multiple gate electrodes 32 through the interlayer film 70, or it may cover the gate wiring 52 through the interlayer film 70.

[0249] The gate pad electrode 130, like the gate finger electrode 115, includes a second base electrode film 120 and a second main electrode film 122. The second base electrode film 120 forms the lower layer of the gate pad electrode 130, covering the interlayer film 70 in a film-like manner. Like the gate finger electrode 115, the second base electrode film 120 has a laminated structure including a first electrode film 123 and a second electrode film 124. The first electrode film 123 covers the interlayer film 70 in a film-like manner, and the second electrode film 124 covers the first electrode film 123 in a film-like manner. The second main electrode film 122 forms the upper layer of the gate pad electrode 130, covering the second base electrode film 120 in a film-like manner.

[0250] The gate potential applied to the gate pad electrode 130 is applied to the gate wiring 52 via the gate finger electrode 115. The gate potential is transmitted to the plurality of gate electrodes 32 via the wiring path (current path) along the gate wiring 52. As a result, the plurality of gate electrodes 32 are turned on, controlling the on and off states of the plurality of channel regions 26, 27.

[0251] Semiconductor device 1 includes a drain pad electrode 140 covering a second main surface 4. The drain pad electrode 140 is a terminal electrode to which a drain potential is applied from the outside. The drain pad electrode 140 may also be referred to as a "third pad electrode," "third main surface electrode," "third terminal electrode," etc. The drain pad electrode 140 is electrically connected to the second semiconductor region 7. The drain pad electrode 140 may also cover the entire area of ​​the second main surface 4 in a manner connected to the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The drain pad electrode 140 may also partially cover the second main surface 4, with only the periphery of the second main surface exposed.

[0252] The breakdown voltage that can be applied between the source pad electrode 95 and the drain pad electrode 140 (between the first main surface 3 and the second main surface 4) can be 500V or more and 3000V or less. The breakdown voltage can have a value belonging to at least one of the following ranges: 500V or more and 1000V or less, 1000V or more and 1500V or less, 1500V or more and 2000V or less, 2000V or more and 2500V or less, and 2500V or more and 3000V or less.

[0253] Next, refer to Figure 10 The structure of the gate structure 30 and the interlayer film 70 are described in detail. Figure 10 It means Figure 7 An enlarged cross-sectional view of the main part, showing the vicinity of the electrode corner 41 of the gate electrode 32. Figure 10 The structure near electrode corner 41B is described in this paper, but this structure can also be applied to the structure near electrode corner 41A and the structure near wiring corners 61A and 61B.

[0254] As described above, the gate electrode 32 integrally comprises an upper electrode portion 33, electrode sides 34 and 35, and an electrode corner portion 41. Thus, the gate electrode 32 is formed with a protrusion 37 that partially protrudes upwards in cross-section. For example, the gate electrode 32 may also include a base 36 extending from the lower surface of the gate electrode 32 (the contact surface with the insulating film 31) to the upper end of the electrode sides 34 and 35, and a protrusion 37 whose width narrows due to the electrode corner portion 41 and forms the upper electrode portion 33. The area near the electrode sides 34 and 35 of the base 36 becomes a space due to the lack of space on the upper side caused by the electrode corner portion 41, thus selectively thinning the film thickness. Conversely, the region where the protrusion 37 is formed is the portion in the gate electrode 32 where the film thickness selectively thickens.

[0255] In this configuration, the protrusion 37 overlaps with the first source region 23 and the first channel region 26. This allows for a thicker gate electrode 32 on the first channel region 26. Consequently, even with the electrode corner 41 formed, the resistance of the gate electrode 32 on the first channel region 26 can be kept relatively low, thus suppressing a decrease in switching speed responsiveness.

[0256] The interlayer membrane 70 integrally has an insulating upper portion 84 connected to the upper portion 33 of the electrode, an insulating side portion 85 connected to the side portions 34 and 35 of the electrode, and an insulating corner portion 86 connected to the corner portion 41 of the electrode.

[0257] The upper insulating portion 84 extends horizontally along the upper electrode portion 33 in a film-like manner, covering the upper electrode portion 33. The side insulating portion 85 rises vertically from the insulating film 31 and extends along the side electrode portions 34 and 35 in a film-like manner, covering the side electrode portions 34 and 35.

[0258] The insulating corner portion 86 enters the electrode corner portion 41 formed by the recess 42 that bends inward toward the gate electrode 32. More specifically, the insulating corner portion 86 has a first convex surface 87 that bends inward toward the gate electrode 32 along the curvature of the recess 42, and a second convex surface 88 that is in contact with the source pad electrode 95 on the opposite side of the first convex surface 87 and bends obliquely upward toward the gate electrode 32. In cross-section, the insulating corner portion 86 has a first convex surface 87 and a second convex surface 88 that bend in two mutually separate directions. As a result, the thickness of the insulating corner portion 86 (corner thickness T3) is thicker than the thickness of the insulating upper portion 84 (upper portion thickness T1) and the thickness of the insulating side portion 85 (side portion thickness T2).

[0259] The corner thickness T3 can, for example, be the thickness of the interlayer film 70 in the normal direction n relative to both the first tangent L1 of the first convex surface 87 and the second tangent L2 of the second convex surface 88, which is parallel to the first tangent L1. In this configuration, the upper thickness T1 and the side thickness T2 are, for example, The above and Hereinafter, the corner thickness T3 is thicker than the upper thickness T1 and the side thickness T2. Furthermore, in the total thickness of the interlayer film 70 including the first oxide film 72 and the second oxide film 73, the corner thickness T3 only needs to be thicker than the upper thickness T1 and the side thickness T2.

[0260] Figure 11 This is a schematic diagram showing the wafer 150 used in the manufacture of semiconductor device 1. (Refer to...) Figure 11Wafer 150 is the substrate of chip 2, including SiC single crystal. Wafer 150 is formed into a flat disk shape. Of course, wafer 150 can also be formed into a flat cuboid shape. Wafer 150 has a first wafer main surface 151 on one side, a second wafer main surface 152 on the other side, and a wafer side surface 153 connecting the first wafer main surface 151 and the second wafer main surface 152.

[0261] The first wafer principal surface 151 corresponds to the first principal surface 3 of the chip 2, and the second wafer principal surface 152 corresponds to the second principal surface 4 of the chip 2. Both the first wafer principal surface 151 and the second wafer principal surface 152 are formed from the c-plane of a SiC single crystal. The first wafer principal surface 151 is formed from the silicon plane of a SiC single crystal, and the second wafer principal surface 152 is formed from the carbon plane of a SiC single crystal. The wafer 150 (the first wafer principal surface 151 and the second wafer principal surface 152) has the aforementioned offset direction and offset angle.

[0262] The wafer 150 has a mark 154 on its side surface 153 indicating the crystal orientation of the SiC single crystal. The mark 154 may also include either or both of an orientation plane and an orientation notch. The orientation plane is formed by a cut portion that appears as a straight line when viewed from above. The orientation notch is formed by a cut portion that is cut into a concave shape (e.g., a pointed shape) towards the center of the first wafer main surface 151 when viewed from above.

[0263] Marker 154 may also include either or both of a first orientation plane extending along the m-axis and a second orientation plane extending along the a-axis. Marker 154 may also include either or both of an orientation notch recessed in the m-axis direction and an orientation notch recessed in the a-axis direction.

[0264] The wafer 150 includes a first semiconductor region 6 in the region (surface layer) on the side of the first wafer main surface 151. The first semiconductor region 6 is formed as a layer extending along the first wafer main surface 151. In this configuration, the first semiconductor region 6 is composed of an epitaxial layer (specifically a SiC epitaxial layer).

[0265] The wafer 150 includes a second semiconductor region 7 in the region (surface portion) on the second main surface 152. The second semiconductor region 7 is formed as a layer extending along the second main surface 4 and is electrically connected to the first semiconductor region 6. In this configuration, the second semiconductor region 7 is constituted by a wafer body (specifically, a SiC wafer). That is, in this configuration, the wafer 150 is constituted by an epitaxial wafer (so-called epitaxial wafer) having a stacked structure including a wafer body and an epitaxial layer.

[0266] For example, on wafer 150, multiple device regions 155 and multiple cut-off lines 156 are defined by alignment marks, etc. Each device region 155 is a region corresponding to semiconductor device 1. The multiple device regions 155 are each set as quadrilateral shapes when viewed from above.

[0267] In this configuration, multiple device regions 155 are arranged in a matrix shape along the first direction X and the second direction Y when viewed from above. The multiple device regions 155 are spaced apart from the periphery of the first wafer main surface 151 when viewed from above. Multiple predetermined cutting lines 156 are arranged in a grid shape extending along the first direction X and the second direction Y to divide the multiple device regions 155.

[0268] Figures 12A to 12M This is a cross-sectional view showing a method for manufacturing semiconductor device 1. Figures 12A to 12M The image shows a cross-section of a portion of the active region 8 within a device region 155.

[0269] Reference Figure 12A First, prepare the aforementioned wafer 150. Next, refer to... Figure 12B Multiple host regions 20 are formed by selectively introducing p-type impurities into the surface layer of the first wafer host surface 151 via ion implantation through a mask (not shown). Additionally, multiple host regions 21 are formed by selectively introducing p-type impurities into the surface layer of the first wafer host surface 151 via ion implantation through a mask (not shown). Furthermore, multiple source regions 23 and 24 are formed by selectively introducing n-type impurities into the surface layer of the first wafer host surface 151 via ion implantation through a mask (not shown).

[0270] Furthermore, p-type impurities are selectively introduced into the surface layer of the first wafer main surface 151 via ion implantation through a mask (not shown) to form multiple contact regions 25. Additionally, p-type impurities are selectively introduced into the surface layer of the first wafer main surface 151 via ion implantation through a mask (not shown) to form terminal regions 45. Furthermore, p-type impurities are selectively introduced into the surface layer of the first wafer main surface 151 via ion implantation through a mask (not shown) to form multiple field regions 47.

[0271] The order of the formation processes of the main body region 20, the outer main body region 21, the source region 23, the source region 24, the contact region 25, the terminal region 45, and the field region 47 is arbitrary. The formation process of the outer main body region 21 can also be performed simultaneously with the formation process of the main body region 20. The formation process of the field region 47 can also be performed simultaneously with the formation process of the main body region 20 or the formation process of the terminal region 45.

[0272] Next, refer to Figure 12CA substrate insulating film 160 is formed covering the main surface 151 of the first wafer. The substrate insulating film 160 is the substrate of the insulating film 31 and the peripheral insulating film 51. The substrate insulating film 160 can also be formed by CVD (Chemical Vapor Deposition) or oxidation treatment (e.g., thermal oxidation treatment).

[0273] Next, refer to Figure 12D A base electrode 161 is formed on a substrate insulating film 160. The base electrode 161 is the substrate for the gate electrode 32 and the gate wiring 52. The base electrode 161 comprises conductive polysilicon. The base electrode 161 can also be formed by CVD. The base electrode 161 has a base electrode surface 162 extending along the substrate insulating film 160.

[0274] Next, refer to Figure 12E A mask 168 with a predetermined layout is formed on the base electrode 161 (base electrode surface 162). The mask 168 may also be an organic mask (e.g., a resist mask). The mask 168 has a plurality of openings 169 that expose areas other than a plurality of mask portions covering the areas where the plurality of gate electrodes 32 are to be formed.

[0275] The next step is the etching process of the base electrode 161. In this step, isotropic etching is performed through mask 168, followed by anisotropic etching. First, refer to... Figure 12F The base electrode 161 is isotropically removed from the base electrode surface 162 in both the thickness direction and the lateral direction via isotropic etching through mask 168. This results in a recess 163 formed in the base electrode 161 directly below the opening 169. The recess 163 has recessed corners 164 at both ends along the lateral direction of the first wafer main surface 151, curving inwards towards the base electrode 161.

[0276] Next, refer to Figure 12G The remaining portion of the base electrode 161 is removed in the thickness direction from the bottom surface of the recess 163 to the substrate insulating film 160 through anisotropic etching via mask 168. This forms a plurality of gate electrodes 32, each having an upper electrode portion 33, electrode sides 34 and 35, and an electrode corner portion 41. The arc-shaped electrode corner portion 41 is formed by the recess corner portion 164. Additionally, gate wiring 52, having an upper wiring portion 53, wiring sides 54 and 55, and wiring corner portion 61, is formed. After the formation processes of the gate electrodes 32 and the gate wiring 52, mask 168 is removed.

[0277] Next, refer to Figure 12HAn interlayer film 70 is formed on the main surface 151 of the first wafer. In this process, an interlayer film 70 is formed having portions that directly cover the gate electrode 32, including the upper electrode portion 33, the first electrode side portion 34, the second electrode side portion 35, and the electrode corner portion 41. Additionally, an interlayer film 70 is formed having portions that directly cover the gate wiring 52, including the upper wiring portion 53, the first wiring side portion 54, the second wiring side portion 55, and the wiring corner portion 61.

[0278] In this manner, the interlayer film 70 has a laminated structure including a first oxide film 72 and a second oxide film 73 (see reference). Figure 7 The first oxide film 72 comprises a silicon oxide film without added impurities. The second oxide film 73 comprises a silicon oxide film containing phosphorus. The first oxide film 72 can also be formed by CVD. The second oxide film 73 can also be formed by CVD. After the formation process of the second oxide film 73, a reflow process (heat treatment process) is performed on the interlayer film 70. As a result, the corners and surface roughness of the interlayer film 70 are smoothed.

[0279] Next, refer to Figure 12I A mask 174 with a predetermined layout is disposed on the interlayer film 70. The mask 174 exposes the areas where a plurality of source openings 90, a plurality of external openings 92 and a plurality of gate openings 94 should be formed, and covers the areas outside them.

[0280] Next, refer to Figure 12J Unwanted portions of the interlayer film 70 and the substrate insulating film 160 are removed by etching via mask 174. In this process, unwanted portions of the second oxide film 73, the first oxide film 72, and the substrate insulating film 160 are removed sequentially. The etching method can be wet etching and / or dry etching. Anisotropic dry etching (e.g., RIE (Reactive Ion Etching)) is preferred.

[0281] Thus, multiple source openings 90, multiple external openings 92, and multiple gate openings 94 are formed on the interlayer film 70. Additionally, an insulating film 31 and a peripheral insulating film 51 are formed. This process may also include a process for forming multiple source recesses 91 and a process for forming multiple external recesses 93. In this case, a process is performed to further excavate the portions of the first wafer main surface 151 exposed from the multiple source openings 90 and multiple external openings 92 toward the second wafer main surface 152. Afterwards, the mask 174 is removed.

[0282] Next, refer to Figure 12K Through reflow processing, a second convex surface 88, bending obliquely upward toward the gate electrode 32, is formed at the upper corner of the interlayer film 70. The reflow conditions are as follows: Figure 12JThe condition that the upper corner of the etched, pointed interlayer film 70 becomes rounded is acceptable, without particular restrictions. For example, it can be appropriately determined based on the film thickness, film quality, and opening width of the source opening 90.

[0283] Next, refer to Figure 12L A first substrate electrode film 100 and a second substrate electrode film 120 are formed on the interlayer film 70. The first substrate electrode film 100 and the second substrate electrode film 120 can be formed by sputtering or vapor deposition.

[0284] Next, refer to Figure 12M A first main electrode film 102 and a second main electrode film 122 are formed on the first base electrode film 100 and the second base electrode film 120, respectively. The first main electrode film 102 and the second main electrode film 122 may also include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may also include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The first main electrode film 102 and the second main electrode film 122 may also be formed by sputtering or vapor deposition.

[0285] Then, a drain pad electrode 140 is formed on the main surface 152 of the second wafer. The drain pad electrode 140 can be formed by sputtering or vapor deposition. Then, the wafer 150 is cut using a dicing line 156 to cut out a plurality of semiconductor devices 1. Through the above processes, the semiconductor devices 1 are manufactured.

[0286] For example, to meet the requirements of device miniaturization, multiple gate structures 30 are sometimes arranged with a narrow pitch. Because the distance between adjacent gate structures 30 is narrowed, if the interlayer film 70 is thickened in the same way to ensure withstand voltage, the width W of the source opening 90 for the source contact becomes very small. The reduction in the width W of the source opening 90 decreases the embedment of the metal (source pad electrode 95) into the source opening 90. If the embedment is reduced, gaps are created at the location of the source opening 90, leading to problems such as plating solution inflow and poor wire bonding (e.g., insufficient strength during wire bonding). On the other hand, as a countermeasure to this problem, if the interlayer film 70 is thinned, the film thickness of the insulating corner 86 cannot be sufficiently ensured after the interlayer film 70 is reflowed, reducing the reliability of the gate-source insulation.

[0287] Therefore, according to this semiconductor device 1, since an electrode corner 41 is formed on the gate electrode 32, the corner thickness T3 of the interlayer film 70 can be selectively made thicker than the upper thickness T1 and the side thickness T2. Thus, after forming the source opening 90, the insulating corner 86 is formed into an arc shape like the second convex surface 88 by reflow, even though it is thinner than before reflow (see reference). Figure 12KThis also ensures that the insulating corner 86 of sufficient thickness is formed on the electrode corner 41. Therefore, it is possible to meet the requirement of narrow spacing of the gate structure 30 and improve the withstand voltage reliability. On the other hand, the side thickness T2 can be formed to be relatively thin, thus suppressing the generation of voids in the source opening 90.

[0288] Especially in the case of a semiconductor device 1 with SiC, its characteristics (physical properties) differ from those of lateral Si semiconductor devices such as LSI, and an extremely high voltage is applied. Therefore, by improving the insulation reliability between the gate and source, a semiconductor device 1 with appropriate electrical characteristics is provided.

[0289] The following shows a modified example of the gate electrode 32. Figure 13 This is a cross-sectional view showing a first modified example of the gate electrode 32.

[0290] Reference Figure 13 The electrode corner 41 of the gate electrode 32 does not necessarily have to be formed in an arc shape. For example, the electrode corner 41 may also be formed by a flat inclined wall 43 that slopes downward from the upper electrode portion 33 toward the electrode sides 34, 35. The electrode corner 41 may also be a flat inclined wall 43 that slopes upward from the upper end of the electrode sides 34, 35 toward the inner side of the gate electrode 32 in the width direction. In this case, the insulating corner portion 86 may also have a flat surface 44 that is in contact with the inclined wall 43 and slopes along the inclined wall 43.

[0291] Even when the electrode corner 41 is formed by the inclined wall 43, the thickness of the insulating corner 86 (corner thickness T3) can be made thicker than the thickness of the insulating upper part 84 (upper part thickness T1) and the thickness of the insulating side part 85 (side part thickness T2).

[0292] Figures 14A-14B It means and Figure 13 A diagram showing the process related to the formation of the gate electrode 32.

[0293] Reference Figure 14A In order to form the electrode corner 41 with the inclined wall 43, after forming a mask 168 on the base electrode 161 (base electrode surface 162) (see reference). Figure 12E The base electrode 161 is removed in a conical shape from the base electrode surface 162 toward the thickness direction via anisotropic tapered etching through mask 168. At this time, the dry etching conditions can be appropriately set so that the base electrode 161 is etched in an inclined direction rather than perpendicularly. Thus, a recess 165 is formed in the base electrode 161 directly below the opening 169. The recess 165 has recessed corners 166 at both ends along the lateral direction of the first wafer main surface 151, formed by flat inclined walls sloping obliquely upward toward the base electrode 161.

[0294] Next, refer to Figure 14B The remaining portion of the base electrode 161 is removed in the thickness direction from the bottom surface of the recess 165 to the substrate insulating film 160 through anisotropic vertical etching via mask 168. This forms a plurality of gate electrodes 32, each having an upper electrode portion 33, electrode side portions 34 and 35, and an electrode corner portion 41 (sloping wall 43). The sloping wall 43 of the electrode corner portion 41 is formed by the recess corner portion 166.

[0295] Afterwards, through conducting Figures 12H to 12M The process yields Figure 13 Semiconductor device 1 is shown.

[0296] Figure 15 This is a cross-sectional view showing a second modified example of the gate electrode. (Refer to...) Figure 15 The electrode corner 41 of the gate electrode 32 does not necessarily have to be formed in an arc shape. For example, the electrode corner 41 may also be formed by an arc portion 48 that connects the upper electrode portion 33 and the electrode side portions 34, 35 in an arc shape that curves obliquely upward toward the gate electrode 32. In this case, the insulating corner portion 86 may also have a concave surface 49 that is connected to the arc portion 48 and is formed in an arc shape along the arc portion 48. The concave surface 49 is a surface that curves in the same direction as the second convex surface 88 of the insulating corner portion 86.

[0297] Even when the electrode corner 41 is formed by the arc portion 48, the thickness of the insulating corner portion 86 (corner thickness T3) can be made thicker than the thickness of the insulating upper portion 84 (upper portion thickness T1) and the thickness of the insulating side portion 85 (side portion thickness T2).

[0298] Figures 16A-16B It means and Figure 15 A diagram showing the process related to the formation of the gate electrode 32.

[0299] Reference Figure 16A In order to form the electrode corner 41 with the arc portion 48, a mask 168 is formed on the base electrode 161 (base electrode surface 162) (see reference). Figure 12E The base electrode 161 is removed in the thickness direction from the base electrode surface 162 to the substrate insulating film 160 through anisotropic etching via mask 168. As a result, a plurality of gate electrodes 32 with pointed electrode corners 41 are formed.

[0300] Next, refer to Figure 16BA thermal oxide film 50 is formed on the surface of the gate electrode 32 through thermal oxidation. The thermal oxidation of the gate electrode 32 proceeds from the upper part 33 in the vertical direction (longitudinal direction) and from the side parts 34 and 35 in the horizontal direction (lateral direction). At the electrode corner 41, thermal oxidation proceeds in both the longitudinal and lateral directions, thereby oxidizing and removing the sharp corner of the electrode corner 41, forming an arc-shaped arc portion 48.

[0301] Afterwards, through conducting Figures 12H to 12M The process yields Figure 13 Semiconductor device 1 is shown.

[0302] The embodiments of the present disclosure have been described above, but the semiconductor device 1 of the present disclosure can also be implemented in other ways.

[0303] For example, in the various embodiments described, a structure in which the relationship between the a-axis direction and the m-axis direction is interchanged may also be adopted. The specific structure in this case is obtained by interchangeping the "a-axis direction (deviation direction)" and the "m-axis direction (direction orthogonal to the deviation direction)" in the foregoing description and figures.

[0304] In the various embodiments described, a structure in which the conductivity type of an "n-type" semiconductor region is reversed to "p-type" and the conductivity type of a "p-type" semiconductor region is reversed to "n-type" can also be used. The specific structure in this case is obtained by replacing "n-type" with "p-type" and "p-type" with "n-type" in the foregoing description and figures.

[0305] In the various embodiments described, a chip 2 comprising a SiC single crystal (first semiconductor region 6 and second semiconductor region 7) is used. However, the chip 2 (first semiconductor region 6 and second semiconductor region 7) may also comprise a single crystal of a wide bandgap semiconductor other than SiC. A wide bandgap semiconductor is a semiconductor having a bandgap larger than that of silicon. Examples of single crystals that are wide bandgap semiconductors include gallium nitride, diamond, and gallium oxide. Of course, the chip 2 (first semiconductor region 6 and second semiconductor region 7) may also comprise single-crystal silicon.

[0306] In the various embodiments described, an n-type second semiconductor region 7 is shown. However, a p-type second semiconductor region 7 may be used instead of an n-type second semiconductor region 7. In this case, an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of a MISFET structure. In this case, as described above, the "source" of the MISFET structure is replaced by the "emitter" of the IGBT structure, and the "drain" of the MISFET structure is replaced by the "collector" of the IGBT structure. The p-type second semiconductor region 7 may also include an impurity region containing p-type impurities that is implanted into the surface layer of the second main surface 4 of the chip 2 by ion implantation.

[0307] Hereinafter, examples of features extracted from this specification and accompanying drawings are shown. Hereinafter, alphanumeric characters, etc., denote corresponding constituent elements in the foregoing embodiments, but do not imply that the scope of each item (clause) is limited to the embodiments. The term "semiconductor device" in the following item can be replaced as needed with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "MISFET device," "IGBT device," etc.

[0308] [Appendix 1-1] A semiconductor device 1 includes:

[0309] Chip 2 has a main surface 3;

[0310] A gate electrode 32 is formed on the main surface 3. The gate electrode 32 has: an upper electrode portion 33 along the main surface 3; electrode side portions 34 and 35 that stand out from the main surface 3; and an electrode corner portion 41 formed by a portion of the material of the gate electrode 32, connecting the upper electrode portion 33 and the electrode side portions 34 and 35.

[0311] Interlayer film 70, which covers the gate electrode 32;

[0312] An opening 90, formed separately from the electrode sides 34, 35 in the interlayer film 70 along the transverse direction of the main surface 3, exposes a portion of the main surface 3 as a contact surface; and

[0313] Surface electrode 95, formed on the interlayer film 70, is mechanically and electrically connected to the contact surface within the opening 90; and

[0314] The interlayer film 70 includes an insulating upper portion 84 that contacts the upper portion 33 of the electrode, an insulating side portion 85 that contacts the side portions 34 and 35 of the electrode, and an insulating corner portion 86 that contacts the corner portion 41 of the electrode.

[0315] The corner thickness T3 of the interlayer film 70 of the insulating corner portion 86 is thicker than at least one of the upper thickness T1 of the interlayer film 70 of the insulating upper portion 84 and the side thickness T2 of the interlayer film 70 of the insulating side portion 85.

[0316] For example, to meet the requirements of device miniaturization, multiple gate electrodes 32 are sometimes arranged with a narrow spacing. Because the distance between adjacent gate electrodes 32 is narrowed, if the interlayer film 70 is uniformly thickened to ensure withstand voltage, the width of the exposed opening 90 at the contact surface becomes very small. This reduction in the width of the opening 90 decreases the embedding of the metal into the opening 90. If the embedding is reduced, gaps are created at the location of the opening 90, leading to problems such as the inflow of plating solution and poor wire bonding (e.g., insufficient strength during wire bonding). On the other hand, as a countermeasure to this problem, if the interlayer film 70 is made thinner, the film thickness at the insulating corner 86 cannot be sufficiently ensured after the interlayer film 70 is reflowed, resulting in reduced insulation reliability.

[0317] Therefore, according to this method, since a portion of the material of the gate electrode 32 is missing, forming an electrode corner 41 on the gate electrode 32, the corner thickness T3 of the interlayer film 70 can be selectively made thicker than the upper thickness T1 and the side thickness T2. Thus, even if the insulating corner 86 is thinner than before reflow after the opening 90 is formed, a sufficiently thick insulating corner 86 can be ensured on the electrode corner 41. Therefore, the requirement for narrower spacing of the gate electrode 32 can be met, and the withstand voltage reliability can be improved. On the other hand, since the side thickness T2 can be formed relatively thin, voids in the opening 90 can be suppressed.

[0318] [Appendix 1-2] In the semiconductor device 1 according to Appendix 1-1, wherein,

[0319] The electrode corner 41 includes an arc-shaped recess 42 that curves inward toward the gate electrode 32.

[0320] [Appendix 1-3] In the semiconductor device 1 according to Appendix 1-2, wherein,

[0321] The insulating corner portion 86 has a first convex surface 87 that curves inward toward the gate electrode 32 along the curvature of the recess 42.

[0322] The corner thickness T3 includes the thickness of the interlayer film 70 in the normal direction n relative to the tangent L1 of the first convex surface 87.

[0323] [Appendix 1-4] In the semiconductor device 1 according to Appendix 1-2, wherein,

[0324] The insulating corner portion 86 has: a first convex surface 87 that bends along the curvature of the recess 42 toward the inside of the gate electrode 32; and a second convex surface 88 that is in contact with the surface electrode 95 on the opposite side of the first convex surface 87 and bends obliquely upward toward the gate electrode 32.

[0325] The corner thickness T3 includes the thickness of the interlayer film 70 in the normal direction n of both the first tangent L1 relative to the first convex surface 87 and the second tangent L2 relative to the second convex surface 88, which is parallel to the first tangent L1.

[0326] [Appendix 1-5] In the semiconductor device 1 according to Appendix 1-1, wherein,

[0327] The electrode corner 41 includes a flat, inclined wall 43 that slopes downward from the upper electrode 33 toward the electrode side portions 34 and 35.

[0328] [Appendix 1-6] In the semiconductor device 1 according to Appendix 1-1, wherein,

[0329] The electrode corner portion 41 includes an arc portion 48 that connects the upper electrode portion 33 and the electrode side portions 34 and 35 in an arc shape that curves obliquely upward toward the gate electrode 32.

[0330] [Appendix 1-7] Semiconductor device 1 according to any one of Appendix 1-1 to Appendix 1-6,

[0331] It also includes a plurality of gate electrodes 32, which are arranged at intervals on the main surface 3.

[0332] The opening 90 is divided in the region between the plurality of gate electrodes 32.

[0333] [Appendix 1-8] The semiconductor device 1 according to any one of Appendix 1-1 to Appendix 1-7, wherein,

[0334] The opening 90 has an aspect ratio D / W along the depth direction of the opening 90.

[0335] The corner thickness T3 is thicker than both the upper thickness T1 and the side thickness T2.

[0336] [Appendix 1-9] The semiconductor device 1 according to any one of Appendix 1-1 to Appendix 1-8, wherein,

[0337] The upper thickness T1 and the side thickness T2 are The above and the following.

[0338] [Appendix 1-10] The semiconductor device 1 according to any one of Appendix 1-1 to Appendix 1-9, wherein,

[0339] The width of the opening 90 is 0.2 μm or more and 3 μm or less, and the depth of the opening 90 is 0.2 μm or more and 2 μm or less.

[0340] [Appendix 1-11] The semiconductor device 1 according to any one of Appendices 1-1 to 1-10, wherein,

[0341] The interlayer film 70 includes a first oxide film 72 without impurities covering the gate electrode 32, and a second oxide film 73 containing phosphorus and covering the first oxide film 72.

[0342] The opening 90 extends through both the first oxide film 72 and the second oxide film 73.

[0343] [Appendix 1-12] The semiconductor device 1 according to any one of Appendix 1-1 to Appendix 1-11 further includes:

[0344] A semiconductor region 6 of the first conductivity type is formed on the surface portion of the main surface 3;

[0345] The main body region 20 of the second conductivity type is formed on the surface layer of the semiconductor region 6;

[0346] Impurity regions 23 and 24 of the first conductivity type are formed on the surface of the main body region 20;

[0347] Channels 26 and 27 are formed on the surface portion of the main body region 20 in the region between the semiconductor region 6 and the impurity regions 23 and 24; and

[0348] An insulating film 31, which covers the channels 26 and 27 on the main surface 3, is sandwiched between the gate electrode 32 and the channels 26 and 27.

[0349] The opening 90 exposes a portion of the impurity regions 23 and 24 on the contact surface.

[0350] The surface electrode 95 is electrically connected to the impurity regions 23 and 24 within the opening 90.

[0351] [Appendix 1-13] The semiconductor device 1 according to any one of Appendix 1-1 to Appendix 1-12, wherein,

[0352] The chip 2 is a SiC chip 2.

[0353] [Appendix 1-14] A method for manufacturing a semiconductor device 1 includes:

[0354] The process of forming a base electrode 161 on the main surface 151 of wafer 150;

[0355] The base electrode 161 is selectively isotropically etched in the thickness direction, followed by anisotropic etching, thereby forming a gate electrode 32 having an upper electrode portion 33 along the main surface 151, electrode side portions 34 and 35 standing from the main surface 151, and an electrode corner portion 41 including an arc-shaped recess 42 that connects the upper electrode portion 33 and the electrode side portions 34 and 35 and bends inward toward the base electrode 161.

[0356] The process of forming an interlayer film 70 on the main surface 151 to cover the gate electrode 32;

[0357] The process of forming an opening 90 on the interlayer film 70 in a manner that separates it from the electrode sides 34, 35 in the transverse direction along the main surface 151, thereby exposing a portion of the main surface 151 as a contact surface; and

[0358] The process of forming a surface electrode 95 on the interlayer film 70 in such a way that it is mechanically and electrically connected to the contact surface within the opening 90.

[0359] [Appendix 1-15] A method for manufacturing a semiconductor device 1 includes:

[0360] The process of forming a base electrode 161 on the main surface 151 of wafer 150;

[0361] The base electrode 161 is selectively anisotropically tapered etched in the thickness direction, followed by anisotropically vertical etched, thereby forming a gate electrode 32 having an upper electrode portion 33 along the main surface 151, electrode side portions 34, 35 standing from the main surface 151, and an electrode corner portion 41 including a flat inclined wall 43 connecting the upper electrode portion 33 and the electrode side portions 34, 35 and sloping downward from the upper electrode portion 33 to the electrode side portions 34, 35;

[0362] The process of forming an interlayer film 70 on the main surface 151 to cover the gate electrode 32;

[0363] The process of forming an opening 90 on the interlayer film 70 in a manner that separates it from the electrode sides 34, 35 in the transverse direction along the main surface 151, thereby exposing a portion of the main surface 151 as a contact surface; and

[0364] The process of forming a surface electrode 95 on the interlayer film 70 in such a way that it is mechanically and electrically connected to the contact surface within the opening 90.

[0365] [Appendix 1-16] A method for manufacturing a semiconductor device 1 includes:

[0366] The process of forming a base electrode 161 comprising polysilicon on the main surface 151 of wafer 150;

[0367] A process of forming a gate electrode 32 having an upper electrode portion 33 along the main surface 151, electrode side portions 34 and 35 standing from the main surface 151, and an electrode corner portion 41 connecting the upper electrode portion 33 and the electrode side portions 34 and 35 by selectively anisotropically etching the base electrode 161 in the thickness direction.

[0368] The process of forming an arc-shaped portion 48 that curves obliquely upward toward the gate electrode 32 by thermal oxidation of the gate electrode 32;

[0369] The process of forming an interlayer film 70 on the main surface 151 to cover the gate electrode 32;

[0370] The process of forming an opening 90 on the interlayer film 70 in a manner that separates it from the electrode sides 34, 35 in the transverse direction along the main surface 151, thereby exposing a portion of the main surface 151 as a contact surface; and

[0371] The process of forming a surface electrode 95 on the interlayer film 70 in such a way that it is mechanically and electrically connected to the contact surface within the opening 90.

[0372] [Appendix 1-17] The method for manufacturing the semiconductor device 1 according to any one of Appendix 1-14 to Appendix 1-16 includes:

[0373] The process of forming a convex surface 88 that curves obliquely upward toward the gate electrode 32 at the upper corner of the opening 90 of the interlayer film 70 through a reflow process.

[0374] Symbol Explanation

[0375] 1—Semiconductor device, 2—Chip, 3—First main surface, 4—Second main surface, 5A—First side surface, 5B—Second side surface, 5C—Third side surface, 5D—Fourth side surface, 6—First semiconductor region, 7—Second semiconductor region, 8—Active region, 9—Outer peripheral region, 20—Main body region, 21—Outer main body region, 22—Surface drift region, 23—First source region, 24—Second source region, 25—Contact region, 26—First channel region, 27—Second channel region, 30—Gate structure, 31—Insulating film, 32—Gate electrode, 33—Top of electrode, 34—Side of first electrode, 35—Side of second electrode, 36—Base, 37—Protrusion, 41—Electrode corner, 41A— Electrode corner, 41B—Electrode corner, 42—Recess, 43—Sloping wall, 44—Flat surface, 45—Termination region, 46—Overlap region, 47—Field region, 48—Arc portion, 49—Concave surface, 50—Thermal oxide film, 51—Outer peripheral insulating film, 52—Gate wiring, 53—Upper part of wiring, 54—First wiring side, 55—Second wiring side, 61—Wiring corner, 61A—Wiring corner, 61B—Wiring corner, 70—Interlayer film, 72—First oxide film, 73—Second oxide film, 74—First cover portion, 75—Second cover portion, 76—Third cover portion, 77—First wiring cover portion, 78—Second wiring cover portion, 79—Third wiring cover portion, 80—First upper cover portion, 81 —Second upper cover portion, 82—First upper wiring cover portion, 83—Second upper wiring cover portion, 84—Upper insulating portion, 85—Insulating side portion, 86—Insulating corner portion, 87—First convex surface, 88—Second convex surface, 90—Source opening, 91—Source recess, 92—Outer opening, 93—Outer recess, 94—Gate opening, 95—Source pad electrode, 96—First pad portion, 97—Second pad portion, 98—Third pad portion, 100—First substrate electrode film, 102—First main electrode film, 103—First electrode film, 104—Second electrode film, 110—Source finger electrode, 115—Gate finger electrode, 120—Second substrate electrode film, 122—Second main electrode film, 123—First electrode film 124—Second electrode film, 130—Gate pad electrode, 140—Drain pad electrode, 150—Wafer, 151—First wafer main surface, 152—Second wafer main surface, 153—Wafer side surface, 154—Mark, 155—Device area, 156—Tearing line, 160—Substrate insulating film, 161—Base electrode, 162—Base electrode surface, 163—Recess, 164—Recess corner, 165—Recess, 166—Recess corner, 168—Mask, 169—Opening, 174—Mask, L1—First tangent, L2—Second tangent, T1—Upper thickness, T2—Side thickness, T3—Corner thickness, X—First direction, Y—Second direction, Z—Vertical direction, n—Normal direction.

Claims

1. A semiconductor device, characterized in that, include: A chip has a main surface; A gate electrode, formed on the main surface, has an upper electrode portion extending along the main surface; The electrode side, which stands upright from the main surface; And an electrode corner portion, which is formed by a partial absence of material from the gate electrode, connecting the upper part of the electrode and the side part of the electrode; An interlayer film covering the gate electrode; An opening is formed in the interlayer film in a transverse direction along the main surface, partially separated from the electrode side, so that a portion of the main surface is exposed as a contact surface; as well as A surface electrode, formed on the interlayer film, is mechanically and electrically connected to the contact surface within the opening. The interlayer film includes: an insulating upper portion, which is in contact with the upper portion of the electrode; and an insulating side portion, which is in contact with the side portion of the electrode. And the insulating corner portion, which is connected to the electrode corner portion, The corner thickness of the interlayer film at the insulating corner is thicker than at least one of the upper thickness of the interlayer film at the upper insulating portion and the side thickness of the interlayer film at the insulating side portion.

2. The semiconductor device according to claim 1, characterized in that, The electrode corner includes an arc-shaped recess that curves inward toward the gate electrode.

3. The semiconductor device according to claim 2, characterized in that, The insulating corner portion has a first convex surface that curves inward toward the gate electrode along the curvature of the recess. The corner thickness includes the thickness of the interlayer film in the normal direction relative to the tangent of the first convex surface.

4. The semiconductor device according to claim 2, characterized in that, The insulating corner portion has: a first convex surface that curves inward toward the gate electrode along the curvature of the recess; and a second convex surface that is in contact with the surface electrode on the opposite side of the first convex surface and curves obliquely upward toward the gate electrode. The corner thickness includes the thickness of the interlayer film in the normal directions of both a first tangent relative to the first convex surface and a second tangent parallel to the first tangent relative to the second convex surface.

5. The semiconductor device according to claim 1, characterized in that, The electrode corner includes a flat, sloping wall that slopes downward from the top of the electrode toward the side of the electrode.

6. The semiconductor device according to claim 1, characterized in that, The electrode corner includes an arc portion that connects the upper part of the electrode and the side part of the electrode in an arc shape that curves obliquely upward toward the gate electrode.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that, It also includes a plurality of gate electrodes arranged at intervals on the main surface. The opening is divided in the region between the plurality of gate electrodes.

8. The semiconductor device according to any one of claims 1 to 7, characterized in that, The opening has an aspect ratio along its depth direction. The corner thickness is greater than both the upper thickness and the side thickness.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that, The upper thickness and the side thickness are The above and the following.

10. The semiconductor device according to any one of claims 1 to 9, characterized in that, The width of the opening is 0.2 μm or more and 3 μm or less, and the depth of the opening is 0.2 μm or more and 2 μm or less.

11. The semiconductor device according to any one of claims 1 to 10, characterized in that, The interlayer film includes a first oxide film without impurities covering the gate electrode, and a second oxide film containing phosphorus and covering the first oxide film. The opening extends through both the first oxide film and the second oxide film.

12. The semiconductor device according to any one of claims 1 to 11, characterized in that, Also includes: A semiconductor region of a first conductivity type is formed on the surface portion of the main surface; The main region of the second conductivity type is formed on the surface layer of the semiconductor region; A first conductivity type of impurity region is formed in the surface portion of the main body region; A channel is formed in the surface portion of the main region in the region between the semiconductor region and the impurity region; as well as An insulating film, which covers the channel on the main surface and is sandwiched between the gate electrode and the channel, The opening exposes a portion of the impurity region on the contact surface. The surface electrode is electrically connected to the impurity region within the opening.

13. The semiconductor device according to any one of claims 1 to 12, characterized in that, The chip is a SiC chip.

14. A method for manufacturing a semiconductor device, characterized in that, The process includes the following steps: The base electrode is formed on the main surface of the wafer; The base electrode is selectively etched isotropically in the thickness direction, followed by anisotropic etching, thereby forming a gate electrode having an upper electrode portion along the main surface, an electrode side portion standing up from the main surface, and an electrode corner portion including an arc-shaped concave portion that connects the upper electrode portion and the electrode side portion and bends inward toward the base electrode. An interlayer film is formed on the main surface in such a way as to cover the gate electrode; An opening is formed on the interlayer film in such a way that it is separated from the electrode side in the transverse direction along the main surface, exposing a portion of the main surface as a contact surface; as well as A surface electrode is formed on the interlayer film in such a way that it is mechanically and electrically connected to the contact surface within the opening.

15. A method for manufacturing a semiconductor device, characterized in that, The process includes the following steps: The base electrode is formed on the main surface of the wafer; The base electrode is selectively anisotropically tapered etched in the thickness direction, followed by anisotropic vertical etched, thereby forming a gate electrode having an upper electrode portion along the main surface, an electrode side portion standing up from the main surface, and an electrode corner portion including a flat inclined wall connecting the upper electrode portion and the electrode side portion and sloping downward from the upper electrode portion to the electrode side portion. An interlayer film is formed on the main surface in such a way as to cover the gate electrode; An opening is formed on the interlayer film in such a way that it is separated from the electrode side in the transverse direction along the main surface, exposing a portion of the main surface as a contact surface; as well as A surface electrode is formed on the interlayer film in such a way that it is mechanically and electrically connected to the contact surface within the opening.

16. A method for manufacturing a semiconductor device, characterized in that, The process includes the following steps: A base electrode, comprising polycrystalline silicon, is formed on the main surface of the wafer; By selectively etching the base electrode anisotropically in the thickness direction, a gate electrode is formed having an upper electrode portion along the main surface, an electrode side portion standing up from the main surface, and an electrode corner portion connecting the upper electrode portion and the electrode side portion. By thermally oxidizing the gate electrode, an arc-shaped portion that curves obliquely upward toward the gate electrode is formed at the corner of the electrode. An interlayer film is formed on the main surface in such a way as to cover the gate electrode; The interlayer film is formed in such a way that it is separated from the electrode side in the transverse direction along the main surface, exposing a portion of the main surface as a contact surface; as well as A surface electrode is formed on the interlayer film in such a way that it is mechanically and electrically connected to the contact surface within the opening.

17. The semiconductor device according to any one of claims 14 to 16, characterized in that, This includes a process of forming a convex surface that curves obliquely upward toward the gate electrode at the upper corner of the opening in the interlayer film through a reflow process.

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