Detection panel and flat panel detector

Abstract

A detection panel and a flat panel detector, the detection panel comprising: a substrate (100); a thin film transistor (200) located on the substrate (100); the thin film transistor (200) comprises a gate layer (01), an active layer (03) and a source-drain layer (110); the photosensitive part (400) is positioned on one side, deviating from the substrate (100), of the thin film transistor (200); the photosensitive part (400) comprises a bottom electrode (11), a PIN layer (12) and a top electrode (14) which are sequentially arranged away from the substrate (100); the bottom electrode (11) is electrically connected with the thin film transistor (200) through the source drain electrode layer (110); the at least one electrode layer (300) is located between the bottom electrode (11) and the substrate (100), each electrode layer in the at least one electrode layer (300) and one conducting layer in the thin film transistor (200) are arranged on the same layer, and the orthographic projection of each electrode layer on the substrate (100) completely falls into the area range of the orthographic projection of the bottom electrode (11) on the substrate (100); at least one storage capacitor including a first storage capacitor is formed between the at least one electrode layer (300) and the bottom electrode (11), and a second storage capacitor is formed between the bottom electrode (11) and the top electrode (14).

Description

Detection panel and flat panel detector

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on February 21, 2024, with application number 202410194512.X and invention name "Detection panel, method for preparing detection panel and flat panel detector", the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present disclosure relates to the field of photoelectric detection technology, and in particular to a detection panel and a flat panel detector. Background Art

[0004] Traditional X-ray imaging technology is analog, with low resolution and poor pixel quality. Digital X-ray imaging technology can directly convert X-ray images into electronic digital signals (direct method). Alternatively, it can first convert X-ray photons into visible light signals, and then convert the visible light signals into electronic digital signals (indirect method).

[0005] Furthermore, X-ray digital imaging technology is widely used in fields such as medical testing, industrial non-destructive testing, and security inspection and protection. The quality of images captured by X-ray detectors is closely related to their performance, with key parameters including spatial resolution, response uniformity, contrast sensitivity, dynamic range, acquisition speed, and frame rate. In particular, with technological advancements, the application scenarios of X-ray detectors have evolved from static to dynamic. Dynamic applications require high sensitivity, high dynamic range, high frame rate, and short response time, and accordingly, a higher dynamic range is required for X-ray detectors.

[0006] As a result, how to improve the dynamic range of X-ray detectors has become a technical problem that needs to be solved urgently. Summary of the Invention

[0007] The present disclosure provides a detection panel and a flat panel detector, the specific solutions are as follows:

[0008] An embodiment of the present disclosure provides a detection panel, comprising:

[0009] substrate;

[0010] A thin film transistor is located on the substrate; the thin film transistor includes a gate layer, an active layer and a source and drain layer;

[0011] a photosensitive portion located on a side of the thin film transistor facing away from the substrate; the photosensitive portion comprises a bottom electrode, a PIN layer, and a top electrode sequentially arranged away from the substrate; the bottom electrode is electrically connected to the thin film transistor via the source and drain layer;

[0012] At least one electrode layer is located between the bottom electrode and the substrate, and each electrode layer in the at least one electrode layer is arranged on the same layer as one of the conductive layers in the thin film transistor, and the orthographic projection of each electrode layer on the substrate completely falls within the area of ​​the orthographic projection of the bottom electrode on the substrate; at least one storage capacitor including a first storage capacitor is formed between the at least one electrode layer and the bottom electrode, and a second storage capacitor is formed between the bottom electrode and the top electrode.

[0013] Optionally, in the embodiment of the present disclosure, the at least one electrode layer is a first electrode layer provided at the same layer as the gate layer, and the at least one storage capacitor is the first storage capacitor formed between the first electrode layer and the bottom electrode.

[0014] Optionally, in the embodiment of the present disclosure, the at least one electrode layer is a second electrode layer arranged in the same layer as the source and drain layer, and the at least one storage capacitor is the first storage capacitor formed between the second electrode layer and the bottom electrode.

[0015] Optionally, in an embodiment of the present disclosure, the at least one electrode layer includes a first electrode layer arranged in the same layer as the gate layer, and a second electrode layer arranged in the same layer as the source and drain layer; the at least one storage capacitor also includes a third storage capacitor formed between the second electrode layer and the bottom electrode, and the first storage capacitor is formed by the first electrode layer and the second electrode layer.

[0016] Optionally, in an embodiment of the present disclosure, the source-drain layer includes a source layer located on the side of the active layer away from the substrate, the source layer is arranged in a stepped manner, and the source layer includes a first connection portion, a second connection portion and a third connection portion that are connected in sequence; the first connection portion and the third connection portion are both arranged in a direction parallel to the plane where the substrate is located; the distance between the first connection portion and the substrate is greater than the distance between the third connection portion and the substrate, and the orthographic projection of the first connection portion on the substrate and the orthographic projection of the third connection portion on the substrate do not overlap with each other.

[0017] Optionally, in an embodiment of the present disclosure, a lap portion is provided at one end of the third connecting portion facing away from the second connecting portion, the lap portion is electrically connected to the bottom electrode and the first electrode layer respectively, and a groove structure is provided on the side of the lap portion facing away from the first electrode layer.

[0018] Optionally, in an embodiment of the present disclosure, it also includes a bias electrode located on the side of the top electrode facing away from the substrate, and a bias bus arranged around the display area of ​​the detection panel, wherein the bias bus is electrically connected to a first conductive layer arranged on the same layer as the bottom electrode; the first conductive layer is electrically connected to the second electrode layer through a first via hole penetrating the insulating layer between the bottom electrode and the source and drain layer, and is electrically connected to the bias electrode through a second via hole penetrating the insulating layer between the bottom electrode and the bias electrode.

[0019] Optionally, in an embodiment of the present disclosure, the bias bus includes a first type of transfer structure, a second type of transfer structure and a third type of transfer structure, and the first type of transfer structure, the second type of transfer structure and the third type of transfer structure are respectively electrically connected through a second conductive layer arranged on the same layer as the bias electrode.

[0020] Optionally, in an embodiment of the present disclosure, it also includes an internal short-circuit ring arranged around the display area, and the first type of transfer structure and the second type of transfer structure are both located on the side of the internal short-circuit ring away from the display area; the third type of transfer structure is located between the internal short-circuit ring and the display area; the first type of transfer structure is symmetrically distributed with the display area as the center along the direction parallel to the data line in the detection panel; the second type of transfer structure is respectively located at the diagonal positions of the display area and is diagonally symmetrically arranged; the third type of transfer structure is symmetrically distributed with the display area as the center along the direction parallel to the gate line in the detection panel.

[0021] Optionally, in an embodiment of the present disclosure, the first type of adapter structure includes multiple first adapter units; multiple groups of via combinations are opened on each first adapter unit along the direction parallel to the data line in the detection panel, each group of via combinations includes at least one pair of vias, and each pair of vias includes the first via and the second via.

[0022] Optionally, in an embodiment of the present disclosure, a window structure is provided between two adjacent groups of via combinations, and an orthographic projection area of ​​the window structure on the substrate is larger than an orthographic projection area of ​​each via in each group of via combinations on the substrate.

[0023] Optionally, in an embodiment of the present disclosure, it also includes multiple read signal lines located in the peripheral area of ​​the detection panel; a read signal line is arranged between two adjacent first adapter units located on the same side of the display area in the first type of adapter structure; each read signal line is electrically connected to the data line in the display area.

[0024] Optionally, in an embodiment of the present disclosure, the second type adapter structure includes multiple second adapter units; multiple groups of via combinations are opened on each second adapter unit along a direction parallel to the data line in the detection panel, and each group of via combinations includes at least two second vias.

[0025] Optionally, in an embodiment of the present disclosure, the third type of transfer structure includes multiple third transfer units; a gate line is arranged between two adjacent third transfer units located on the same side of the display area in the third type of transfer structure; each gate line is electrically connected to the gate layer of the thin film transistor.

[0026] Optionally, in the embodiment of the present disclosure, it also includes a bias electrode located on the side of the top electrode facing away from the substrate, and a transparent electrode layer located on the side of the bias electrode facing away from the substrate, and the orthographic projection of the bottom electrode on the substrate completely falls within the area of ​​the orthographic projection of the transparent electrode layer on the substrate; the at least one storage capacitor also includes a fourth storage capacitor composed of the bias electrode and the transparent electrode layer.

[0027] Optionally, in the embodiment of the present disclosure, it also includes a first passivation layer located between the bottom electrode and the source and drain layer, a first resin layer located between the first passivation layer and the source and drain layer, a second passivation layer located on the side of the bias electrode close to the substrate, a second resin layer located between the second passivation layer and the PIN layer, and a third passivation layer located between the bias electrode and the transparent electrode layer; the bottom electrode is electrically connected to the source and drain layer through a third via hole penetrating the first passivation layer and a fourth via hole penetrating the first resin layer in sequence; the bias electrode is electrically connected to the top electrode through a fifth via hole penetrating the second passivation layer and the second resin layer in sequence.

[0028] Optionally, in the embodiment of the present disclosure, the orthographic projection of the fifth via on the substrate completely falls within the area of ​​the orthographic projection of the thin film transistor on the substrate; the orthographic projection of the third via on the substrate completely falls within the area of ​​the orthographic projection of the fourth via on the substrate.

[0029] Optionally, in an embodiment of the present disclosure, the second passivation layer is provided as a whole layer, the orthographic projection of the third passivation layer on the substrate and the orthographic projection of the bias electrode on the substrate are arranged to overlap with each other, and the orthographic projection of the third passivation layer on the substrate completely falls within the area of ​​the orthographic projection of the second passivation layer on the substrate.

[0030] Optionally, in an embodiment of the present disclosure, the third passivation layer is provided as a whole layer, the orthographic projection of the second passivation layer on the substrate and the orthographic projection of the bias electrode on the substrate are arranged to overlap with each other, and the orthographic projection of the second passivation layer on the substrate completely falls within the area of ​​the orthographic projection of the third passivation layer on the substrate.

[0031] Optionally, in an embodiment of the present disclosure, the first electrode layer includes a first main body portion and a first extension portion, which extends outward and is symmetrically arranged relative to the first extension portions on both sides of the first main body portion in a direction parallel to the gate lines in the detection panel, and the first extension portion is used to be electrically connected to the first bias line in the detection panel, and the bias electrode is used to be electrically connected to the second bias line in the detection panel.

[0032] Optionally, in an embodiment of the present disclosure, the orthographic projections of the first main body portion and the bias electrode on the substrate do not overlap with each other, and at the overlapping position of the first extension portion and the bias electrode, the maximum size of the corresponding part of the first extension portion is smaller than the maximum size at the non-overlapping position; at the overlapping position of the bias electrode and the first extension portion, the maximum size of the corresponding part of the bias electrode is smaller than the maximum size at the non-overlapping position.

[0033] Optionally, in an embodiment of the present disclosure, the second electrode layer includes a second main body portion and a second extension portion, which extends outward and is symmetrically arranged relative to the second extension portions on both sides of the second main body portion in a direction parallel to the data line in the detection panel, and the second extension portion is used to be electrically connected to the first bias line in the detection panel, and the bias electrode is used to be electrically connected to the second bias line in the detection panel.

[0034] Optionally, in the embodiment of the present disclosure, a gate insulating layer is further included between the active layer and the gate layer, and the gate insulating layer includes a silicon nitride layer and a silicon oxide layer which are sequentially arranged away from the substrate.

[0035] Accordingly, an embodiment of the present disclosure provides a flat panel detector, comprising:

[0036] A detection panel as described in any one of the above. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] FIG1 is a schematic structural diagram of a detection panel provided in an embodiment of the present disclosure;

[0038] FIG2 is a schematic diagram of a structure of a detection panel provided in an embodiment of the present disclosure;

[0039] FIG3 is a schematic diagram of a structure of a detection panel provided in an embodiment of the present disclosure;

[0040] FIG4 is a schematic diagram of a top view of a detection panel provided in an embodiment of the present disclosure;

[0041] FIG5 is an enlarged schematic diagram of one structure of area Q in FIG4 ;

[0042] FIG6 is a schematic diagram of a cross-sectional structure taken along the direction indicated by MM in FIG5 ;

[0043] FIG7 is a schematic diagram of a top view of a detection panel provided in an embodiment of the present disclosure;

[0044] FIG8 is a schematic diagram of a cross-sectional structure along the direction NN in FIG7 ;

[0045] FIG9 is a schematic diagram of a top view of a detection panel according to an embodiment of the present disclosure;

[0046] FIG10 is a schematic diagram of a cross-sectional structure along the direction OO in FIG9 ;

[0047] FIG11 is a SEM schematic diagram of a local area in FIG9 ;

[0048] FIG12 is a schematic diagram of a top view of a detection panel according to an embodiment of the present disclosure;

[0049] FIG13 is a schematic diagram of a cross-sectional structure along the direction PP in FIG12 ;

[0050] FIG14 is a SEM schematic diagram of FIG12 ;

[0051] FIG15 is a schematic diagram of a top view of a detection panel according to an embodiment of the present disclosure;

[0052] FIG16 is a schematic diagram of a cross-sectional structure along the direction indicated by QQ in FIG15 ;

[0053] FIG17 is a schematic diagram of a top view of a detection panel according to an embodiment of the present disclosure;

[0054] FIG18 is a schematic diagram of a cross-sectional structure along the direction indicated by RR in FIG17 ;

[0055] FIG19 is a schematic diagram of a top view of a detection panel according to an embodiment of the present disclosure;

[0056] FIG20 is an enlarged schematic diagram of a partial region structure of the first extension portion and the top electrode in FIG19;

[0057] FIG21 is a schematic diagram of a top view of a detection panel according to an embodiment of the present disclosure;

[0058] FIG22 is a schematic diagram of a cross-sectional structure along the direction indicated by LL in FIG21 ;

[0059] FIG23 is a schematic diagram of a cross-sectional structure along the direction SS in FIG21;

[0060] FIG24 is a schematic diagram of a cross-sectional structure along the direction indicated by TT in FIG21;

[0061] FIG25( a ) is a schematic top view of one structure of the first electrode layer in FIG12 ;

[0062] FIG25( b ) is a schematic top view of one structure of the second electrode layer in FIG12 ;

[0063] FIG25( c ) is a schematic top view of one of the structures of the first electrode layer and the second electrode layer in FIG12 ;

[0064] FIG26 is a schematic diagram of one structure of the first electrode layer and the second electrode layer in the detection panel provided by an embodiment of the present disclosure;

[0065] FIG. 27( a ) to FIG. 27 ( m ) are flowcharts showing one process for preparing the detection panel shown in FIG. 12 . DETAILED DESCRIPTION

[0066] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0067] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0068] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0069] In the related art, for the indirect type, the principle of the X-ray detector is that the X-ray photons are converted into visible light signals through the scintillator layer or phosphor layer of the indirect conversion type X-ray flat panel detector, and then the visible light signals are converted into electrical signals under the action of the photodiode, and finally the electrical signals are read and output by the thin film transistor (TFT), and the electrical signals are converted into digital signals after analog-to-digital (A / D) conversion; the photodiode is equivalent to a capacitor under negative bias, and the free electrons generated after exposure to light are equivalent to capacitor discharge, and the pixel voltage drops from 1V to -6V; through TFT control, the read chip (Read Out Integrated Circuit, ROIC) reads the charge loss of each pixel in sequence and converts it into a grayscale image. The storage capacitance of the pixel and the feedback capacitance of the detector circuit board will affect the dynamic range and sensitivity of the detector. The storage capacitance of the conventional detection panel only includes the capacitance between the bottom electrode of the photosensitive part and the conductive film layer on the upper surface of the PIN layer, which cannot meet the requirements of high dynamic range.

[0070] In view of this, embodiments of the present disclosure provide a detection panel and a flat panel detector for improving the dynamic range of the detector.

[0071] With reference to FIG. 1 to FIG. 22 , an embodiment of the present disclosure provides a detection panel, including:

[0072] substrate 100;

[0073] Exemplarily, the substrate 100 may be a silicon-based substrate 100 or a glass-based substrate 100 , which is not limited herein.

[0074] A thin film transistor 200 is located on the substrate 100 ; the thin film transistor 200 includes a gate layer 01 , an active layer 03 and a source / drain layer 110 ;

[0075] Exemplarily, the thin film transistor 200 may be a bottom-gate structure. Accordingly, the thin film transistor 200 includes a gate layer 01, an active layer 03, and a source-drain electrode layer 110, which are sequentially disposed away from the substrate 100. The source-drain electrode layer 110 includes a source electrode layer 05 and a drain electrode layer 04, which are spaced apart. Exemplarily, the thin film transistor 200 may also be a top-gate structure. Accordingly, the thin film transistor 200 includes an active layer 03, a gate layer 01, and a source-drain electrode layer 110, which are sequentially disposed away from the substrate 100. In the embodiments of the present disclosure, unless otherwise specified, the bottom-gate thin film transistor 200 is taken as an example to explain the relevant technical solutions in the embodiments of the present disclosure.

[0076] The photosensitive portion 400 is located on a side of the thin film transistor 200 facing away from the substrate 100 . The photosensitive portion 400 includes a bottom electrode 11 , a PIN layer 12 , and a top electrode 14 , which are sequentially arranged away from the substrate 100 . The bottom electrode 11 is electrically connected to the thin film transistor 200 via the source / drain layer 110 .

[0077] During the specific implementation process, the detection panel also includes a photosensitive portion 400 located on the side of the thin film transistor 200 facing away from the substrate 100. Exemplarily, the photosensitive portion 400 can be a photodiode for converting between optical signals and electrical signals. For example, the photosensitive portion 400 can be a photodiode with a PIN structure. Exemplarily, the photosensitive portion 400 includes a bottom electrode 11, a PIN layer 12, and a top electrode 14, which are sequentially arranged away from the substrate 100. The PIN layer 12 includes a P-type semiconductor layer, an N-type semiconductor layer, and an intrinsic semiconductor layer located between the P-type semiconductor layer and the N-type semiconductor layer. In addition, the bottom electrode 11 is electrically connected to the thin film transistor 200 through the source and drain layer 110. In this way, the photosensitive portion 400 can be controlled by the thin film transistor 200.

[0078] At least one electrode layer 300 is located between the bottom electrode 11 and the substrate 100, and each electrode layer in the at least one electrode layer 300 is arranged on the same layer as one of the conductive layers in the thin film transistor 200, and the orthographic projection of each electrode layer on the substrate 100 completely falls within the area of ​​the orthographic projection of the bottom electrode 11 on the substrate 100; at least one storage capacitor including a first storage capacitor is formed between the at least one electrode layer 300 and the bottom electrode 11, and a second storage capacitor is formed between the bottom electrode 11 and the top electrode 14.

[0079] In a specific implementation, the detection panel further includes at least one electrode layer 300 located between the bottom electrode 11 and the substrate 100. The at least one electrode layer 300 can be one layer, two layers, or three or more layers, without limitation. Furthermore, each electrode layer in the at least one electrode layer 300 is disposed co-located with one of the conductive layers in the thin-film transistor 200. For example, the conductive layer in the thin-film transistor 200 can be the gate layer 01 or the source / drain layer 110.

[0080] It should be noted that, in the embodiments of the present disclosure, unless otherwise specified, "same layer" refers to the same layer deposited and prepared in the process; or, deposited by different processes but physically located in the same layer.

[0081] Furthermore, the orthographic projections of each of the at least one electrode layer 300 on the substrate 100 completely fall within the orthographic projection area of ​​the bottom electrode 11 on the substrate 100. At least one storage capacitor, including a first storage capacitor, is formed between the at least one electrode layer 300 and the bottom electrode 11, and a second storage capacitor is formed between the bottom electrode 11 and the top electrode 14. Thus, by adding at least one additional electrode layer 300 to the detection panel, the total storage capacitance, including at least the first storage capacitor and the second storage capacitor, can be increased to a certain extent compared to the storage capacitance of a conventional detection panel, thereby effectively improving the dynamic range of the detection panel.

[0082] In the embodiment of the present disclosure, at least one electrode layer 300 may be provided in the following implementation manners, but is not limited thereto.

[0083] In one exemplary embodiment, FIG1 is a schematic structural diagram of a detection panel provided by an embodiment of the present disclosure. Specifically, the at least one electrode layer 300 is a first electrode layer 07 disposed on the same layer as the gate layer 01, and the at least one storage capacitor is the first storage capacitor formed between the first electrode layer 07 and the bottom electrode 11.

[0084] Still referring to the exemplary embodiment shown in FIG1 , at least one electrode layer 300 includes a first electrode layer 07 disposed in the same layer as the gate layer 01. Accordingly, a first storage capacitor can be formed between the first electrode layer 07 and the bottom electrode 11. Thus, the total storage capacitance of the detection panel includes the first storage capacitance formed between the first electrode layer 07 and the bottom electrode 11, and the second storage capacitance formed between the bottom electrode 11 and the top electrode 14. Thus, by adding the additional first electrode layer 07 to the detection panel, the total storage capacitance, including the first storage capacitance and the second storage capacitance, can be increased to a certain extent compared to the storage capacitance of a conventional detection panel, thereby effectively improving the dynamic range of the detection panel.

[0085] Illustratively, during the fabrication process, the first electrode layer 07 and the gate layer 01 in the thin-film transistor 200 are formed by depositing the same conductive material. Illustratively, different processes may be used to deposit the conductive materials required for the respective layers to form the first electrode layer 07 and the gate layer 01. Physically, the first electrode layer 07 and the gate layer 01 are located on the same layer within the detection panel.

[0086] In one exemplary embodiment, FIG2 is a schematic structural diagram of a detection panel provided by an embodiment of the present disclosure. Specifically, the at least one electrode layer 300 is a second electrode layer 08 disposed in the same layer as the source / drain layer 110, and the at least one storage capacitor is the first storage capacitor formed between the second electrode layer 08 and the bottom electrode 11.

[0087] Still referring to the exemplary embodiment shown in FIG2 , at least one electrode layer 300 includes a second electrode layer 08 disposed in the same layer as the source / drain electrode layer 110. Accordingly, a first storage capacitor can be formed between the second electrode layer 08 and the bottom electrode 11. Thus, the total storage capacitance of the detection panel includes the first storage capacitance formed between the second electrode layer 08 and the bottom electrode 11, and the second storage capacitance formed between the bottom electrode 11 and the top electrode 14. Thus, by adding an additional first electrode layer 07 to the detection panel, the total storage capacitance can be increased to a certain extent by including the first storage capacitance and the second storage capacitance compared to the storage capacitance of a conventional detection panel, thereby effectively improving the dynamic range of the detection panel.

[0088] Illustratively, during the fabrication process, the second electrode layer 08 and the source / drain layer 110 in the thin film transistor 200 are formed by depositing the same conductive material. Illustratively, different processes may be used to deposit the conductive materials required for the respective layers to form the second electrode layer 08 and the source / drain layer 110. Physically, the second electrode layer 08 and the source / drain layer 110 are located on the same layer within the detection panel.

[0089] In one exemplary embodiment, FIG3 shows a schematic structural diagram of a detection panel provided by an embodiment of the present disclosure. Specifically, the at least one electrode layer 300 includes a first electrode layer 07 disposed on the same layer as the gate layer 01, and a second electrode layer 08 disposed on the same layer as the source / drain layer 110. The at least one storage capacitor also includes a third storage capacitor formed between the second electrode layer 08 and the bottom electrode 11. The first storage capacitor is formed by the first electrode layer 07 and the second electrode layer 08.

[0090] Still referring to the exemplary embodiment shown in FIG3 , at least one electrode layer 300 includes a first electrode layer 07 disposed on the same layer as the gate layer 01, and a second electrode layer 08 disposed on the same layer as the source / drain layer 110. Accordingly, a third storage capacitor can be formed between the second electrode layer 08 and the bottom electrode 11. In addition, a first storage capacitor is formed between the first electrode layer 07 and the second electrode layer 08. Thus, the total storage capacitance of the detection panel includes the third storage capacitance formed between the second electrode layer 08 and the bottom electrode 11, and the first storage capacitance formed between the first electrode layer 07 and the second electrode layer 08. Thus, by adding the additional first electrode layer 07 and the second electrode layer 08 to the detection panel, the inclusion of the third storage capacitance and the first storage capacitance can, to a certain extent, increase the total storage capacitance compared to the storage capacitance of a conventional detection panel, thereby effectively improving the dynamic range of the detection panel.

[0091] Exemplarily, during the preparation process, the first electrode layer 07 and the gate layer 01 in the thin film transistor 200 are film layers formed by depositing the same layer of conductive material. Exemplarily, different processes may be used to deposit the conductive materials required for the corresponding film layers to form the first electrode layer 07 and the gate layer 01; physically, the first electrode layer 07 and the gate layer 01 are located in the same layer within the detection panel. During the preparation process, the second electrode layer 08 and the source and drain layer 110 in the thin film transistor 200 are film layers formed by depositing the same layer of conductive material. Exemplarily, different processes may be used to deposit the conductive materials required for the corresponding film layers to form the second electrode layer 08 and the source and drain layer 110; physically, the second electrode layer 08 and the source and drain layer 110 are located in the same layer within the detection panel.

[0092] Still referring to the exemplary embodiment shown in Figure 3, the source-drain layer 110 includes a source layer 05 located on the side of the active layer 03 away from the substrate 100, the source layer 05 is arranged in a stepped manner, and the source layer 05 includes a first connecting portion 051, a second connecting portion 052 and a third connecting portion 053 that are connected in sequence; the first connecting portion 051 and the third connecting portion 053 are both arranged in a direction parallel to the plane of the substrate 100; the distance between the first connecting portion 051 and the substrate 100 is greater than the distance between the third connecting portion 053 and the substrate 100, and the orthographic projection of the first connecting portion 051 on the substrate 100 and the orthographic projection of the third connecting portion 053 on the substrate 100 do not overlap with each other.

[0093] Still combining with the exemplary embodiment shown in Figure 3, a lap portion 054 is provided at one end of the third connecting portion 053 away from the second connecting portion 052, and the lap portion 054 is electrically connected to the bottom electrode 11 and the first electrode layer 07 respectively, and a groove structure 055 is provided on the side of the lap portion 054 away from the first electrode layer 07.

[0094] In a specific implementation, to achieve electrical connection between the thin-film transistor 200 and the photosensitive portion 400, an overlapping portion 054 is provided at one end of the third connecting portion 053 facing away from the second connecting portion 052. A groove structure 055 is also provided on the side of the overlapping portion 054 facing away from the first electrode layer 07. The overlapping portion 054 is electrically connected to the bottom electrode 11 and the first electrode layer 07, respectively, through the groove structure 055. This prevents the detection panel from over-sizing the overall via hole at the location of the groove structure 055, thereby increasing the pixel fill rate.

[0095] In the embodiment of the present disclosure, in combination with Figures 4 to 6, Figure 4 is a schematic diagram of a top view structure of a detection panel provided in the embodiment of the present disclosure; Figure 5 is an enlarged schematic diagram of a structure of area Q in Figure 4; and Figure 6 is a schematic diagram of a cross-sectional structure along the direction indicated by MM in Figure 5. Specifically, the detection panel further includes a bias electrode 16 located on the side of the top electrode 14 facing away from the substrate 100, and a bias bus (Bias Bus) 500 arranged around the display area AA of the detection panel, the bias bus 500 being electrically connected to a first conductive layer 111 provided on the same layer as the bottom electrode 11; the first conductive layer 111 is electrically connected to the second electrode layer 08 via a first via H1 penetrating the insulating layer between the bottom electrode 11 and the source-drain layer 110, and is electrically connected to the bias electrode 16 via a second via H2 penetrating the insulating layer between the bottom electrode 11 and the bias electrode 16.

[0096] Still referring to the exemplary embodiment shown in FIG4 , the detection panel includes a display area AA and a peripheral area BB surrounding the display area AA; the detection panel also includes a bias electrode 16 located on the side of the top electrode 14 facing away from the substrate 100, and a bias bus 500 arranged around the display area AA, that is, the bias bus 500 is arranged in the peripheral area BB. In this way, a bias signal can be applied to the pixels in the display area AA via the bias bus 500, thereby ensuring the uniformity of the bias signal. In addition, the bias bus 500 is electrically connected to the first conductive layer 111 arranged on the same layer as the bottom electrode 11. During the preparation process, the bottom electrode 11 and the first conductive layer 111 are film layers formed by depositing the same layer of conductive material. For example, different processes can be used to deposit the conductive materials required for the corresponding film layers to form the bottom electrode 11 and the first conductive layer 111; physically, the bottom electrode 11 and the first conductive layer 111 are located on the same layer within the detection panel.

[0097] Still referring to FIG6 , the first conductive layer 111 can be electrically connected to the second electrode layer 08 via a first via H1 that penetrates the insulating layer between the bottom electrode 11 and the source / drain layer 110. In this way, the bias signal from the bias bus 500 can be transmitted to the first conductive layer 111, and then transmitted to the second electrode layer 08 via the first via H1 through the first conductive layer 111, thereby enabling the loading of the bias signal to the second electrode layer 08 of the corresponding pixel. Simultaneously, the bias signal from the bias bus 500 can be transmitted to the first conductive layer 111, and then transmitted to the bias electrode 16 via the second via H2 through the first conductive layer 111, thereby enabling the loading of the bias signal to the top electrode 14 of the corresponding pixel. In this way, while improving the storage capacitance of the detection panel, the detection performance of the detection panel is also taken into account.

[0098] In the embodiment of the present disclosure, the bias bus 500 may be configured in the following manner, but is not limited thereto.

[0099] Still referring to the exemplary embodiment shown in FIG. 4 , the bias bus 500 includes a first-type transfer structure 501, a second-type transfer structure 502, and a third-type transfer structure 503. The first-type transfer structure 501, the second-type transfer structure 502, and the third-type transfer structure 503 are electrically connected via a second conductive layer 161 disposed on the same layer as the bias electrode 16. This ensures that the bias bus 500 effectively loads the bias signal to the pixel. In actual manufacturing, the first-type transfer structure 501, the second-type transfer structure 502, and the third-type transfer structure 503 can be rationally arranged to effectively utilize the layout space of the detection panel.

[0100] It should be noted that during the fabrication process, the bias electrode 16 and the second conductive layer 161 are formed by depositing the same conductive material. For example, the bias electrode 16 and the second conductive layer 161 can be formed by depositing the conductive materials required for the respective layers using different processes. Physically, the bias electrode 16 and the second conductive layer 161 are located on the same layer within the detection panel.

[0101] Still combining with the exemplary embodiment shown in Figure 4, the detection panel also includes an inner short ring (Inner Short Ring) 19 arranged around the display area AA, and the first-type transfer structure 501 and the second-type transfer structure 502 are both located on the side of the inner short ring 19 away from the display area AA; the third-type transfer structure 503 is located between the inner short ring 19 and the display area AA; the first-type transfer structure 501 is symmetrically distributed with the display area AA as the center along a direction parallel to the data line D in the detection panel; the second-type transfer structure 502 is respectively located at the diagonal positions of the display area AA and is diagonally symmetrically arranged; the third-type transfer structure 503 is symmetrically distributed with the display area AA as the center along a direction parallel to the gate line (gate) G in the detection panel.

[0102] In practice, the internal shorting ring 19 is used to provide electrostatic discharge (ESD) protection for the detection panel, effectively reducing detection failures caused by electrostatic discharge, such as screen flickering, dead pixels, or screen distortion, thereby improving the reliability and stability of the detection panel and extending its service life. The direction indicated by arrow X in FIG4 is parallel to the gate lines G within the detection panel, and the direction indicated by arrow Y is parallel to the data lines D within the detection panel.

[0103] In the embodiment of the present disclosure, the first type of adapter structure 501 includes multiple first adapter units 5011; multiple groups of via combinations are opened on each of the first adapter units 5011 along the direction parallel to the data line D in the detection panel, each group of via combinations includes at least one pair of vias, and each pair of vias includes the first via H1 and the second via H2.

[0104] In the specific implementation process, the number of the multiple first adapter units 5011 can be two, or three or more, which is not limited here. The number of via combinations provided on each first adapter unit 5011 can be two, or two or more, which is not limited here. The at least one pair of vias included in each via combination can be one, or two or more, which is not limited here. Each pair of vias includes a first via H1 that penetrates the insulating layer between the bottom electrode 11 and the source-drain layer 110, and a second via H2 that penetrates the insulating layer between the bottom electrode 11 and the bias electrode 16.

[0105] Still referring to the exemplary embodiment shown in FIG4 , the first-type adapter structure 501 includes six first adapter units 5011. Each first adapter unit 5011 has three via hole combinations, each via hole combination including a pair of via holes. This ensures the effective transmission of the bias signal on the first-type adapter structure 501.

[0106] In the embodiment of the present disclosure, a window structure 5012 is provided between two adjacent via hole combinations, and the orthographic projection area of ​​the window structure 5012 on the substrate 100 is larger than the orthographic projection area of ​​each via hole in each via hole combination on the substrate 100.

[0107] Still referring to the exemplary embodiment shown in FIG4 , a window structure 5012 is provided between two adjacent via-hole groups on the first adapter unit 5011. This reduces the unevenness of the aluminum film at the location of the window structure 5012 during subsequent packaging, improves adhesion to the cover plate, and ensures the structural stability of the detection panel.

[0108] In the embodiment of the present disclosure, the detection panel also includes a plurality of read signal lines (Read Out) Ro located in the peripheral area BB of the detection panel; a read signal line Ro is arranged between two adjacent first adapter units 5011 located on the same side of the display area AA in the first type adapter structure 501; each read signal line Ro is electrically connected to the data line D in the display area AA.

[0109] In a specific implementation, a read signal line Ro is provided between two adjacent first adapter units 5011 located on the same side of the display area AA in the first-type adapter structure 501. This read signal line Ro is electrically connected to the corresponding data line D within the display area AA. This enables the detection panel to effectively read the detection signals of the corresponding pixels within the display area AA. Furthermore, the specific number of the multiple read signal lines Ro can be the same as the specific number of data lines D within the detection panel, or can be the same as the specific number of first adapter units 5011 located on the same side of the display area AA.

[0110] In the embodiment of the present disclosure, the second-type adapter structure 502 includes multiple second adapter units 5021; multiple groups of via combinations are opened on each second adapter unit 5021 along the direction parallel to the data line D in the detection panel, and each group of via combinations includes at least two second vias H2.

[0111] In the specific implementation process, the multiple second adapter units 5021 can be two, or three or more, which is not limited here. Along the direction parallel to the data line D in the detection panel, each second adapter unit 5021 is provided with multiple groups of via combinations, and the multiple groups of via combinations can be two groups, or three or more groups, which is not limited here. Each group of via combinations includes at least two second vias H2, and the at least two second vias H2 can be two, or three or more. Still in combination with the exemplary embodiment shown in Figure 4, the second type of adapter structure 502 includes four second adapter units 5021, and each second adapter unit 5021 is respectively located at the diagonal position of the display area AA; along the direction parallel to the data line D in the detection panel, each second adapter unit 5021 is provided with three groups of via combinations, and each group of via combinations includes three second vias H2.

[0112] In the embodiment of the present disclosure, the third-type transfer structure 503 includes multiple third transfer units 5031; a gate line G is arranged between two adjacent third transfer units 5031 located on the same side of the display area AA in the third-type transfer structure 503; each gate line G is electrically connected to the gate layer 01 of the thin film transistor 200.

[0113] In the specific implementation process, the multiple third adapter units 5031 can be two, or three or more, which is not limited here. In addition, a gate line G is provided between two adjacent third adapter units 5031 located on the same side of the display area AA in the third type adapter structure 503. At least one group of via combinations is provided on each third adapter unit 5031 along the direction parallel to the data line D in the detection panel, and each group of via combinations includes at least two second vias H2. The at least two second vias H2 can be two, or three or more, which is not limited here. In one exemplary embodiment, each third adapter unit 5031 can be provided with multiple groups of via combinations, and a window structure 5012 can be provided between two adjacent groups of via combinations, which is not limited here. In addition, in actual applications, the specific number of third adapter units 5031 located on the same side of the display area AA in the third type adapter structure 503 can be the same as the specific number of gate lines G in the display area AA of the detection panel. Still referring to the exemplary embodiment shown in FIG. 4 , the third type adapter structure 503 includes six third adapter units 5031 . Three third adapter units 5031 are provided on the same side of the display area AA in the third type adapter structure 503 .

[0114] It should be noted that, in order to illustrate the specific setting of the bias bus 500 in the embodiment of the present disclosure, in the exemplary embodiment shown in FIG4 , only the situation in which six pixels, three gate lines G and three data lines D are set in the display area AA is illustrated. In the specific implementation process, the relevant settings are not limited to this, and can be set according to actual needs. In the embodiment of the present disclosure, the orthographic projection areas of the second vias H2 on the substrate 100 are equal. The "equal" mentioned here can be roughly equal or approximately equal, and is not limited here. In addition, in actual applications, the more vias are opened in each group of via combinations, the more uniform the transmission of the corresponding bias signal. Of course, in the actual process of manufacturing the detection panel, the arrangement of the vias on each adapter unit on various adapter structures can be set according to actual application needs.

[0115] In the embodiment of the present disclosure, in combination with Figures 7 to 19, the detection panel also includes a bias electrode 16 located on the side of the top electrode 14 facing away from the substrate 100, and a transparent electrode layer 18 located on the side of the bias electrode 16 facing away from the substrate 100, and the orthographic projection of the bottom electrode 11 on the substrate 100 completely falls within the area of ​​the orthographic projection of the transparent electrode layer 18 on the substrate 100; the at least one storage capacitor also includes a fourth storage capacitor composed of the bias electrode 16 and the transparent electrode layer 18.

[0116] In a specific implementation process, the detection panel also includes a bias electrode 16 located on the side of the top electrode 14 facing away from the substrate 100, and a transparent electrode layer 18 located on the side of the bias electrode 16 facing away from the substrate 100. Exemplarily, the transparent electrode layer 18 can be indium tin oxide (ITO) or indium zinc oxide (IZO), which is not limited here. In addition, the orthographic projection of the bottom electrode 11 on the substrate 100 completely falls within the area of ​​the orthographic projection of the transparent electrode layer 18 on the substrate 100. In this way, the fourth storage capacitor formed between the transparent electrode layer 18 and the bias electrode 16 can be maximized, thereby improving the dynamic range of the detection panel to a certain extent.

[0117] In one exemplary embodiment, FIG7 shows a schematic top view of a detection panel, and FIG8 shows a schematic cross-sectional view taken along the direction indicated by line NN in FIG7 . Specifically, the detection panel comprises at least one electrode layer 300, a first electrode layer 07, disposed on the same layer as the gate layer 01. The detection panel also includes a bias electrode 16 located on the side of the top electrode 14 facing away from the substrate 100, and a transparent electrode layer 18 located on the side of the bias electrode 16 facing away from the substrate 100. In this exemplary embodiment, bias signals can be applied to the first electrode layer 07 and the bias electrode 16, respectively, to form a first storage capacitor between the first electrode layer 07 and the bottom electrode 11, a second storage capacitor between the bottom electrode 11 and the top electrode 14, and a fourth storage capacitor between the bias electrode 16 and the transparent electrode layer 18. As a result, compared to the storage capacitors of conventional detection panels, the total storage capacitor includes the first storage capacitor, the second storage capacitor, and the fourth storage capacitor, thereby improving the dynamic range of the detection panel to a certain extent.

[0118] In one exemplary embodiment, the orthographic projection of the PIN layer 12 on the substrate 100 completely falls within the area of ​​the orthographic projection of the transparent electrode layer 18 on the substrate 100, but a certain distance exists between the transparent electrode layers 18 of two adjacent pixels. In the actual manufacturing process, the area of ​​the transparent electrode layer 18 is maximized to increase the fourth storage capacitance between the bias electrode 16 and the transparent electrode layer 18, thereby significantly increasing the storage capacitance of the entire pixel and improving the dynamic range of the detection panel.

[0119] In one exemplary embodiment, FIG9 is a schematic diagram of a top view of a detection panel, FIG10 is a schematic diagram of a cross-sectional structure along the direction indicated by OO in FIG9 , and FIG11 is a schematic diagram of a scanning electron microscope (SEM) of a local area in FIG9 . In the SEM image shown in FIG11 , GI is a gate insulating layer, PVX1-1 & PVX1-2 are fourth passivation layers, RESIN0 is a first resin layer, PVX1-3 is a first passivation layer, buffer is a buffer layer, PIN is a PIN layer; RESIN1 is a second resin layer, PVX2 is a second passivation layer, PVX3 is a third passivation layer, ITO is a transparent electrode layer, SD is a source-drain layer, and SD2 is a bottom electrode. Specifically, at least one electrode layer 300 of the detection panel is a second electrode layer 08 disposed in the same layer as the source / drain layer 110. The detection panel also includes a bias electrode 16 located on the side of the top electrode 14 facing away from the substrate 100, and a transparent electrode layer 18 located on the side of the bias electrode 16 facing away from the substrate 100. In this exemplary embodiment, bias signals can be applied to the second electrode layer 08 and the bias electrode 16, respectively, so that a first storage capacitor is formed between the second electrode layer 08 and the bottom electrode 11, a second storage capacitor is formed between the bottom electrode 11 and the top electrode 14, and a fourth storage capacitor is formed between the bias electrode 16 and the transparent electrode layer 18. In this way, compared to the storage capacitor of a conventional detection panel, the total storage capacitor includes the first storage capacitor, the second storage capacitor, and the fourth storage capacitor, thereby improving the dynamic range of the detection panel to a certain extent.

[0120] In one exemplary embodiment, FIG12 shows a schematic top view of a detection panel, FIG13 shows a schematic cross-sectional view along the direction indicated by PP in FIG12, and FIG14 shows an SEM view of FIG12. Specifically, the at least one electrode layer 300 of the detection panel includes a first electrode layer 07 disposed in the same layer as the gate layer 01 and a second electrode layer 08 disposed in the same layer as the source / drain layer 110. The detection panel also includes a bias electrode 16 located on the side of the top electrode 14 facing away from the substrate 100, and a transparent electrode layer 18 located on the side of the bias electrode 16 facing away from the substrate 100. In this exemplary embodiment, bias signals can be applied to the second electrode layer 08 and the bias electrode 16, respectively, so that a first storage capacitor is formed between the first electrode layer 07 and the second electrode layer 08, a second storage capacitor is formed between the bottom electrode 11 and the top electrode 14, a third storage capacitor is formed between the second electrode layer 08 and the bottom electrode 11, and a fourth storage capacitor is formed between the bias electrode 16 and the transparent electrode layer 18. As a result, compared with the storage capacitor of a conventional detection panel, the total storage capacitor includes the first storage capacitor, the second storage capacitor and the fourth storage capacitor, thereby improving the dynamic range of the detection panel to a certain extent.

[0121] In the embodiment of the present disclosure, still in combination with Figures 7 to 19, the detection panel also includes a first passivation layer 06 located between the bottom electrode 11 and the source-drain layer 110, a first resin layer 09 located between the first passivation layer 06 and the source-drain layer 110, a second passivation layer 15 located on the side of the bias electrode 16 close to the substrate 100, a second resin layer 13 located between the second passivation layer 15 and the PIN layer 12, and a third passivation layer 17 located between the bias electrode 16 and the transparent electrode layer 18; the bottom electrode 11 is electrically connected to the source-drain layer 110 through a third via H3 penetrating the first passivation layer 06 and a fourth via H4 penetrating the first resin layer 09 in sequence; the bias electrode 16 is electrically connected to the top electrode 14 through a fifth via H5 penetrating the second passivation layer 15 and the second resin layer 13 in sequence.

[0122] In a specific implementation, the materials of the first passivation layer 06, the second passivation layer 15, and the third passivation layer 17 can be inorganic insulating materials such as silicon nitride and silicon oxide. In addition, the first passivation layer 06 is provided with a third via H3, the first resin layer 09 is provided with a fourth via H4, and the second passivation layer 15 and the second resin layer 13 are provided with a fifth via H5. In actual application, the bottom electrode 11 is electrically connected to the source and drain layer 110 via the third via H3 penetrating the first passivation layer 06 and the fourth via H4 penetrating the first resin layer 09. The bias electrode 16 is electrically connected to the top electrode 14 via the fifth via H5 penetrating the second passivation layer 15 and the second resin layer 13. This ensures that the thin film transistor 200 can effectively control the photosensitive portion 400.

[0123] It should be noted that, in combination with Figure 14, at the position where the bottom electrode 11 is electrically connected to the source and drain layer 110, since the first passivation layer 06 has a third via H3 and the first resin layer 09 has a fourth via H4, in the actual preparation process, the surface of the transparent electrode layer 18 at the corresponding position facing away from the substrate 100 may be uneven. In the subsequent process of preparing the scintillator by evaporating cesium iodide (CsI) crystal material, since the film thickness of the scintillator is one hundred times the film thickness of the transparent electrode layer 18, it will not affect the detection characteristics of the detection panel, nor will it affect the flatness of the CsI package.

[0124] In the embodiment of the present disclosure, still in combination with Figures 7 to 19, the orthographic projection of the fifth via H5 on the substrate 100 completely falls within the area of ​​the orthographic projection of the thin film transistor 200 on the substrate 100; the orthographic projection of the third via H3 on the substrate 100 completely falls within the area of ​​the orthographic projection of the fourth via H4 on the substrate 100.

[0125] In one exemplary embodiment, the orthographic projections of the bottom electrode 11 and the PIN layer 12 on the substrate 100 cover the orthographic projection of the thin-film transistor 200 on the substrate 100. On the one hand, the bottom electrode 11 and the PIN layer 12 provide a certain degree of light shielding, effectively blocking radiation from reaching the active layer 03 of the thin-film transistor 200 and preventing the thin-film transistor 200 from failing. On the other hand, the orthographic projection of the fifth via H5, which electrically connects the bias electrode 16 to the top electrode 14, on the substrate 100 completely falls within the orthographic projection of the thin-film transistor 200 on the substrate 100. Therefore, in practical applications, the bias electrode 16 can simply cover the top of the thin-film transistor 200 and does not need to extend into the interior of the pixel. This reduces the area required for the bias electrode 16 and increases the pixel fill rate.

[0126] It should be noted that in the exemplary embodiment shown in FIG9 , at the third and fourth via holes H3 and H4, the source layer 05 in the source-drain layer 110 needs to wrap around the third and fourth via holes H3 and H4. In actual fabrication, the wrapping ratio between the third connecting portion 053 in the source layer 05 and the apertures of the third and fourth via holes H3 and H4, respectively, can be set to P:R:S=13:27:34, where P represents the aperture of the third via hole H3 penetrating the first passivation layer 06, R represents the aperture of the fourth via hole H4 penetrating the first resin layer 09, and S represents the size of the third connecting portion 053 in the source layer 05. This ensures sufficient spacing between the source layer 05 and the second electrode layer 08, ensuring the subsequent formation of the required storage capacitor.

[0127] In the embodiment of the present disclosure, the second passivation layer 15 and the third passivation layer 17 may be disposed in the following manner, but are not limited thereto. In the exemplary embodiments shown in Figures 1 to 14 , the second passivation layer 15 and the third passivation layer 17 are disposed as a uniform layer within the same pixel.

[0128] In one exemplary embodiment, as shown in Figures 15 and 16, where Figure 15 is a schematic top view of the detection panel and Figure 16 is a schematic cross-sectional view along the direction indicated by line QQ in Figure 15, specifically, the second passivation layer 15 is provided as a whole layer, the orthographic projection of the third passivation layer 17 on the substrate 100 overlaps with the orthographic projection of the bias electrode 16 on the substrate 100, and the orthographic projection of the third passivation layer 17 on the substrate 100 completely falls within the region of the orthographic projection of the second passivation layer 15 on the substrate 100.

[0129] Still referring to the exemplary embodiment shown in FIG15 , within the same pixel, the orthographic projection of the third passivation layer 17 on the substrate 100 and the orthographic projection of the bias electrode 16 on the substrate 100 are arranged to overlap with each other, where “overlap” refers to partial or complete overlap. Moreover, the second passivation layer 15 is arranged as a whole layer, and the orthographic projection of the third passivation layer 17 on the substrate 100 completely falls within the area of ​​the orthographic projection of the second passivation layer 15 on the substrate 100. In this way, compared with the exemplary embodiment shown in FIG13 , the distance between a portion of the transparent electrode layer 18 and the bias electrode 16 is shortened, thereby increasing the storage capacitance between the two. In this way, the dynamic range of the detection panel is improved to a certain extent.

[0130] In one exemplary embodiment, as shown in Figures 17 and 18, where Figure 17 is a schematic top view of the detection panel, and Figure 18 is a schematic cross-sectional view along the direction indicated by RR in Figure 17, specifically, the third passivation layer 17 is provided as a whole layer, the orthographic projection of the second passivation layer 15 on the substrate 100 and the orthographic projection of the bias electrode 16 on the substrate 100 are arranged to overlap with each other, and the orthographic projection of the second passivation layer 15 on the substrate 100 completely falls within the area of ​​the orthographic projection of the third passivation layer 17 on the substrate 100.

[0131] Still referring to the exemplary embodiment shown in FIG17 , within the same pixel, the orthographic projection of the second passivation layer 15 on the substrate 100 and the orthographic projection of the bias electrode 16 on the substrate 100 are arranged to overlap with each other, where “overlap” refers to partial or complete overlap. Moreover, the third passivation layer 17 is arranged as a whole layer, and the orthographic projection of the second passivation layer 15 on the substrate 100 completely falls within the area of ​​the orthographic projection of the third passivation layer 17 on the substrate 100. In this way, compared with the exemplary embodiment shown in FIG13 , the distance between a portion of the transparent electrode layer 18 and the bias electrode 16 is shortened, thereby increasing the storage capacitance between the two. In this way, the dynamic range of the detection panel is improved to a certain extent.

[0132] In one exemplary embodiment, within the same pixel, the orthographic projection of the second passivation layer 15 on the substrate 100 overlaps with the orthographic projection of the bias electrode 16 on the substrate 100, the orthographic projection of the third passivation layer 17 on the substrate 100 overlaps with the orthographic projection of the bias electrode 16 on the substrate 100, and the orthographic projection of the second passivation layer 15 on the substrate 100 overlaps with the orthographic projection of the third passivation layer 17 on the substrate 100. In this way, compared to the exemplary embodiments shown in Figures 15 and 17, the distance between a portion of the transparent electrode layer 18 and the bias electrode 16 is shortened, thereby increasing the storage capacitance between the two. This improves the dynamic range of the detection panel to a certain extent.

[0133] In the embodiment of the present disclosure, the first electrode layer 07 and the second electrode layer 08 may be arranged in the following manner, which is not limited here.

[0134] In one of the exemplary embodiments, still in combination with Figure 7, the first electrode layer 07 includes a first main body portion 071 and a first extension portion 072, which extends outward and is symmetrically arranged on both sides of the first main body portion 071 in a direction parallel to the gate line G in the detection panel. The first extension portion 072 is used to be electrically connected to the first bias line B1 in the detection panel, and the bias electrode 16 is used to be electrically connected to the second bias line B2 in the detection panel.

[0135] In a specific implementation, both the first bias line B1 and the second bias line B2 are electrically connected to the bias bus 500. The first electrode layer 07 is provided on the same layer as the gate layer 01, and is arranged parallel to the gate lines G within the detection panel. The first extensions 072 of the first electrode layer 07 are symmetrically arranged on opposite sides of the first body portion 071, extending outward. This effectively prevents overlap capacitance between the first electrode layer 07 and the gate layer 01, while ensuring efficient transmission of the bias signal.

[0136] In one exemplary embodiment, as shown in Figures 19 and 20, Figure 19 is a schematic top view of a detection panel, and Figure 20 is an enlarged schematic diagram of a partial region of the first extension portion 072 and the bias electrode 16 in Figure 19. Specifically, the orthographic projections of the first body portion 071 and the bias electrode 16 on the substrate 100 do not overlap, and at the overlapping position of the first extension portion 072 and the bias electrode 16, the maximum dimension of the corresponding portion of the first extension portion 072 is smaller than the maximum dimension at the non-overlapping position; and at the overlapping position of the bias electrode 16 and the first extension portion 072, the maximum dimension of the corresponding portion of the bias electrode 16 is smaller than the maximum dimension at the non-overlapping position.

[0137] Still referring to the exemplary embodiment shown in FIG. 20 , D1 represents the maximum dimension of the corresponding portion of the first extension portion 072 at the overlapping position between the first extension portion 072 and the bias electrode 16, and D2 represents the maximum dimension of the corresponding portion of the first extension portion 072 at the non-overlapping position between the first extension portion 072 and the bias electrode 16, where D1 is smaller than D2. T1 represents the maximum dimension of the corresponding portion of the bias electrode 16, and T2 represents the maximum dimension of the corresponding portion of the bias electrode 16 at the non-overlapping position between the bias electrode 16 and the first extension portion 072, where T1 is smaller than T2. ​​Furthermore, the orthographic projections of the first body portion 071 and the bias electrode 16 on the substrate 100 do not overlap. This effectively reduces the overlapping area between the first electrode layer 07 and the bias electrode 16, thereby reducing the overlap capacitance between the two and lowering pixel noise.

[0138] In one of the exemplary embodiments, as shown in Figures 9, 12, 15 and 17, the second electrode layer 08 includes a second main body portion 081 and a second extension portion 082, which extends outward and is symmetrically arranged relative to the second extension portions 082 arranged on both sides of the second main body portion 081 in a direction parallel to the data line D in the detection panel. The second extension portion 082 is used to be electrically connected to the first bias line B1 in the detection panel, and the bias electrode 16 is used to be electrically connected to the second bias line B2 in the detection panel.

[0139] In a specific implementation, both the first bias line B1 and the second bias line B2 are electrically connected to the bias bus 500. The second electrode layer 08 is provided on the same layer as the source-drain layer 110. The second extensions 082 of the second electrode layer 08 extend outward and symmetrically on opposite sides of the second main portion 081, parallel to the data line D within the detection panel. This effectively prevents overlap capacitance between the second electrode layer 08 and the source-drain layer 110, reducing the load on the data line D while also lowering pixel noise.

[0140] In the embodiment of the present disclosure, the detection panel further includes a gate insulating layer 02 located between the active layer 03 and the gate layer 01 . The gate insulating layer 02 includes a silicon nitride layer 600 and a silicon oxide layer 700 sequentially disposed away from the substrate 100 .

[0141] In one exemplary embodiment, as shown in Figures 21 and 22, Figure 21 is a schematic diagram of a top view of the detection panel, and Figure 22 is a schematic diagram of a cross-sectional structure along the direction indicated by LL in Figure 21. Specifically, the gate insulating layer 02 located between the active layer 03 and the gate layer 01 includes a silicon nitride layer 600 and a silicon oxide layer 700, which are sequentially arranged away from the substrate 100. In this way, even when the thin film transistor 200 is an oxide thin film transistor 200, hydrogen in the insulating layer can be effectively prevented from diffusing into the oxide semiconductor layer, thereby preventing the oxide semiconductor layer from becoming a conductor, thereby ensuring the high mobility and device stability of the oxide thin film transistor 200.

[0142] It should be noted that, in addition to the above-mentioned related film layer structures, the embodiments of the present disclosure also include other film layer structures. Exemplarily, the detection panel also includes a hydrogen barrier layer 10 located between the bottom electrode 11 and the first passivation layer 06, a fourth passivation layer 800 located between the first resin layer 09 and the source and drain layer 110, and a buffer layer 900 located between the second resin layer 13 and the top electrode 14. In the specific preparation process, the buffer layer 900 can play the role of absorption and buffering, and the hydrogen barrier layer 10 can play the role of blocking hydrogen atoms and hydrogen molecules to protect the internal components of the detection panel. Of course, other film layer structures can also be set according to actual application needs, which are not limited here.

[0143] In the disclosed embodiment, the materials of the first electrode layer 07, the second electrode layer 08, the bottom electrode 11, and the bias electrode 16 can be composite metal materials. For example, the material of the first electrode layer 07 can be Al / Mo, and the material of the second electrode layer 08, the bottom electrode 11, and the bias electrode 16 can be Mo / Al / Mo. Of course, the materials of the relevant electrodes can also be set according to actual application needs, and this is not limited here.

[0144] It should be noted that in the aforementioned exemplary embodiments, the orthographic projection of the first electrode layer 07 on the substrate 100 completely falls within the orthographic projection of the bottom electrode 11 on the substrate 100, and the orthographic projection of the second electrode layer 08 on the substrate 100 completely falls within the orthographic projection of the bottom electrode 11 on the substrate 100. Still referring to the exemplary embodiment shown in FIG21 , both the first electrode layer 07 and the second electrode layer 08 are enclosed by the bottom electrode 11. As shown in FIG23 and FIG24 , FIG23 is a schematic cross-sectional view taken along the direction indicated by line SS in FIG21 , and FIG24 is a schematic cross-sectional view taken along the direction indicated by line TT in FIG21 . Specifically, both the first electrode layer 07 and the second electrode layer 08 are covered by the bottom electrode 11, and the areas of the first electrode layer 07 and the second electrode layer 08 are smaller than those of the bottom electrode 11. Still referring to FIG23 , a certain distance is provided between the edge of the first electrode layer 07 and the gate lines within the detection panel, reducing the coupling capacitance between the first electrode layer 07 and the gate lines. Still referring to FIG24 , there is a certain distance between the edge of the second electrode layer 08 and the data line D in the detection panel, thereby reducing the coupling capacitance between the second electrode layer 08 and the data line D. In this way, while improving the dynamic range, the impact of the first electrode layer 07 and the second electrode layer 08 on the detection performance of the detection panel is reduced.

[0145] In the disclosed embodiments, unless otherwise specified, the bottom electrode 11 covering the first electrode layer 07 refers to the bottom electrode 11 covering the portion of the first electrode layer 07 excluding the first extension 072 (i.e., the first main portion 071); and the bottom electrode 11 covering the second electrode layer 08 refers to the bottom electrode 11 covering the portion of the second electrode layer 08 excluding the second extension 082 (i.e., the second main portion 081). Of course, the bottom electrode 11 may also cover a portion of the first extension 072 and a portion of the second extension 082, without limitation herein.

[0146] In one exemplary embodiment, within the area corresponding to the overlapping area of ​​the first electrode layer 07 and the second electrode layer 08, along the direction parallel to the gate line G in the detection panel, the maximum dimension W1 of the first electrode layer 07 is smaller than the maximum dimension W2 of the second electrode layer 08; and / or, along the direction parallel to the data line D in the detection panel, the maximum dimension L1 of the first electrode layer 07 is smaller than the maximum dimension L2 of the second electrode layer 08.

[0147] In combination with the exemplary embodiment shown in Figure 12, as shown in Figures 25(a) to 25(c), Figure 25(a) is a schematic diagram of a top-down structure of the first electrode layer 07 in Figure 12, and Figure 25(b) is a schematic diagram of a top-down structure of the second electrode layer 08 in Figure 12; Figure 25(c) is a schematic diagram of a top-down structure of the first electrode layer 07 and the second electrode layer 08 in Figure 12; specifically, Figure 25(a) illustrates the orthographic projection of the first electrode layer 07 on the substrate 100, Figure 25(b) illustrates the orthographic projection of the second electrode layer 08 on the substrate 100, and Figure 25(c) illustrates the overlap of the orthographic projections of the first electrode layer 07 and the second electrode layer 08 on the substrate 100. In this exemplary embodiment, within the region corresponding to the overlap of the first electrode layer 07 and the second electrode layer 08, along a direction parallel to the gate lines G within the detection panel, the maximum dimension W1 of the first electrode layer 07 is smaller than the maximum dimension W2 of the second electrode layer 08, and along a direction parallel to the data lines D within the detection panel, the maximum dimension L1 of the first electrode layer 07 is smaller than the maximum dimension L2 of the second electrode layer 08. This exemplary embodiment does not illustrate the bottom electrode 11. In actual fabrication, along a direction parallel to the gate lines G within the detection panel, the dimensions of the bottom electrode 11 are larger than the dimensions of the first electrode layer 07 and the second electrode layer 08. Accordingly, the maximum dimension of the second electrode layer 08 is between the maximum dimensions of the first electrode layer 07 and the maximum dimensions of the bottom electrode 11. Along a direction parallel to the data lines D within the detection panel, the dimensions of the bottom electrode 11 are larger than the dimensions of the first electrode layer 07 and the second electrode layer 08. Accordingly, the maximum dimension of the second electrode layer 08 is between the maximum dimensions of the first electrode layer 07 and the maximum dimensions of the bottom electrode 11.

[0148] Still in combination with the exemplary embodiment shown in Figure 23, the area of ​​the first electrode layer 07 is further reduced so that the maximum dimension L1 of the first electrode layer 07 is smaller than the maximum dimension L2 of the second electrode layer 08 along the direction parallel to the data line D in the detection panel. This can increase the distance between the first electrode layer 07 and the gate line, thereby reducing the coupling capacitance between the first electrode layer 07 and the gate line. At the same time, since the size of the second electrode layer 08 is larger, the size of the storage capacitance formed between the second electrode layer 08 and the bottom electrode 11 is guaranteed.

[0149] In one exemplary embodiment, within the area corresponding to the overlapping area of ​​the first electrode layer 07 and the second electrode layer 08, along the direction parallel to the gate line G in the detection panel, the maximum dimension W2 of the second electrode layer 08 is smaller than the maximum dimension W1 of the first electrode layer 07; and / or, along the direction parallel to the data line D in the detection panel, the maximum dimension L2 of the second electrode layer 08 is smaller than the maximum dimension L1 of the first electrode layer 07.

[0150] As shown in FIG26 , along a direction parallel to the gate lines G within the detection panel, the maximum dimension W2 of the second electrode layer 08 is smaller than the maximum dimension W1 of the first electrode layer 07; and along a direction parallel to the data lines D within the detection panel, the maximum dimension L2 of the second electrode layer 08 is smaller than the maximum dimension L1 of the first electrode layer 07. In this exemplary embodiment, the bottom electrode 11 is not illustrated. In actual fabrication, along a direction parallel to the gate lines G within the detection panel, the dimensions of the bottom electrode 11 are larger than the dimensions of the first electrode layer 07 and the second electrode layer 08. Accordingly, the maximum dimension of the first electrode layer 07 is between the maximum dimensions of the second electrode layer 08 and the maximum dimensions of the bottom electrode 11. Along a direction parallel to the data lines D within the detection panel, the dimensions of the bottom electrode 11 are larger than the dimensions of the first electrode layer 07 and the second electrode layer 08. Accordingly, the maximum dimension of the first electrode layer 07 is between the maximum dimensions of the second electrode layer 08 and the maximum dimensions of the bottom electrode 11.

[0151] Still in combination with the exemplary embodiment shown in Figure 24, the area of ​​the second electrode layer 08 is further reduced so that the maximum dimension W2 of the second electrode layer 08 is smaller than the maximum dimension W1 of the first electrode layer 07 along the direction parallel to the data line D in the detection panel. This can increase the distance between the second electrode layer 08 and the data line D, thereby reducing the coupling capacitance between the second electrode layer 08 and the data line D. At the same time, since the signal on the data line D has a greater impact on noise than the signal on the gate line, the total noise of the pixel can be effectively reduced by reducing the area of ​​the second electrode layer 08.

[0152] In order to more clearly illustrate the specific structure of the detection panel provided by the embodiment of the present disclosure, the specific preparation process of the detection panel shown in Figure 12 is explained in detail below in combination with the process flow chart shown in Figures 27(a) to 27(m).

[0153] FIG27( a ): Preparation of the gate layer 01 and the first electrode layer 07 of the thin film transistor 200 ;

[0154] Figure 27(b): Preparation of active layer 03;

[0155] FIG27( c ): A via hole is opened through the gate insulating layer 02 ;

[0156] FIG27( d ): A source-drain electrode layer 110 is formed on the side of the active layer 03 facing away from the substrate 100 , and a second electrode layer 08 is formed on top of the first electrode layer 07 ;

[0157] FIG27( e ): a first resin layer 09 is formed above the thin film transistor 200 and the second electrode layer 08 , and a fourth via hole H4 is formed through the first resin layer 09 ;

[0158] FIG27( f ): A first passivation layer 06 is formed on the first resin layer 09 , and a third via hole H3 is formed through the first passivation layer 06 ;

[0159] FIG27( g ): Preparation of hydrogen barrier layer 10;

[0160] FIG27( h ): A bottom electrode 11 is formed on the hydrogen barrier layer 10 ;

[0161] FIG27( i ): A PIN layer 12 , a top electrode 14 , and a buffer layer 900 are sequentially formed above the bottom electrode 11 ;

[0162] FIG27( j ): Preparing a second resin layer 13 and preparing a via hole penetrating the second resin layer 13 ;

[0163] FIG27( k ): Preparing a second passivation layer 15 and a via hole penetrating the second passivation layer 15 ;

[0164] Figure 27(l): Preparation of bias electrode 16;

[0165] FIG27( m ): Preparation of transparent electrode layer 18 .

[0166] Based on the same disclosed concept, an embodiment of the present disclosure further provides a flat panel detector, which includes a detection panel as described above. For example, the flat panel detector may be an X-ray detector.

[0167] In the embodiment of the present disclosure, the detection panel may include a pixel array composed of a plurality of pixels. The structure of each pixel in the pixel array may refer to the description of the aforementioned related parts and will not be repeated here.

[0168] Taking the exemplary embodiment shown in Figure 4 as an example, the thin film transistor 200 of each pixel in the detection panel is electrically connected to the data line D, the second electrode layer 08 is electrically connected to the bias bus 500 through the first bias line B1, and the top electrode 14 is electrically connected to the bias bus 500 through the bias electrode 16 and the second bias line B2.

[0169] The principle of solving the problem by the flat panel detector is similar to that of the aforementioned detection panel. Therefore, the implementation of the flat panel detector can refer to the implementation of the aforementioned detection panel, and the repeated parts will not be repeated.

[0170] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0171] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A detection panel, wherein: include: substrate; A thin film transistor is located on the substrate; the thin film transistor includes a gate layer, an active layer and a source and drain layer; a photosensitive portion located on a side of the thin film transistor facing away from the substrate; the photosensitive portion comprises a bottom electrode, a PIN layer, and a top electrode sequentially arranged away from the substrate; the bottom electrode is electrically connected to the thin film transistor via the source and drain layer; At least one electrode layer is located between the bottom electrode and the substrate, and each electrode layer in the at least one electrode layer is arranged on the same layer as one of the conductive layers in the thin film transistor, and the orthographic projection of each electrode layer on the substrate completely falls within the area of ​​the orthographic projection of the bottom electrode on the substrate; at least one storage capacitor including a first storage capacitor is formed between the at least one electrode layer and the bottom electrode, and a second storage capacitor is formed between the bottom electrode and the top electrode.

2. The detection panel according to claim 1, wherein The at least one electrode layer is a first electrode layer provided at the same layer as the gate layer, and the at least one storage capacitor is the first storage capacitor formed between the first electrode layer and the bottom electrode.

3. The detection panel according to claim 1, wherein: The at least one electrode layer is a second electrode layer provided in the same layer as the source and drain electrode layer, and the at least one storage capacitor is the first storage capacitor formed between the second electrode layer and the bottom electrode.

4. The detection panel according to claim 1, wherein: The at least one electrode layer includes a first electrode layer arranged in the same layer as the gate layer, and a second electrode layer arranged in the same layer as the source and drain layer; the at least one storage capacitor also includes a third storage capacitor formed between the second electrode layer and the bottom electrode, and the first storage capacitor is formed by the first electrode layer and the second electrode layer.

5. The detection panel according to claim 4, wherein: The source-drain layer includes a source layer located on the side of the active layer facing away from the substrate, the source layer is arranged in a stepped manner, and the source layer includes a first connecting portion, a second connecting portion, and a third connecting portion that are connected in sequence; the first connecting portion and the third connecting portion are both arranged in a direction parallel to the plane where the substrate is located; the distance between the first connecting portion and the substrate is greater than the distance between the third connecting portion and the substrate, and the orthographic projection of the first connecting portion on the substrate and the orthographic projection of the third connecting portion on the substrate do not overlap with each other.

6. The detection panel according to claim 5, wherein: An overlapping portion is provided at one end of the third connecting portion away from the second connecting portion. The overlapping portion is electrically connected to the bottom electrode and the first electrode layer respectively, and a groove structure is provided on one side of the overlapping portion away from the first electrode layer.

7. The detection panel according to any one of claims 4 to 6, wherein: It also includes a bias electrode located on the side of the top electrode facing away from the substrate, and a bias bus arranged around the display area of ​​the detection panel, wherein the bias bus is electrically connected to a first conductive layer arranged on the same layer as the bottom electrode; the first conductive layer is electrically connected to the second electrode layer through a first via hole penetrating the insulating layer between the bottom electrode and the source and drain layer, and is electrically connected to the bias electrode through a second via hole penetrating the insulating layer between the bottom electrode and the bias electrode.

8. The detection panel according to claim 7, wherein: The bias bus includes a first type of transfer structure, a second type of transfer structure and a third type of transfer structure, and the first type of transfer structure, the second type of transfer structure and the third type of transfer structure are respectively electrically connected through a second conductive layer arranged on the same layer as the bias electrode.

9. The detection panel according to claim 8, wherein: It also includes an internal short-circuit ring arranged around the display area, wherein the first-type switching structure and the second-type switching structure are both located on a side of the internal short-circuit ring away from the display area; The third type of transfer structure is located between the internal short-circuit ring and the display area; the first type of transfer structure is symmetrically distributed with the display area as the center along the direction parallel to the data line in the detection panel; the second type of transfer structure is respectively located at the diagonal positions of the display area and is arranged diagonally symmetrically; the third type of transfer structure is symmetrically distributed with the display area as the center along the direction parallel to the gate line in the detection panel.

10. The detection panel according to claim 9, wherein: The first type of switching structure includes a plurality of first switching units; A plurality of via hole combinations are provided on each first adapter unit along a direction parallel to the data lines in the detection panel. Each via hole combination includes at least one pair of via holes, and each pair of via holes includes the first via hole and the second via hole.

11. The detection panel according to claim 10, wherein: A window structure is provided between two adjacent groups of via hole combinations, and an orthographic projection area of ​​the window structure on the substrate is larger than an orthographic projection area of ​​each via hole in each group of via hole combinations on the substrate.

12. The detection panel according to claim 10 or 11, wherein: It also includes multiple read signal lines located in the peripheral area of ​​the detection panel; a read signal line is set between two adjacent first transfer units located on the same side of the display area in the first type transfer structure; each read signal line is electrically connected to the data line in the display area.

13. The detection panel according to claim 9, wherein: The second type of transfer structure includes a plurality of second transfer units; each second transfer unit is provided with a plurality of via combinations along a direction parallel to the data line in the detection panel, and each via combination includes at least two second vias.

14. The detection panel according to claim 9, wherein: The third type switching structure includes a plurality of third switching units; a gate line is provided between two adjacent third switching units located on the same side of the display area in the third type switching structure; each gate line is electrically connected to the gate layer of the thin film transistor.

15. The detection panel according to any one of claims 1-6, 8-11, 13, and 14, wherein: It also includes a bias electrode located on the side of the top electrode facing away from the substrate, and a transparent electrode layer located on the side of the bias electrode facing away from the substrate, and the orthographic projection of the bottom electrode on the substrate completely falls within the area of ​​the orthographic projection of the transparent electrode layer on the substrate; the at least one storage capacitor also includes a fourth storage capacitor formed by the bias electrode and the transparent electrode layer.

16. The detection panel according to claim 15, wherein: The device further includes a first passivation layer located between the bottom electrode and the source / drain electrode layer, a first resin layer located between the first passivation layer and the source / drain electrode layer, a second passivation layer located on a side of the bias electrode close to the substrate, a second resin layer located between the second passivation layer and the PIN layer, and a third passivation layer located between the bias electrode and the transparent electrode layer; the bottom electrode is electrically connected to the source / drain electrode layer via a third via hole penetrating the first passivation layer and a fourth via hole penetrating the first resin layer in sequence; The bias electrode is electrically connected to the top electrode through a fifth via hole that sequentially penetrates the second passivation layer and the second resin layer.

17. The detection panel according to claim 16, wherein: The orthographic projection of the fifth via on the substrate completely falls within the area of ​​the orthographic projection of the thin film transistor on the substrate; the orthographic projection of the third via on the substrate completely falls within the area of ​​the orthographic projection of the fourth via on the substrate.

18. The detection panel according to claim 16, wherein: The second passivation layer is arranged as a whole layer, the orthographic projection of the third passivation layer on the substrate and the orthographic projection of the bias electrode on the substrate are arranged to overlap with each other, and the orthographic projection of the third passivation layer on the substrate completely falls within the area of ​​the orthographic projection of the second passivation layer on the substrate.

19. The detection panel according to claim 16, wherein: The third passivation layer is arranged as a whole layer, the orthographic projection of the second passivation layer on the substrate and the orthographic projection of the bias electrode on the substrate are arranged to overlap with each other, and the orthographic projection of the second passivation layer on the substrate completely falls within the area of ​​the orthographic projection of the third passivation layer on the substrate.

20. The detection panel according to claim 2, wherein: The first electrode layer includes a first main body and a first extension portion, which extends outward and is symmetrically arranged relative to the first extension portions on both sides of the first main body in a direction parallel to the gate lines in the detection panel. The first extension portion is used to be electrically connected to the first bias line in the detection panel, and the bias electrode is used to be electrically connected to the second bias line in the detection panel.

21. The detection panel according to claim 20, wherein: The orthographic projections of the first main portion and the bias electrode on the substrate do not overlap with each other, and at an overlapping position of the first extension portion and the bias electrode, a maximum dimension of a corresponding portion of the first extension portion is smaller than a maximum dimension at a non-overlapping position; At an overlapping position between the bias electrode and the first extension portion, a maximum dimension of a corresponding portion of the bias electrode is smaller than a maximum dimension at a non-overlapping position.

22. The detection panel according to claim 3 or 4, wherein: The second electrode layer includes a second main body and a second extension portion, which extends outward and symmetrically relative to the second extension portions on both sides of the second main body portion in a direction parallel to the data line in the detection panel. The second extension portion is used to be electrically connected to the first bias line in the detection panel, and the bias electrode is used to be electrically connected to the second bias line in the detection panel.

23. The detection panel according to any one of claims 1-6, 8-11, 13, 14, 16-21, wherein: It also includes a gate insulating layer located between the active layer and the gate layer, and the gate insulating layer includes a silicon nitride layer and a silicon oxide layer sequentially arranged away from the substrate.

24. A flat panel detector, wherein: include: A detection panel as claimed in any one of claims 1 to 23.

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