Charging and discharging capacitance detection circuit based on dynamic switching of GPIO port and temperature drift compensation method

Abstract

This invention discloses a charging / discharging capacitor detection circuit and temperature drift compensation method based on dynamic switching of GPIO ports, belonging to the field of electronic measurement technology. The circuit includes: a capacitor under test branch, comprising a capacitor under test, resistor R1, and resistor R2 connected in series, with a GPIO interface PA connected between the capacitor under test and resistor R1, and a GPIO interface PB connected between resistor R1 and resistor R2; a reference capacitor branch, comprising a reference capacitor, resistor R4, and resistor R5 connected in series, with a GPIO interface PD connected between the reference capacitor and resistor R4, and a GPIO interface PE connected between resistor R4 and resistor R5; a charge accumulation circuit, comprising analog switches S1 and S2, capacitors C1 and C2, and resistors R3 and R6 connected in parallel with capacitors C1 and C2 respectively; and an operational amplifier for receiving signals from capacitors C1 and C2 and suppressing common-mode signals.

Description

Technical Field

[0001] This invention relates to the field of electronic measurement technology, specifically to a charging and discharging capacitor detection circuit and a temperature drift compensation method based on dynamic switching of GPIO ports. Background Technology

[0002] The charge-discharge capacitor detection circuit converts the capacitance value into a precisely measurable time or voltage parameter by periodically controlling the charging and discharging sequence of the capacitor under test (Cx). Its typical structure includes: the capacitor under test (Cx) and a reference capacitor (Cref), a multi-channel analog switch array, a charging / discharging current-limiting resistor, and a core controller (DP). During the detection process, DP precisely controls the state switching sequence of the GPIO ports to switch the charging, discharging, and charge transfer states of the capacitor under test, thereby obtaining the charging / discharging time and voltage parameters related to the capacitance value. This technology, with its simple structure and low cost, is widely used in component capacitance testing in electronic manufacturing, capacitive sensor signal acquisition (such as proximity sensing and liquid level monitoring), and high-precision measurement in industrial automation control systems.

[0003] However, existing technologies still have the following main problems in application:

[0004] The parasitic junction capacitance (Cp) of analog switches can cause time-varying interference and exhibit temperature-sensitive characteristics. The parasitic junction capacitance (Cp) formed by the internal PN junction of analog switches (such as MOSFETs or transmission gate structures) is an inherent defect.

[0005] During steady-state operation, the parasitic junction capacitance (Cp) forms a parallel interference path with the capacitor under test (Cx), causing a shift in the equivalent measured capacitance value. More seriously, the parasitic junction capacitance (Cp) itself has a negative temperature coefficient (typically approximately -50ppm / ℃ to -200ppm / ℃). When the ambient temperature changes, its capacitance drift is coupled and superimposed with the actual change in the measured capacitance Cx, producing a difficult-to-distinguish "temperature drift noise."

[0006] Traditional static compensation methods cannot track such dynamic drifts, which ultimately leads to a sharp deterioration in detection accuracy over a wide temperature range (-40℃~85℃), severely restricting the reliability of the system in harsh environments such as automotive electronics and outdoor equipment.

[0007] Conventional solutions, such as discrete temperature compensation circuits and multiple calibration cycles, suffer from drawbacks such as limited compensation range, poor real-time performance, and high system complexity. Therefore, there is an urgent need for an innovative solution that achieves synchronous suppression of temperature drift at the system architecture level. Summary of the Invention

[0008] To address the shortcomings of existing technologies, this invention proposes a charging / discharging capacitor detection circuit and a temperature drift compensation method based on dynamic switching of GPIO ports.

[0009] The objective of this invention can be achieved through the following technical solutions:

[0010] In a first aspect, the present invention relates to a charge / discharge capacitor detection circuit, comprising:

[0011] The test capacitor branch includes a test capacitor, a resistor R1 and a resistor R2 connected in series, and a GPIO interface PA is connected between the test capacitor and the resistor R1, and a GPIO interface PB is connected between the resistor R1 and the resistor R2.

[0012] The reference capacitor branch includes a reference capacitor, a resistor R4, and a resistor R5 connected in series. A GPIO interface PD is connected between the reference capacitor and the resistor R4, and a GPIO interface PE is connected between the resistor R4 and the resistor R5.

[0013] A charge accumulation circuit includes analog switch S1, analog switch S2, capacitor C1, capacitor C2, and resistors R3 and R6 connected in parallel with capacitors C1 and C2, respectively. One end of analog switch S1 and analog switch S2 is connected to the ends of resistors R2 and R5, respectively, and the other end of analog switch S1 and analog switch S2 can be selectively connected to capacitors C1 and C2.

[0014] And an operational amplifier, used to receive the signals from capacitors C1 and C2, and capable of suppressing common-mode signals.

[0015] Optionally, the charge accumulation circuit further includes a GPIO interface PC for controlling the switching state of analog switch S1 and analog switch S2; during the discharge phase, the GPIO interface PC controls analog switch S1 and analog switch S2 to switch, so that the capacitor under test Cx and the reference capacitor Cref alternately charge capacitor C1 and capacitor C2.

[0016] Optionally, a delay time T is provided between the step of controlling the output of the high-impedance state of the GPIO interfaces PA and PD and the step of controlling the output of the high-impedance state of the GPIO interfaces PB and PE.

[0017] Optionally, the capacitance values ​​of capacitor C1 and capacitor C2 are more than 1000 times the capacitance values ​​of the capacitor under test and the reference capacitor, and the dynamic switching frequency of the states of GPIO interface PA, GPIO interface PB, GPIO interface PD and / or GPIO interface PE is more than 1000 times the switching frequency of analog switch S1 and analog switch S2.

[0018] Optionally, the capacitance of capacitor C1 is more than 1000 times the parasitic junction capacitance of analog switch S1, the capacitance of capacitor C2 is more than 1000 times the parasitic junction capacitance of analog switch S2, and the dynamic state switching frequency of GPIO interface PA, GPIO interface PB, GPIO interface PD and / or GPIO interface PE is more than 1000 times the switching frequency of analog switch S1 and analog switch S2.

[0019] Optionally, during the charging phase, the GPIO interfaces PA and PD output high levels to charge the capacitor under test and the reference capacitor, respectively; the GPIO interfaces PB and PE output low levels.

[0020] During the discharge phase, GPIO interfaces PA, PD, PB, and PE switch to a high-impedance state.

[0021] Optionally, the capacitance values ​​of capacitor C1 and / or capacitor C2 are configured to be in the nF range; the other end of the reference capacitor and / or the capacitor under test is a virtual ground.

[0022] Optionally, it also includes a low-pass filter and a data acquisition card, with the output of the operational amplifier connected in sequence to the low-pass filter and the data acquisition card.

[0023] A second aspect of the present invention relates to a charging and discharging electric detection method, comprising the following steps:

[0024] Construct or use the above-described charge / discharge capacitor detection circuit;

[0025] During the charging phase, GPIO interfaces PA and PD output high levels to charge the capacitor under test and the reference capacitor, respectively, while GPIO interfaces PB and PE output low levels. Resistors R2 and R5 discharge the parasitic junction capacitance of the switches, reducing the potential difference between the parasitic junction capacitances of analog switches S1 and S2.

[0026] During the discharge phase, GPIO interfaces PA, PD, PB, and PE switch to a high-impedance state, controlling the precise switching of the charging and discharging paths. The GPIO interface PC controls the switching between analog switches S1 and S2, allowing the capacitor under test and the reference capacitor to alternately charge capacitors C1 and C2.

[0027] A third aspect of the present invention relates to a sensor configured with the above-described charge / discharge capacitor detection circuit.

[0028] The beneficial effects of this invention are:

[0029] Dual-path temperature drift suppression: The charging and discharging paths are dynamically switched via GPIO ports to eliminate temperature drift caused by the parasitic junction capacitances (Cp1, Cp2) of the switch.

[0030] Improved noise robustness: The differential architecture provides excellent common-mode rejection ratio, and delay control blocks transient surge interference during charging and discharging.

[0031] Industrial-grade reliability: Achieves picofarad (pF) level high-precision measurement over a wide temperature range, suitable for high-interference scenarios such as automotive electronics. Attached Figure Description

[0032] The invention will now be further described with reference to the accompanying drawings.

[0033] Figure 1 This is a schematic diagram of the charge / discharge capacitor detection circuit for suppressing temperature drift in this application;

[0034] Figure 2 This is the timing diagram for the signal output of the five GPIO ports in this application. Detailed Implementation

[0035] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0036] like Figure 1 As shown, in some embodiments of the present invention, a parasitic parameter and temperature drift compensation circuit for a charging and discharging capacitor detection circuit is disclosed, including: a capacitor under test Cx, a reference capacitor Cref, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a first GPIO port PA, a second GPIO port PB, a first analog switch S1, a third GPIO port PC, a second analog switch S2, a fourth GPIO port PD, a fifth GPIO port PE, a first capacitor C1, a second capacitor C2, and a differential operational amplifier A1, etc.

[0037] To achieve nanosecond-level precision synchronous control of the states of multiple GPIO ports, a preferred embodiment of the digital processor (DP) described in this invention employs a Field-Programmable Gate Array (FPGA) or a Complex Programmable Logic Device (CPLD). The inherent advantages of the FPGA / CPLD lie in its hardware's parallel processing capabilities and deterministic timing characteristics. Internally, synchronous timing logic is constructed using hardware description languages ​​(such as VHDL or Verilog) to generate multiple, phase-precise clock and control signals that directly drive its I / O pins. Specifically, the state switching control logic of the GPIO ports (including switching between high, low, and high impedance states and controlling the delay time T) is encoded as hardware circuitry, such as a state machine or counter chain. This control logic is synchronously driven by a global clock signal, and all its output state transitions occur at the clock edge, thus achieving nanosecond-level or even picosecond-level precision and extremely low jitter. The high-impedance state (Z) is directly enabled by the tri-state control signals of the I / O blocks within the FPGA / CPLD; this is natively supported in hardware, resulting in extremely fast response and no delay. Compared to software sequential execution schemes, this implementation scheme does not rely on interrupts or DMA, completely eliminating the timing uncertainty caused by software overhead. Thus, it achieves the dynamic switching mechanism required by this invention with the highest accuracy and reliability, providing the most solid timing foundation for parasitic parameter compensation.

[0038] In this embodiment, the capacitor under test Cx serves as a capacitance sensor, with one end virtually grounded. One end of the first resistor R1 is connected to the capacitor under test Cx, and the other end is connected to the second GPIO port PB. One end of the fourth resistor R4 is connected to the reference capacitor Cref, and the other end is connected to the fifth GPIO port PE. One end of the second resistor R2 is connected to the second GPIO port PB, and the other end is directly connected to the input terminal of the first analog switch S1. One end of the fifth resistor R5 is connected to the fifth GPIO port PE, and the other end is connected to the input terminal of the second analog switch S2. The two output terminals S1A and S1B of the first analog switch S1 are connected to the first capacitor C1 and the second capacitor C2, respectively. The two output terminals S2A and S2B of the second analog switch S2 are connected to the second capacitor C2 and the first capacitor C1, respectively. One end of the first capacitor C1 is connected to one end of the third resistor R3 and the non-inverting input terminal of the operational amplifier A1, and the other end is grounded. One end of the second capacitor C2 is connected to one end of the sixth resistor R6 and the inverting input terminal of the operational amplifier A1, and the other end is grounded. The third GPIO port PC controls the switching frequency of the first analog switch S1 and the second analog switch S2.

[0039] During the charging phase, the first GPIO port PA and the fourth GPIO port PD output high levels to charge the capacitor under test Cx and the reference capacitor Cref, respectively. The second GPIO port PB and the fifth GPIO port PE output low levels to prevent the power supply voltage from charging the subsequent circuit (first capacitor C1, second capacitor C2 and analog switch parasitic junction capacitors (Cp1, Cp2)). At the same time, the second resistor R2, the third resistor R3, the fifth resistor R5 and the sixth resistor R6 discharge the charge of the switch parasitic junction capacitors (Cp1, Cp2) to reduce the potential difference between the parasitic junction capacitors of the first analog switch S1 and the second analog switch S2.

[0040] After entering the discharge stage, the first GPIO port PA and the fourth GPIO port PD are first controlled to switch to the high impedance state (Z) and delayed for a time T (T is the preset delay time). Then, the third GPIO port PC is controlled to switch the first analog switch S1 and the second analog switch S2. The capacitor under test Cx and the reference capacitor Cref are alternately charged by the first capacitor C1 and the second capacitor C2 through these two switches.

[0041] The discharge signals of the first capacitor C1 and the second capacitor C2 are respectively input to the non-inverting input and the inverting input of the differential operational amplifier A1. The output of the differential operational amplifier is connected to a low-pass filter and a data acquisition card. At this time, the output of the operational amplifier A1 will generate a corresponding voltage output. The rate of change of the output voltage is linearly related to the capacitance value of the capacitor Cx under test.

[0042] In some examples, the first analog switch S1 and the second analog switch S2 are controlled by a third GPIO port PC.

[0043] In some examples, the capacitance of the first capacitor C1 and the capacitance of the second capacitor C2 are more than 1,000 times the capacitance of the capacitor under test Cx and the reference capacitor Cref, and the dynamic switching frequency of the states of the first GPIO port PA, the second GPIO port PB, the fourth GPIO port PD and / or the fifth GPIO port PE is more than 1,000 times the switching frequency of the analog switch S1 and the analog switch S2.

[0044] In some examples, the capacitance of the first capacitor C1 is more than 1000 times the capacitance of the parasitic junction capacitance (Cp1) of the first analog switch S1, and the capacitance of the second capacitor C2 is more than 1000 times the capacitance of the parasitic junction capacitance (Cp2) of the second analog switch S2. Furthermore, the dynamic switching frequency of the states of the first GPIO port PA, the second GPIO port PB, the fourth GPIO port PD, and / or the fifth GPIO port PE is more than 1000 times the switching frequency of analog switches S1 and S2. In some more specific examples, the capacitance values ​​of the first capacitor C1 and the second capacitor C2 are set to the nF level. During discharge, because their capacitance values ​​are much larger than the parasitic junction capacitances Cp1 and Cp2 (pf level) at the input terminals of the two analog switches, the parasitic junction capacitances (Cp1, Cp2) of the analog switches can be ignored.

[0045] In other embodiments of the present invention, a method for compensating for parasitic parameters and temperature drift in a charge / discharge capacitor detection circuit is disclosed, comprising the following steps:

[0046] Construct the parasitic parameters and temperature drift compensation circuit for the above-mentioned capacitor charging and discharging detection circuit.

[0047] During the charging phase, the first GPIO port PA and the fourth GPIO port PD output high levels to charge the capacitor under test Cx and the reference capacitor Cref, respectively. The second GPIO port PB and the fifth GPIO port PE output low levels to prevent the power supply voltage from charging the subsequent circuit (first capacitor C1, second capacitor C2 and the parasitic junction capacitances of the analog switches (Cp1, Cp2)). At the same time, the second resistor R2 and the fifth resistor R5 discharge the charge of the parasitic junction capacitances of the switches (Cp1, Cp2), reducing the potential difference between the parasitic junction capacitances of the first analog switch S1 and the second analog switch S2, thereby reducing the influence of the parasitic junction capacitances of the analog switches (Cp1, Cp2) on the detection circuit.

[0048] During the discharge phase, the first GPIO interface, the fourth GPIO interface, the second GPIO port PB, and the fifth GPIO interface switch to a high-impedance state to control the precise switching of the charging and discharging path. The third GPIO port controls the switching between the first analog switch S1 and the second analog switch S2, so that the capacitor under test Cx and the reference capacitor Cref alternately charge the first capacitor C1 and the second capacitor C2.

[0049] Optionally, a delay time T is provided between the step of switching the first GPIO port PA and the fourth GPIO interface PD to a high-impedance state and the step of controlling the second GPIO port PB and the fifth GPIO interface PE to a high-impedance state.

[0050] In some examples, the delay time T is not a fixed value. Its core function is to ensure that the transient surge current generated by the disconnection of the first GPIO port PA and the fourth GPIO port PD during the switch to the high impedance state is fully discharged through the ground wire, and that the potential of the relevant nodes reaches a stable state, thus preventing transient interference from coupling to the sensitive signal acquisition circuit in the subsequent stage. The specific value of the delay time T can be adjusted according to the parasitic parameters in the actual circuit, the capacitance values ​​of the capacitor under test Cx and the reference capacitor Cref, the resistance values ​​of the bleeder resistors (such as R1, R4), and the transient response characteristics of the analog switch. The principle for determining it is that it must be greater than the settling time required for the aforementioned transient process (i.e., surge current discharge and circuit stabilization).

[0051] In a preferred embodiment of the present invention, the delay time T can be conveniently configured as an integer number of cycles of the FPGA / CPLD global clock (e.g., 1 or 2 clock cycles). By adjusting the system clock frequency of the FPGA / CPLD, the actual value of T can be flexibly and finely adjusted to adapt to different circuit parameters and environmental conditions.

[0052] More specifically, the parasitic parameter and temperature drift compensation method and circuit for a charging / discharging capacitor detection circuit of the present invention includes a capacitor under test Cx, a reference capacitor Cref, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a first GPIO port PA, a second GPIO port PB, a first analog switch S1, a third GPIO port PC, a second analog switch S2, a fourth GPIO port PD, a fifth GPIO port PE, a first capacitor C1, a second capacitor C2, and a differential operational amplifier A1, etc. The capacitor under test Cx and the reference capacitor Cref are connected to virtual ground at one end, and the other end is connected to the first GPIO port PA and the fourth GPIO port PD, respectively. One end of the first resistor R1 is connected to the capacitor under test Cx, and the other end is connected to the second GPIO port PB. One end of the fourth resistor R4 is connected to the reference capacitor Cref, and the other end is connected to the fifth GPIO port PE. One end of the second resistor R2 is connected to the second GPIO port PB, and the other end is directly connected to the input terminal of the first analog switch S1. One end of the fifth resistor R5 is connected to the fifth GPIO port PE, and the other end is connected to the input terminal of the second analog switch S2. The two output terminals S1A and S1B of the first analog switch S1 are connected to the first capacitor C1 and the second capacitor C2, respectively. The two output terminals S2A and S2B of the second analog switch S2 are connected to the second capacitor C2 and the first capacitor C1, respectively. One end of the first capacitor C1 is connected to one end of the third resistor R3 and the non-inverting input terminal of the operational amplifier A1, and the other end is grounded. One end of the second capacitor C2 is connected to one end of the sixth resistor R6 and the inverting input terminal of the operational amplifier A1, and the other end is grounded. The third GPIO port PC controls the switching frequency of the first analog switch S1 and the second analog switch S2.

[0053] In other embodiments of the present invention, a method for detecting capacitance using the circuit described above is disclosed, which may include the following steps:

[0054] During the charging phase, the first GPIO port PA and the fourth GPIO port PD output high levels to charge the capacitor under test Cx and the reference capacitor Cref, respectively. The second GPIO port PB and the fifth GPIO port PE output low levels to prevent the power supply voltage from charging the subsequent circuit (first capacitor C1, second capacitor C2 and the parasitic junction capacitors of the analog switches (Cp1, Cp2)). At the same time, the second resistor R2 and the fifth resistor R5 discharge the charge of the parasitic junction capacitors of the switches (Cp1, Cp2), reduce the potential difference between the parasitic junction capacitors of the first analog switch S1 and the second analog switch S2, and eliminate the residual charge of the parasitic junction capacitors (Cp1, Cp2).

[0055] During the discharge phase, the first GPIO port PA, the fourth GPIO port PD, the second GPIO port PB, and the fifth GPIO port PE are switched to a high-impedance state, and the fourth GPIO port PD outputs a low level. Then, the first analog switch S1 and the second analog switch S2 are switched by controlling the third GPIO port PC, so that the capacitor under test Cx and the reference capacitor Cref alternately charge the first capacitor C1 and the second capacitor C2 through these two switches.

[0056] During the charging process, the parasitic junction capacitance (Cp1) of the first analog switch S1 is discharged through the second resistor R2 and the third resistor R3 by grounding the second GPIO port PB, and the parasitic junction capacitance (Cp2) of the second analog switch S2 is discharged through the fifth resistor R5 and the sixth resistor R6 by grounding the fifth GPIO port PE, thereby reducing the influence of the parasitic junction capacitance (Cp1, Cp2) of the analog switches on the detection circuit.

[0057] During the discharge process, firstly, the first GPIO port PA and the fourth GPIO port PD are switched to a high-impedance state (Z). After a delay of T, the second GPIO port PB and the fifth GPIO port PE are switched to a high-impedance state (Z). This allows the surge current that may be generated during the charging and discharging of the capacitor under test Cx and the reference capacitor Cref to be discharged through the ground wire, preventing coupling to the first capacitor C1 and the second capacitor C2, avoiding transient current coupling to the signal chain, and ensuring stable operation. Subsequently, the third GPIO port PC is controlled to switch the first analog switch S1 and the second analog switch S2. The capacitor under test Cx and the reference capacitor Cref alternately charge the first capacitor C1 and the second capacitor C2 through these two switches.

[0058] The discharge signals of the first capacitor C1 and the second capacitor C2 are input to the non-inverting input and the inverting input of the differential operational amplifier, respectively. The output of the differential operational amplifier is connected to the data acquisition card to calculate the capacitance value of the capacitor Cx under test.

[0059] The signal output timing diagrams for each GPIO port in the above process are as follows: Figure 2 As shown.

[0060] In summary, by optimizing the control logic and circuit design of the analog switch, this invention effectively suppresses the temperature drift phenomenon of the parasitic junction capacitance (Cp1, Cp2) of the analog switch in the charging and discharging capacitor detection circuit, thereby improving the accuracy and stability of capacitor detection.

[0061] In the description of this specification, references to terms such as "an embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0062] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention.

Claims

1. A method for detecting charging and discharging capacitors, characterized in that, Includes the following steps: Constructing or using a charge / discharge capacitor detection circuit, including: The test capacitor branch includes a test capacitor, a resistor R1 and a resistor R2 connected in series, and a GPIO interface PA is connected between the test capacitor and the resistor R1, and a GPIO interface PB is connected between the resistor R1 and the resistor R2. The reference capacitor branch includes a reference capacitor, a resistor R4, and a resistor R5 connected in series. A GPIO interface PD is connected between the reference capacitor and the resistor R4, and a GPIO interface PE is connected between the resistor R4 and the resistor R5. A charge accumulation circuit includes analog switch S1, analog switch S2, capacitor C1, capacitor C2, and resistors R3 and R6 connected in parallel with capacitors C1 and C2, respectively. One end of analog switch S1 and analog switch S2 is connected to the ends of resistors R2 and R5, respectively, and the other end of analog switch S1 and analog switch S2 can be selectively connected to capacitors C1 and C2. And an operational amplifier, used to receive the signals from capacitors C1 and C2, and capable of suppressing common-mode signals; The charge accumulation circuit also includes a GPIO interface PC for controlling the switching states of analog switches S1 and S2. During the charging phase, GPIO interfaces PA and PD output high levels to charge the capacitor under test and the reference capacitor, respectively, while GPIO interfaces PB and PE output low levels. Resistors R2 and R5 discharge the parasitic junction capacitance of the switches, reducing the potential difference between the parasitic junction capacitances of analog switches S1 and S2. During the discharge phase, GPIO interfaces PA, PD, PB, and PE switch to a high-impedance state, controlling the precise switching of the charging and discharging paths. The GPIO interface PC controls the switching between analog switches S1 and S2, allowing the capacitor under test and the reference capacitor to alternately charge capacitors C1 and C2.

2. The charging and discharging capacitor detection method according to claim 1, characterized in that, There is a delay time T between the steps of controlling the output of high impedance states of GPIO interfaces PA and PD and the output of high impedance states of GPIO interfaces PB and PE.

3. The charging and discharging capacitor detection method according to claim 1, characterized in that, The capacitance values ​​of capacitor C1 and capacitor C2 are more than 1000 times the capacitance values ​​of the capacitor under test and the reference capacitor, and the dynamic switching frequency of the states of GPIO interface PA, GPIO interface PB, GPIO interface PD, and GPIO interface PE is more than 1000 times the switching frequency of analog switch S1 and analog switch S2.

4. The charging and discharging capacitor detection method according to claim 1, characterized in that, The capacitance of capacitor C1 is more than 1000 times the capacitance of the parasitic junction of analog switch S1, the capacitance of capacitor C2 is more than 1000 times the capacitance of the parasitic junction of analog switch S2, and the dynamic switching frequency of the states of GPIO interfaces PA, PB, PD, and PE is more than 1000 times the switching frequency of analog switches S1 and S2.

5. The charging and discharging capacitor detection method according to claim 1, characterized in that, The capacitance values ​​of capacitors C1 and C2 are configured to be in the nF range; the other end of the reference capacitor and the capacitor under test is a virtual ground.

6. The charging and discharging capacitor detection method according to claim 1, characterized in that, It also includes a low-pass filter and a data acquisition card, with the output of the operational amplifier connected in sequence to the low-pass filter and the data acquisition card.

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